2 * Copyright (c) 1990 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
37 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
38 * $DragonFly: src/sys/i386/isa/Attic/clock.c,v 1.3 2003/06/29 07:37:06 dillon Exp $
42 * Routines to handle clock hardware.
46 * inittodr, settodr and support routines written
47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
52 #include "opt_clock.h"
55 #include <sys/param.h>
56 #include <sys/systm.h>
58 #include <sys/kernel.h>
62 #include <sys/sysctl.h>
65 #include <machine/clock.h>
66 #ifdef CLK_CALIBRATION_LOOP
68 #include <machine/cputypes.h>
69 #include <machine/frame.h>
70 #include <machine/ipl.h>
71 #include <machine/limits.h>
72 #include <machine/md_var.h>
73 #include <machine/psl.h>
75 #include <machine/segments.h>
77 #if defined(SMP) || defined(APIC_IO)
78 #include <machine/smp.h>
79 #endif /* SMP || APIC_IO */
80 #include <machine/specialreg.h>
82 #include <i386/isa/icu.h>
83 #include <i386/isa/isa.h>
85 #include <i386/isa/timerreg.h>
87 #include <i386/isa/intr_machdep.h>
91 #include <i386/isa/mca_machdep.h>
95 #define disable_intr() CLOCK_DISABLE_INTR()
96 #define enable_intr() CLOCK_ENABLE_INTR()
99 #include <i386/isa/intr_machdep.h>
100 /* The interrupt triggered by the 8254 (timer) chip */
102 static u_long read_intr_count __P((int vec));
103 static void setup_8254_mixed_mode __P((void));
108 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
109 * can use a simple formula for leap years.
111 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
112 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
114 #define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x))
117 * Time in timer cycles that it takes for microtime() to disable interrupts
118 * and latch the count. microtime() currently uses "cli; outb ..." so it
119 * normally takes less than 2 timer cycles. Add a few for cache misses.
120 * Add a few more to allow for latency in bogus calls to microtime() with
121 * interrupts already disabled.
123 #define TIMER0_LATCH_COUNT 20
126 * Maximum frequency that we are willing to allow for timer0. Must be
127 * low enough to guarantee that the timer interrupt handler returns
128 * before the next timer interrupt.
130 #define TIMER0_MAX_FREQ 20000
132 int adjkerntz; /* local offset from GMT in seconds */
134 int disable_rtc_set; /* disable resettodr() if != 0 */
135 volatile u_int idelayed;
136 int statclock_disable;
137 u_int stat_imask = SWI_CLOCK_MASK;
139 #define TIMER_FREQ 1193182
141 u_int timer_freq = TIMER_FREQ;
142 int timer0_max_count;
145 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
147 static int beeping = 0;
148 static u_int clk_imask = HWI_MASK | SWI_MASK;
149 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
150 static u_int hardclock_max_count;
151 static u_int32_t i8254_lastcount;
152 static u_int32_t i8254_offset;
153 static int i8254_ticked;
155 * XXX new_function and timer_func should not handle clockframes, but
156 * timer_func currently needs to hold hardclock to handle the
157 * timer0_state == 0 case. We should use inthand_add()/inthand_remove()
158 * to switch between clkintr() and a slightly different timerintr().
160 static void (*new_function) __P((struct clockframe *frame));
161 static u_int new_rate;
162 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
163 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
164 static u_int timer0_prescaler_count;
166 /* Values for timerX_state: */
168 #define RELEASE_PENDING 1
170 #define ACQUIRE_PENDING 3
172 static u_char timer0_state;
173 static u_char timer2_state;
174 static void (*timer_func) __P((struct clockframe *frame)) = hardclock;
175 static u_int tsc_present;
177 static unsigned i8254_get_timecount __P((struct timecounter *tc));
178 static unsigned tsc_get_timecount __P((struct timecounter *tc));
179 static void set_timer_freq(u_int freq, int intr_freq);
181 static struct timecounter tsc_timecounter = {
182 tsc_get_timecount, /* get_timecount */
184 ~0u, /* counter_mask */
189 SYSCTL_OPAQUE(_debug, OID_AUTO, tsc_timecounter, CTLFLAG_RD,
190 &tsc_timecounter, sizeof(tsc_timecounter), "S,timecounter", "");
192 static struct timecounter i8254_timecounter = {
193 i8254_get_timecount, /* get_timecount */
195 ~0u, /* counter_mask */
200 SYSCTL_OPAQUE(_debug, OID_AUTO, i8254_timecounter, CTLFLAG_RD,
201 &i8254_timecounter, sizeof(i8254_timecounter), "S,timecounter", "");
204 clkintr(struct clockframe frame)
206 if (timecounter->tc_get_timecount == i8254_get_timecount) {
211 i8254_offset += timer0_max_count;
218 switch (timer0_state) {
225 if ((timer0_prescaler_count += timer0_max_count)
226 >= hardclock_max_count) {
227 timer0_prescaler_count -= hardclock_max_count;
233 case ACQUIRE_PENDING:
235 i8254_offset = i8254_get_timecount(NULL);
237 timer0_max_count = TIMER_DIV(new_rate);
238 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
239 outb(TIMER_CNTR0, timer0_max_count & 0xff);
240 outb(TIMER_CNTR0, timer0_max_count >> 8);
242 timer_func = new_function;
243 timer0_state = ACQUIRED;
247 case RELEASE_PENDING:
248 if ((timer0_prescaler_count += timer0_max_count)
249 >= hardclock_max_count) {
251 i8254_offset = i8254_get_timecount(NULL);
253 timer0_max_count = hardclock_max_count;
255 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
256 outb(TIMER_CNTR0, timer0_max_count & 0xff);
257 outb(TIMER_CNTR0, timer0_max_count >> 8);
259 timer0_prescaler_count = 0;
260 timer_func = hardclock;
261 timer0_state = RELEASED;
268 /* Reset clock interrupt by asserting bit 7 of port 0x61 */
270 outb(0x61, inb(0x61) | 0x80);
275 * The acquire and release functions must be called at ipl >= splclock().
278 acquire_timer0(int rate, void (*function) __P((struct clockframe *frame)))
282 if (rate <= 0 || rate > TIMER0_MAX_FREQ)
284 switch (timer0_state) {
287 timer0_state = ACQUIRE_PENDING;
290 case RELEASE_PENDING:
291 if (rate != old_rate)
294 * The timer has been released recently, but is being
295 * re-acquired before the release completed. In this
296 * case, we simply reclaim it as if it had not been
299 timer0_state = ACQUIRED;
303 return (-1); /* busy */
305 new_function = function;
306 old_rate = new_rate = rate;
311 acquire_timer2(int mode)
314 if (timer2_state != RELEASED)
316 timer2_state = ACQUIRED;
319 * This access to the timer registers is as atomic as possible
320 * because it is a single instruction. We could do better if we
321 * knew the rate. Use of splclock() limits glitches to 10-100us,
322 * and this is probably good enough for timer2, so we aren't as
323 * careful with it as with timer0.
325 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
333 switch (timer0_state) {
336 timer0_state = RELEASE_PENDING;
339 case ACQUIRE_PENDING:
340 /* Nothing happened yet, release quickly. */
341 timer0_state = RELEASED;
354 if (timer2_state != ACQUIRED)
356 timer2_state = RELEASED;
357 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
362 * This routine receives statistical clock interrupts from the RTC.
363 * As explained above, these occur at 128 interrupts per second.
364 * When profiling, we receive interrupts at a rate of 1024 Hz.
366 * This does not actually add as much overhead as it sounds, because
367 * when the statistical clock is active, the hardclock driver no longer
368 * needs to keep (inaccurate) statistics on its own. This decouples
369 * statistics gathering from scheduling interrupts.
371 * The RTC chip requires that we read status register C (RTC_INTR)
372 * to acknowledge an interrupt, before it will generate the next one.
373 * Under high interrupt load, rtcintr() can be indefinitely delayed and
374 * the clock can tick immediately after the read from RTC_INTR. In this
375 * case, the mc146818A interrupt signal will not drop for long enough
376 * to register with the 8259 PIC. If an interrupt is missed, the stat
377 * clock will halt, considerably degrading system performance. This is
378 * why we use 'while' rather than a more straightforward 'if' below.
379 * Stat clock ticks can still be lost, causing minor loss of accuracy
380 * in the statistics, but the stat clock will no longer stop.
383 rtcintr(struct clockframe frame)
385 while (rtcin(RTC_INTR) & RTCIR_PERIOD)
393 DB_SHOW_COMMAND(rtc, rtc)
395 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
396 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
397 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
398 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
411 /* Select timer0 and latch counter value. */
412 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
414 low = inb(TIMER_CNTR0);
415 high = inb(TIMER_CNTR0);
419 return ((high << 8) | low);
423 * Wait "n" microseconds.
424 * Relies on timer 1 counting down from (timer_freq / hz)
425 * Note: timer had better have been programmed before this is first used!
430 int delta, prev_tick, tick, ticks_left;
435 static int state = 0;
439 for (n1 = 1; n1 <= 10000000; n1 *= 10)
444 printf("DELAY(%d)...", n);
447 * Guard against the timer being uninitialized if we are called
448 * early for console i/o.
450 if (timer0_max_count == 0)
451 set_timer_freq(timer_freq, hz);
454 * Read the counter first, so that the rest of the setup overhead is
455 * counted. Guess the initial overhead is 20 usec (on most systems it
456 * takes about 1.5 usec for each of the i/o's in getit(). The loop
457 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The
458 * multiplications and divisions to scale the count take a while).
461 n -= 0; /* XXX actually guess no initial overhead */
463 * Calculate (n * (timer_freq / 1e6)) without using floating point
464 * and without any avoidable overflows.
470 * Use fixed point to avoid a slow division by 1000000.
471 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest.
472 * 2^15 is the first power of 2 that gives exact results
473 * for n between 0 and 256.
475 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15;
478 * Don't bother using fixed point, although gcc-2.7.2
479 * generates particularly poor code for the long long
480 * division, since even the slow way will complete long
481 * before the delay is up (unless we're interrupted).
483 ticks_left = ((u_int)n * (long long)timer_freq + 999999)
486 while (ticks_left > 0) {
491 delta = prev_tick - tick;
494 delta += timer0_max_count;
496 * Guard against timer0_max_count being wrong.
497 * This shouldn't happen in normal operation,
498 * but it may happen if set_timer_freq() is
508 printf(" %d calls to getit() at %d usec each\n",
509 getit_calls, (n + 5) / getit_calls);
514 sysbeepstop(void *chan)
516 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
522 sysbeep(int pitch, int period)
526 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
528 /* Something else owns it. */
530 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */
533 outb(TIMER_CNTR2, pitch);
534 outb(TIMER_CNTR2, (pitch>>8));
537 /* enable counter2 output to speaker */
538 outb(IO_PPI, inb(IO_PPI) | 3);
540 timeout(sysbeepstop, (void *)NULL, period);
547 * RTC support routines
560 val = inb(IO_RTC + 1);
567 writertc(u_char reg, u_char val)
575 outb(IO_RTC + 1, val);
576 inb(0x84); /* XXX work around wrong order in rtcin() */
583 return(bcd2bin(rtcin(port)));
587 calibrate_clocks(void)
590 u_int count, prev_count, tot_count;
591 int sec, start_sec, timeout;
594 printf("Calibrating clock(s) ... ");
595 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
599 /* Read the mc146818A seconds counter. */
601 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
602 sec = rtcin(RTC_SEC);
609 /* Wait for the mC146818A seconds counter to change. */
612 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
613 sec = rtcin(RTC_SEC);
614 if (sec != start_sec)
621 /* Start keeping track of the i8254 counter. */
622 prev_count = getit();
623 if (prev_count == 0 || prev_count > timer0_max_count)
630 old_tsc = 0; /* shut up gcc */
633 * Wait for the mc146818A seconds counter to change. Read the i8254
634 * counter for each iteration since this is convenient and only
635 * costs a few usec of inaccuracy. The timing of the final reads
636 * of the counters almost matches the timing of the initial reads,
637 * so the main cause of inaccuracy is the varying latency from
638 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
639 * rtcin(RTC_SEC) that returns a changed seconds count. The
640 * maximum inaccuracy from this cause is < 10 usec on 486's.
644 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
645 sec = rtcin(RTC_SEC);
647 if (count == 0 || count > timer0_max_count)
649 if (count > prev_count)
650 tot_count += prev_count - (count - timer0_max_count);
652 tot_count += prev_count - count;
654 if (sec != start_sec)
661 * Read the cpu cycle counter. The timing considerations are
662 * similar to those for the i8254 clock.
665 tsc_freq = rdtsc() - old_tsc;
669 printf("TSC clock: %u Hz, ", tsc_freq);
670 printf("i8254 clock: %u Hz\n", tot_count);
676 printf("failed, using default i8254 clock of %u Hz\n",
682 set_timer_freq(u_int freq, int intr_freq)
685 int new_timer0_max_count;
690 new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq);
691 if (new_timer0_max_count != timer0_max_count) {
692 timer0_max_count = new_timer0_max_count;
693 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
694 outb(TIMER_CNTR0, timer0_max_count & 0xff);
695 outb(TIMER_CNTR0, timer0_max_count >> 8);
708 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
709 outb(TIMER_CNTR0, timer0_max_count & 0xff);
710 outb(TIMER_CNTR0, timer0_max_count >> 8);
719 /* Restore all of the RTC's "status" (actually, control) registers. */
720 writertc(RTC_STATUSB, RTCSB_24HR);
721 writertc(RTC_STATUSA, rtc_statusa);
722 writertc(RTC_STATUSB, rtc_statusb);
726 * Restore all the timers non-atomically (XXX: should be atomically).
728 * This function is called from apm_default_resume() to restore all the timers.
729 * This should not be necessary, but there are broken laptops that do not
730 * restore all the timers on resume.
736 i8254_restore(); /* restore timer_freq and hz */
737 rtc_restore(); /* reenable RTC interrupts */
741 * Initialize 8254 timer 0 early so that it can be used in DELAY().
742 * XXX initialization of other timers is unintentionally left blank.
749 if (cpu_feature & CPUID_TSC)
754 writertc(RTC_STATUSA, rtc_statusa);
755 writertc(RTC_STATUSB, RTCSB_24HR);
757 set_timer_freq(timer_freq, hz);
758 freq = calibrate_clocks();
759 #ifdef CLK_CALIBRATION_LOOP
762 "Press a key on the console to abort clock calibration\n");
763 while (cncheckc() == -1)
769 * Use the calibrated i8254 frequency if it seems reasonable.
770 * Otherwise use the default, and don't use the calibrated i586
773 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq;
774 if (delta < timer_freq / 100) {
775 #ifndef CLK_USE_I8254_CALIBRATION
778 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
785 "%d Hz differs from default of %d Hz by more than 1%%\n",
790 set_timer_freq(timer_freq, hz);
791 i8254_timecounter.tc_frequency = timer_freq;
792 init_timecounter(&i8254_timecounter);
794 #ifndef CLK_USE_TSC_CALIBRATION
798 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
802 if (tsc_present && tsc_freq == 0) {
804 * Calibration of the i586 clock relative to the mc146818A
805 * clock failed. Do a less accurate calibration relative
806 * to the i8254 clock.
808 u_int64_t old_tsc = rdtsc();
811 tsc_freq = rdtsc() - old_tsc;
812 #ifdef CLK_USE_TSC_CALIBRATION
814 printf("TSC clock: %u Hz (Method B)\n", tsc_freq);
820 * We can not use the TSC in SMP mode, until we figure out a
821 * cheap (impossible), reliable and precise (yeah right!) way
822 * to synchronize the TSCs of all the CPUs.
823 * Curse Intel for leaving the counter out of the I/O APIC.
828 * We can not use the TSC if we support APM. Precise timekeeping
829 * on an APM'ed machine is at best a fools pursuit, since
830 * any and all of the time spent in various SMM code can't
831 * be reliably accounted for. Reading the RTC is your only
832 * source of reliable time info. The i8254 looses too of course
833 * but we need to have some kind of time...
834 * We don't know at this point whether APM is going to be used
835 * or not, nor when it might be activated. Play it safe.
838 #endif /* NAPM > 0 */
840 if (tsc_present && tsc_freq != 0 && !tsc_is_broken) {
841 tsc_timecounter.tc_frequency = tsc_freq;
842 init_timecounter(&tsc_timecounter);
845 #endif /* !defined(SMP) */
849 * Initialize the time of day register, based on the time base which is, e.g.
853 inittodr(time_t base)
855 unsigned long sec, days;
865 set_timecounter(&ts);
869 /* Look if we have a RTC present and the time is valid */
870 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
873 /* wait for time update to complete */
874 /* If RTCSA_TUP is zero, we have at least 244us before next update */
876 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
882 #ifdef USE_RTC_CENTURY
883 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
885 year = readrtc(RTC_YEAR) + 1900;
893 month = readrtc(RTC_MONTH);
894 for (m = 1; m < month; m++)
895 days += daysinmonth[m-1];
896 if ((month > 2) && LEAPYEAR(year))
898 days += readrtc(RTC_DAY) - 1;
900 for (y = 1970; y < year; y++)
901 days += DAYSPERYEAR + LEAPYEAR(y);
902 sec = ((( days * 24 +
903 readrtc(RTC_HRS)) * 60 +
904 readrtc(RTC_MIN)) * 60 +
906 /* sec now contains the number of seconds, since Jan 1 1970,
907 in the local time zone */
909 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
911 y = time_second - sec;
912 if (y <= -2 || y >= 2) {
913 /* badly off, adjust it */
916 set_timecounter(&ts);
922 printf("Invalid time in real time clock.\n");
923 printf("Check and reset the date immediately!\n");
927 * Write system time back to RTC
942 /* Disable RTC updates and interrupts. */
943 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
945 /* Calculate local time to put in RTC */
947 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
949 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
950 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
951 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
953 /* We have now the days since 01-01-1970 in tm */
954 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
955 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
957 y++, m = DAYSPERYEAR + LEAPYEAR(y))
960 /* Now we have the years in y and the day-of-the-year in tm */
961 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
962 #ifdef USE_RTC_CENTURY
963 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
969 if (m == 1 && LEAPYEAR(y))
976 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
977 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
979 /* Reenable RTC updates and interrupts. */
980 writertc(RTC_STATUSB, rtc_statusb);
985 * Start both clocks running.
993 struct intrec *clkdesc;
996 if (statclock_disable) {
998 * The stat interrupt mask is different without the
999 * statistics clock. Also, don't set the interrupt
1000 * flag which would normally cause the RTC to generate
1003 stat_imask = HWI_MASK | SWI_MASK;
1004 rtc_statusb = RTCSB_24HR;
1006 /* Setting stathz to nonzero early helps avoid races. */
1007 stathz = RTC_NOPROFRATE;
1008 profhz = RTC_PROFRATE;
1011 /* Finish initializing 8253 timer 0. */
1014 apic_8254_intr = isa_apic_irq(0);
1015 apic_8254_trial = 0;
1016 if (apic_8254_intr >= 0 ) {
1017 if (apic_int_type(0, 0) == 3)
1018 apic_8254_trial = 1;
1020 /* look for ExtInt on pin 0 */
1021 if (apic_int_type(0, 0) == 3) {
1022 apic_8254_intr = apic_irq(0, 0);
1023 setup_8254_mixed_mode();
1025 panic("APIC_IO: Cannot route 8254 interrupt to CPU");
1028 clkdesc = inthand_add("clk", apic_8254_intr, (inthand2_t *)clkintr,
1029 NULL, &clk_imask, INTR_EXCL | INTR_FAST);
1030 INTREN(1 << apic_8254_intr);
1034 inthand_add("clk", 0, (inthand2_t *)clkintr, NULL, &clk_imask,
1035 INTR_EXCL | INTR_FAST);
1038 #endif /* APIC_IO */
1040 /* Initialize RTC. */
1041 writertc(RTC_STATUSA, rtc_statusa);
1042 writertc(RTC_STATUSB, RTCSB_24HR);
1044 /* Don't bother enabling the statistics clock. */
1045 if (statclock_disable)
1047 diag = rtcin(RTC_DIAG);
1049 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
1052 if (isa_apic_irq(8) != 8)
1053 panic("APIC RTC != 8");
1054 #endif /* APIC_IO */
1056 inthand_add("rtc", 8, (inthand2_t *)rtcintr, NULL, &stat_imask,
1057 INTR_EXCL | INTR_FAST);
1063 #endif /* APIC_IO */
1065 writertc(RTC_STATUSB, rtc_statusb);
1068 if (apic_8254_trial) {
1070 printf("APIC_IO: Testing 8254 interrupt delivery\n");
1071 while (read_intr_count(8) < 6)
1073 if (read_intr_count(apic_8254_intr) < 3) {
1075 * The MP table is broken.
1076 * The 8254 was not connected to the specified pin
1078 * Workaround: Limited variant of mixed mode.
1080 INTRDIS(1 << apic_8254_intr);
1081 inthand_remove(clkdesc);
1082 printf("APIC_IO: Broken MP table detected: "
1083 "8254 is not connected to "
1084 "IOAPIC #%d intpin %d\n",
1085 int_to_apicintpin[apic_8254_intr].ioapic,
1086 int_to_apicintpin[apic_8254_intr].int_pin);
1088 * Revoke current ISA IRQ 0 assignment and
1089 * configure a fallback interrupt routing from
1090 * the 8254 Timer via the 8259 PIC to the
1091 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
1092 * We reuse the low level interrupt handler number.
1094 if (apic_irq(0, 0) < 0) {
1095 revoke_apic_irq(apic_8254_intr);
1096 assign_apic_irq(0, 0, apic_8254_intr);
1098 apic_8254_intr = apic_irq(0, 0);
1099 setup_8254_mixed_mode();
1100 inthand_add("clk", apic_8254_intr,
1101 (inthand2_t *)clkintr,
1102 NULL, &clk_imask, INTR_EXCL | INTR_FAST);
1103 INTREN(1 << apic_8254_intr);
1107 if (apic_int_type(0, 0) != 3 ||
1108 int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
1109 int_to_apicintpin[apic_8254_intr].int_pin != 0)
1110 printf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1111 int_to_apicintpin[apic_8254_intr].ioapic,
1112 int_to_apicintpin[apic_8254_intr].int_pin);
1115 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
1122 read_intr_count(int vec)
1125 up = intr_countp[vec];
1132 setup_8254_mixed_mode()
1135 * Allow 8254 timer to INTerrupt 8259:
1136 * re-initialize master 8259:
1137 * reset; prog 4 bytes, single ICU, edge triggered
1139 outb(IO_ICU1, 0x13);
1140 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */
1141 outb(IO_ICU1 + 1, 0x00); /* ignore slave */
1142 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
1143 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
1145 /* program IO APIC for type 3 INT on INT0 */
1146 if (ext_int_setup(0, 0) < 0)
1147 panic("8254 redirect via APIC pin0 impossible!");
1152 setstatclockrate(int newhz)
1154 if (newhz == RTC_PROFRATE)
1155 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1157 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1158 writertc(RTC_STATUSA, rtc_statusa);
1162 sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS)
1168 * Use `i8254' instead of `timer' in external names because `timer'
1169 * is is too generic. Should use it everywhere.
1172 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
1173 if (error == 0 && req->newptr != NULL) {
1174 if (timer0_state != RELEASED)
1175 return (EBUSY); /* too much trouble to handle */
1176 set_timer_freq(freq, hz);
1177 i8254_timecounter.tc_frequency = freq;
1178 update_timecounter(&i8254_timecounter);
1183 SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW,
1184 0, sizeof(u_int), sysctl_machdep_i8254_freq, "IU", "");
1187 sysctl_machdep_tsc_freq(SYSCTL_HANDLER_ARGS)
1192 if (tsc_timecounter.tc_frequency == 0)
1193 return (EOPNOTSUPP);
1195 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
1196 if (error == 0 && req->newptr != NULL) {
1198 tsc_timecounter.tc_frequency = tsc_freq;
1199 update_timecounter(&tsc_timecounter);
1204 SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_INT | CTLFLAG_RW,
1205 0, sizeof(u_int), sysctl_machdep_tsc_freq, "IU", "");
1208 i8254_get_timecount(struct timecounter *tc)
1217 /* Select timer0 and latch counter value. */
1218 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
1220 low = inb(TIMER_CNTR0);
1221 high = inb(TIMER_CNTR0);
1222 count = timer0_max_count - ((high << 8) | low);
1223 if (count < i8254_lastcount ||
1224 (!i8254_ticked && (clkintr_pending ||
1225 ((count < 20 || (!(ef & PSL_I) && count < timer0_max_count / 2u)) &&
1227 #define lapic_irr1 ((volatile u_int *)&lapic)[0x210 / 4] /* XXX XXX */
1228 /* XXX this assumes that apic_8254_intr is < 24. */
1229 (lapic_irr1 & (1 << apic_8254_intr))))
1231 (inb(IO_ICU1) & 1)))
1235 i8254_offset += timer0_max_count;
1237 i8254_lastcount = count;
1238 count += i8254_offset;
1245 tsc_get_timecount(struct timecounter *tc)
1250 #ifdef KERN_TIMESTAMP
1251 #define KERN_TIMESTAMP_SIZE 16384
1252 static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1253 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1254 sizeof(tsc), "LU", "Kernel timestamps");
1260 tsc[i] = (u_int32_t)rdtsc();
1263 if (i >= KERN_TIMESTAMP_SIZE)
1265 tsc[i] = 0; /* mark last entry */
1267 #endif KERN_TIMESTAMP