2 * Copyright (c) 1990 William Jolitz.
3 * Copyright (c) 1991 The Regents of the University of California.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by the University of
17 * California, Berkeley and its contributors.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
35 * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $
36 * $DragonFly: src/sys/i386/isa/Attic/npx.c,v 1.18 2004/05/04 12:22:46 hmp Exp $
40 #include "opt_debug_npx.h"
41 #include "opt_math_emulate.h"
43 #include <sys/param.h>
44 #include <sys/systm.h>
46 #include <sys/kernel.h>
47 #include <sys/malloc.h>
48 #include <sys/module.h>
49 #include <sys/sysctl.h>
51 #include <machine/bus.h>
54 #include <sys/syslog.h>
56 #include <sys/signalvar.h>
57 #include <sys/thread2.h>
60 #include <machine/asmacros.h>
62 #include <machine/cputypes.h>
63 #include <machine/frame.h>
64 #include <machine/ipl.h>
65 #include <machine/md_var.h>
66 #include <machine/pcb.h>
67 #include <machine/psl.h>
69 #include <machine/clock.h>
71 #include <machine/resource.h>
72 #include <machine/specialreg.h>
73 #include <machine/segments.h>
74 #include <machine/globaldata.h>
77 #include <i386/isa/icu.h>
78 #include <i386/isa/intr_machdep.h>
79 #include <bus/isa/i386/isa.h>
83 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
86 /* Configuration flags. */
87 #define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0)
88 #define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1)
89 #define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2)
90 #define NPX_PREFER_EMULATOR (1 << 3)
94 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr)))
95 #define fnclex() __asm("fnclex")
96 #define fninit() __asm("fninit")
97 #define fnop() __asm("fnop")
98 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr)))
99 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
100 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr)))
101 #define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop")
102 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr)))
103 #ifndef CPU_DISABLE_SSE
104 #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr)))
105 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
107 #define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
108 : : "n" (CR0_TS) : "ax")
109 #define stop_emulating() __asm("clts")
111 #else /* not __GNUC__ */
113 void fldcw (caddr_t addr);
117 void fnsave (caddr_t addr);
118 void fnstcw (caddr_t addr);
119 void fnstsw (caddr_t addr);
120 void fp_divide_by_0 (void);
121 void frstor (caddr_t addr);
122 #ifndef CPU_DISABLE_SSE
123 void fxsave (caddr_t addr);
124 void fxrstor (caddr_t addr);
126 void start_emulating (void);
127 void stop_emulating (void);
129 #endif /* __GNUC__ */
131 #ifndef CPU_DISABLE_SSE
132 #define GET_FPU_EXSW_PTR(td) \
134 &(td)->td_savefpu->sv_xmm.sv_ex_sw : \
135 &(td)->td_savefpu->sv_87.sv_ex_sw)
136 #else /* CPU_DISABLE_SSE */
137 #define GET_FPU_EXSW_PTR(td) \
138 (&(td)->td_savefpu->sv_87.sv_ex_sw)
139 #endif /* CPU_DISABLE_SSE */
141 typedef u_char bool_t;
143 static int npx_attach (device_t dev);
144 void npx_intr (void *);
145 static void npx_identify (driver_t *driver, device_t parent);
146 static int npx_probe (device_t dev);
147 static int npx_probe1 (device_t dev);
148 static void fpusave (union savefpu *);
149 static void fpurstor (union savefpu *);
151 int hw_float; /* XXX currently just alias for npx_exists */
153 SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint,
154 CTLFLAG_RD, &hw_float, 0,
155 "Floatingpoint instructions executed in hardware");
158 static u_int npx0_imask = SWI_CLOCK_MASK;
159 static struct gate_descriptor npx_idt_probeintr;
160 static int npx_intrno;
161 static volatile u_int npx_intrs_while_probing;
162 static volatile u_int npx_traps_while_probing;
165 static bool_t npx_ex16;
166 static bool_t npx_exists;
167 static bool_t npx_irq13;
168 static int npx_irq; /* irq number */
172 * Special interrupt handlers. Someday intr0-intr15 will be used to count
173 * interrupts. We'll still need a special exception 16 handler. The busy
174 * latch stuff in probeintr() can be moved to npxprobe().
180 .type " __XSTRING(CNAME(probeintr)) ",@function \n\
181 " __XSTRING(CNAME(probeintr)) ": \n\
183 incl " __XSTRING(CNAME(npx_intrs_while_probing)) " \n\
185 movb $0x20,%al # EOI (asm in strings loses cpp features) \n\
186 outb %al,$0xa0 # IO_ICU2 \n\
187 outb %al,$0x20 # IO_ICU1 \n\
189 outb %al,$0xf0 # clear BUSY# latch \n\
198 .type " __XSTRING(CNAME(probetrap)) ",@function \n\
199 " __XSTRING(CNAME(probetrap)) ": \n\
201 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\
208 * Identify routine. Create a connection point on our parent for probing.
211 npx_identify(driver, parent)
217 child = BUS_ADD_CHILD(parent, 0, "npx", 0);
219 panic("npx_identify");
223 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait
224 * whether the device exists or not (XXX should be elsewhere). Set flags
225 * to tell npxattach() what to do. Modify device struct if npx doesn't
226 * need to use interrupts. Return 1 if device exists.
234 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0)
236 return npx_probe1(dev);
242 u_char save_icu1_mask;
243 u_char save_icu2_mask;
244 struct gate_descriptor save_idt_npxintr;
245 struct gate_descriptor save_idt_npxtrap;
247 * This routine is now just a wrapper for npxprobe1(), to install
248 * special npx interrupt and trap handlers, to enable npx interrupts
249 * and to disable other interrupts. Someday isa_configure() will
250 * install suitable handlers and run with interrupts enabled so we
251 * won't need to do so much here.
253 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0)
255 npx_intrno = NRSVIDT + npx_irq;
256 save_eflags = read_eflags();
258 save_icu1_mask = inb(IO_ICU1 + 1);
259 save_icu2_mask = inb(IO_ICU2 + 1);
260 save_idt_npxintr = idt[npx_intrno];
261 save_idt_npxtrap = idt[16];
262 outb(IO_ICU1 + 1, ~IRQ_SLAVE);
263 outb(IO_ICU2 + 1, ~(1 << (npx_irq - 8)));
264 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
265 setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
266 npx_idt_probeintr = idt[npx_intrno];
268 result = npx_probe1(dev);
270 outb(IO_ICU1 + 1, save_icu1_mask);
271 outb(IO_ICU2 + 1, save_icu2_mask);
272 idt[npx_intrno] = save_idt_npxintr;
273 idt[16] = save_idt_npxtrap;
274 write_eflags(save_eflags);
290 * Partially reset the coprocessor, if any. Some BIOS's don't reset
291 * it after a warm boot.
293 outb(0xf1, 0); /* full reset on some systems, NOP on others */
294 outb(0xf0, 0); /* clear BUSY# latch */
296 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT
297 * instructions. We must set the CR0_MP bit and use the CR0_TS
298 * bit to control the trap, because setting the CR0_EM bit does
299 * not cause WAIT instructions to trap. It's important to trap
300 * WAIT instructions - otherwise the "wait" variants of no-wait
301 * control instructions would degenerate to the "no-wait" variants
302 * after FP context switches but work correctly otherwise. It's
303 * particularly important to trap WAITs when there is no NPX -
304 * otherwise the "wait" variants would always degenerate.
306 * Try setting CR0_NE to get correct error reporting on 486DX's.
307 * Setting it should fail or do nothing on lesser processors.
309 load_cr0(rcr0() | CR0_MP | CR0_NE);
311 * But don't trap while we're probing.
315 * Finish resetting the coprocessor, if any. If there is an error
316 * pending, then we may get a bogus IRQ13, but probeintr() will handle
317 * it OK. Bogus halts have never been observed, but we enabled
318 * IRQ13 and cleared the BUSY# latch early to handle them anyway.
324 * Exception 16 MUST work for SMP.
327 npx_ex16 = hw_float = npx_exists = 1;
328 device_set_desc(dev, "math processor");
332 device_set_desc(dev, "math processor");
335 * Don't use fwait here because it might hang.
336 * Don't use fnop here because it usually hangs if there is no FPU.
338 DELAY(1000); /* wait for any IRQ13 */
340 if (npx_intrs_while_probing != 0)
341 printf("fninit caused %u bogus npx interrupt(s)\n",
342 npx_intrs_while_probing);
343 if (npx_traps_while_probing != 0)
344 printf("fninit caused %u bogus npx trap(s)\n",
345 npx_traps_while_probing);
348 * Check for a status of mostly zero.
352 if ((status & 0xb8ff) == 0) {
354 * Good, now check for a proper control word.
358 if ((control & 0x1f3f) == 0x033f) {
359 hw_float = npx_exists = 1;
361 * We have an npx, now divide by 0 to see if exception
364 control &= ~(1 << 2); /* enable divide by 0 trap */
366 npx_traps_while_probing = npx_intrs_while_probing = 0;
368 if (npx_traps_while_probing != 0) {
370 * Good, exception 16 works.
375 if (npx_intrs_while_probing != 0) {
380 * Bad, we are stuck with IRQ13.
384 * npxattach would be too late to set npx0_imask
386 npx0_imask |= (1 << npx_irq);
389 * We allocate these resources permanently,
390 * so there is no need to keep track of them.
393 r = bus_alloc_resource(dev, SYS_RES_IOPORT,
394 &rid, IO_NPX, IO_NPX,
395 IO_NPXSIZE, RF_ACTIVE);
397 panic("npx: can't get ports");
399 r = bus_alloc_resource(dev, SYS_RES_IRQ,
400 &rid, npx_irq, npx_irq,
403 panic("npx: can't get IRQ");
404 BUS_SETUP_INTR(device_get_parent(dev),
405 dev, r, INTR_TYPE_MISC,
408 panic("npx: can't create intr");
413 * Worse, even IRQ13 is broken. Use emulator.
418 * Probe failed, but we want to get to npxattach to initialize the
419 * emulator and say that it has been installed. XXX handle devices
420 * that aren't really devices better.
427 * Attach routine - announce which it is, and wire into system
434 #if (defined(I586_CPU) || defined(I686_CPU)) && !defined(CPU_DISABLE_SSE)
438 if (resource_int_value("npx", 0, "flags", &flags) != 0)
442 device_printf(dev, "flags 0x%x ", flags);
444 device_printf(dev, "using IRQ 13 interface\n");
446 #if defined(MATH_EMULATE) || defined(GPL_MATH_EMULATE)
448 if (!(flags & NPX_PREFER_EMULATOR))
449 device_printf(dev, "INT 16 interface\n");
451 device_printf(dev, "FPU exists, but flags request "
453 hw_float = npx_exists = 0;
455 } else if (npx_exists) {
456 device_printf(dev, "error reporting broken; using 387 emulator\n");
457 hw_float = npx_exists = 0;
459 device_printf(dev, "387 emulator\n");
462 device_printf(dev, "INT 16 interface\n");
463 if (flags & NPX_PREFER_EMULATOR) {
464 device_printf(dev, "emulator requested, but none compiled "
465 "into kernel, using FPU\n");
468 device_printf(dev, "no 387 emulator in kernel and no FPU!\n");
471 npxinit(__INITIAL_NPXCW__);
473 #if (defined(I586_CPU) || defined(I686_CPU)) && !defined(CPU_DISABLE_SSE)
475 * The asm_mmx_*() routines actually use XMM as well, so only
476 * enable them if we have SSE2 and are using FXSR (fxsave/fxrstore).
478 TUNABLE_INT_FETCH("kern.mmxopt", &mmxopt);
479 if ((cpu_feature & CPUID_MMX) && (cpu_feature & CPUID_SSE) &&
480 (cpu_feature & CPUID_SSE2) &&
481 npx_ex16 && npx_exists && mmxopt && cpu_fxsr
483 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY) == 0) {
484 bcopy_vector = (void **)asm_xmm_bcopy;
485 ovbcopy_vector = (void **)asm_xmm_bcopy;
486 memcpy_vector = (void **)asm_xmm_memcpy;
487 printf("Using XMM optimized bcopy/copyin/copyout\n");
489 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BZERO) == 0) {
492 } else if ((cpu_feature & CPUID_MMX) && (cpu_feature & CPUID_SSE) &&
493 npx_ex16 && npx_exists && mmxopt && cpu_fxsr
495 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY) == 0) {
496 bcopy_vector = (void **)asm_mmx_bcopy;
497 ovbcopy_vector = (void **)asm_mmx_bcopy;
498 memcpy_vector = (void **)asm_mmx_memcpy;
499 printf("Using MMX optimized bcopy/copyin/copyout\n");
501 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BZERO) == 0) {
507 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists &&
508 timezero("i586_bzero()", i586_bzero) <
509 timezero("bzero()", bzero) * 4 / 5) {
510 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) {
511 bcopy_vector = i586_bcopy;
512 ovbcopy_vector = i586_bcopy;
514 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO))
516 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) {
517 copyin_vector = i586_copyin;
518 copyout_vector = i586_copyout;
522 return (0); /* XXX unused */
526 * Initialize floating point unit.
532 static union savefpu dummy;
537 * fninit has the same h/w bugs as fnsave. Use the detoxified
538 * fnsave to throw away any junk in the fpu. npxsave() initializes
539 * the fpu and sets npxthread = NULL as important side effects.
543 #ifndef CPU_DISABLE_SSE
544 /* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */
549 fpusave(curthread->td_savefpu);
554 * Free coprocessor (if we have it).
557 npxexit(struct proc *p)
560 if (p->p_thread == mdcpu->gd_npxthread)
561 npxsave(curthread->td_savefpu);
564 u_int masked_exceptions;
567 curthread->td_savefpu->sv_87.sv_env.en_cw
568 & curthread->td_savefpu->sv_87.sv_env.en_sw & 0x7f;
570 * Log exceptions that would have trapped with the old
571 * control word (overflow, divide by 0, and invalid operand).
573 if (masked_exceptions & 0x0d)
575 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n",
576 p->p_pid, p->p_comm, masked_exceptions);
582 * The following mechanism is used to ensure that the FPE_... value
583 * that is passed as a trapcode to the signal handler of the user
584 * process does not have more than one bit set.
586 * Multiple bits may be set if the user process modifies the control
587 * word while a status word bit is already set. While this is a sign
588 * of bad coding, we have no choise than to narrow them down to one
589 * bit, since we must not send a trapcode that is not exactly one of
592 * The mechanism has a static table with 127 entries. Each combination
593 * of the 7 FPU status word exception bits directly translates to a
594 * position in this table, where a single FPE_... value is stored.
595 * This FPE_... value stored there is considered the "most important"
596 * of the exception bits and will be sent as the signal code. The
597 * precedence of the bits is based upon Intel Document "Numerical
598 * Applications", Chapter "Special Computational Situations".
600 * The macro to choose one of these values does these steps: 1) Throw
601 * away status word bits that cannot be masked. 2) Throw away the bits
602 * currently masked in the control word, assuming the user isn't
603 * interested in them anymore. 3) Reinsert status word bit 7 (stack
604 * fault) if it is set, which cannot be masked but must be presered.
605 * 4) Use the remaining bits to point into the trapcode table.
607 * The 6 maskable bits in order of their preference, as stated in the
608 * above referenced Intel manual:
609 * 1 Invalid operation (FP_X_INV)
612 * 1c Operand of unsupported format
614 * 2 QNaN operand (not an exception, irrelavant here)
615 * 3 Any other invalid-operation not mentioned above or zero divide
616 * (FP_X_INV, FP_X_DZ)
617 * 4 Denormal operand (FP_X_DNML)
618 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
619 * 6 Inexact result (FP_X_IMP)
621 static char fpetable[128] = {
623 FPE_FLTINV, /* 1 - INV */
624 FPE_FLTUND, /* 2 - DNML */
625 FPE_FLTINV, /* 3 - INV | DNML */
626 FPE_FLTDIV, /* 4 - DZ */
627 FPE_FLTINV, /* 5 - INV | DZ */
628 FPE_FLTDIV, /* 6 - DNML | DZ */
629 FPE_FLTINV, /* 7 - INV | DNML | DZ */
630 FPE_FLTOVF, /* 8 - OFL */
631 FPE_FLTINV, /* 9 - INV | OFL */
632 FPE_FLTUND, /* A - DNML | OFL */
633 FPE_FLTINV, /* B - INV | DNML | OFL */
634 FPE_FLTDIV, /* C - DZ | OFL */
635 FPE_FLTINV, /* D - INV | DZ | OFL */
636 FPE_FLTDIV, /* E - DNML | DZ | OFL */
637 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
638 FPE_FLTUND, /* 10 - UFL */
639 FPE_FLTINV, /* 11 - INV | UFL */
640 FPE_FLTUND, /* 12 - DNML | UFL */
641 FPE_FLTINV, /* 13 - INV | DNML | UFL */
642 FPE_FLTDIV, /* 14 - DZ | UFL */
643 FPE_FLTINV, /* 15 - INV | DZ | UFL */
644 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
645 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
646 FPE_FLTOVF, /* 18 - OFL | UFL */
647 FPE_FLTINV, /* 19 - INV | OFL | UFL */
648 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
649 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
650 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
651 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
652 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
653 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
654 FPE_FLTRES, /* 20 - IMP */
655 FPE_FLTINV, /* 21 - INV | IMP */
656 FPE_FLTUND, /* 22 - DNML | IMP */
657 FPE_FLTINV, /* 23 - INV | DNML | IMP */
658 FPE_FLTDIV, /* 24 - DZ | IMP */
659 FPE_FLTINV, /* 25 - INV | DZ | IMP */
660 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
661 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
662 FPE_FLTOVF, /* 28 - OFL | IMP */
663 FPE_FLTINV, /* 29 - INV | OFL | IMP */
664 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
665 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
666 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
667 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
668 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
669 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
670 FPE_FLTUND, /* 30 - UFL | IMP */
671 FPE_FLTINV, /* 31 - INV | UFL | IMP */
672 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
673 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
674 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
675 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
676 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
677 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
678 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
679 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
680 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
681 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
682 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
683 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
684 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
685 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
686 FPE_FLTSUB, /* 40 - STK */
687 FPE_FLTSUB, /* 41 - INV | STK */
688 FPE_FLTUND, /* 42 - DNML | STK */
689 FPE_FLTSUB, /* 43 - INV | DNML | STK */
690 FPE_FLTDIV, /* 44 - DZ | STK */
691 FPE_FLTSUB, /* 45 - INV | DZ | STK */
692 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
693 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
694 FPE_FLTOVF, /* 48 - OFL | STK */
695 FPE_FLTSUB, /* 49 - INV | OFL | STK */
696 FPE_FLTUND, /* 4A - DNML | OFL | STK */
697 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
698 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
699 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
700 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
701 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
702 FPE_FLTUND, /* 50 - UFL | STK */
703 FPE_FLTSUB, /* 51 - INV | UFL | STK */
704 FPE_FLTUND, /* 52 - DNML | UFL | STK */
705 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
706 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
707 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
708 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
709 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
710 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
711 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
712 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
713 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
714 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
715 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
716 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
717 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
718 FPE_FLTRES, /* 60 - IMP | STK */
719 FPE_FLTSUB, /* 61 - INV | IMP | STK */
720 FPE_FLTUND, /* 62 - DNML | IMP | STK */
721 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
722 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
723 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
724 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
725 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
726 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
727 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
728 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
729 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
730 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
731 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
732 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
733 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
734 FPE_FLTUND, /* 70 - UFL | IMP | STK */
735 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
736 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
737 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
738 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
739 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
740 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
741 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
742 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
743 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
744 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
745 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
746 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
747 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
748 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
749 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
753 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
755 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now
756 * depend on longjmp() restoring a usable state. Restoring the state
757 * or examining it might fail if we didn't clear exceptions.
759 * The error code chosen will be one of the FPE_... macros. It will be
760 * sent as the second argument to old BSD-style signal handlers and as
761 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
763 * XXX the FP state is not preserved across signal handlers. So signal
764 * handlers cannot afford to do FP unless they preserve the state or
765 * longjmp() out. Both preserving the state and longjmp()ing may be
766 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable
767 * solution for signals other than SIGFPE.
769 * The MP lock is not held on entry (see i386/i386/exception.s) and
770 * should not be held on exit.
778 struct intrframe *frame;
781 if (mdcpu->gd_npxthread == NULL || !npx_exists) {
783 printf("npxintr: npxthread = %p, curthread = %p, npx_exists = %d\n",
784 mdcpu->gd_npxthread, curthread, npx_exists);
785 panic("npxintr from nowhere");
787 if (mdcpu->gd_npxthread != curthread) {
789 printf("npxintr: npxthread = %p, curthread = %p, npx_exists = %d\n",
790 mdcpu->gd_npxthread, curthread, npx_exists);
791 panic("npxintr from non-current process");
794 exstat = GET_FPU_EXSW_PTR(curthread);
803 * Pass exception to process.
805 frame = (struct intrframe *)&dummy; /* XXX */
806 if ((ISPL(frame->if_cs) == SEL_UPL) || (frame->if_eflags & PSL_VM)) {
808 * Interrupt is essentially a trap, so we can afford to call
809 * the SIGFPE handler (if any) as soon as the interrupt
812 * XXX little or nothing is gained from this, and plenty is
813 * lost - the interrupt frame has to contain the trap frame
814 * (this is otherwise only necessary for the rescheduling trap
815 * in doreti, and the frame for that could easily be set up
816 * just before it is used).
818 curproc->p_md.md_regs = INTR_TO_TRAPFRAME(frame);
820 * Encode the appropriate code for detailed information on
824 fpetable[(*exstat & ~control & 0x3f) | (*exstat & 0x40)];
825 trapsignal(curproc, SIGFPE, code);
828 * Nested interrupt. These losers occur when:
829 * o an IRQ13 is bogusly generated at a bogus time, e.g.:
830 * o immediately after an fnsave or frstor of an
832 * o a couple of 386 instructions after
833 * "fstpl _memvar" causes a stack overflow.
834 * These are especially nasty when combined with a
836 * o an IRQ13 occurs at the same time as another higher-
837 * priority interrupt.
839 * Treat them like a true async interrupt.
841 psignal(curproc, SIGFPE);
847 * Implement device not available (DNA) exception
849 * It would be better to switch FP context here (if curthread != npxthread)
850 * and not necessarily for every context switch, but it is too hard to
851 * access foreign pcb's.
860 if (mdcpu->gd_npxthread != NULL) {
861 printf("npxdna: npxthread = %p, curthread = %p\n",
862 mdcpu->gd_npxthread, curthread);
868 * Record new context early in case frstor causes an IRQ13.
870 mdcpu->gd_npxthread = curthread;
871 exstat = GET_FPU_EXSW_PTR(curthread);
874 * The following frstor may cause an IRQ13 when the state being
875 * restored has a pending error. The error will appear to have been
876 * triggered by the current (npx) user instruction even when that
877 * instruction is a no-wait instruction that should not trigger an
878 * error (e.g., fnclex). On at least one 486 system all of the
879 * no-wait instructions are broken the same as frstor, so our
880 * treatment does not amplify the breakage. On at least one
881 * 386/Cyrix 387 system, fnclex works correctly while frstor and
882 * fnsave are broken, so our treatment breaks fnclex if it is the
883 * first FPU instruction after a context switch.
885 fpurstor(curthread->td_savefpu);
892 * Wrapper for fnsave instruction to handle h/w bugs. If there is an error
893 * pending, then fnsave generates a bogus IRQ13 on some systems. Force
894 * any IRQ13 to be handled immediately, and then ignore it. This routine is
895 * often called at splhigh so it must not use many system services. In
896 * particular, it's much easier to install a special handler than to
897 * guarantee that it's safe to use npxintr() and its supporting code.
899 * WARNING! This call is made during a switch and the MP lock will be
900 * setup for the new target thread rather then the current thread, so we
901 * cannot do anything here that depends on the *_mplock() functions as
902 * we may trip over their assertions.
908 #if defined(SMP) || !defined(CPU_DISABLE_SSE)
914 mdcpu->gd_npxthread = NULL;
917 #else /* !SMP and CPU_DISABLE_SSE */
921 u_char old_icu1_mask;
922 u_char old_icu2_mask;
923 struct gate_descriptor save_idt_npxintr;
926 save_eflags = read_eflags();
928 old_icu1_mask = inb(IO_ICU1 + 1);
929 old_icu2_mask = inb(IO_ICU2 + 1);
930 save_idt_npxintr = idt[npx_intrno];
931 outb(IO_ICU1 + 1, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask));
932 outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8));
933 idt[npx_intrno] = npx_idt_probeintr;
939 mdcpu->gd_npxthread = NULL;
941 icu1_mask = inb(IO_ICU1 + 1); /* masks may have changed */
942 icu2_mask = inb(IO_ICU2 + 1);
944 (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask));
946 (icu2_mask & ~(npx0_imask >> 8))
947 | (old_icu2_mask & (npx0_imask >> 8)));
948 idt[npx_intrno] = save_idt_npxintr;
949 write_eflags(save_eflags); /* back to usual state */
959 #ifndef CPU_DISABLE_SSE
972 #ifndef CPU_DISABLE_SSE
980 static device_method_t npx_methods[] = {
981 /* Device interface */
982 DEVMETHOD(device_identify, npx_identify),
983 DEVMETHOD(device_probe, npx_probe),
984 DEVMETHOD(device_attach, npx_attach),
985 DEVMETHOD(device_detach, bus_generic_detach),
986 DEVMETHOD(device_shutdown, bus_generic_shutdown),
987 DEVMETHOD(device_suspend, bus_generic_suspend),
988 DEVMETHOD(device_resume, bus_generic_resume),
993 static driver_t npx_driver = {
999 static devclass_t npx_devclass;
1002 * We prefer to attach to the root nexus so that the usual case (exception 16)
1003 * doesn't describe the processor as being `on isa'.
1005 DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0);