1 /* $OpenBSD: if_nfe.c,v 1.63 2006/06/17 18:00:43 brad Exp $ */
2 /* $DragonFly: src/sys/dev/netif/nfe/if_nfe.c,v 1.26 2008/06/27 13:47:36 sephe Exp $ */
5 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
7 * This code is derived from software contributed to The DragonFly Project
8 * by Sepherosa Ziehau <sepherosa@gmail.com> and
9 * Matthew Dillon <dillon@apollo.backplane.com>
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
21 * 3. Neither the name of The DragonFly Project nor the names of its
22 * contributors may be used to endorse or promote products derived
23 * from this software without specific, prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
28 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
29 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
30 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
31 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
33 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
34 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
35 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr>
41 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org>
43 * Permission to use, copy, modify, and distribute this software for any
44 * purpose with or without fee is hereby granted, provided that the above
45 * copyright notice and this permission notice appear in all copies.
47 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
48 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
49 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
50 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
51 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
52 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
53 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
56 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */
58 #include "opt_polling.h"
59 #include "opt_ethernet.h"
61 #include <sys/param.h>
62 #include <sys/endian.h>
63 #include <sys/kernel.h>
65 #include <sys/interrupt.h>
68 #include <sys/serialize.h>
69 #include <sys/socket.h>
70 #include <sys/sockio.h>
71 #include <sys/sysctl.h>
73 #include <net/ethernet.h>
76 #include <net/if_arp.h>
77 #include <net/if_dl.h>
78 #include <net/if_media.h>
79 #include <net/ifq_var.h>
80 #include <net/if_types.h>
81 #include <net/if_var.h>
82 #include <net/vlan/if_vlan_var.h>
83 #include <net/vlan/if_vlan_ether.h>
85 #include <bus/pci/pcireg.h>
86 #include <bus/pci/pcivar.h>
87 #include <bus/pci/pcidevs.h>
89 #include <dev/netif/mii_layer/mii.h>
90 #include <dev/netif/mii_layer/miivar.h>
92 #include "miibus_if.h"
94 #include <dev/netif/nfe/if_nfereg.h>
95 #include <dev/netif/nfe/if_nfevar.h>
98 #define NFE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
100 static int nfe_probe(device_t);
101 static int nfe_attach(device_t);
102 static int nfe_detach(device_t);
103 static void nfe_shutdown(device_t);
104 static int nfe_resume(device_t);
105 static int nfe_suspend(device_t);
107 static int nfe_miibus_readreg(device_t, int, int);
108 static void nfe_miibus_writereg(device_t, int, int, int);
109 static void nfe_miibus_statchg(device_t);
111 #ifdef DEVICE_POLLING
112 static void nfe_poll(struct ifnet *, enum poll_cmd, int);
114 static void nfe_intr(void *);
115 static int nfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
116 static void nfe_rxeof(struct nfe_softc *);
117 static void nfe_txeof(struct nfe_softc *);
118 static int nfe_encap(struct nfe_softc *, struct nfe_tx_ring *,
120 static void nfe_start(struct ifnet *);
121 static void nfe_watchdog(struct ifnet *);
122 static void nfe_init(void *);
123 static void nfe_stop(struct nfe_softc *);
124 static struct nfe_jbuf *nfe_jalloc(struct nfe_softc *);
125 static void nfe_jfree(void *);
126 static void nfe_jref(void *);
127 static int nfe_jpool_alloc(struct nfe_softc *, struct nfe_rx_ring *);
128 static void nfe_jpool_free(struct nfe_softc *, struct nfe_rx_ring *);
129 static int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
130 static void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
131 static int nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
132 static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
133 static int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
134 static void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
135 static int nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
136 static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
137 static int nfe_ifmedia_upd(struct ifnet *);
138 static void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
139 static void nfe_setmulti(struct nfe_softc *);
140 static void nfe_get_macaddr(struct nfe_softc *, uint8_t *);
141 static void nfe_set_macaddr(struct nfe_softc *, const uint8_t *);
142 static void nfe_tick(void *);
143 static void nfe_ring_dma_addr(void *, bus_dma_segment_t *, int, int);
144 static void nfe_buf_dma_addr(void *, bus_dma_segment_t *, int, bus_size_t,
146 static void nfe_set_paddr_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
148 static void nfe_set_ready_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
150 static int nfe_newbuf_std(struct nfe_softc *, struct nfe_rx_ring *, int,
152 static int nfe_newbuf_jumbo(struct nfe_softc *, struct nfe_rx_ring *, int,
155 static int nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS);
160 static int nfe_debug = 0;
161 static int nfe_rx_ring_count = NFE_RX_RING_DEF_COUNT;
162 static int nfe_imtime = -1;
164 TUNABLE_INT("hw.nfe.rx_ring_count", &nfe_rx_ring_count);
165 TUNABLE_INT("hw.nfe.imtime", &nfe_imtime);
166 TUNABLE_INT("hw.nfe.debug", &nfe_debug);
168 #define DPRINTF(sc, fmt, ...) do { \
169 if ((sc)->sc_debug) { \
170 if_printf(&(sc)->arpcom.ac_if, \
175 #define DPRINTFN(sc, lv, fmt, ...) do { \
176 if ((sc)->sc_debug >= (lv)) { \
177 if_printf(&(sc)->arpcom.ac_if, \
182 #else /* !NFE_DEBUG */
184 #define DPRINTF(sc, fmt, ...)
185 #define DPRINTFN(sc, lv, fmt, ...)
187 #endif /* NFE_DEBUG */
191 bus_dma_segment_t *segs;
194 static const struct nfe_dev {
199 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN,
200 "NVIDIA nForce Fast Ethernet" },
202 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN,
203 "NVIDIA nForce2 Fast Ethernet" },
205 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1,
206 "NVIDIA nForce3 Gigabit Ethernet" },
208 /* XXX TGEN the next chip can also be found in the nForce2 Ultra 400Gb
209 chipset, and possibly also the 400R; it might be both nForce2- and
210 nForce3-based boards can use the same MCPs (= southbridges) */
211 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2,
212 "NVIDIA nForce3 Gigabit Ethernet" },
214 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3,
215 "NVIDIA nForce3 Gigabit Ethernet" },
217 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4,
218 "NVIDIA nForce3 Gigabit Ethernet" },
220 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5,
221 "NVIDIA nForce3 Gigabit Ethernet" },
223 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1,
224 "NVIDIA CK804 Gigabit Ethernet" },
226 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2,
227 "NVIDIA CK804 Gigabit Ethernet" },
229 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1,
230 "NVIDIA MCP04 Gigabit Ethernet" },
232 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2,
233 "NVIDIA MCP04 Gigabit Ethernet" },
235 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1,
236 "NVIDIA MCP51 Gigabit Ethernet" },
238 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2,
239 "NVIDIA MCP51 Gigabit Ethernet" },
241 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1,
242 "NVIDIA MCP55 Gigabit Ethernet" },
244 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2,
245 "NVIDIA MCP55 Gigabit Ethernet" },
247 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1,
248 "NVIDIA MCP61 Gigabit Ethernet" },
250 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2,
251 "NVIDIA MCP61 Gigabit Ethernet" },
253 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3,
254 "NVIDIA MCP61 Gigabit Ethernet" },
256 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4,
257 "NVIDIA MCP61 Gigabit Ethernet" },
259 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1,
260 "NVIDIA MCP65 Gigabit Ethernet" },
262 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2,
263 "NVIDIA MCP65 Gigabit Ethernet" },
265 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3,
266 "NVIDIA MCP65 Gigabit Ethernet" },
268 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4,
269 "NVIDIA MCP65 Gigabit Ethernet" },
271 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1,
272 "NVIDIA MCP67 Gigabit Ethernet" },
274 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2,
275 "NVIDIA MCP67 Gigabit Ethernet" },
277 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3,
278 "NVIDIA MCP67 Gigabit Ethernet" },
280 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4,
281 "NVIDIA MCP67 Gigabit Ethernet" },
283 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1,
284 "NVIDIA MCP73 Gigabit Ethernet" },
286 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2,
287 "NVIDIA MCP73 Gigabit Ethernet" },
289 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3,
290 "NVIDIA MCP73 Gigabit Ethernet" },
292 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4,
293 "NVIDIA MCP73 Gigabit Ethernet" },
295 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1,
296 "NVIDIA MCP77 Gigabit Ethernet" },
298 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2,
299 "NVIDIA MCP77 Gigabit Ethernet" },
301 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3,
302 "NVIDIA MCP77 Gigabit Ethernet" },
304 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4,
305 "NVIDIA MCP77 Gigabit Ethernet" },
307 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1,
308 "NVIDIA MCP79 Gigabit Ethernet" },
310 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2,
311 "NVIDIA MCP79 Gigabit Ethernet" },
313 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3,
314 "NVIDIA MCP79 Gigabit Ethernet" },
316 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4,
317 "NVIDIA MCP79 Gigabit Ethernet" },
322 static device_method_t nfe_methods[] = {
323 /* Device interface */
324 DEVMETHOD(device_probe, nfe_probe),
325 DEVMETHOD(device_attach, nfe_attach),
326 DEVMETHOD(device_detach, nfe_detach),
327 DEVMETHOD(device_suspend, nfe_suspend),
328 DEVMETHOD(device_resume, nfe_resume),
329 DEVMETHOD(device_shutdown, nfe_shutdown),
332 DEVMETHOD(bus_print_child, bus_generic_print_child),
333 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
336 DEVMETHOD(miibus_readreg, nfe_miibus_readreg),
337 DEVMETHOD(miibus_writereg, nfe_miibus_writereg),
338 DEVMETHOD(miibus_statchg, nfe_miibus_statchg),
343 static driver_t nfe_driver = {
346 sizeof(struct nfe_softc)
349 static devclass_t nfe_devclass;
351 DECLARE_DUMMY_MODULE(if_nfe);
352 MODULE_DEPEND(if_nfe, miibus, 1, 1, 1);
353 DRIVER_MODULE(if_nfe, pci, nfe_driver, nfe_devclass, 0, 0);
354 DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, 0, 0);
357 nfe_probe(device_t dev)
359 const struct nfe_dev *n;
362 vid = pci_get_vendor(dev);
363 did = pci_get_device(dev);
364 for (n = nfe_devices; n->desc != NULL; ++n) {
365 if (vid == n->vid && did == n->did) {
366 struct nfe_softc *sc = device_get_softc(dev);
369 case PCI_PRODUCT_NVIDIA_NFORCE_LAN:
370 case PCI_PRODUCT_NVIDIA_NFORCE2_LAN:
371 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN1:
372 sc->sc_flags = NFE_NO_PWRCTL;
374 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2:
375 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3:
376 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4:
377 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5:
378 sc->sc_flags = NFE_JUMBO_SUP |
382 case PCI_PRODUCT_NVIDIA_MCP51_LAN1:
383 case PCI_PRODUCT_NVIDIA_MCP51_LAN2:
384 case PCI_PRODUCT_NVIDIA_MCP61_LAN1:
385 case PCI_PRODUCT_NVIDIA_MCP61_LAN2:
386 case PCI_PRODUCT_NVIDIA_MCP61_LAN3:
387 case PCI_PRODUCT_NVIDIA_MCP61_LAN4:
388 case PCI_PRODUCT_NVIDIA_MCP67_LAN1:
389 case PCI_PRODUCT_NVIDIA_MCP67_LAN2:
390 case PCI_PRODUCT_NVIDIA_MCP67_LAN3:
391 case PCI_PRODUCT_NVIDIA_MCP67_LAN4:
392 case PCI_PRODUCT_NVIDIA_MCP73_LAN1:
393 case PCI_PRODUCT_NVIDIA_MCP73_LAN2:
394 case PCI_PRODUCT_NVIDIA_MCP73_LAN3:
395 case PCI_PRODUCT_NVIDIA_MCP73_LAN4:
396 sc->sc_flags = NFE_40BIT_ADDR;
398 case PCI_PRODUCT_NVIDIA_CK804_LAN1:
399 case PCI_PRODUCT_NVIDIA_CK804_LAN2:
400 case PCI_PRODUCT_NVIDIA_MCP04_LAN1:
401 case PCI_PRODUCT_NVIDIA_MCP04_LAN2:
402 sc->sc_flags = NFE_JUMBO_SUP |
407 case PCI_PRODUCT_NVIDIA_MCP65_LAN1:
408 case PCI_PRODUCT_NVIDIA_MCP65_LAN2:
409 case PCI_PRODUCT_NVIDIA_MCP65_LAN3:
410 case PCI_PRODUCT_NVIDIA_MCP65_LAN4:
411 sc->sc_flags = NFE_JUMBO_SUP |
414 case PCI_PRODUCT_NVIDIA_MCP55_LAN1:
415 case PCI_PRODUCT_NVIDIA_MCP55_LAN2:
416 sc->sc_flags = NFE_JUMBO_SUP |
421 case PCI_PRODUCT_NVIDIA_MCP77_LAN1:
422 case PCI_PRODUCT_NVIDIA_MCP77_LAN2:
423 case PCI_PRODUCT_NVIDIA_MCP77_LAN3:
424 case PCI_PRODUCT_NVIDIA_MCP77_LAN4:
425 case PCI_PRODUCT_NVIDIA_MCP79_LAN1:
426 case PCI_PRODUCT_NVIDIA_MCP79_LAN2:
427 case PCI_PRODUCT_NVIDIA_MCP79_LAN3:
428 case PCI_PRODUCT_NVIDIA_MCP79_LAN4:
429 sc->sc_flags = NFE_40BIT_ADDR |
434 device_set_desc(dev, n->desc);
435 device_set_async_attach(dev, TRUE);
443 nfe_attach(device_t dev)
445 struct nfe_softc *sc = device_get_softc(dev);
446 struct ifnet *ifp = &sc->arpcom.ac_if;
447 uint8_t eaddr[ETHER_ADDR_LEN];
450 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
451 lwkt_serialize_init(&sc->sc_jbuf_serializer);
454 * Initialize sysctl variables
456 sc->sc_imtime = nfe_imtime;
457 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
458 sc->sc_rx_ring_count = nfe_rx_ring_count;
459 sc->sc_debug = nfe_debug;
461 sc->sc_mem_rid = PCIR_BAR(0);
464 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
467 mem = pci_read_config(dev, sc->sc_mem_rid, 4);
468 irq = pci_read_config(dev, PCIR_INTLINE, 4);
470 device_printf(dev, "chip is in D%d power mode "
471 "-- setting to D0\n", pci_get_powerstate(dev));
473 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
475 pci_write_config(dev, sc->sc_mem_rid, mem, 4);
476 pci_write_config(dev, PCIR_INTLINE, irq, 4);
478 #endif /* !BURN_BRIDGE */
480 /* Enable bus mastering */
481 pci_enable_busmaster(dev);
483 /* Allocate IO memory */
484 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
485 &sc->sc_mem_rid, RF_ACTIVE);
486 if (sc->sc_mem_res == NULL) {
487 device_printf(dev, "cound not allocate io memory\n");
490 sc->sc_memh = rman_get_bushandle(sc->sc_mem_res);
491 sc->sc_memt = rman_get_bustag(sc->sc_mem_res);
495 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
497 RF_SHAREABLE | RF_ACTIVE);
498 if (sc->sc_irq_res == NULL) {
499 device_printf(dev, "could not allocate irq\n");
505 NFE_WRITE(sc, NFE_WOL_CTL, 0);
507 nfe_get_macaddr(sc, eaddr);
510 * Allocate Tx and Rx rings.
512 error = nfe_alloc_tx_ring(sc, &sc->txq);
514 device_printf(dev, "could not allocate Tx ring\n");
518 error = nfe_alloc_rx_ring(sc, &sc->rxq);
520 device_printf(dev, "could not allocate Rx ring\n");
527 sysctl_ctx_init(&sc->sc_sysctl_ctx);
528 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
529 SYSCTL_STATIC_CHILDREN(_hw),
531 device_get_nameunit(dev),
533 if (sc->sc_sysctl_tree == NULL) {
534 device_printf(dev, "can't add sysctl node\n");
538 SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
539 SYSCTL_CHILDREN(sc->sc_sysctl_tree),
540 OID_AUTO, "imtimer", CTLTYPE_INT | CTLFLAG_RW,
541 sc, 0, nfe_sysctl_imtime, "I",
542 "Interrupt moderation time (usec). "
543 "-1 to disable interrupt moderation.");
544 SYSCTL_ADD_INT(NULL, SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
545 "rx_ring_count", CTLFLAG_RD, &sc->sc_rx_ring_count,
547 SYSCTL_ADD_INT(NULL, SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
548 "debug", CTLFLAG_RW, &sc->sc_debug,
549 0, "control debugging printfs");
551 error = mii_phy_probe(dev, &sc->sc_miibus, nfe_ifmedia_upd,
554 device_printf(dev, "MII without any phy\n");
559 ifp->if_mtu = ETHERMTU;
560 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
561 ifp->if_ioctl = nfe_ioctl;
562 ifp->if_start = nfe_start;
563 #ifdef DEVICE_POLLING
564 ifp->if_poll = nfe_poll;
566 ifp->if_watchdog = nfe_watchdog;
567 ifp->if_init = nfe_init;
568 ifq_set_maxlen(&ifp->if_snd, NFE_IFQ_MAXLEN);
569 ifq_set_ready(&ifp->if_snd);
571 ifp->if_capabilities = IFCAP_VLAN_MTU;
573 if (sc->sc_flags & NFE_HW_VLAN)
574 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
577 if (sc->sc_flags & NFE_HW_CSUM) {
578 ifp->if_capabilities |= IFCAP_HWCSUM;
579 ifp->if_hwassist = NFE_CSUM_FEATURES;
582 sc->sc_flags &= ~NFE_HW_CSUM;
584 ifp->if_capenable = ifp->if_capabilities;
586 callout_init(&sc->sc_tick_ch);
588 ether_ifattach(ifp, eaddr, NULL);
590 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, nfe_intr, sc,
591 &sc->sc_ih, ifp->if_serializer);
593 device_printf(dev, "could not setup intr\n");
598 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->sc_irq_res));
599 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
608 nfe_detach(device_t dev)
610 struct nfe_softc *sc = device_get_softc(dev);
612 if (device_is_attached(dev)) {
613 struct ifnet *ifp = &sc->arpcom.ac_if;
615 lwkt_serialize_enter(ifp->if_serializer);
617 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_ih);
618 lwkt_serialize_exit(ifp->if_serializer);
623 if (sc->sc_miibus != NULL)
624 device_delete_child(dev, sc->sc_miibus);
625 bus_generic_detach(dev);
627 if (sc->sc_sysctl_tree != NULL)
628 sysctl_ctx_free(&sc->sc_sysctl_ctx);
630 if (sc->sc_irq_res != NULL) {
631 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
635 if (sc->sc_mem_res != NULL) {
636 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
640 nfe_free_tx_ring(sc, &sc->txq);
641 nfe_free_rx_ring(sc, &sc->rxq);
647 nfe_shutdown(device_t dev)
649 struct nfe_softc *sc = device_get_softc(dev);
650 struct ifnet *ifp = &sc->arpcom.ac_if;
652 lwkt_serialize_enter(ifp->if_serializer);
654 lwkt_serialize_exit(ifp->if_serializer);
658 nfe_suspend(device_t dev)
660 struct nfe_softc *sc = device_get_softc(dev);
661 struct ifnet *ifp = &sc->arpcom.ac_if;
663 lwkt_serialize_enter(ifp->if_serializer);
665 lwkt_serialize_exit(ifp->if_serializer);
671 nfe_resume(device_t dev)
673 struct nfe_softc *sc = device_get_softc(dev);
674 struct ifnet *ifp = &sc->arpcom.ac_if;
676 lwkt_serialize_enter(ifp->if_serializer);
677 if (ifp->if_flags & IFF_UP)
679 lwkt_serialize_exit(ifp->if_serializer);
685 nfe_miibus_statchg(device_t dev)
687 struct nfe_softc *sc = device_get_softc(dev);
688 struct mii_data *mii = device_get_softc(sc->sc_miibus);
689 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET;
691 phy = NFE_READ(sc, NFE_PHY_IFACE);
692 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T);
694 seed = NFE_READ(sc, NFE_RNDSEED);
695 seed &= ~NFE_SEED_MASK;
697 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) {
698 phy |= NFE_PHY_HDX; /* half-duplex */
699 misc |= NFE_MISC1_HDX;
702 switch (IFM_SUBTYPE(mii->mii_media_active)) {
703 case IFM_1000_T: /* full-duplex only */
704 link |= NFE_MEDIA_1000T;
705 seed |= NFE_SEED_1000T;
706 phy |= NFE_PHY_1000T;
709 link |= NFE_MEDIA_100TX;
710 seed |= NFE_SEED_100TX;
711 phy |= NFE_PHY_100TX;
714 link |= NFE_MEDIA_10T;
715 seed |= NFE_SEED_10T;
719 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */
721 NFE_WRITE(sc, NFE_PHY_IFACE, phy);
722 NFE_WRITE(sc, NFE_MISC1, misc);
723 NFE_WRITE(sc, NFE_LINKSPEED, link);
727 nfe_miibus_readreg(device_t dev, int phy, int reg)
729 struct nfe_softc *sc = device_get_softc(dev);
733 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
735 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
736 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
740 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);
742 for (ntries = 0; ntries < 1000; ntries++) {
744 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
747 if (ntries == 1000) {
748 DPRINTFN(sc, 2, "timeout waiting for PHY %s\n", "");
752 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) {
753 DPRINTFN(sc, 2, "could not read PHY %s\n", "");
757 val = NFE_READ(sc, NFE_PHY_DATA);
758 if (val != 0xffffffff && val != 0)
759 sc->mii_phyaddr = phy;
761 DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val);
767 nfe_miibus_writereg(device_t dev, int phy, int reg, int val)
769 struct nfe_softc *sc = device_get_softc(dev);
773 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
775 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
776 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
780 NFE_WRITE(sc, NFE_PHY_DATA, val);
781 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;
782 NFE_WRITE(sc, NFE_PHY_CTL, ctl);
784 for (ntries = 0; ntries < 1000; ntries++) {
786 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
792 DPRINTFN(sc, 2, "could not write to PHY %s\n", "");
796 #ifdef DEVICE_POLLING
799 nfe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
801 struct nfe_softc *sc = ifp->if_softc;
803 ASSERT_SERIALIZED(ifp->if_serializer);
807 /* Disable interrupts */
808 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
810 case POLL_DEREGISTER:
811 /* enable interrupts */
812 NFE_WRITE(sc, NFE_IRQ_MASK, sc->sc_irq_enable);
814 case POLL_AND_CHECK_STATUS:
817 if (ifp->if_flags & IFF_RUNNING) {
830 struct nfe_softc *sc = arg;
831 struct ifnet *ifp = &sc->arpcom.ac_if;
834 r = NFE_READ(sc, NFE_IRQ_STATUS);
836 return; /* not for us */
837 NFE_WRITE(sc, NFE_IRQ_STATUS, r);
839 DPRINTFN(sc, 5, "%s: interrupt register %x\n", __func__, r);
841 if (r & NFE_IRQ_LINK) {
842 NFE_READ(sc, NFE_PHY_STATUS);
843 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
844 DPRINTF(sc, "link state changed %s\n", "");
847 if (ifp->if_flags & IFF_RUNNING) {
857 nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
859 struct nfe_softc *sc = ifp->if_softc;
860 struct ifreq *ifr = (struct ifreq *)data;
861 struct mii_data *mii;
866 if (((sc->sc_flags & NFE_JUMBO_SUP) &&
867 ifr->ifr_mtu > NFE_JUMBO_MTU) ||
868 ((sc->sc_flags & NFE_JUMBO_SUP) == 0 &&
869 ifr->ifr_mtu > ETHERMTU)) {
871 } else if (ifp->if_mtu != ifr->ifr_mtu) {
872 ifp->if_mtu = ifr->ifr_mtu;
877 if (ifp->if_flags & IFF_UP) {
879 * If only the PROMISC or ALLMULTI flag changes, then
880 * don't do a full re-init of the chip, just update
883 if ((ifp->if_flags & IFF_RUNNING) &&
884 ((ifp->if_flags ^ sc->sc_if_flags) &
885 (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
888 if (!(ifp->if_flags & IFF_RUNNING))
892 if (ifp->if_flags & IFF_RUNNING)
895 sc->sc_if_flags = ifp->if_flags;
899 if (ifp->if_flags & IFF_RUNNING)
904 mii = device_get_softc(sc->sc_miibus);
905 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
908 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) & IFCAP_HWCSUM;
909 if (mask && (ifp->if_capabilities & IFCAP_HWCSUM)) {
910 ifp->if_capenable ^= mask;
911 if (IFCAP_TXCSUM & ifp->if_capenable)
912 ifp->if_hwassist = NFE_CSUM_FEATURES;
914 ifp->if_hwassist = 0;
916 if (ifp->if_flags & IFF_RUNNING)
921 error = ether_ioctl(ifp, cmd, data);
928 nfe_rxeof(struct nfe_softc *sc)
930 struct ifnet *ifp = &sc->arpcom.ac_if;
931 struct nfe_rx_ring *ring = &sc->rxq;
933 #ifdef ETHER_INPUT_CHAIN
934 struct mbuf_chain chain[MAXCPU];
938 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
940 #ifdef ETHER_INPUT_CHAIN
941 ether_input_chain_init(chain);
945 struct nfe_rx_data *data = &ring->data[ring->cur];
950 if (sc->sc_flags & NFE_40BIT_ADDR) {
951 struct nfe_desc64 *desc64 = &ring->desc64[ring->cur];
953 flags = le16toh(desc64->flags);
954 len = le16toh(desc64->length) & 0x3fff;
956 struct nfe_desc32 *desc32 = &ring->desc32[ring->cur];
958 flags = le16toh(desc32->flags);
959 len = le16toh(desc32->length) & 0x3fff;
962 if (flags & NFE_RX_READY)
967 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
968 if (!(flags & NFE_RX_VALID_V1))
971 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) {
972 flags &= ~NFE_RX_ERROR;
973 len--; /* fix buffer length */
976 if (!(flags & NFE_RX_VALID_V2))
979 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) {
980 flags &= ~NFE_RX_ERROR;
981 len--; /* fix buffer length */
985 if (flags & NFE_RX_ERROR) {
992 if (sc->sc_flags & NFE_USE_JUMBO)
993 error = nfe_newbuf_jumbo(sc, ring, ring->cur, 0);
995 error = nfe_newbuf_std(sc, ring, ring->cur, 0);
1002 m->m_pkthdr.len = m->m_len = len;
1003 m->m_pkthdr.rcvif = ifp;
1005 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
1006 (flags & NFE_RX_CSUMOK)) {
1007 if (flags & NFE_RX_IP_CSUMOK_V2) {
1008 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1013 (NFE_RX_UDP_CSUMOK_V2 | NFE_RX_TCP_CSUMOK_V2)) {
1014 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1016 CSUM_FRAG_NOT_CHECKED;
1017 m->m_pkthdr.csum_data = 0xffff;
1022 #ifdef ETHER_INPUT_CHAIN
1024 ether_input_chain2(ifp, m, chain);
1026 ether_input_chain(ifp, m, chain);
1029 ifp->if_input(ifp, m);
1032 nfe_set_ready_rxdesc(sc, ring, ring->cur);
1033 sc->rxq.cur = (sc->rxq.cur + 1) % sc->sc_rx_ring_count;
1037 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1038 #ifdef ETHER_INPUT_CHAIN
1039 ether_input_dispatch(chain);
1045 nfe_txeof(struct nfe_softc *sc)
1047 struct ifnet *ifp = &sc->arpcom.ac_if;
1048 struct nfe_tx_ring *ring = &sc->txq;
1049 struct nfe_tx_data *data = NULL;
1051 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
1052 while (ring->next != ring->cur) {
1055 if (sc->sc_flags & NFE_40BIT_ADDR)
1056 flags = le16toh(ring->desc64[ring->next].flags);
1058 flags = le16toh(ring->desc32[ring->next].flags);
1060 if (flags & NFE_TX_VALID)
1063 data = &ring->data[ring->next];
1065 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
1066 if (!(flags & NFE_TX_LASTFRAG_V1) && data->m == NULL)
1069 if ((flags & NFE_TX_ERROR_V1) != 0) {
1070 if_printf(ifp, "tx v1 error 0x%4b\n", flags,
1077 if (!(flags & NFE_TX_LASTFRAG_V2) && data->m == NULL)
1080 if ((flags & NFE_TX_ERROR_V2) != 0) {
1081 if_printf(ifp, "tx v2 error 0x%4b\n", flags,
1089 if (data->m == NULL) { /* should not get there */
1091 "last fragment bit w/o associated mbuf!\n");
1095 /* last fragment of the mbuf chain transmitted */
1096 bus_dmamap_sync(ring->data_tag, data->map,
1097 BUS_DMASYNC_POSTWRITE);
1098 bus_dmamap_unload(ring->data_tag, data->map);
1105 KKASSERT(ring->queued >= 0);
1106 ring->next = (ring->next + 1) % NFE_TX_RING_COUNT;
1109 if (data != NULL) { /* at least one slot freed */
1110 ifp->if_flags &= ~IFF_OACTIVE;
1116 nfe_encap(struct nfe_softc *sc, struct nfe_tx_ring *ring, struct mbuf *m0)
1118 struct nfe_dma_ctx ctx;
1119 bus_dma_segment_t segs[NFE_MAX_SCATTER];
1120 struct nfe_tx_data *data, *data_map;
1122 struct nfe_desc64 *desc64 = NULL;
1123 struct nfe_desc32 *desc32 = NULL;
1128 data = &ring->data[ring->cur];
1130 data_map = data; /* Remember who owns the DMA map */
1132 ctx.nsegs = NFE_MAX_SCATTER;
1134 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
1135 nfe_buf_dma_addr, &ctx, BUS_DMA_NOWAIT);
1136 if (error && error != EFBIG) {
1137 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
1141 if (error) { /* error == EFBIG */
1144 m_new = m_defrag(m0, MB_DONTWAIT);
1145 if (m_new == NULL) {
1146 if_printf(&sc->arpcom.ac_if,
1147 "could not defrag TX mbuf\n");
1154 ctx.nsegs = NFE_MAX_SCATTER;
1156 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
1157 nfe_buf_dma_addr, &ctx,
1160 if_printf(&sc->arpcom.ac_if,
1161 "could not map defraged TX mbuf\n");
1168 if (ring->queued + ctx.nsegs >= NFE_TX_RING_COUNT - 1) {
1169 bus_dmamap_unload(ring->data_tag, map);
1174 /* setup h/w VLAN tagging */
1175 if (m0->m_flags & M_VLANTAG)
1176 vtag = m0->m_pkthdr.ether_vlantag;
1178 if (sc->arpcom.ac_if.if_capenable & IFCAP_TXCSUM) {
1179 if (m0->m_pkthdr.csum_flags & CSUM_IP)
1180 flags |= NFE_TX_IP_CSUM;
1181 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
1182 flags |= NFE_TX_TCP_CSUM;
1186 * XXX urm. somebody is unaware of how hardware works. You
1187 * absolutely CANNOT set NFE_TX_VALID on the next descriptor in
1188 * the ring until the entire chain is actually *VALID*. Otherwise
1189 * the hardware may encounter a partially initialized chain that
1190 * is marked as being ready to go when it in fact is not ready to
1194 for (i = 0; i < ctx.nsegs; i++) {
1195 j = (ring->cur + i) % NFE_TX_RING_COUNT;
1196 data = &ring->data[j];
1198 if (sc->sc_flags & NFE_40BIT_ADDR) {
1199 desc64 = &ring->desc64[j];
1200 #if defined(__LP64__)
1201 desc64->physaddr[0] =
1202 htole32(segs[i].ds_addr >> 32);
1204 desc64->physaddr[1] =
1205 htole32(segs[i].ds_addr & 0xffffffff);
1206 desc64->length = htole16(segs[i].ds_len - 1);
1207 desc64->vtag = htole32(vtag);
1208 desc64->flags = htole16(flags);
1210 desc32 = &ring->desc32[j];
1211 desc32->physaddr = htole32(segs[i].ds_addr);
1212 desc32->length = htole16(segs[i].ds_len - 1);
1213 desc32->flags = htole16(flags);
1216 /* csum flags and vtag belong to the first fragment only */
1217 flags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_CSUM);
1221 KKASSERT(ring->queued <= NFE_TX_RING_COUNT);
1224 /* the whole mbuf chain has been DMA mapped, fix last descriptor */
1225 if (sc->sc_flags & NFE_40BIT_ADDR) {
1226 desc64->flags |= htole16(NFE_TX_LASTFRAG_V2);
1228 if (sc->sc_flags & NFE_JUMBO_SUP)
1229 flags = NFE_TX_LASTFRAG_V2;
1231 flags = NFE_TX_LASTFRAG_V1;
1232 desc32->flags |= htole16(flags);
1236 * Set NFE_TX_VALID backwards so the hardware doesn't see the
1237 * whole mess until the first descriptor in the map is flagged.
1239 for (i = ctx.nsegs - 1; i >= 0; --i) {
1240 j = (ring->cur + i) % NFE_TX_RING_COUNT;
1241 if (sc->sc_flags & NFE_40BIT_ADDR) {
1242 desc64 = &ring->desc64[j];
1243 desc64->flags |= htole16(NFE_TX_VALID);
1245 desc32 = &ring->desc32[j];
1246 desc32->flags |= htole16(NFE_TX_VALID);
1249 ring->cur = (ring->cur + ctx.nsegs) % NFE_TX_RING_COUNT;
1251 /* Exchange DMA map */
1252 data_map->map = data->map;
1256 bus_dmamap_sync(ring->data_tag, map, BUS_DMASYNC_PREWRITE);
1264 nfe_start(struct ifnet *ifp)
1266 struct nfe_softc *sc = ifp->if_softc;
1267 struct nfe_tx_ring *ring = &sc->txq;
1271 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
1275 m0 = ifq_dequeue(&ifp->if_snd, NULL);
1279 ETHER_BPF_MTAP(ifp, m0);
1281 if (nfe_encap(sc, ring, m0) != 0) {
1282 ifp->if_flags |= IFF_OACTIVE;
1289 * `m0' may be freed in nfe_encap(), so
1290 * it should not be touched any more.
1293 if (count == 0) /* nothing sent */
1296 /* Sync TX descriptor ring */
1297 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1300 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl);
1303 * Set a timeout in case the chip goes out to lunch.
1309 nfe_watchdog(struct ifnet *ifp)
1311 struct nfe_softc *sc = ifp->if_softc;
1313 if (ifp->if_flags & IFF_RUNNING) {
1314 if_printf(ifp, "watchdog timeout - lost interrupt recovered\n");
1319 if_printf(ifp, "watchdog timeout\n");
1321 nfe_init(ifp->if_softc);
1329 struct nfe_softc *sc = xsc;
1330 struct ifnet *ifp = &sc->arpcom.ac_if;
1338 * Switching between jumbo frames and normal frames should
1339 * be done _after_ nfe_stop() but _before_ nfe_init_rx_ring().
1341 if (ifp->if_mtu > ETHERMTU) {
1342 sc->sc_flags |= NFE_USE_JUMBO;
1343 sc->rxq.bufsz = NFE_JBYTES;
1345 if_printf(ifp, "use jumbo frames\n");
1347 sc->sc_flags &= ~NFE_USE_JUMBO;
1348 sc->rxq.bufsz = MCLBYTES;
1350 if_printf(ifp, "use non-jumbo frames\n");
1353 error = nfe_init_tx_ring(sc, &sc->txq);
1359 error = nfe_init_rx_ring(sc, &sc->rxq);
1365 NFE_WRITE(sc, NFE_TX_POLL, 0);
1366 NFE_WRITE(sc, NFE_STATUS, 0);
1368 sc->rxtxctl = NFE_RXTX_BIT2;
1369 if (sc->sc_flags & NFE_40BIT_ADDR)
1370 sc->rxtxctl |= NFE_RXTX_V3MAGIC;
1371 else if (sc->sc_flags & NFE_JUMBO_SUP)
1372 sc->rxtxctl |= NFE_RXTX_V2MAGIC;
1374 if (ifp->if_capenable & IFCAP_RXCSUM)
1375 sc->rxtxctl |= NFE_RXTX_RXCSUM;
1378 * Although the adapter is capable of stripping VLAN tags from received
1379 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on
1380 * purpose. This will be done in software by our network stack.
1382 if (sc->sc_flags & NFE_HW_VLAN)
1383 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT;
1385 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl);
1387 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1389 if (sc->sc_flags & NFE_HW_VLAN)
1390 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE);
1392 NFE_WRITE(sc, NFE_SETUP_R6, 0);
1394 /* set MAC address */
1395 nfe_set_macaddr(sc, sc->arpcom.ac_enaddr);
1397 /* tell MAC where rings are in memory */
1399 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32);
1401 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff);
1403 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32);
1405 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff);
1407 NFE_WRITE(sc, NFE_RING_SIZE,
1408 (sc->sc_rx_ring_count - 1) << 16 |
1409 (NFE_TX_RING_COUNT - 1));
1411 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz);
1413 /* force MAC to wakeup */
1414 tmp = NFE_READ(sc, NFE_PWR_STATE);
1415 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP);
1417 tmp = NFE_READ(sc, NFE_PWR_STATE);
1418 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID);
1421 * NFE_IMTIMER generates a periodic interrupt via NFE_IRQ_TIMER.
1422 * It is unclear how wide the timer is. Base programming does
1423 * not seem to effect NFE_IRQ_TX_DONE or NFE_IRQ_RX_DONE so
1424 * we don't get any interrupt moderation. TX moderation is
1425 * possible by using the timer interrupt instead of TX_DONE.
1427 * It is unclear whether there are other bits that can be
1428 * set to make the NFE device actually do interrupt moderation
1431 * For now set a 128uS interval as a placemark, but don't use
1434 if (sc->sc_imtime < 0)
1435 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME_DEFAULT);
1437 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME(sc->sc_imtime));
1439 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC);
1440 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC);
1441 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC);
1443 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */
1444 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC);
1446 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC);
1448 sc->rxtxctl &= ~NFE_RXTX_BIT2;
1449 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1451 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl);
1456 nfe_ifmedia_upd(ifp);
1459 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START);
1462 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START);
1464 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1466 #ifdef DEVICE_POLLING
1467 if ((ifp->if_flags & IFF_POLLING) == 0)
1469 /* enable interrupts */
1470 NFE_WRITE(sc, NFE_IRQ_MASK, sc->sc_irq_enable);
1472 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
1474 ifp->if_flags |= IFF_RUNNING;
1475 ifp->if_flags &= ~IFF_OACTIVE;
1478 * If we had stuff in the tx ring before its all cleaned out now
1479 * so we are not going to get an interrupt, jump-start any pending
1486 nfe_stop(struct nfe_softc *sc)
1488 struct ifnet *ifp = &sc->arpcom.ac_if;
1490 callout_stop(&sc->sc_tick_ch);
1493 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1496 * Are NFE_TX_CTL and NFE_RX_CTL polled by the chip microcontroller
1497 * or do they directly reset/terminate the DMA hardware? Nobody
1502 * (1) Delay before zeroing out NFE_TX_CTL. This seems to help a
1503 * watchdog timeout that occurs after a stop/init sequence. I am
1504 * theorizing that a TX KICK occuring just prior to a reinit (e.g.
1505 * due to dhclient) is queueing an interrupt to the microcontroller
1506 * which gets delayed until after we clear the control registers
1507 * down below, resulting in mass confusion. TX KICK is clearly
1508 * hardware aided whereas the other bits in the control register
1509 * are more likely to be polled by the microcontroller.
1511 * (2) Delay after zeroing out TX and RX CTL registers, under the
1512 * assumption that primary DMA is initiated and terminated by
1513 * the microcontroller and not hardware (and anyway, one can hardly
1514 * expect the DMA engine to just instantly stop!). We don't want
1515 * to rip the rings out from under it before it has had a chance to
1521 NFE_WRITE(sc, NFE_TX_CTL, 0);
1524 NFE_WRITE(sc, NFE_RX_CTL, 0);
1526 /* Disable interrupts */
1527 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
1531 /* Reset Tx and Rx rings */
1532 nfe_reset_tx_ring(sc, &sc->txq);
1533 nfe_reset_rx_ring(sc, &sc->rxq);
1537 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1539 int i, j, error, descsize;
1542 if (sc->sc_flags & NFE_40BIT_ADDR) {
1543 desc = (void **)&ring->desc64;
1544 descsize = sizeof(struct nfe_desc64);
1546 desc = (void **)&ring->desc32;
1547 descsize = sizeof(struct nfe_desc32);
1550 ring->jbuf = kmalloc(sizeof(struct nfe_jbuf) * NFE_JPOOL_COUNT,
1551 M_DEVBUF, M_WAITOK | M_ZERO);
1552 ring->data = kmalloc(sizeof(struct nfe_rx_data) * sc->sc_rx_ring_count,
1553 M_DEVBUF, M_WAITOK | M_ZERO);
1555 ring->bufsz = MCLBYTES;
1556 ring->cur = ring->next = 0;
1558 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1559 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1561 sc->sc_rx_ring_count * descsize, 1,
1562 sc->sc_rx_ring_count * descsize,
1565 if_printf(&sc->arpcom.ac_if,
1566 "could not create desc RX DMA tag\n");
1570 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1573 if_printf(&sc->arpcom.ac_if,
1574 "could not allocate RX desc DMA memory\n");
1575 bus_dma_tag_destroy(ring->tag);
1580 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1581 sc->sc_rx_ring_count * descsize,
1582 nfe_ring_dma_addr, &ring->physaddr,
1585 if_printf(&sc->arpcom.ac_if,
1586 "could not load RX desc DMA map\n");
1587 bus_dmamem_free(ring->tag, *desc, ring->map);
1588 bus_dma_tag_destroy(ring->tag);
1593 if (sc->sc_flags & NFE_JUMBO_SUP) {
1594 error = nfe_jpool_alloc(sc, ring);
1596 if_printf(&sc->arpcom.ac_if,
1597 "could not allocate jumbo frames\n");
1602 error = bus_dma_tag_create(NULL, 1, 0,
1603 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1605 MCLBYTES, 1, MCLBYTES,
1606 0, &ring->data_tag);
1608 if_printf(&sc->arpcom.ac_if,
1609 "could not create RX mbuf DMA tag\n");
1613 /* Create a spare RX mbuf DMA map */
1614 error = bus_dmamap_create(ring->data_tag, 0, &ring->data_tmpmap);
1616 if_printf(&sc->arpcom.ac_if,
1617 "could not create spare RX mbuf DMA map\n");
1618 bus_dma_tag_destroy(ring->data_tag);
1619 ring->data_tag = NULL;
1623 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1624 error = bus_dmamap_create(ring->data_tag, 0,
1625 &ring->data[i].map);
1627 if_printf(&sc->arpcom.ac_if,
1628 "could not create %dth RX mbuf DMA mapn", i);
1634 for (j = 0; j < i; ++j)
1635 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1636 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1637 bus_dma_tag_destroy(ring->data_tag);
1638 ring->data_tag = NULL;
1643 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1647 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1648 struct nfe_rx_data *data = &ring->data[i];
1650 if (data->m != NULL) {
1651 if ((sc->sc_flags & NFE_USE_JUMBO) == 0)
1652 bus_dmamap_unload(ring->data_tag, data->map);
1657 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1659 ring->cur = ring->next = 0;
1663 nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1667 for (i = 0; i < sc->sc_rx_ring_count; ++i) {
1670 /* XXX should use a function pointer */
1671 if (sc->sc_flags & NFE_USE_JUMBO)
1672 error = nfe_newbuf_jumbo(sc, ring, i, 1);
1674 error = nfe_newbuf_std(sc, ring, i, 1);
1676 if_printf(&sc->arpcom.ac_if,
1677 "could not allocate RX buffer\n");
1681 nfe_set_ready_rxdesc(sc, ring, i);
1683 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1689 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1691 if (ring->data_tag != NULL) {
1692 struct nfe_rx_data *data;
1695 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1696 data = &ring->data[i];
1698 if (data->m != NULL) {
1699 bus_dmamap_unload(ring->data_tag, data->map);
1702 bus_dmamap_destroy(ring->data_tag, data->map);
1704 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1705 bus_dma_tag_destroy(ring->data_tag);
1708 nfe_jpool_free(sc, ring);
1710 if (ring->jbuf != NULL)
1711 kfree(ring->jbuf, M_DEVBUF);
1712 if (ring->data != NULL)
1713 kfree(ring->data, M_DEVBUF);
1715 if (ring->tag != NULL) {
1718 if (sc->sc_flags & NFE_40BIT_ADDR)
1719 desc = ring->desc64;
1721 desc = ring->desc32;
1723 bus_dmamap_unload(ring->tag, ring->map);
1724 bus_dmamem_free(ring->tag, desc, ring->map);
1725 bus_dma_tag_destroy(ring->tag);
1729 static struct nfe_jbuf *
1730 nfe_jalloc(struct nfe_softc *sc)
1732 struct ifnet *ifp = &sc->arpcom.ac_if;
1733 struct nfe_jbuf *jbuf;
1735 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1737 jbuf = SLIST_FIRST(&sc->rxq.jfreelist);
1739 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext);
1742 if_printf(ifp, "no free jumbo buffer\n");
1745 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1751 nfe_jfree(void *arg)
1753 struct nfe_jbuf *jbuf = arg;
1754 struct nfe_softc *sc = jbuf->sc;
1755 struct nfe_rx_ring *ring = jbuf->ring;
1757 if (&ring->jbuf[jbuf->slot] != jbuf)
1758 panic("%s: free wrong jumbo buffer\n", __func__);
1759 else if (jbuf->inuse == 0)
1760 panic("%s: jumbo buffer already freed\n", __func__);
1762 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1763 atomic_subtract_int(&jbuf->inuse, 1);
1764 if (jbuf->inuse == 0)
1765 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1766 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1772 struct nfe_jbuf *jbuf = arg;
1773 struct nfe_rx_ring *ring = jbuf->ring;
1775 if (&ring->jbuf[jbuf->slot] != jbuf)
1776 panic("%s: ref wrong jumbo buffer\n", __func__);
1777 else if (jbuf->inuse == 0)
1778 panic("%s: jumbo buffer already freed\n", __func__);
1780 atomic_add_int(&jbuf->inuse, 1);
1784 nfe_jpool_alloc(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1786 struct nfe_jbuf *jbuf;
1787 bus_addr_t physaddr;
1792 * Allocate a big chunk of DMA'able memory.
1794 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1795 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1797 NFE_JPOOL_SIZE, 1, NFE_JPOOL_SIZE,
1800 if_printf(&sc->arpcom.ac_if,
1801 "could not create jumbo DMA tag\n");
1805 error = bus_dmamem_alloc(ring->jtag, (void **)&ring->jpool,
1806 BUS_DMA_WAITOK, &ring->jmap);
1808 if_printf(&sc->arpcom.ac_if,
1809 "could not allocate jumbo DMA memory\n");
1810 bus_dma_tag_destroy(ring->jtag);
1815 error = bus_dmamap_load(ring->jtag, ring->jmap, ring->jpool,
1816 NFE_JPOOL_SIZE, nfe_ring_dma_addr, &physaddr,
1819 if_printf(&sc->arpcom.ac_if,
1820 "could not load jumbo DMA map\n");
1821 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1822 bus_dma_tag_destroy(ring->jtag);
1827 /* ..and split it into 9KB chunks */
1828 SLIST_INIT(&ring->jfreelist);
1831 for (i = 0; i < NFE_JPOOL_COUNT; i++) {
1832 jbuf = &ring->jbuf[i];
1839 jbuf->physaddr = physaddr;
1841 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1844 physaddr += NFE_JBYTES;
1851 nfe_jpool_free(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1853 if (ring->jtag != NULL) {
1854 bus_dmamap_unload(ring->jtag, ring->jmap);
1855 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1856 bus_dma_tag_destroy(ring->jtag);
1861 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1863 int i, j, error, descsize;
1866 if (sc->sc_flags & NFE_40BIT_ADDR) {
1867 desc = (void **)&ring->desc64;
1868 descsize = sizeof(struct nfe_desc64);
1870 desc = (void **)&ring->desc32;
1871 descsize = sizeof(struct nfe_desc32);
1875 ring->cur = ring->next = 0;
1877 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1878 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1880 NFE_TX_RING_COUNT * descsize, 1,
1881 NFE_TX_RING_COUNT * descsize,
1884 if_printf(&sc->arpcom.ac_if,
1885 "could not create TX desc DMA map\n");
1889 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1892 if_printf(&sc->arpcom.ac_if,
1893 "could not allocate TX desc DMA memory\n");
1894 bus_dma_tag_destroy(ring->tag);
1899 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1900 NFE_TX_RING_COUNT * descsize,
1901 nfe_ring_dma_addr, &ring->physaddr,
1904 if_printf(&sc->arpcom.ac_if,
1905 "could not load TX desc DMA map\n");
1906 bus_dmamem_free(ring->tag, *desc, ring->map);
1907 bus_dma_tag_destroy(ring->tag);
1912 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1913 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1915 NFE_JBYTES * NFE_MAX_SCATTER,
1916 NFE_MAX_SCATTER, NFE_JBYTES,
1917 0, &ring->data_tag);
1919 if_printf(&sc->arpcom.ac_if,
1920 "could not create TX buf DMA tag\n");
1924 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1925 error = bus_dmamap_create(ring->data_tag, 0,
1926 &ring->data[i].map);
1928 if_printf(&sc->arpcom.ac_if,
1929 "could not create %dth TX buf DMA map\n", i);
1936 for (j = 0; j < i; ++j)
1937 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1938 bus_dma_tag_destroy(ring->data_tag);
1939 ring->data_tag = NULL;
1944 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1948 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1949 struct nfe_tx_data *data = &ring->data[i];
1951 if (sc->sc_flags & NFE_40BIT_ADDR)
1952 ring->desc64[i].flags = 0;
1954 ring->desc32[i].flags = 0;
1956 if (data->m != NULL) {
1957 bus_dmamap_sync(ring->data_tag, data->map,
1958 BUS_DMASYNC_POSTWRITE);
1959 bus_dmamap_unload(ring->data_tag, data->map);
1964 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1967 ring->cur = ring->next = 0;
1971 nfe_init_tx_ring(struct nfe_softc *sc __unused,
1972 struct nfe_tx_ring *ring __unused)
1978 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1980 if (ring->data_tag != NULL) {
1981 struct nfe_tx_data *data;
1984 for (i = 0; i < NFE_TX_RING_COUNT; ++i) {
1985 data = &ring->data[i];
1987 if (data->m != NULL) {
1988 bus_dmamap_unload(ring->data_tag, data->map);
1991 bus_dmamap_destroy(ring->data_tag, data->map);
1994 bus_dma_tag_destroy(ring->data_tag);
1997 if (ring->tag != NULL) {
2000 if (sc->sc_flags & NFE_40BIT_ADDR)
2001 desc = ring->desc64;
2003 desc = ring->desc32;
2005 bus_dmamap_unload(ring->tag, ring->map);
2006 bus_dmamem_free(ring->tag, desc, ring->map);
2007 bus_dma_tag_destroy(ring->tag);
2012 nfe_ifmedia_upd(struct ifnet *ifp)
2014 struct nfe_softc *sc = ifp->if_softc;
2015 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2017 if (mii->mii_instance != 0) {
2018 struct mii_softc *miisc;
2020 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2021 mii_phy_reset(miisc);
2029 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2031 struct nfe_softc *sc = ifp->if_softc;
2032 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2035 ifmr->ifm_status = mii->mii_media_status;
2036 ifmr->ifm_active = mii->mii_media_active;
2040 nfe_setmulti(struct nfe_softc *sc)
2042 struct ifnet *ifp = &sc->arpcom.ac_if;
2043 struct ifmultiaddr *ifma;
2044 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN];
2045 uint32_t filter = NFE_RXFILTER_MAGIC;
2048 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
2049 bzero(addr, ETHER_ADDR_LEN);
2050 bzero(mask, ETHER_ADDR_LEN);
2054 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN);
2055 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN);
2057 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2060 if (ifma->ifma_addr->sa_family != AF_LINK)
2063 maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
2064 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2065 addr[i] &= maddr[i];
2066 mask[i] &= ~maddr[i];
2070 for (i = 0; i < ETHER_ADDR_LEN; i++)
2074 addr[0] |= 0x01; /* make sure multicast bit is set */
2076 NFE_WRITE(sc, NFE_MULTIADDR_HI,
2077 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2078 NFE_WRITE(sc, NFE_MULTIADDR_LO,
2079 addr[5] << 8 | addr[4]);
2080 NFE_WRITE(sc, NFE_MULTIMASK_HI,
2081 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]);
2082 NFE_WRITE(sc, NFE_MULTIMASK_LO,
2083 mask[5] << 8 | mask[4]);
2085 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M;
2086 NFE_WRITE(sc, NFE_RXFILTER, filter);
2090 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr)
2094 tmp = NFE_READ(sc, NFE_MACADDR_LO);
2095 addr[0] = (tmp >> 8) & 0xff;
2096 addr[1] = (tmp & 0xff);
2098 tmp = NFE_READ(sc, NFE_MACADDR_HI);
2099 addr[2] = (tmp >> 24) & 0xff;
2100 addr[3] = (tmp >> 16) & 0xff;
2101 addr[4] = (tmp >> 8) & 0xff;
2102 addr[5] = (tmp & 0xff);
2106 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr)
2108 NFE_WRITE(sc, NFE_MACADDR_LO,
2109 addr[5] << 8 | addr[4]);
2110 NFE_WRITE(sc, NFE_MACADDR_HI,
2111 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2117 struct nfe_softc *sc = arg;
2118 struct ifnet *ifp = &sc->arpcom.ac_if;
2119 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2121 lwkt_serialize_enter(ifp->if_serializer);
2124 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
2126 lwkt_serialize_exit(ifp->if_serializer);
2130 nfe_ring_dma_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2135 KASSERT(nseg == 1, ("too many segments, should be 1\n"));
2137 *((uint32_t *)arg) = seg->ds_addr;
2141 nfe_buf_dma_addr(void *arg, bus_dma_segment_t *segs, int nsegs,
2142 bus_size_t mapsz __unused, int error)
2144 struct nfe_dma_ctx *ctx = arg;
2150 KASSERT(nsegs <= ctx->nsegs,
2151 ("too many segments(%d), should be <= %d\n",
2152 nsegs, ctx->nsegs));
2155 for (i = 0; i < nsegs; ++i)
2156 ctx->segs[i] = segs[i];
2160 nfe_newbuf_std(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2163 struct nfe_rx_data *data = &ring->data[idx];
2164 struct nfe_dma_ctx ctx;
2165 bus_dma_segment_t seg;
2170 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2173 m->m_len = m->m_pkthdr.len = MCLBYTES;
2177 error = bus_dmamap_load_mbuf(ring->data_tag, ring->data_tmpmap,
2178 m, nfe_buf_dma_addr, &ctx,
2179 wait ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
2182 if_printf(&sc->arpcom.ac_if, "could map RX mbuf %d\n", error);
2186 /* Unload originally mapped mbuf */
2187 bus_dmamap_unload(ring->data_tag, data->map);
2189 /* Swap this DMA map with tmp DMA map */
2191 data->map = ring->data_tmpmap;
2192 ring->data_tmpmap = map;
2194 /* Caller is assumed to have collected the old mbuf */
2197 nfe_set_paddr_rxdesc(sc, ring, idx, seg.ds_addr);
2199 bus_dmamap_sync(ring->data_tag, data->map, BUS_DMASYNC_PREREAD);
2204 nfe_newbuf_jumbo(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2207 struct nfe_rx_data *data = &ring->data[idx];
2208 struct nfe_jbuf *jbuf;
2211 MGETHDR(m, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA);
2215 jbuf = nfe_jalloc(sc);
2218 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
2219 "-- packet dropped!\n");
2223 m->m_ext.ext_arg = jbuf;
2224 m->m_ext.ext_buf = jbuf->buf;
2225 m->m_ext.ext_free = nfe_jfree;
2226 m->m_ext.ext_ref = nfe_jref;
2227 m->m_ext.ext_size = NFE_JBYTES;
2229 m->m_data = m->m_ext.ext_buf;
2230 m->m_flags |= M_EXT;
2231 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
2233 /* Caller is assumed to have collected the old mbuf */
2236 nfe_set_paddr_rxdesc(sc, ring, idx, jbuf->physaddr);
2238 bus_dmamap_sync(ring->jtag, ring->jmap, BUS_DMASYNC_PREREAD);
2243 nfe_set_paddr_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2244 bus_addr_t physaddr)
2246 if (sc->sc_flags & NFE_40BIT_ADDR) {
2247 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2249 #if defined(__LP64__)
2250 desc64->physaddr[0] = htole32(physaddr >> 32);
2252 desc64->physaddr[1] = htole32(physaddr & 0xffffffff);
2254 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2256 desc32->physaddr = htole32(physaddr);
2261 nfe_set_ready_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx)
2263 if (sc->sc_flags & NFE_40BIT_ADDR) {
2264 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2266 desc64->length = htole16(ring->bufsz);
2267 desc64->flags = htole16(NFE_RX_READY);
2269 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2271 desc32->length = htole16(ring->bufsz);
2272 desc32->flags = htole16(NFE_RX_READY);
2277 nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS)
2279 struct nfe_softc *sc = arg1;
2280 struct ifnet *ifp = &sc->arpcom.ac_if;
2283 lwkt_serialize_enter(ifp->if_serializer);
2286 error = sysctl_handle_int(oidp, &v, 0, req);
2287 if (error || req->newptr == NULL)
2294 if (sc->sc_imtime != v) {
2295 int old_imtime = sc->sc_imtime;
2298 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
2300 if ((ifp->if_flags & (IFF_POLLING | IFF_RUNNING))
2302 if (old_imtime > 0 && sc->sc_imtime > 0) {
2303 NFE_WRITE(sc, NFE_IMTIMER,
2304 NFE_IMTIME(sc->sc_imtime));
2305 } else if ((old_imtime * sc->sc_imtime) < 0) {
2311 lwkt_serialize_exit(ifp->if_serializer);