2 * Copyright (c) 1999 Seigo Tanimura
5 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in
6 * cwcealdr1.zip, the sample sources by Crystal Semiconductor.
7 * Copyright (c) 1996-1998 Crystal Semiconductor Corp.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * $FreeBSD: src/sys/dev/sound/pci/csa.c,v 1.8.2.12 2002/10/05 19:53:18 orion Exp $
31 * $DragonFly: src/sys/dev/sound/pci/csa.c,v 1.3 2003/08/07 21:17:13 dillon Exp $
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/kernel.h>
38 #include <sys/malloc.h>
39 #include <sys/module.h>
40 #include <machine/resource.h>
41 #include <machine/bus.h>
43 #include <sys/soundcard.h>
44 #include <dev/sound/pcm/sound.h>
45 #include <dev/sound/chip.h>
46 #include <dev/sound/pci/csareg.h>
47 #include <dev/sound/pci/csavar.h>
49 #include <bus/pci/pcireg.h>
50 #include <bus/pci/pcivar.h>
52 #include "gnu/csaimg.h"
54 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/csa.c,v 1.3 2003/08/07 21:17:13 dillon Exp $");
56 /* This is the pci device id. */
57 #define CS4610_PCI_ID 0x60011013
58 #define CS4614_PCI_ID 0x60031013
59 #define CS4615_PCI_ID 0x60041013
61 /* Here is the parameter structure per a device. */
63 device_t dev; /* device */
64 csa_res res; /* resources */
66 device_t pcm; /* pcm device */
67 driver_intr_t* pcmintr; /* pcm intr */
68 void *pcmintr_arg; /* pcm intr arg */
69 device_t midi; /* midi device */
70 driver_intr_t* midiintr; /* midi intr */
71 void *midiintr_arg; /* midi intr arg */
72 void *ih; /* cookie */
74 struct csa_card *card;
75 struct csa_bridgeinfo binfo; /* The state of this bridge. */
78 typedef struct csa_softc *sc_p;
80 static int csa_probe(device_t dev);
81 static int csa_attach(device_t dev);
82 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
83 u_long start, u_long end, u_long count, u_int flags);
84 static int csa_release_resource(device_t bus, device_t child, int type, int rid,
86 static int csa_setup_intr(device_t bus, device_t child,
87 struct resource *irq, int flags,
88 driver_intr_t *intr, void *arg, void **cookiep);
89 static int csa_teardown_intr(device_t bus, device_t child,
90 struct resource *irq, void *cookie);
91 static driver_intr_t csa_intr;
92 static int csa_initialize(sc_p scp);
93 static void csa_resetdsp(csa_res *resp);
94 static int csa_downloadimage(csa_res *resp);
96 static devclass_t csa_devclass;
112 devclass_t pci_devclass;
113 device_t *pci_devices, *pci_children, *busp, *childp;
114 int pci_count = 0, pci_childcount = 0;
117 bus_space_tag_t btag;
119 if ((pci_devclass = devclass_find("pci")) == NULL) {
123 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
125 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
127 device_get_children(*busp, &pci_children, &pci_childcount);
128 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) {
129 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) {
130 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10;
132 btag = I386_BUS_SPACE_IO;
134 control = bus_space_read_2(btag, 0x0, port);
136 control |= run? 0 : 0x2000;
137 bus_space_write_2(btag, 0x0, port, control);
138 free(pci_devices, M_TEMP);
139 free(pci_children, M_TEMP);
143 free(pci_children, M_TEMP);
146 free(pci_devices, M_TEMP);
153 static struct csa_card cards_4610[] = {
154 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0},
157 static struct csa_card cards_4614[] = {
158 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0},
159 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1},
160 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0},
161 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
162 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
163 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0},
164 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0},
165 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0},
166 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0},
169 static struct csa_card cards_4615[] = {
170 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0},
173 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0};
178 struct csa_card *cards;
181 static struct card_type cards[] = {
182 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610},
183 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614},
184 {CS4615_PCI_ID, "CS4615", cards_4615},
188 static struct card_type *
189 csa_findcard(device_t dev)
194 while (cards[i].devid != 0) {
195 if (pci_get_devid(dev) == cards[i].devid)
203 csa_findsubcard(device_t dev)
206 struct card_type *card;
207 struct csa_card *subcard;
209 card = csa_findcard(dev);
212 subcard = card->cards;
214 while (subcard[i].subvendor != 0) {
215 if (pci_get_subvendor(dev) == subcard[i].subvendor
216 && pci_get_subdevice(dev) == subcard[i].subdevice) {
225 csa_probe(device_t dev)
227 struct card_type *card;
229 card = csa_findcard(dev);
231 device_set_desc(dev, card->name);
238 csa_attach(device_t dev)
243 struct sndcard_func *func;
246 scp = device_get_softc(dev);
248 /* Fill in the softc. */
249 bzero(scp, sizeof(*scp));
252 /* Wake up the device. */
253 stcmd = pci_read_config(dev, PCIR_COMMAND, 2);
254 if ((stcmd & PCIM_CMD_MEMEN) == 0 || (stcmd & PCIM_CMD_BUSMASTEREN) == 0) {
255 stcmd |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
256 pci_write_config(dev, PCIR_COMMAND, stcmd, 2);
259 /* Allocate the resources. */
261 scp->card = csa_findsubcard(dev);
262 scp->binfo.card = scp->card;
263 printf("csa: card is %s\n", scp->card->name);
264 resp->io_rid = PCIR_MAPS;
265 resp->io = bus_alloc_resource(dev, SYS_RES_MEMORY, &resp->io_rid, 0, ~0, 1, RF_ACTIVE);
266 if (resp->io == NULL)
268 resp->mem_rid = PCIR_MAPS + 4;
269 resp->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &resp->mem_rid, 0, ~0, 1, RF_ACTIVE);
270 if (resp->mem == NULL)
273 resp->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &resp->irq_rid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
274 if (resp->irq == NULL)
277 /* Enable interrupt. */
278 if (snd_setup_intr(dev, resp->irq, INTR_MPSAFE, csa_intr, scp, &scp->ih))
281 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
282 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
285 /* Initialize the chip. */
286 if (csa_initialize(scp))
289 /* Reset the Processor. */
292 /* Download the Processor Image to the processor. */
293 if (csa_downloadimage(resp))
296 /* Attach the children. */
299 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO);
304 func->varinfo = &scp->binfo;
305 func->func = SCF_PCM;
306 scp->pcm = device_add_child(dev, "pcm", -1);
307 device_set_ivars(scp->pcm, func);
310 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO);
315 func->varinfo = &scp->binfo;
316 func->func = SCF_MIDI;
317 scp->midi = device_add_child(dev, "midi", -1);
318 device_set_ivars(scp->midi, func);
320 bus_generic_attach(dev);
325 bus_teardown_intr(dev, resp->irq, scp->ih);
327 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
329 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
331 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
336 csa_detach(device_t dev)
342 scp = device_get_softc(dev);
346 if (scp->midi != NULL)
347 err = device_delete_child(dev, scp->midi);
352 if (scp->pcm != NULL)
353 err = device_delete_child(dev, scp->pcm);
358 bus_teardown_intr(dev, resp->irq, scp->ih);
359 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
360 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
361 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
363 return bus_generic_detach(dev);
366 static struct resource *
367 csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
368 u_long start, u_long end, u_long count, u_int flags)
372 struct resource *res;
374 scp = device_get_softc(bus);
402 csa_release_resource(device_t bus, device_t child, int type, int rid,
409 * The following three functions deal with interrupt handling.
410 * An interrupt is primarily handled by the bridge driver.
411 * The bridge driver then determines the child devices to pass
412 * the interrupt. Certain information of the device can be read
413 * only once(eg the value of HISR). The bridge driver is responsible
414 * to pass such the information to the children.
418 csa_setup_intr(device_t bus, device_t child,
419 struct resource *irq, int flags,
420 driver_intr_t *intr, void *arg, void **cookiep)
424 struct sndcard_func *func;
426 scp = device_get_softc(bus);
430 * Look at the function code of the child to determine
431 * the appropriate hander for it.
433 func = device_get_ivars(child);
434 if (func == NULL || irq != resp->irq)
437 switch (func->func) {
440 scp->pcmintr_arg = arg;
444 scp->midiintr = intr;
445 scp->midiintr_arg = arg;
452 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
453 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
459 csa_teardown_intr(device_t bus, device_t child,
460 struct resource *irq, void *cookie)
464 struct sndcard_func *func;
466 scp = device_get_softc(bus);
470 * Look at the function code of the child to determine
471 * the appropriate hander for it.
473 func = device_get_ivars(child);
474 if (func == NULL || irq != resp->irq || cookie != scp)
477 switch (func->func) {
480 scp->pcmintr_arg = NULL;
484 scp->midiintr = NULL;
485 scp->midiintr_arg = NULL;
495 /* The interrupt handler */
505 /* Is this interrupt for us? */
506 hisr = csa_readio(resp, BA0_HISR);
507 if ((hisr & 0x7fffffff) == 0) {
509 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
514 * Pass the value of HISR via struct csa_bridgeinfo.
515 * The children get access through their ivars.
517 scp->binfo.hisr = hisr;
519 /* Invoke the handlers of the children. */
520 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) {
521 scp->pcmintr(scp->pcmintr_arg);
522 hisr &= ~(HISR_VC0 | HISR_VC1);
524 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) {
525 scp->midiintr(scp->midiintr_arg);
530 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
534 csa_initialize(sc_p scp)
537 u_int32_t acsts, acisv;
543 * First, blast the clock control register to zero so that the PLL starts
544 * out in a known state, and blast the master serial port control register
545 * to zero so that the serial ports also start out in a known state.
547 csa_writeio(resp, BA0_CLKCR1, 0);
548 csa_writeio(resp, BA0_SERMC1, 0);
551 * If we are in AC97 mode, then we must set the part to a host controlled
552 * AC-link. Otherwise, we won't be able to bring up the link.
555 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */
557 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */
561 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
562 * spec) and then drive it high. This is done for non AC97 modes since
563 * there might be logic external to the CS461x that uses the ARST# line
566 csa_writeio(resp, BA0_ACCTL, 1);
568 csa_writeio(resp, BA0_ACCTL, 0);
570 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN);
573 * The first thing we do here is to enable sync generation. As soon
574 * as we start receiving bit clock, we'll start producing the SYNC
577 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
580 * Now wait for a short while to allow the AC97 part to start
581 * generating bit clock (so we don't try to start the PLL without an
587 * Set the serial port timing configuration, so that
588 * the clock control circuit gets its clock from the correct place.
590 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97);
594 * Write the selected clock control setup to the hardware. Do not turn on
595 * SWCE yet (if requested), so that the devices clocked by the output of
596 * PLL are not clocked until the PLL is stable.
598 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
599 csa_writeio(resp, BA0_PLLM, 0x3a);
600 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8);
605 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP);
608 * Wait until the PLL has stabilized.
613 * Turn on clocking of the core so that we can setup the serial ports.
615 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE);
618 * Fill the serial port FIFOs with silence.
620 csa_clearserialfifos(resp);
623 * Set the serial port FIFO pointer to the first sample in the FIFO.
626 csa_writeio(resp, BA0_SERBSP, 0);
630 * Write the serial port configuration to the part. The master
631 * enable bit is not set until all other values have been written.
633 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
634 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
635 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
638 * Wait for the codec ready signal from the AC97 codec.
641 for (i = 0 ; i < 1000 ; i++) {
643 * First, lets wait a short while to let things settle out a bit,
644 * and to prevent retrying the read too quickly.
649 * Read the AC97 status register to see if we've seen a CODEC READY
650 * signal from the AC97 codec.
652 acsts = csa_readio(resp, BA0_ACSTS);
653 if ((acsts & ACSTS_CRDY) != 0)
658 * Make sure we sampled CODEC READY.
660 if ((acsts & ACSTS_CRDY) == 0)
664 * Assert the vaid frame signal so that we can start sending commands
667 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
670 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
671 * the codec is pumping ADC data across the AC-link.
674 for (i = 0 ; i < 1000 ; i++) {
676 * First, lets wait a short while to let things settle out a bit,
677 * and to prevent retrying the read too quickly.
680 DELAY(10000000L); /* clw */
685 * Read the input slot valid register and see if input slots 3 and
688 acisv = csa_readio(resp, BA0_ACISV);
689 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
693 * Make sure we sampled valid input slots 3 and 4. If not, then return
696 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4))
700 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
701 * commense the transfer of digital audio data to the AC97 codec.
703 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
706 * Power down the DAC and ADC. We will power them up (if) when we need
710 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300);
714 * Turn off the Processor by turning off the software clock enable flag in
715 * the clock control register.
718 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE;
719 csa_writeio(resp, BA0_CLKCR1, clkcr1);
723 * Enable interrupts on the part.
726 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
733 csa_clearserialfifos(csa_res *resp)
736 u_int8_t clkcr1, serbst;
739 * See if the devices are powered down. If so, we must power them up first
740 * or they will not respond.
743 clkcr1 = csa_readio(resp, BA0_CLKCR1);
744 if ((clkcr1 & CLKCR1_SWCE) == 0) {
745 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE);
750 * We want to clear out the serial port FIFOs so we don't end up playing
751 * whatever random garbage happens to be in them. We fill the sample FIFOs
752 * with zero (silence).
754 csa_writeio(resp, BA0_SERBWP, 0);
756 /* Fill all 256 sample FIFO locations. */
758 for (i = 0 ; i < 256 ; i++) {
759 /* Make sure the previous FIFO write operation has completed. */
760 for (j = 0 ; j < 5 ; j++) {
762 serbst = csa_readio(resp, BA0_SERBST);
763 if ((serbst & SERBST_WBSY) == 0)
766 if ((serbst & SERBST_WBSY) != 0) {
768 csa_writeio(resp, BA0_CLKCR1, clkcr1);
770 /* Write the serial port FIFO index. */
771 csa_writeio(resp, BA0_SERBAD, i);
772 /* Tell the serial port to load the new value into the FIFO location. */
773 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC);
776 * Now, if we powered up the devices, then power them back down again.
777 * This is kinda ugly, but should never happen.
780 csa_writeio(resp, BA0_CLKCR1, clkcr1);
784 csa_resetdsp(csa_res *resp)
789 * Write the reset bit of the SP control register.
791 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP);
794 * Write the control register.
796 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN);
799 * Clear the trap registers.
801 for (i = 0 ; i < 8 ; i++) {
802 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i);
803 csa_writemem(resp, BA1_TWPR, 0xffff);
805 csa_writemem(resp, BA1_DREG, 0);
808 * Set the frame timer to reflect the number of cycles per frame.
810 csa_writemem(resp, BA1_FRMT, 0xadf);
814 csa_downloadimage(csa_res *resp)
817 u_int32_t tmp, src, dst, count, data;
819 for (i = 0; i < CLEAR__COUNT; i++) {
820 dst = ClrStat[i].BA1__DestByteOffset;
821 count = ClrStat[i].BA1__SourceSize;
822 for (tmp = 0; tmp < count; tmp += 4)
823 csa_writemem(resp, dst + tmp, 0x00000000);
826 for (i = 0; i < FILL__COUNT; i++) {
828 dst = FillStat[i].Offset;
829 count = FillStat[i].Size;
830 for (tmp = 0; tmp < count; tmp += 4) {
831 data = FillStat[i].pFill[src];
832 csa_writemem(resp, dst + tmp, data);
841 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data)
844 u_int32_t acsda, acctl, acsts;
847 * Make sure that there is not data sitting around from a previous
848 * uncompleted access. ACSDA = Status Data Register = 47Ch
850 acsda = csa_readio(resp, BA0_ACSDA);
853 * Setup the AC97 control registers on the CS461x to send the
854 * appropriate command to the AC97 to perform the read.
855 * ACCAD = Command Address Register = 46Ch
856 * ACCDA = Command Data Register = 470h
857 * ACCTL = Control Register = 460h
858 * set DCV - will clear when process completed
859 * set CRW - Read command
860 * set VFRM - valid frame enabled
861 * set ESYN - ASYNC generation enabled
862 * set RSTN - ARST# inactive, AC97 codec not reset
866 * Get the actual AC97 register from the offset
868 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
869 csa_writeio(resp, BA0_ACCDA, 0);
870 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
873 * Wait for the read to occur.
876 for (i = 0 ; i < 10 ; i++) {
878 * First, we want to wait for a short time.
883 * Now, check to see if the read has completed.
884 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
886 acctl = csa_readio(resp, BA0_ACCTL);
887 if ((acctl & ACCTL_DCV) == 0)
892 * Make sure the read completed.
894 if ((acctl & ACCTL_DCV) != 0)
898 * Wait for the valid status bit to go active.
901 for (i = 0 ; i < 10 ; i++) {
903 * Read the AC97 status register.
904 * ACSTS = Status Register = 464h
906 acsts = csa_readio(resp, BA0_ACSTS);
908 * See if we have valid status.
909 * VSTS - Valid Status
911 if ((acsts & ACSTS_VSTS) != 0)
914 * Wait for a short while.
920 * Make sure we got valid status.
922 if ((acsts & ACSTS_VSTS) == 0)
926 * Read the data returned from the AC97 register.
927 * ACSDA = Status Data Register = 474h
929 *data = csa_readio(resp, BA0_ACSDA);
935 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data)
941 * Setup the AC97 control registers on the CS461x to send the
942 * appropriate command to the AC97 to perform the write.
943 * ACCAD = Command Address Register = 46Ch
944 * ACCDA = Command Data Register = 470h
945 * ACCTL = Control Register = 460h
946 * set DCV - will clear when process completed
947 * set VFRM - valid frame enabled
948 * set ESYN - ASYNC generation enabled
949 * set RSTN - ARST# inactive, AC97 codec not reset
953 * Get the actual AC97 register from the offset
955 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
956 csa_writeio(resp, BA0_ACCDA, data);
957 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
960 * Wait for the write to occur.
963 for (i = 0 ; i < 10 ; i++) {
965 * First, we want to wait for a short time.
970 * Now, check to see if the read has completed.
971 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
973 acctl = csa_readio(resp, BA0_ACCTL);
974 if ((acctl & ACCTL_DCV) == 0)
979 * Make sure the write completed.
981 if ((acctl & ACCTL_DCV) != 0)
988 csa_readio(csa_res *resp, u_long offset)
992 if (offset < BA0_AC97_RESET)
993 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff;
995 if (csa_readcodec(resp, offset, &ul))
1002 csa_writeio(csa_res *resp, u_long offset, u_int32_t data)
1004 if (offset < BA0_AC97_RESET)
1005 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data);
1007 csa_writecodec(resp, offset, data);
1011 csa_readmem(csa_res *resp, u_long offset)
1013 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset);
1017 csa_writemem(csa_res *resp, u_long offset, u_int32_t data)
1019 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data);
1022 static device_method_t csa_methods[] = {
1023 /* Device interface */
1024 DEVMETHOD(device_probe, csa_probe),
1025 DEVMETHOD(device_attach, csa_attach),
1026 DEVMETHOD(device_detach, csa_detach),
1027 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1028 DEVMETHOD(device_suspend, bus_generic_suspend),
1029 DEVMETHOD(device_resume, bus_generic_resume),
1032 DEVMETHOD(bus_print_child, bus_generic_print_child),
1033 DEVMETHOD(bus_alloc_resource, csa_alloc_resource),
1034 DEVMETHOD(bus_release_resource, csa_release_resource),
1035 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1036 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1037 DEVMETHOD(bus_setup_intr, csa_setup_intr),
1038 DEVMETHOD(bus_teardown_intr, csa_teardown_intr),
1043 static driver_t csa_driver = {
1046 sizeof(struct csa_softc),
1050 * csa can be attached to a pci bus.
1052 DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0);
1053 MODULE_DEPEND(snd_csa, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
1054 MODULE_VERSION(snd_csa, 1);