2 * Copyright (c) 1997 Semen Ustimenko (semenu@FreeBSD.org)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $FreeBSD: src/sys/dev/tx/if_tx.c,v 1.61.2.1 2002/10/29 01:43:49 semenu Exp $
27 * $DragonFly: src/sys/dev/netif/tx/if_tx.c,v 1.16 2005/02/20 03:08:29 joerg Exp $
31 * EtherPower II 10/100 Fast Ethernet (SMC 9432 serie)
33 * These cards are based on SMC83c17x (EPIC) chip and one of the various
34 * PHYs (QS6612, AC101 and LXT970 were seen). The media support depends on
35 * card model. All cards support 10baseT/UTP and 100baseTX half- and full-
36 * duplex (SMB9432TX). SMC9432BTX also supports 10baseT/BNC. SMC9432FTX also
37 * supports fibre optics.
39 * Thanks are going to Steve Bauer and Jason Wright.
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/sockio.h>
46 #include <sys/malloc.h>
47 #include <sys/kernel.h>
48 #include <sys/socket.h>
49 #include <sys/queue.h>
52 #include <net/ifq_var.h>
53 #include <net/if_arp.h>
54 #include <net/ethernet.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
60 #include <net/vlan/if_vlan_var.h>
62 #include <vm/vm.h> /* for vtophys */
63 #include <vm/pmap.h> /* for vtophys */
64 #include <machine/bus_memio.h>
65 #include <machine/bus_pio.h>
66 #include <machine/bus.h>
67 #include <machine/resource.h>
68 #include <machine/clock.h> /* for DELAY */
72 #include <bus/pci/pcireg.h>
73 #include <bus/pci/pcivar.h>
75 #include "../mii_layer/mii.h"
76 #include "../mii_layer/miivar.h"
77 #include "../mii_layer/miidevs.h"
78 #include "../mii_layer/lxtphyreg.h"
80 #include "miibus_if.h"
85 static int epic_ifioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
86 static void epic_intr(void *);
87 static void epic_tx_underrun(epic_softc_t *);
88 static int epic_common_attach(epic_softc_t *);
89 static void epic_ifstart(struct ifnet *);
90 static void epic_ifwatchdog(struct ifnet *);
91 static void epic_stats_update(void *);
92 static int epic_init(epic_softc_t *);
93 static void epic_stop(epic_softc_t *);
94 static void epic_rx_done(epic_softc_t *);
95 static void epic_tx_done(epic_softc_t *);
96 static int epic_init_rings(epic_softc_t *);
97 static void epic_free_rings(epic_softc_t *);
98 static void epic_stop_activity(epic_softc_t *);
99 static int epic_queue_last_packet(epic_softc_t *);
100 static void epic_start_activity(epic_softc_t *);
101 static void epic_set_rx_mode(epic_softc_t *);
102 static void epic_set_tx_mode(epic_softc_t *);
103 static void epic_set_mc_table(epic_softc_t *);
104 static u_int8_t epic_calchash(caddr_t);
105 static int epic_read_eeprom(epic_softc_t *,u_int16_t);
106 static void epic_output_eepromw(epic_softc_t *, u_int16_t);
107 static u_int16_t epic_input_eepromw(epic_softc_t *);
108 static u_int8_t epic_eeprom_clock(epic_softc_t *,u_int8_t);
109 static void epic_write_eepromreg(epic_softc_t *,u_int8_t);
110 static u_int8_t epic_read_eepromreg(epic_softc_t *);
112 static int epic_read_phy_reg(epic_softc_t *, int, int);
113 static void epic_write_phy_reg(epic_softc_t *, int, int, int);
115 static int epic_miibus_readreg(device_t, int, int);
116 static int epic_miibus_writereg(device_t, int, int, int);
117 static void epic_miibus_statchg(device_t);
118 static void epic_miibus_mediainit(device_t);
120 static int epic_ifmedia_upd(struct ifnet *);
121 static void epic_ifmedia_sts(struct ifnet *, struct ifmediareq *);
123 static int epic_probe(device_t);
124 static int epic_attach(device_t);
125 static void epic_shutdown(device_t);
126 static int epic_detach(device_t);
127 static struct epic_type *epic_devtype(device_t);
129 static device_method_t epic_methods[] = {
130 /* Device interface */
131 DEVMETHOD(device_probe, epic_probe),
132 DEVMETHOD(device_attach, epic_attach),
133 DEVMETHOD(device_detach, epic_detach),
134 DEVMETHOD(device_shutdown, epic_shutdown),
137 DEVMETHOD(miibus_readreg, epic_miibus_readreg),
138 DEVMETHOD(miibus_writereg, epic_miibus_writereg),
139 DEVMETHOD(miibus_statchg, epic_miibus_statchg),
140 DEVMETHOD(miibus_mediainit, epic_miibus_mediainit),
145 static driver_t epic_driver = {
151 static devclass_t epic_devclass;
153 DECLARE_DUMMY_MODULE(if_tx);
154 MODULE_DEPEND(if_tx, miibus, 1, 1, 1);
155 DRIVER_MODULE(if_tx, pci, epic_driver, epic_devclass, 0, 0);
156 DRIVER_MODULE(miibus, tx, miibus_driver, miibus_devclass, 0, 0);
158 static struct epic_type epic_devs[] = {
159 { SMC_VENDORID, SMC_DEVICEID_83C170,
160 "SMC EtherPower II 10/100" },
170 t = epic_devtype(dev);
173 device_set_desc(dev, t->name);
180 static struct epic_type *
188 while(t->name != NULL) {
189 if ((pci_get_vendor(dev) == t->ven_id) &&
190 (pci_get_device(dev) == t->dev_id)) {
198 #if defined(EPIC_USEIOSPACE)
199 #define EPIC_RES SYS_RES_IOPORT
200 #define EPIC_RID PCIR_BASEIO
202 #define EPIC_RES SYS_RES_MEMORY
203 #define EPIC_RID PCIR_BASEMEM
207 * Attach routine: map registers, allocate softc, rings and descriptors.
208 * Reset to known state.
222 sc = device_get_softc(dev);
223 unit = device_get_unit(dev);
225 /* Preinitialize softc structure */
226 bzero(sc, sizeof(epic_softc_t));
229 callout_init(&sc->tx_stat_timer);
231 /* Fill ifnet structure */
233 if_initname(ifp, "tx", unit);
235 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_MULTICAST;
236 ifp->if_ioctl = epic_ifioctl;
237 ifp->if_start = epic_ifstart;
238 ifp->if_watchdog = epic_ifwatchdog;
239 ifp->if_init = (if_init_f_t*)epic_init;
241 ifp->if_baudrate = 10000000;
242 ifq_set_maxlen(&ifp->if_snd, TX_RING_SIZE - 1);
243 ifq_set_ready(&ifp->if_snd);
245 /* Enable ports, memory and busmastering */
246 command = pci_read_config(dev, PCIR_COMMAND, 4);
247 command |= PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
248 pci_write_config(dev, PCIR_COMMAND, command, 4);
249 command = pci_read_config(dev, PCIR_COMMAND, 4);
251 #if defined(EPIC_USEIOSPACE)
252 if ((command & PCIM_CMD_PORTEN) == 0) {
253 device_printf(dev, "failed to enable I/O mapping!\n");
258 if ((command & PCIM_CMD_MEMEN) == 0) {
259 device_printf(dev, "failed to enable memory mapping!\n");
266 sc->res = bus_alloc_resource(dev, EPIC_RES, &rid, 0, ~0, 1,
269 if (sc->res == NULL) {
270 device_printf(dev, "couldn't map ports/memory\n");
275 sc->sc_st = rman_get_bustag(sc->res);
276 sc->sc_sh = rman_get_bushandle(sc->res);
278 /* Allocate interrupt */
280 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
281 RF_SHAREABLE | RF_ACTIVE);
283 if (sc->irq == NULL) {
284 device_printf(dev, "couldn't map interrupt\n");
285 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
290 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
291 epic_intr, sc, &sc->sc_ih);
294 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
295 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
296 device_printf(dev, "couldn't set up irq\n");
300 /* Do OS independent part, including chip wakeup and reset */
301 error = epic_common_attach(sc);
303 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
304 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
305 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
310 /* Do ifmedia setup */
311 if (mii_phy_probe(dev, &sc->miibus,
312 epic_ifmedia_upd, epic_ifmedia_sts)) {
313 device_printf(dev, "ERROR! MII without any PHY!?\n");
314 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
315 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
316 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
321 /* board type and ... */
323 for(i=0x2c;i<0x32;i++) {
324 tmp = epic_read_eeprom(sc, i);
325 if (' ' == (u_int8_t)tmp) break;
326 printf("%c", (u_int8_t)tmp);
328 if (' ' == (u_int8_t)tmp) break;
329 printf("%c", (u_int8_t)tmp);
333 /* Attach to OS's managers */
334 ether_ifattach(ifp, sc->sc_macaddr);
335 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
344 * Detach driver and free resources
356 sc = device_get_softc(dev);
357 ifp = &sc->arpcom.ac_if;
363 bus_generic_detach(dev);
364 device_delete_child(dev, sc->miibus);
366 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
367 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
368 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
370 free(sc->tx_flist, M_DEVBUF);
371 free(sc->tx_desc, M_DEVBUF);
372 free(sc->rx_desc, M_DEVBUF);
383 * Stop all chip I/O so that the kernel's probe routines don't
384 * get confused by errant DMAs when rebooting.
392 sc = device_get_softc(dev);
400 * This is if_ioctl handler.
403 epic_ifioctl(ifp, command, data, cr)
409 epic_softc_t *sc = ifp->if_softc;
410 struct mii_data *mii;
411 struct ifreq *ifr = (struct ifreq *) data;
419 error = ether_ioctl(ifp, command, data);
422 if (ifp->if_mtu == ifr->ifr_mtu)
425 /* XXX Though the datasheet doesn't imply any
426 * limitations on RX and TX sizes beside max 64Kb
427 * DMA transfer, seems we can't send more then 1600
428 * data bytes per ethernet packet. (Transmitter hangs
429 * up if more data is sent)
431 if (ifr->ifr_mtu + ifp->if_hdrlen <= EPIC_MAX_MTU) {
432 ifp->if_mtu = ifr->ifr_mtu;
441 * If the interface is marked up and stopped, then start it.
442 * If it is marked down and running, then stop it.
444 if (ifp->if_flags & IFF_UP) {
445 if ((ifp->if_flags & IFF_RUNNING) == 0) {
450 if (ifp->if_flags & IFF_RUNNING) {
456 /* Handle IFF_PROMISC and IFF_ALLMULTI flags */
457 epic_stop_activity(sc);
458 epic_set_mc_table(sc);
459 epic_set_rx_mode(sc);
460 epic_start_activity(sc);
465 epic_set_mc_table(sc);
471 mii = device_get_softc(sc->miibus);
472 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
484 * OS-independed part of attach process. allocate memory for descriptors
485 * and frag lists, wake up chip, read MAC address and PHY identyfier.
486 * Return -1 on failure.
489 epic_common_attach(sc)
494 sc->tx_flist = malloc(sizeof(struct epic_frag_list)*TX_RING_SIZE,
495 M_DEVBUF, M_WAITOK | M_ZERO);
496 sc->tx_desc = malloc(sizeof(struct epic_tx_desc)*TX_RING_SIZE,
497 M_DEVBUF, M_WAITOK | M_ZERO);
498 sc->rx_desc = malloc(sizeof(struct epic_rx_desc)*RX_RING_SIZE,
499 M_DEVBUF, M_WAITOK | M_ZERO);
501 /* Bring the chip out of low-power mode. */
502 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
505 /* Workaround for Application Note 7-15 */
506 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
508 /* Read mac address from EEPROM */
509 for (i = 0; i < ETHER_ADDR_LEN / sizeof(u_int16_t); i++)
510 ((u_int16_t *)sc->sc_macaddr)[i] = epic_read_eeprom(sc,i);
512 /* Set Non-Volatile Control Register from EEPROM */
513 CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F);
516 sc->tx_threshold = TRANSMIT_THRESHOLD;
517 sc->txcon = TXCON_DEFAULT;
518 sc->miicfg = MIICFG_SMI_ENABLE;
519 sc->phyid = EPIC_UNKN_PHY;
523 sc->cardvend = pci_read_config(sc->dev, PCIR_SUBVEND_0, 2);
524 sc->cardid = pci_read_config(sc->dev, PCIR_SUBDEV_0, 2);
526 if (sc->cardvend != SMC_VENDORID)
527 device_printf(sc->dev, "unknown card vendor %04xh\n", sc->cardvend);
533 * This is if_start handler. It takes mbufs from if_snd queue
534 * and queue them for transmit, one by one, until TX ring become full
535 * or queue become empty.
541 epic_softc_t *sc = ifp->if_softc;
542 struct epic_tx_buffer *buf;
543 struct epic_tx_desc *desc;
544 struct epic_frag_list *flist;
549 while (sc->pending_txs < TX_RING_SIZE) {
550 buf = sc->tx_buffer + sc->cur_tx;
551 desc = sc->tx_desc + sc->cur_tx;
552 flist = sc->tx_flist + sc->cur_tx;
554 /* Get next packet to send */
555 m0 = ifq_dequeue(&ifp->if_snd);
557 /* If nothing to send, return */
561 /* Fill fragments list */
563 (NULL != m) && (i < EPIC_MAX_FRAGS);
564 m = m->m_next, i++) {
565 flist->frag[i].fraglen = m->m_len;
566 flist->frag[i].fragaddr = vtophys(mtod(m, caddr_t));
570 /* If packet was more than EPIC_MAX_FRAGS parts, */
571 /* recopy packet to new allocated mbuf cluster */
580 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t));
581 flist->frag[0].fraglen =
582 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
583 m->m_pkthdr.rcvif = ifp;
586 flist->frag[0].fragaddr = vtophys(mtod(m, caddr_t));
593 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
594 desc->control = 0x01;
596 max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
597 desc->status = 0x8000;
598 CSR_WRITE_4(sc, COMMAND, COMMAND_TXQUEUED);
600 /* Set watchdog timer */
606 ifp->if_flags |= IFF_OACTIVE;
613 * Synopsis: Finish all received frames.
620 struct ifnet *ifp = &sc->sc_if;
621 struct epic_rx_buffer *buf;
622 struct epic_rx_desc *desc;
625 while ((sc->rx_desc[sc->cur_rx].status & 0x8000) == 0) {
626 buf = sc->rx_buffer + sc->cur_rx;
627 desc = sc->rx_desc + sc->cur_rx;
629 /* Switch to next descriptor */
630 sc->cur_rx = (sc->cur_rx+1) & RX_RING_MASK;
633 * Check for RX errors. This should only happen if
634 * SAVE_ERRORED_PACKETS is set. RX errors generate
635 * RXE interrupt usually.
637 if ((desc->status & 1) == 0) {
638 sc->sc_if.if_ierrors++;
639 desc->status = 0x8000;
643 /* Save packet length and mbuf contained packet */
644 len = desc->rxlength - ETHER_CRC_LEN;
647 /* Try to get mbuf cluster */
648 EPIC_MGETCLUSTER(buf->mbuf);
649 if (NULL == buf->mbuf) {
651 desc->status = 0x8000;
656 /* Point to new mbuf, and give descriptor to chip */
657 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t));
658 desc->status = 0x8000;
660 /* First mbuf in packet holds the ethernet and packet headers */
661 m->m_pkthdr.rcvif = ifp;
662 m->m_pkthdr.len = m->m_len = len;
664 /* Give mbuf to OS */
665 (*ifp->if_input)(ifp, m);
667 /* Successfuly received frame */
675 * Synopsis: Do last phase of transmission. I.e. if desc is
676 * transmitted, decrease pending_txs counter, free mbuf contained
677 * packet, switch to next descriptor and repeat until no packets
678 * are pending or descriptor is not transmitted yet.
684 struct epic_tx_buffer *buf;
685 struct epic_tx_desc *desc;
688 while (sc->pending_txs > 0) {
689 buf = sc->tx_buffer + sc->dirty_tx;
690 desc = sc->tx_desc + sc->dirty_tx;
691 status = desc->status;
693 /* If packet is not transmitted, thou followed */
694 /* packets are not transmitted too */
695 if (status & 0x8000) break;
697 /* Packet is transmitted. Switch to next and */
700 sc->dirty_tx = (sc->dirty_tx + 1) & TX_RING_MASK;
704 /* Check for errors and collisions */
705 if (status & 0x0001) sc->sc_if.if_opackets++;
706 else sc->sc_if.if_oerrors++;
707 sc->sc_if.if_collisions += (status >> 8) & 0x1F;
708 #if defined(EPIC_DIAG)
709 if ((status & 0x1001) == 0x1001)
710 device_printf(sc->dev, "Tx ERROR: excessive coll. number\n");
714 if (sc->pending_txs < TX_RING_SIZE)
715 sc->sc_if.if_flags &= ~IFF_OACTIVE;
725 epic_softc_t * sc = (epic_softc_t *) arg;
728 while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) {
729 CSR_WRITE_4(sc, INTSTAT, status);
731 if (status & (INTSTAT_RQE|INTSTAT_RCC|INTSTAT_OVW)) {
733 if (status & (INTSTAT_RQE|INTSTAT_OVW)) {
734 #if defined(EPIC_DIAG)
735 if (status & INTSTAT_OVW)
736 device_printf(sc->dev, "RX buffer overflow\n");
737 if (status & INTSTAT_RQE)
738 device_printf(sc->dev, "RX FIFO overflow\n");
740 if ((CSR_READ_4(sc, COMMAND) & COMMAND_RXQUEUED) == 0)
741 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED);
742 sc->sc_if.if_ierrors++;
746 if (status & (INTSTAT_TXC|INTSTAT_TCC|INTSTAT_TQE)) {
748 if (!ifq_is_empty(&sc->sc_if.if_snd))
749 epic_ifstart(&sc->sc_if);
752 /* Check for rare errors */
753 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
754 INTSTAT_APE|INTSTAT_DPE|INTSTAT_TXU|INTSTAT_RXE)) {
755 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
756 INTSTAT_APE|INTSTAT_DPE)) {
757 device_printf(sc->dev, "PCI fatal errors occured: %s%s%s%s\n",
758 (status&INTSTAT_PMA)?"PMA ":"",
759 (status&INTSTAT_PTA)?"PTA ":"",
760 (status&INTSTAT_APE)?"APE ":"",
761 (status&INTSTAT_DPE)?"DPE":""
770 if (status & INTSTAT_RXE) {
771 #if defined(EPIC_DIAG)
772 device_printf(sc->dev, "CRC/Alignment error\n");
774 sc->sc_if.if_ierrors++;
777 if (status & INTSTAT_TXU) {
778 epic_tx_underrun(sc);
779 sc->sc_if.if_oerrors++;
784 /* If no packets are pending, then no timeouts */
785 if (sc->pending_txs == 0) sc->sc_if.if_timer = 0;
791 * Handle the TX underrun error: increase the TX threshold
792 * and restart the transmitter.
798 if (sc->tx_threshold > TRANSMIT_THRESHOLD_MAX) {
799 sc->txcon &= ~TXCON_EARLY_TRANSMIT_ENABLE;
800 #if defined(EPIC_DIAG)
801 device_printf(sc->dev, "Tx UNDERRUN: early TX disabled\n");
804 sc->tx_threshold += 0x40;
805 #if defined(EPIC_DIAG)
806 device_printf(sc->dev, "Tx UNDERRUN: TX threshold increased to %d\n",
811 /* We must set TXUGO to reset the stuck transmitter */
812 CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO);
814 /* Update the TX threshold */
815 epic_stop_activity(sc);
816 epic_set_tx_mode(sc);
817 epic_start_activity(sc);
823 * Synopsis: This one is called if packets wasn't transmitted
824 * during timeout. Try to deallocate transmitted packets, and
825 * if success continue to work.
831 epic_softc_t *sc = ifp->if_softc;
836 device_printf(sc->dev, "device timeout %d packets\n", sc->pending_txs);
838 /* Try to finish queued packets */
841 /* If not successful */
842 if (sc->pending_txs > 0) {
844 ifp->if_oerrors+=sc->pending_txs;
846 /* Reinitialize board */
847 device_printf(sc->dev, "reinitialization\n");
852 device_printf(sc->dev, "seems we can continue normaly\n");
855 if (!ifq_is_empty(&ifp->if_snd))
862 * Despite the name of this function, it doesn't update statistics, it only
863 * helps in autonegotiation process.
866 epic_stats_update(void *xsc)
868 epic_softc_t *sc = xsc;
869 struct mii_data * mii;
874 mii = device_get_softc(sc->miibus);
877 callout_reset(&sc->tx_stat_timer, hz, epic_stats_update, sc);
886 epic_ifmedia_upd(ifp)
890 struct mii_data *mii;
892 struct mii_softc *miisc;
896 mii = device_get_softc(sc->miibus);
897 ifm = &mii->mii_media;
898 media = ifm->ifm_cur->ifm_media;
900 /* Do not do anything if interface is not up */
901 if ((ifp->if_flags & IFF_UP) == 0)
905 * Lookup current selected PHY
907 if (IFM_INST(media) == sc->serinst) {
908 sc->phyid = EPIC_SERIAL;
911 /* If we're not selecting serial interface, select MII mode */
912 sc->miicfg &= ~MIICFG_SERIAL_ENABLE;
913 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
915 /* Default to unknown PHY */
916 sc->phyid = EPIC_UNKN_PHY;
918 /* Lookup selected PHY */
919 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
920 miisc = LIST_NEXT(miisc, mii_list)) {
921 if (IFM_INST(media) == miisc->mii_inst) {
927 /* Identify selected PHY */
929 int id1, id2, model, oui;
931 id1 = PHY_READ(sc->physc, MII_PHYIDR1);
932 id2 = PHY_READ(sc->physc, MII_PHYIDR2);
934 oui = MII_OUI(id1, id2);
935 model = MII_MODEL(id2);
937 case MII_OUI_QUALSEMI:
938 if (model == MII_MODEL_QUALSEMI_QS6612)
939 sc->phyid = EPIC_QS6612_PHY;
941 case MII_OUI_xxALTIMA:
942 if (model == MII_MODEL_xxALTIMA_AC101)
943 sc->phyid = EPIC_AC101_PHY;
945 case MII_OUI_xxLEVEL1:
946 if (model == MII_MODEL_xxLEVEL1_LXT970)
947 sc->phyid = EPIC_LXT970_PHY;
954 * Do PHY specific card setup
957 /* Call this, to isolate all not selected PHYs and
962 /* Do our own setup */
964 case EPIC_QS6612_PHY:
967 /* We have to powerup fiber tranceivers */
968 if (IFM_SUBTYPE(media) == IFM_100_FX)
969 sc->miicfg |= MIICFG_694_ENABLE;
971 sc->miicfg &= ~MIICFG_694_ENABLE;
972 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
975 case EPIC_LXT970_PHY:
976 /* We have to powerup fiber tranceivers */
977 cfg = PHY_READ(sc->physc, MII_LXTPHY_CONFIG);
978 if (IFM_SUBTYPE(media) == IFM_100_FX)
979 cfg |= CONFIG_LEDC1 | CONFIG_LEDC0;
981 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0);
982 PHY_WRITE(sc->physc, MII_LXTPHY_CONFIG, cfg);
986 /* Select serial PHY, (10base2/BNC usually) */
987 sc->miicfg |= MIICFG_694_ENABLE | MIICFG_SERIAL_ENABLE;
988 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
990 /* There is no driver to fill this */
991 mii->mii_media_active = media;
992 mii->mii_media_status = 0;
994 /* We need to call this manualy as i wasn't called
997 epic_miibus_statchg(sc->dev);
1001 device_printf(sc->dev, "ERROR! Unknown PHY selected\n");
1009 * Report current media status.
1012 epic_ifmedia_sts(ifp, ifmr)
1014 struct ifmediareq *ifmr;
1017 struct mii_data *mii;
1018 struct ifmedia *ifm;
1021 mii = device_get_softc(sc->miibus);
1022 ifm = &mii->mii_media;
1024 /* Nothing should be selected if interface is down */
1025 if ((ifp->if_flags & IFF_UP) == 0) {
1026 ifmr->ifm_active = IFM_NONE;
1027 ifmr->ifm_status = 0;
1032 /* Call underlying pollstat, if not serial PHY */
1033 if (sc->phyid != EPIC_SERIAL)
1036 /* Simply copy media info */
1037 ifmr->ifm_active = mii->mii_media_active;
1038 ifmr->ifm_status = mii->mii_media_status;
1044 * Callback routine, called on media change.
1047 epic_miibus_statchg(dev)
1051 struct mii_data *mii;
1054 sc = device_get_softc(dev);
1055 mii = device_get_softc(sc->miibus);
1056 media = mii->mii_media_active;
1058 sc->txcon &= ~(TXCON_LOOPBACK_MODE | TXCON_FULL_DUPLEX);
1060 /* If we are in full-duplex mode or loopback operation,
1061 * we need to decouple receiver and transmitter.
1063 if (IFM_OPTIONS(media) & (IFM_FDX | IFM_LOOP))
1064 sc->txcon |= TXCON_FULL_DUPLEX;
1066 /* On some cards we need manualy set fullduplex led */
1067 if (sc->cardid == SMC9432FTX ||
1068 sc->cardid == SMC9432FTX_SC) {
1069 if (IFM_OPTIONS(media) & IFM_FDX)
1070 sc->miicfg |= MIICFG_694_ENABLE;
1072 sc->miicfg &= ~MIICFG_694_ENABLE;
1074 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1077 /* Update baudrate */
1078 if (IFM_SUBTYPE(media) == IFM_100_TX ||
1079 IFM_SUBTYPE(media) == IFM_100_FX)
1080 sc->sc_if.if_baudrate = 100000000;
1082 sc->sc_if.if_baudrate = 10000000;
1084 epic_stop_activity(sc);
1085 epic_set_tx_mode(sc);
1086 epic_start_activity(sc);
1092 epic_miibus_mediainit(dev)
1096 struct mii_data *mii;
1097 struct ifmedia *ifm;
1100 sc = device_get_softc(dev);
1101 mii = device_get_softc(sc->miibus);
1102 ifm = &mii->mii_media;
1104 /* Add Serial Media Interface if present, this applies to
1107 if (CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) {
1108 /* Store its instance */
1109 sc->serinst = mii->mii_instance++;
1111 /* Add as 10base2/BNC media */
1112 media = IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->serinst);
1113 ifmedia_add(ifm, media, 0, NULL);
1115 /* Report to user */
1116 device_printf(sc->dev, "serial PHY detected (10Base2/BNC)\n");
1123 * Reset chip, allocate rings, and update media.
1129 struct ifnet *ifp = &sc->sc_if;
1134 /* If interface is already running, then we need not do anything */
1135 if (ifp->if_flags & IFF_RUNNING) {
1140 /* Soft reset the chip (we have to power up card before) */
1141 CSR_WRITE_4(sc, GENCTL, 0);
1142 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1145 * Reset takes 15 pci ticks which depends on PCI bus speed.
1146 * Assuming it >= 33000000 hz, we have wait at least 495e-6 sec.
1151 CSR_WRITE_4(sc, GENCTL, 0);
1153 /* Workaround for Application Note 7-15 */
1154 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
1156 /* Initialize rings */
1157 if (epic_init_rings(sc)) {
1158 device_printf(sc->dev, "failed to init rings\n");
1163 /* Give rings to EPIC */
1164 CSR_WRITE_4(sc, PRCDAR, vtophys(sc->rx_desc));
1165 CSR_WRITE_4(sc, PTCDAR, vtophys(sc->tx_desc));
1167 /* Put node address to EPIC */
1168 CSR_WRITE_4(sc, LAN0, ((u_int16_t *)sc->sc_macaddr)[0]);
1169 CSR_WRITE_4(sc, LAN1, ((u_int16_t *)sc->sc_macaddr)[1]);
1170 CSR_WRITE_4(sc, LAN2, ((u_int16_t *)sc->sc_macaddr)[2]);
1172 /* Set tx mode, includeing transmit threshold */
1173 epic_set_tx_mode(sc);
1175 /* Compute and set RXCON. */
1176 epic_set_rx_mode(sc);
1178 /* Set multicast table */
1179 epic_set_mc_table(sc);
1181 /* Enable interrupts by setting the interrupt mask. */
1182 CSR_WRITE_4(sc, INTMASK,
1183 INTSTAT_RCC | /* INTSTAT_RQE | INTSTAT_OVW | INTSTAT_RXE | */
1184 /* INTSTAT_TXC | */ INTSTAT_TCC | INTSTAT_TQE | INTSTAT_TXU |
1187 /* Acknowledge all pending interrupts */
1188 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT));
1190 /* Enable interrupts, set for PCI read multiple and etc */
1191 CSR_WRITE_4(sc, GENCTL,
1192 GENCTL_ENABLE_INTERRUPT | GENCTL_MEMORY_READ_MULTIPLE |
1193 GENCTL_ONECOPY | GENCTL_RECEIVE_FIFO_THRESHOLD64);
1195 /* Mark interface running ... */
1196 if (ifp->if_flags & IFF_UP) ifp->if_flags |= IFF_RUNNING;
1197 else ifp->if_flags &= ~IFF_RUNNING;
1200 ifp->if_flags &= ~IFF_OACTIVE;
1202 /* Start Rx process */
1203 epic_start_activity(sc);
1205 /* Set appropriate media */
1206 epic_ifmedia_upd(ifp);
1208 callout_reset(&sc->tx_stat_timer, hz, epic_stats_update, sc);
1216 * Synopsis: calculate and set Rx mode. Chip must be in idle state to
1220 epic_set_rx_mode(sc)
1223 u_int32_t flags = sc->sc_if.if_flags;
1224 u_int32_t rxcon = RXCON_DEFAULT;
1226 #if defined(EPIC_EARLY_RX)
1227 rxcon |= RXCON_EARLY_RX;
1230 rxcon |= (flags & IFF_PROMISC) ? RXCON_PROMISCUOUS_MODE : 0;
1232 CSR_WRITE_4(sc, RXCON, rxcon);
1238 * Synopsis: Set transmit control register. Chip must be in idle state to
1242 epic_set_tx_mode(sc)
1245 if (sc->txcon & TXCON_EARLY_TRANSMIT_ENABLE)
1246 CSR_WRITE_4(sc, ETXTHR, sc->tx_threshold);
1248 CSR_WRITE_4(sc, TXCON, sc->txcon);
1252 * Synopsis: Program multicast filter honoring IFF_ALLMULTI and IFF_PROMISC
1253 * flags. (Note, that setting PROMISC bit in EPIC's RXCON will only touch
1254 * individual frames, multicast filter must be manually programmed)
1256 * Note: EPIC must be in idle state.
1259 epic_set_mc_table(sc)
1262 struct ifnet *ifp = &sc->sc_if;
1263 struct ifmultiaddr *ifma;
1264 u_int16_t filter[4];
1267 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1268 CSR_WRITE_4(sc, MC0, 0xFFFF);
1269 CSR_WRITE_4(sc, MC1, 0xFFFF);
1270 CSR_WRITE_4(sc, MC2, 0xFFFF);
1271 CSR_WRITE_4(sc, MC3, 0xFFFF);
1281 #if defined(__DragonFly__) || __FreeBSD_version < 500000
1282 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1284 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1286 if (ifma->ifma_addr->sa_family != AF_LINK)
1288 h = epic_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1289 filter[h >> 4] |= 1 << (h & 0xF);
1292 CSR_WRITE_4(sc, MC0, filter[0]);
1293 CSR_WRITE_4(sc, MC1, filter[1]);
1294 CSR_WRITE_4(sc, MC2, filter[2]);
1295 CSR_WRITE_4(sc, MC3, filter[3]);
1301 * Synopsis: calculate EPIC's hash of multicast address.
1307 u_int32_t crc, carry;
1311 /* Compute CRC for the address value. */
1312 crc = 0xFFFFFFFF; /* initial value */
1314 for (i = 0; i < 6; i++) {
1316 for (j = 0; j < 8; j++) {
1317 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
1321 crc = (crc ^ 0x04c11db6) | carry;
1325 return ((crc >> 26) & 0x3F);
1330 * Synopsis: Start receive process and transmit one, if they need.
1333 epic_start_activity(sc)
1336 /* Start rx process */
1337 CSR_WRITE_4(sc, COMMAND,
1338 COMMAND_RXQUEUED | COMMAND_START_RX |
1339 (sc->pending_txs?COMMAND_TXQUEUED:0));
1343 * Synopsis: Completely stop Rx and Tx processes. If TQE is set additional
1344 * packet needs to be queued to stop Tx DMA.
1347 epic_stop_activity(sc)
1352 /* Stop Tx and Rx DMA */
1353 CSR_WRITE_4(sc, COMMAND,
1354 COMMAND_STOP_RX | COMMAND_STOP_RDMA | COMMAND_STOP_TDMA);
1356 /* Wait Rx and Tx DMA to stop (why 1 ms ??? XXX) */
1357 for (i=0; i<0x1000; i++) {
1358 status = CSR_READ_4(sc, INTSTAT) & (INTSTAT_TXIDLE | INTSTAT_RXIDLE);
1359 if (status == (INTSTAT_TXIDLE | INTSTAT_RXIDLE))
1364 /* Catch all finished packets */
1368 status = CSR_READ_4(sc, INTSTAT);
1370 if ((status & INTSTAT_RXIDLE) == 0)
1371 device_printf(sc->dev, "ERROR! Can't stop Rx DMA\n");
1373 if ((status & INTSTAT_TXIDLE) == 0)
1374 device_printf(sc->dev, "ERROR! Can't stop Tx DMA\n");
1377 * May need to queue one more packet if TQE, this is rare
1378 * but existing case.
1380 if ((status & INTSTAT_TQE) && !(status & INTSTAT_TXIDLE))
1381 (void) epic_queue_last_packet(sc);
1386 * The EPIC transmitter may stuck in TQE state. It will not go IDLE until
1387 * a packet from current descriptor will be copied to internal RAM. We
1388 * compose a dummy packet here and queue it for transmission.
1390 * XXX the packet will then be actually sent over network...
1393 epic_queue_last_packet(sc)
1396 struct epic_tx_desc *desc;
1397 struct epic_frag_list *flist;
1398 struct epic_tx_buffer *buf;
1402 device_printf(sc->dev, "queue last packet\n");
1404 desc = sc->tx_desc + sc->cur_tx;
1405 flist = sc->tx_flist + sc->cur_tx;
1406 buf = sc->tx_buffer + sc->cur_tx;
1408 if ((desc->status & 0x8000) || (buf->mbuf != NULL))
1411 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
1416 m0->m_len = min(MHLEN, ETHER_MIN_LEN-ETHER_CRC_LEN);
1417 flist->frag[0].fraglen = m0->m_len;
1418 m0->m_pkthdr.len = m0->m_len;
1419 m0->m_pkthdr.rcvif = &sc->sc_if;
1420 bzero(mtod(m0,caddr_t), m0->m_len);
1422 /* Fill fragments list */
1423 flist->frag[0].fraglen = m0->m_len;
1424 flist->frag[0].fragaddr = vtophys(mtod(m0, caddr_t));
1425 flist->numfrags = 1;
1427 /* Fill in descriptor */
1430 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
1431 desc->control = 0x01;
1432 desc->txlength = max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
1433 desc->status = 0x8000;
1435 /* Launch transmition */
1436 CSR_WRITE_4(sc, COMMAND, COMMAND_STOP_TDMA | COMMAND_TXQUEUED);
1438 /* Wait Tx DMA to stop (for how long??? XXX) */
1439 for (i=0; i<1000; i++) {
1440 if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE)
1445 if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0)
1446 device_printf(sc->dev, "ERROR! can't stop Tx DMA (2)\n");
1454 * Synopsis: Shut down board and deallocates rings.
1464 sc->sc_if.if_timer = 0;
1466 callout_stop(&sc->tx_stat_timer);
1468 /* Disable interrupts */
1469 CSR_WRITE_4(sc, INTMASK, 0);
1470 CSR_WRITE_4(sc, GENCTL, 0);
1472 /* Try to stop Rx and TX processes */
1473 epic_stop_activity(sc);
1476 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1479 /* Make chip go to bed */
1480 CSR_WRITE_4(sc, GENCTL, GENCTL_POWER_DOWN);
1482 /* Free memory allocated for rings */
1483 epic_free_rings(sc);
1485 /* Mark as stoped */
1486 sc->sc_if.if_flags &= ~IFF_RUNNING;
1493 * Synopsis: This function should free all memory allocated for rings.
1501 for (i=0; i<RX_RING_SIZE; i++) {
1502 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1503 struct epic_rx_desc *desc = sc->rx_desc + i;
1506 desc->buflength = 0;
1509 if (buf->mbuf) m_freem(buf->mbuf);
1513 for (i=0; i<TX_RING_SIZE; i++) {
1514 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1515 struct epic_tx_desc *desc = sc->tx_desc + i;
1518 desc->buflength = 0;
1521 if (buf->mbuf) m_freem(buf->mbuf);
1527 * Synopsis: Allocates mbufs for Rx ring and point Rx descs to them.
1528 * Point Tx descs to fragment lists. Check that all descs and fraglists
1529 * are bounded and aligned properly.
1537 sc->cur_rx = sc->cur_tx = sc->dirty_tx = sc->pending_txs = 0;
1539 for (i = 0; i < RX_RING_SIZE; i++) {
1540 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1541 struct epic_rx_desc *desc = sc->rx_desc + i;
1543 desc->status = 0; /* Owned by driver */
1544 desc->next = vtophys(sc->rx_desc + ((i+1) & RX_RING_MASK));
1546 if ((desc->next & 3) ||
1547 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1548 epic_free_rings(sc);
1552 EPIC_MGETCLUSTER(buf->mbuf);
1553 if (NULL == buf->mbuf) {
1554 epic_free_rings(sc);
1557 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t));
1559 desc->buflength = MCLBYTES; /* Max RX buffer length */
1560 desc->status = 0x8000; /* Set owner bit to NIC */
1563 for (i = 0; i < TX_RING_SIZE; i++) {
1564 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1565 struct epic_tx_desc *desc = sc->tx_desc + i;
1568 desc->next = vtophys(sc->tx_desc + ((i+1) & TX_RING_MASK));
1570 if ((desc->next & 3) ||
1571 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1572 epic_free_rings(sc);
1577 desc->bufaddr = vtophys(sc->tx_flist + i);
1579 if ((desc->bufaddr & 3) ||
1580 ((desc->bufaddr & PAGE_MASK) + sizeof(struct epic_frag_list)) > PAGE_SIZE) {
1581 epic_free_rings(sc);
1590 * EEPROM operation functions
1593 epic_write_eepromreg(sc, val)
1599 CSR_WRITE_1(sc, EECTL, val);
1601 for (i=0; i<0xFF; i++)
1602 if ((CSR_READ_1(sc, EECTL) & 0x20) == 0) break;
1608 epic_read_eepromreg(sc)
1611 return CSR_READ_1(sc, EECTL);
1615 epic_eeprom_clock(sc, val)
1619 epic_write_eepromreg(sc, val);
1620 epic_write_eepromreg(sc, (val | 0x4));
1621 epic_write_eepromreg(sc, val);
1623 return epic_read_eepromreg(sc);
1627 epic_output_eepromw(sc, val)
1633 for (i = 0xF; i >= 0; i--) {
1635 epic_eeprom_clock(sc, 0x0B);
1637 epic_eeprom_clock(sc, 0x03);
1642 epic_input_eepromw(sc)
1645 u_int16_t retval = 0;
1648 for (i = 0xF; i >= 0; i--) {
1649 if (epic_eeprom_clock(sc, 0x3) & 0x10)
1657 epic_read_eeprom(sc, loc)
1664 epic_write_eepromreg(sc, 3);
1666 if (epic_read_eepromreg(sc) & 0x40)
1667 read_cmd = (loc & 0x3F) | 0x180;
1669 read_cmd = (loc & 0xFF) | 0x600;
1671 epic_output_eepromw(sc, read_cmd);
1673 dataval = epic_input_eepromw(sc);
1675 epic_write_eepromreg(sc, 1);
1681 * Here goes MII read/write routines
1684 epic_read_phy_reg(sc, phy, reg)
1690 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01));
1692 for (i = 0; i < 0x100; i++) {
1693 if ((CSR_READ_4(sc, MIICTL) & 0x01) == 0) break;
1697 return (CSR_READ_4(sc, MIIDATA));
1701 epic_write_phy_reg(sc, phy, reg, val)
1707 CSR_WRITE_4(sc, MIIDATA, val);
1708 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02));
1710 for(i=0;i<0x100;i++) {
1711 if ((CSR_READ_4(sc, MIICTL) & 0x02) == 0) break;
1719 epic_miibus_readreg(dev, phy, reg)
1725 sc = device_get_softc(dev);
1727 return (PHY_READ_2(sc, phy, reg));
1731 epic_miibus_writereg(dev, phy, reg, data)
1737 sc = device_get_softc(dev);
1739 PHY_WRITE_2(sc, phy, reg, data);