1 /* $OpenBSD: if_nfe.c,v 1.63 2006/06/17 18:00:43 brad Exp $ */
2 /* $DragonFly: src/sys/dev/netif/nfe/if_nfe.c,v 1.15 2007/08/10 15:29:25 sephe Exp $ */
5 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
7 * This code is derived from software contributed to The DragonFly Project
8 * by Sepherosa Ziehau <sepherosa@gmail.com> and
9 * Matthew Dillon <dillon@apollo.backplane.com>
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
21 * 3. Neither the name of The DragonFly Project nor the names of its
22 * contributors may be used to endorse or promote products derived
23 * from this software without specific, prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
28 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
29 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
30 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
31 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
33 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
34 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
35 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr>
41 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org>
43 * Permission to use, copy, modify, and distribute this software for any
44 * purpose with or without fee is hereby granted, provided that the above
45 * copyright notice and this permission notice appear in all copies.
47 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
48 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
49 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
50 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
51 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
52 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
53 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
56 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */
58 #include "opt_polling.h"
60 #include <sys/param.h>
61 #include <sys/endian.h>
62 #include <sys/kernel.h>
66 #include <sys/serialize.h>
67 #include <sys/socket.h>
68 #include <sys/sockio.h>
69 #include <sys/sysctl.h>
71 #include <net/ethernet.h>
74 #include <net/if_arp.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
77 #include <net/ifq_var.h>
78 #include <net/if_types.h>
79 #include <net/if_var.h>
80 #include <net/vlan/if_vlan_var.h>
82 #include <bus/pci/pcireg.h>
83 #include <bus/pci/pcivar.h>
84 #include <bus/pci/pcidevs.h>
86 #include <dev/netif/mii_layer/mii.h>
87 #include <dev/netif/mii_layer/miivar.h>
89 #include "miibus_if.h"
91 #include <dev/netif/nfe/if_nfereg.h>
92 #include <dev/netif/nfe/if_nfevar.h>
95 #define NFE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
97 static int nfe_probe(device_t);
98 static int nfe_attach(device_t);
99 static int nfe_detach(device_t);
100 static void nfe_shutdown(device_t);
101 static int nfe_resume(device_t);
102 static int nfe_suspend(device_t);
104 static int nfe_miibus_readreg(device_t, int, int);
105 static void nfe_miibus_writereg(device_t, int, int, int);
106 static void nfe_miibus_statchg(device_t);
108 #ifdef DEVICE_POLLING
109 static void nfe_poll(struct ifnet *, enum poll_cmd, int);
111 static void nfe_intr(void *);
112 static int nfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
113 static void nfe_rxeof(struct nfe_softc *);
114 static void nfe_txeof(struct nfe_softc *);
115 static int nfe_encap(struct nfe_softc *, struct nfe_tx_ring *,
117 static void nfe_start(struct ifnet *);
118 static void nfe_watchdog(struct ifnet *);
119 static void nfe_init(void *);
120 static void nfe_stop(struct nfe_softc *);
121 static struct nfe_jbuf *nfe_jalloc(struct nfe_softc *);
122 static void nfe_jfree(void *);
123 static void nfe_jref(void *);
124 static int nfe_jpool_alloc(struct nfe_softc *, struct nfe_rx_ring *);
125 static void nfe_jpool_free(struct nfe_softc *, struct nfe_rx_ring *);
126 static int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
127 static void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
128 static int nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
129 static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
130 static int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
131 static void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
132 static int nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
133 static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
134 static int nfe_ifmedia_upd(struct ifnet *);
135 static void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
136 static void nfe_setmulti(struct nfe_softc *);
137 static void nfe_get_macaddr(struct nfe_softc *, uint8_t *);
138 static void nfe_set_macaddr(struct nfe_softc *, const uint8_t *);
139 static void nfe_tick(void *);
140 static void nfe_ring_dma_addr(void *, bus_dma_segment_t *, int, int);
141 static void nfe_buf_dma_addr(void *, bus_dma_segment_t *, int, bus_size_t,
143 static void nfe_set_paddr_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
145 static void nfe_set_ready_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
147 static int nfe_newbuf_std(struct nfe_softc *, struct nfe_rx_ring *, int,
149 static int nfe_newbuf_jumbo(struct nfe_softc *, struct nfe_rx_ring *, int,
155 static int nfe_debug = 0;
156 static int nfe_rx_ring_count = NFE_RX_RING_DEF_COUNT;
158 TUNABLE_INT("hw.nfe.rx_ring_count", &nfe_rx_ring_count);
160 SYSCTL_NODE(_hw, OID_AUTO, nfe, CTLFLAG_RD, 0, "nVidia GigE parameters");
161 SYSCTL_INT(_hw_nfe, OID_AUTO, rx_ring_count, CTLFLAG_RD, &nfe_rx_ring_count,
162 NFE_RX_RING_DEF_COUNT, "rx ring count");
163 SYSCTL_INT(_hw_nfe, OID_AUTO, debug, CTLFLAG_RW, &nfe_debug, 0,
164 "control debugging printfs");
166 #define DPRINTF(sc, fmt, ...) do { \
168 if_printf(&(sc)->arpcom.ac_if, \
173 #define DPRINTFN(sc, lv, fmt, ...) do { \
174 if (nfe_debug >= (lv)) { \
175 if_printf(&(sc)->arpcom.ac_if, \
180 #else /* !NFE_DEBUG */
182 #define DPRINTF(sc, fmt, ...)
183 #define DPRINTFN(sc, lv, fmt, ...)
185 #endif /* NFE_DEBUG */
189 bus_dma_segment_t *segs;
192 static const struct nfe_dev {
197 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN,
198 "NVIDIA nForce Fast Ethernet" },
200 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN,
201 "NVIDIA nForce2 Fast Ethernet" },
203 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1,
204 "NVIDIA nForce3 Gigabit Ethernet" },
206 /* XXX TGEN the next chip can also be found in the nForce2 Ultra 400Gb
207 chipset, and possibly also the 400R; it might be both nForce2- and
208 nForce3-based boards can use the same MCPs (= southbridges) */
209 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2,
210 "NVIDIA nForce3 Gigabit Ethernet" },
212 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3,
213 "NVIDIA nForce3 Gigabit Ethernet" },
215 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4,
216 "NVIDIA nForce3 Gigabit Ethernet" },
218 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5,
219 "NVIDIA nForce3 Gigabit Ethernet" },
221 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1,
222 "NVIDIA CK804 Gigabit Ethernet" },
224 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2,
225 "NVIDIA CK804 Gigabit Ethernet" },
227 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1,
228 "NVIDIA MCP04 Gigabit Ethernet" },
230 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2,
231 "NVIDIA MCP04 Gigabit Ethernet" },
233 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1,
234 "NVIDIA MCP51 Gigabit Ethernet" },
236 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2,
237 "NVIDIA MCP51 Gigabit Ethernet" },
239 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1,
240 "NVIDIA MCP55 Gigabit Ethernet" },
242 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2,
243 "NVIDIA MCP55 Gigabit Ethernet" },
245 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1,
246 "NVIDIA MCP61 Gigabit Ethernet" },
248 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2,
249 "NVIDIA MCP61 Gigabit Ethernet" },
251 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3,
252 "NVIDIA MCP61 Gigabit Ethernet" },
254 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4,
255 "NVIDIA MCP61 Gigabit Ethernet" },
257 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1,
258 "NVIDIA MCP65 Gigabit Ethernet" },
260 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2,
261 "NVIDIA MCP65 Gigabit Ethernet" },
263 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3,
264 "NVIDIA MCP65 Gigabit Ethernet" },
266 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4,
267 "NVIDIA MCP65 Gigabit Ethernet" },
269 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1,
270 "NVIDIA MCP67 Gigabit Ethernet" },
272 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2,
273 "NVIDIA MCP67 Gigabit Ethernet" },
275 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3,
276 "NVIDIA MCP67 Gigabit Ethernet" },
278 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4,
279 "NVIDIA MCP67 Gigabit Ethernet" }
282 static device_method_t nfe_methods[] = {
283 /* Device interface */
284 DEVMETHOD(device_probe, nfe_probe),
285 DEVMETHOD(device_attach, nfe_attach),
286 DEVMETHOD(device_detach, nfe_detach),
287 DEVMETHOD(device_suspend, nfe_suspend),
288 DEVMETHOD(device_resume, nfe_resume),
289 DEVMETHOD(device_shutdown, nfe_shutdown),
292 DEVMETHOD(bus_print_child, bus_generic_print_child),
293 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
296 DEVMETHOD(miibus_readreg, nfe_miibus_readreg),
297 DEVMETHOD(miibus_writereg, nfe_miibus_writereg),
298 DEVMETHOD(miibus_statchg, nfe_miibus_statchg),
303 static driver_t nfe_driver = {
306 sizeof(struct nfe_softc)
309 static devclass_t nfe_devclass;
311 DECLARE_DUMMY_MODULE(if_nfe);
312 MODULE_DEPEND(if_nfe, miibus, 1, 1, 1);
313 DRIVER_MODULE(if_nfe, pci, nfe_driver, nfe_devclass, 0, 0);
314 DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, 0, 0);
317 nfe_probe(device_t dev)
319 const struct nfe_dev *n;
322 vid = pci_get_vendor(dev);
323 did = pci_get_device(dev);
324 for (n = nfe_devices; n->desc != NULL; ++n) {
325 if (vid == n->vid && did == n->did) {
326 struct nfe_softc *sc = device_get_softc(dev);
329 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2:
330 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3:
331 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4:
332 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5:
333 sc->sc_flags = NFE_JUMBO_SUP |
336 case PCI_PRODUCT_NVIDIA_MCP51_LAN1:
337 case PCI_PRODUCT_NVIDIA_MCP51_LAN2:
338 case PCI_PRODUCT_NVIDIA_MCP61_LAN1:
339 case PCI_PRODUCT_NVIDIA_MCP61_LAN2:
340 case PCI_PRODUCT_NVIDIA_MCP61_LAN3:
341 case PCI_PRODUCT_NVIDIA_MCP61_LAN4:
342 case PCI_PRODUCT_NVIDIA_MCP67_LAN1:
343 case PCI_PRODUCT_NVIDIA_MCP67_LAN2:
344 case PCI_PRODUCT_NVIDIA_MCP67_LAN3:
345 case PCI_PRODUCT_NVIDIA_MCP67_LAN4:
346 sc->sc_flags = NFE_40BIT_ADDR;
348 case PCI_PRODUCT_NVIDIA_CK804_LAN1:
349 case PCI_PRODUCT_NVIDIA_CK804_LAN2:
350 case PCI_PRODUCT_NVIDIA_MCP04_LAN1:
351 case PCI_PRODUCT_NVIDIA_MCP04_LAN2:
352 case PCI_PRODUCT_NVIDIA_MCP65_LAN1:
353 case PCI_PRODUCT_NVIDIA_MCP65_LAN2:
354 case PCI_PRODUCT_NVIDIA_MCP65_LAN3:
355 case PCI_PRODUCT_NVIDIA_MCP65_LAN4:
356 sc->sc_flags = NFE_JUMBO_SUP |
360 case PCI_PRODUCT_NVIDIA_MCP55_LAN1:
361 case PCI_PRODUCT_NVIDIA_MCP55_LAN2:
362 sc->sc_flags = NFE_JUMBO_SUP |
369 device_set_desc(dev, n->desc);
370 device_set_async_attach(dev, TRUE);
378 nfe_attach(device_t dev)
380 struct nfe_softc *sc = device_get_softc(dev);
381 struct ifnet *ifp = &sc->arpcom.ac_if;
382 uint8_t eaddr[ETHER_ADDR_LEN];
385 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
386 lwkt_serialize_init(&sc->sc_jbuf_serializer);
388 sc->sc_mem_rid = PCIR_BAR(0);
391 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
394 mem = pci_read_config(dev, sc->sc_mem_rid, 4);
395 irq = pci_read_config(dev, PCIR_INTLINE, 4);
397 device_printf(dev, "chip is in D%d power mode "
398 "-- setting to D0\n", pci_get_powerstate(dev));
400 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
402 pci_write_config(dev, sc->sc_mem_rid, mem, 4);
403 pci_write_config(dev, PCIR_INTLINE, irq, 4);
405 #endif /* !BURN_BRIDGE */
407 /* Enable bus mastering */
408 pci_enable_busmaster(dev);
410 /* Allocate IO memory */
411 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
412 &sc->sc_mem_rid, RF_ACTIVE);
413 if (sc->sc_mem_res == NULL) {
414 device_printf(dev, "cound not allocate io memory\n");
417 sc->sc_memh = rman_get_bushandle(sc->sc_mem_res);
418 sc->sc_memt = rman_get_bustag(sc->sc_mem_res);
422 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
424 RF_SHAREABLE | RF_ACTIVE);
425 if (sc->sc_irq_res == NULL) {
426 device_printf(dev, "could not allocate irq\n");
431 nfe_get_macaddr(sc, eaddr);
434 * Allocate Tx and Rx rings.
436 error = nfe_alloc_tx_ring(sc, &sc->txq);
438 device_printf(dev, "could not allocate Tx ring\n");
442 error = nfe_alloc_rx_ring(sc, &sc->rxq);
444 device_printf(dev, "could not allocate Rx ring\n");
448 error = mii_phy_probe(dev, &sc->sc_miibus, nfe_ifmedia_upd,
451 device_printf(dev, "MII without any phy\n");
456 ifp->if_mtu = ETHERMTU;
457 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
458 ifp->if_ioctl = nfe_ioctl;
459 ifp->if_start = nfe_start;
460 #ifdef DEVICE_POLLING
461 ifp->if_poll = nfe_poll;
463 ifp->if_watchdog = nfe_watchdog;
464 ifp->if_init = nfe_init;
465 ifq_set_maxlen(&ifp->if_snd, NFE_IFQ_MAXLEN);
466 ifq_set_ready(&ifp->if_snd);
468 ifp->if_capabilities = IFCAP_VLAN_MTU;
470 if (sc->sc_flags & NFE_HW_VLAN)
471 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
474 if (sc->sc_flags & NFE_HW_CSUM) {
475 ifp->if_capabilities |= IFCAP_HWCSUM;
476 ifp->if_hwassist = NFE_CSUM_FEATURES;
479 sc->sc_flags &= ~NFE_HW_CSUM;
481 ifp->if_capenable = ifp->if_capabilities;
483 callout_init(&sc->sc_tick_ch);
485 ether_ifattach(ifp, eaddr, NULL);
487 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, nfe_intr, sc,
488 &sc->sc_ih, ifp->if_serializer);
490 device_printf(dev, "could not setup intr\n");
502 nfe_detach(device_t dev)
504 struct nfe_softc *sc = device_get_softc(dev);
506 if (device_is_attached(dev)) {
507 struct ifnet *ifp = &sc->arpcom.ac_if;
509 lwkt_serialize_enter(ifp->if_serializer);
511 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_ih);
512 lwkt_serialize_exit(ifp->if_serializer);
517 if (sc->sc_miibus != NULL)
518 device_delete_child(dev, sc->sc_miibus);
519 bus_generic_detach(dev);
521 if (sc->sc_irq_res != NULL) {
522 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
526 if (sc->sc_mem_res != NULL) {
527 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
531 nfe_free_tx_ring(sc, &sc->txq);
532 nfe_free_rx_ring(sc, &sc->rxq);
538 nfe_shutdown(device_t dev)
540 struct nfe_softc *sc = device_get_softc(dev);
541 struct ifnet *ifp = &sc->arpcom.ac_if;
543 lwkt_serialize_enter(ifp->if_serializer);
545 lwkt_serialize_exit(ifp->if_serializer);
549 nfe_suspend(device_t dev)
551 struct nfe_softc *sc = device_get_softc(dev);
552 struct ifnet *ifp = &sc->arpcom.ac_if;
554 lwkt_serialize_enter(ifp->if_serializer);
556 lwkt_serialize_exit(ifp->if_serializer);
562 nfe_resume(device_t dev)
564 struct nfe_softc *sc = device_get_softc(dev);
565 struct ifnet *ifp = &sc->arpcom.ac_if;
567 lwkt_serialize_enter(ifp->if_serializer);
568 if (ifp->if_flags & IFF_UP)
570 lwkt_serialize_exit(ifp->if_serializer);
576 nfe_miibus_statchg(device_t dev)
578 struct nfe_softc *sc = device_get_softc(dev);
579 struct mii_data *mii = device_get_softc(sc->sc_miibus);
580 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET;
582 phy = NFE_READ(sc, NFE_PHY_IFACE);
583 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T);
585 seed = NFE_READ(sc, NFE_RNDSEED);
586 seed &= ~NFE_SEED_MASK;
588 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) {
589 phy |= NFE_PHY_HDX; /* half-duplex */
590 misc |= NFE_MISC1_HDX;
593 switch (IFM_SUBTYPE(mii->mii_media_active)) {
594 case IFM_1000_T: /* full-duplex only */
595 link |= NFE_MEDIA_1000T;
596 seed |= NFE_SEED_1000T;
597 phy |= NFE_PHY_1000T;
600 link |= NFE_MEDIA_100TX;
601 seed |= NFE_SEED_100TX;
602 phy |= NFE_PHY_100TX;
605 link |= NFE_MEDIA_10T;
606 seed |= NFE_SEED_10T;
610 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */
612 NFE_WRITE(sc, NFE_PHY_IFACE, phy);
613 NFE_WRITE(sc, NFE_MISC1, misc);
614 NFE_WRITE(sc, NFE_LINKSPEED, link);
618 nfe_miibus_readreg(device_t dev, int phy, int reg)
620 struct nfe_softc *sc = device_get_softc(dev);
624 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
626 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
627 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
631 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);
633 for (ntries = 0; ntries < 1000; ntries++) {
635 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
638 if (ntries == 1000) {
639 DPRINTFN(sc, 2, "timeout waiting for PHY %s\n", "");
643 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) {
644 DPRINTFN(sc, 2, "could not read PHY %s\n", "");
648 val = NFE_READ(sc, NFE_PHY_DATA);
649 if (val != 0xffffffff && val != 0)
650 sc->mii_phyaddr = phy;
652 DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val);
658 nfe_miibus_writereg(device_t dev, int phy, int reg, int val)
660 struct nfe_softc *sc = device_get_softc(dev);
664 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
666 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
667 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
671 NFE_WRITE(sc, NFE_PHY_DATA, val);
672 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;
673 NFE_WRITE(sc, NFE_PHY_CTL, ctl);
675 for (ntries = 0; ntries < 1000; ntries++) {
677 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
683 DPRINTFN(sc, 2, "could not write to PHY %s\n", "");
687 #ifdef DEVICE_POLLING
690 nfe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
692 struct nfe_softc *sc = ifp->if_softc;
696 /* Disable interrupts */
697 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
699 case POLL_DEREGISTER:
700 /* enable interrupts */
701 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED);
703 case POLL_AND_CHECK_STATUS:
706 if (ifp->if_flags & IFF_RUNNING) {
719 struct nfe_softc *sc = arg;
720 struct ifnet *ifp = &sc->arpcom.ac_if;
723 r = NFE_READ(sc, NFE_IRQ_STATUS);
725 return; /* not for us */
726 NFE_WRITE(sc, NFE_IRQ_STATUS, r);
728 DPRINTFN(sc, 5, "%s: interrupt register %x\n", __func__, r);
730 if (r & NFE_IRQ_LINK) {
731 NFE_READ(sc, NFE_PHY_STATUS);
732 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
733 DPRINTF(sc, "link state changed %s\n", "");
736 if (ifp->if_flags & IFF_RUNNING) {
746 nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
748 struct nfe_softc *sc = ifp->if_softc;
749 struct ifreq *ifr = (struct ifreq *)data;
750 struct mii_data *mii;
755 if (((sc->sc_flags & NFE_JUMBO_SUP) &&
756 ifr->ifr_mtu > NFE_JUMBO_MTU) ||
757 ((sc->sc_flags & NFE_JUMBO_SUP) == 0 &&
758 ifr->ifr_mtu > ETHERMTU)) {
760 } else if (ifp->if_mtu != ifr->ifr_mtu) {
761 ifp->if_mtu = ifr->ifr_mtu;
766 if (ifp->if_flags & IFF_UP) {
768 * If only the PROMISC or ALLMULTI flag changes, then
769 * don't do a full re-init of the chip, just update
772 if ((ifp->if_flags & IFF_RUNNING) &&
773 ((ifp->if_flags ^ sc->sc_if_flags) &
774 (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
777 if (!(ifp->if_flags & IFF_RUNNING))
781 if (ifp->if_flags & IFF_RUNNING)
784 sc->sc_if_flags = ifp->if_flags;
788 if (ifp->if_flags & IFF_RUNNING)
793 mii = device_get_softc(sc->sc_miibus);
794 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
797 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) & IFCAP_HWCSUM;
798 if (mask && (ifp->if_capabilities & IFCAP_HWCSUM)) {
799 ifp->if_capenable ^= mask;
800 if (IFCAP_TXCSUM & ifp->if_capenable)
801 ifp->if_hwassist = NFE_CSUM_FEATURES;
803 ifp->if_hwassist = 0;
805 if (ifp->if_flags & IFF_RUNNING)
810 error = ether_ioctl(ifp, cmd, data);
817 nfe_rxeof(struct nfe_softc *sc)
819 struct ifnet *ifp = &sc->arpcom.ac_if;
820 struct nfe_rx_ring *ring = &sc->rxq;
824 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
827 struct nfe_rx_data *data = &ring->data[ring->cur];
832 if (sc->sc_flags & NFE_40BIT_ADDR) {
833 struct nfe_desc64 *desc64 = &ring->desc64[ring->cur];
835 flags = le16toh(desc64->flags);
836 len = le16toh(desc64->length) & 0x3fff;
838 struct nfe_desc32 *desc32 = &ring->desc32[ring->cur];
840 flags = le16toh(desc32->flags);
841 len = le16toh(desc32->length) & 0x3fff;
844 if (flags & NFE_RX_READY)
849 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
850 if (!(flags & NFE_RX_VALID_V1))
853 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) {
854 flags &= ~NFE_RX_ERROR;
855 len--; /* fix buffer length */
858 if (!(flags & NFE_RX_VALID_V2))
861 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) {
862 flags &= ~NFE_RX_ERROR;
863 len--; /* fix buffer length */
867 if (flags & NFE_RX_ERROR) {
874 if (sc->sc_flags & NFE_USE_JUMBO)
875 error = nfe_newbuf_jumbo(sc, ring, ring->cur, 0);
877 error = nfe_newbuf_std(sc, ring, ring->cur, 0);
884 m->m_pkthdr.len = m->m_len = len;
885 m->m_pkthdr.rcvif = ifp;
887 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
888 (flags & NFE_RX_CSUMOK)) {
889 if (flags & NFE_RX_IP_CSUMOK_V2) {
890 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
895 (NFE_RX_UDP_CSUMOK_V2 | NFE_RX_TCP_CSUMOK_V2)) {
896 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
898 m->m_pkthdr.csum_data = 0xffff;
903 ifp->if_input(ifp, m);
905 nfe_set_ready_rxdesc(sc, ring, ring->cur);
906 sc->rxq.cur = (sc->rxq.cur + 1) % nfe_rx_ring_count;
910 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
914 nfe_txeof(struct nfe_softc *sc)
916 struct ifnet *ifp = &sc->arpcom.ac_if;
917 struct nfe_tx_ring *ring = &sc->txq;
918 struct nfe_tx_data *data = NULL;
920 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
921 while (ring->next != ring->cur) {
924 if (sc->sc_flags & NFE_40BIT_ADDR)
925 flags = le16toh(ring->desc64[ring->next].flags);
927 flags = le16toh(ring->desc32[ring->next].flags);
929 if (flags & NFE_TX_VALID)
932 data = &ring->data[ring->next];
934 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
935 if (!(flags & NFE_TX_LASTFRAG_V1) && data->m == NULL)
938 if ((flags & NFE_TX_ERROR_V1) != 0) {
939 if_printf(ifp, "tx v1 error 0x%4b\n", flags,
946 if (!(flags & NFE_TX_LASTFRAG_V2) && data->m == NULL)
949 if ((flags & NFE_TX_ERROR_V2) != 0) {
950 if_printf(ifp, "tx v2 error 0x%4b\n", flags,
958 if (data->m == NULL) { /* should not get there */
960 "last fragment bit w/o associated mbuf!\n");
964 /* last fragment of the mbuf chain transmitted */
965 bus_dmamap_sync(ring->data_tag, data->map,
966 BUS_DMASYNC_POSTWRITE);
967 bus_dmamap_unload(ring->data_tag, data->map);
974 KKASSERT(ring->queued >= 0);
975 ring->next = (ring->next + 1) % NFE_TX_RING_COUNT;
978 if (data != NULL) { /* at least one slot freed */
979 ifp->if_flags &= ~IFF_OACTIVE;
985 nfe_encap(struct nfe_softc *sc, struct nfe_tx_ring *ring, struct mbuf *m0)
987 struct nfe_dma_ctx ctx;
988 bus_dma_segment_t segs[NFE_MAX_SCATTER];
989 struct nfe_tx_data *data, *data_map;
991 struct nfe_desc64 *desc64 = NULL;
992 struct nfe_desc32 *desc32 = NULL;
997 data = &ring->data[ring->cur];
999 data_map = data; /* Remember who owns the DMA map */
1001 ctx.nsegs = NFE_MAX_SCATTER;
1003 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
1004 nfe_buf_dma_addr, &ctx, BUS_DMA_NOWAIT);
1005 if (error && error != EFBIG) {
1006 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
1010 if (error) { /* error == EFBIG */
1013 m_new = m_defrag(m0, MB_DONTWAIT);
1014 if (m_new == NULL) {
1015 if_printf(&sc->arpcom.ac_if,
1016 "could not defrag TX mbuf\n");
1023 ctx.nsegs = NFE_MAX_SCATTER;
1025 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
1026 nfe_buf_dma_addr, &ctx,
1029 if_printf(&sc->arpcom.ac_if,
1030 "could not map defraged TX mbuf\n");
1037 if (ring->queued + ctx.nsegs >= NFE_TX_RING_COUNT - 1) {
1038 bus_dmamap_unload(ring->data_tag, map);
1043 /* setup h/w VLAN tagging */
1044 if ((m0->m_flags & (M_PROTO1 | M_PKTHDR)) == (M_PROTO1 | M_PKTHDR) &&
1045 m0->m_pkthdr.rcvif != NULL &&
1046 m0->m_pkthdr.rcvif->if_type == IFT_L2VLAN) {
1047 struct ifvlan *ifv = m0->m_pkthdr.rcvif->if_softc;
1050 vtag = NFE_TX_VTAG | htons(ifv->ifv_tag);
1053 if (sc->arpcom.ac_if.if_capenable & IFCAP_TXCSUM) {
1054 if (m0->m_pkthdr.csum_flags & CSUM_IP)
1055 flags |= NFE_TX_IP_CSUM;
1056 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
1057 flags |= NFE_TX_TCP_CSUM;
1061 * XXX urm. somebody is unaware of how hardware works. You
1062 * absolutely CANNOT set NFE_TX_VALID on the next descriptor in
1063 * the ring until the entire chain is actually *VALID*. Otherwise
1064 * the hardware may encounter a partially initialized chain that
1065 * is marked as being ready to go when it in fact is not ready to
1069 for (i = 0; i < ctx.nsegs; i++) {
1070 j = (ring->cur + i) % NFE_TX_RING_COUNT;
1071 data = &ring->data[j];
1073 if (sc->sc_flags & NFE_40BIT_ADDR) {
1074 desc64 = &ring->desc64[j];
1075 #if defined(__LP64__)
1076 desc64->physaddr[0] =
1077 htole32(segs[i].ds_addr >> 32);
1079 desc64->physaddr[1] =
1080 htole32(segs[i].ds_addr & 0xffffffff);
1081 desc64->length = htole16(segs[i].ds_len - 1);
1082 desc64->vtag = htole32(vtag);
1083 desc64->flags = htole16(flags);
1085 desc32 = &ring->desc32[j];
1086 desc32->physaddr = htole32(segs[i].ds_addr);
1087 desc32->length = htole16(segs[i].ds_len - 1);
1088 desc32->flags = htole16(flags);
1091 /* csum flags and vtag belong to the first fragment only */
1092 flags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_CSUM);
1096 KKASSERT(ring->queued <= NFE_TX_RING_COUNT);
1099 /* the whole mbuf chain has been DMA mapped, fix last descriptor */
1100 if (sc->sc_flags & NFE_40BIT_ADDR) {
1101 desc64->flags |= htole16(NFE_TX_LASTFRAG_V2);
1103 if (sc->sc_flags & NFE_JUMBO_SUP)
1104 flags = NFE_TX_LASTFRAG_V2;
1106 flags = NFE_TX_LASTFRAG_V1;
1107 desc32->flags |= htole16(flags);
1111 * Set NFE_TX_VALID backwards so the hardware doesn't see the
1112 * whole mess until the first descriptor in the map is flagged.
1114 for (i = ctx.nsegs - 1; i >= 0; --i) {
1115 j = (ring->cur + i) % NFE_TX_RING_COUNT;
1116 if (sc->sc_flags & NFE_40BIT_ADDR) {
1117 desc64 = &ring->desc64[j];
1118 desc64->flags |= htole16(NFE_TX_VALID);
1120 desc32 = &ring->desc32[j];
1121 desc32->flags |= htole16(NFE_TX_VALID);
1124 ring->cur = (ring->cur + ctx.nsegs) % NFE_TX_RING_COUNT;
1126 /* Exchange DMA map */
1127 data_map->map = data->map;
1131 bus_dmamap_sync(ring->data_tag, map, BUS_DMASYNC_PREWRITE);
1139 nfe_start(struct ifnet *ifp)
1141 struct nfe_softc *sc = ifp->if_softc;
1142 struct nfe_tx_ring *ring = &sc->txq;
1146 if (ifp->if_flags & IFF_OACTIVE)
1149 if (ifq_is_empty(&ifp->if_snd))
1153 m0 = ifq_dequeue(&ifp->if_snd, NULL);
1159 if (nfe_encap(sc, ring, m0) != 0) {
1160 ifp->if_flags |= IFF_OACTIVE;
1167 * `m0' may be freed in nfe_encap(), so
1168 * it should not be touched any more.
1171 if (count == 0) /* nothing sent */
1174 /* Sync TX descriptor ring */
1175 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1178 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl);
1181 * Set a timeout in case the chip goes out to lunch.
1187 nfe_watchdog(struct ifnet *ifp)
1189 struct nfe_softc *sc = ifp->if_softc;
1191 if (ifp->if_flags & IFF_RUNNING) {
1192 if_printf(ifp, "watchdog timeout - lost interrupt recovered\n");
1197 if_printf(ifp, "watchdog timeout\n");
1199 nfe_init(ifp->if_softc);
1207 struct nfe_softc *sc = xsc;
1208 struct ifnet *ifp = &sc->arpcom.ac_if;
1216 * Switching between jumbo frames and normal frames should
1217 * be done _after_ nfe_stop() but _before_ nfe_init_rx_ring().
1219 if (ifp->if_mtu > ETHERMTU) {
1220 sc->sc_flags |= NFE_USE_JUMBO;
1221 sc->rxq.bufsz = NFE_JBYTES;
1223 if_printf(ifp, "use jumbo frames\n");
1225 sc->sc_flags &= ~NFE_USE_JUMBO;
1226 sc->rxq.bufsz = MCLBYTES;
1228 if_printf(ifp, "use non-jumbo frames\n");
1231 error = nfe_init_tx_ring(sc, &sc->txq);
1237 error = nfe_init_rx_ring(sc, &sc->rxq);
1243 NFE_WRITE(sc, NFE_TX_UNK, 0);
1244 NFE_WRITE(sc, NFE_STATUS, 0);
1246 sc->rxtxctl = NFE_RXTX_BIT2;
1247 if (sc->sc_flags & NFE_40BIT_ADDR)
1248 sc->rxtxctl |= NFE_RXTX_V3MAGIC;
1249 else if (sc->sc_flags & NFE_JUMBO_SUP)
1250 sc->rxtxctl |= NFE_RXTX_V2MAGIC;
1252 if (ifp->if_capenable & IFCAP_RXCSUM)
1253 sc->rxtxctl |= NFE_RXTX_RXCSUM;
1256 * Although the adapter is capable of stripping VLAN tags from received
1257 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on
1258 * purpose. This will be done in software by our network stack.
1260 if (sc->sc_flags & NFE_HW_VLAN)
1261 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT;
1263 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl);
1265 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1267 if (sc->sc_flags & NFE_HW_VLAN)
1268 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE);
1270 NFE_WRITE(sc, NFE_SETUP_R6, 0);
1272 /* set MAC address */
1273 nfe_set_macaddr(sc, sc->arpcom.ac_enaddr);
1275 /* tell MAC where rings are in memory */
1277 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32);
1279 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff);
1281 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32);
1283 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff);
1285 NFE_WRITE(sc, NFE_RING_SIZE,
1286 (nfe_rx_ring_count - 1) << 16 |
1287 (NFE_TX_RING_COUNT - 1));
1289 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz);
1291 /* force MAC to wakeup */
1292 tmp = NFE_READ(sc, NFE_PWR_STATE);
1293 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP);
1295 tmp = NFE_READ(sc, NFE_PWR_STATE);
1296 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID);
1299 * NFE_IMTIMER generates a periodic interrupt via NFE_IRQ_TIMER.
1300 * It is unclear how wide the timer is. Base programming does
1301 * not seem to effect NFE_IRQ_TX_DONE or NFE_IRQ_RX_DONE so
1302 * we don't get any interrupt moderation. TX moderation is
1303 * possible by using the timer interrupt instead of TX_DONE.
1305 * It is unclear whether there are other bits that can be
1306 * set to make the NFE device actually do interrupt moderation
1309 * For now set a 128uS interval as a placemark, but don't use
1312 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT);
1314 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC);
1315 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC);
1316 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC);
1318 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */
1319 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC);
1321 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC);
1322 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC);
1324 sc->rxtxctl &= ~NFE_RXTX_BIT2;
1325 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1327 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl);
1332 nfe_ifmedia_upd(ifp);
1335 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START);
1338 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START);
1340 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1342 #ifdef DEVICE_POLLING
1343 if ((ifp->if_flags & IFF_POLLING) == 0)
1345 /* enable interrupts */
1346 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED);
1348 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
1350 ifp->if_flags |= IFF_RUNNING;
1351 ifp->if_flags &= ~IFF_OACTIVE;
1354 * If we had stuff in the tx ring before its all cleaned out now
1355 * so we are not going to get an interrupt, jump-start any pending
1362 nfe_stop(struct nfe_softc *sc)
1364 struct ifnet *ifp = &sc->arpcom.ac_if;
1366 callout_stop(&sc->sc_tick_ch);
1369 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1372 * Are NFE_TX_CTL and NFE_RX_CTL polled by the chip microcontroller
1373 * or do they directly reset/terminate the DMA hardware? Nobody
1378 * (1) Delay before zeroing out NFE_TX_CTL. This seems to help a
1379 * watchdog timeout that occurs after a stop/init sequence. I am
1380 * theorizing that a TX KICK occuring just prior to a reinit (e.g.
1381 * due to dhclient) is queueing an interrupt to the microcontroller
1382 * which gets delayed until after we clear the control registers
1383 * down below, resulting in mass confusion. TX KICK is clearly
1384 * hardware aided whereas the other bits in the control register
1385 * are more likely to be polled by the microcontroller.
1387 * (2) Delay after zeroing out TX and RX CTL registers, under the
1388 * assumption that primary DMA is initiated and terminated by
1389 * the microcontroller and not hardware (and anyway, one can hardly
1390 * expect the DMA engine to just instantly stop!). We don't want
1391 * to rip the rings out from under it before it has had a chance to
1397 NFE_WRITE(sc, NFE_TX_CTL, 0);
1400 NFE_WRITE(sc, NFE_RX_CTL, 0);
1402 /* Disable interrupts */
1403 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
1407 /* Reset Tx and Rx rings */
1408 nfe_reset_tx_ring(sc, &sc->txq);
1409 nfe_reset_rx_ring(sc, &sc->rxq);
1413 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1415 int i, j, error, descsize;
1418 if (sc->sc_flags & NFE_40BIT_ADDR) {
1419 desc = (void **)&ring->desc64;
1420 descsize = sizeof(struct nfe_desc64);
1422 desc = (void **)&ring->desc32;
1423 descsize = sizeof(struct nfe_desc32);
1426 ring->jbuf = kmalloc(sizeof(struct nfe_jbuf) * NFE_JPOOL_COUNT,
1427 M_DEVBUF, M_WAITOK | M_ZERO);
1428 ring->data = kmalloc(sizeof(struct nfe_rx_data) * nfe_rx_ring_count,
1429 M_DEVBUF, M_WAITOK | M_ZERO);
1431 ring->bufsz = MCLBYTES;
1432 ring->cur = ring->next = 0;
1434 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1435 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1437 nfe_rx_ring_count * descsize, 1,
1438 nfe_rx_ring_count * descsize,
1441 if_printf(&sc->arpcom.ac_if,
1442 "could not create desc RX DMA tag\n");
1446 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1449 if_printf(&sc->arpcom.ac_if,
1450 "could not allocate RX desc DMA memory\n");
1451 bus_dma_tag_destroy(ring->tag);
1456 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1457 nfe_rx_ring_count * descsize,
1458 nfe_ring_dma_addr, &ring->physaddr,
1461 if_printf(&sc->arpcom.ac_if,
1462 "could not load RX desc DMA map\n");
1463 bus_dmamem_free(ring->tag, *desc, ring->map);
1464 bus_dma_tag_destroy(ring->tag);
1469 if (sc->sc_flags & NFE_JUMBO_SUP) {
1470 error = nfe_jpool_alloc(sc, ring);
1472 if_printf(&sc->arpcom.ac_if,
1473 "could not allocate jumbo frames\n");
1478 error = bus_dma_tag_create(NULL, 1, 0,
1479 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1481 MCLBYTES, 1, MCLBYTES,
1482 0, &ring->data_tag);
1484 if_printf(&sc->arpcom.ac_if,
1485 "could not create RX mbuf DMA tag\n");
1489 /* Create a spare RX mbuf DMA map */
1490 error = bus_dmamap_create(ring->data_tag, 0, &ring->data_tmpmap);
1492 if_printf(&sc->arpcom.ac_if,
1493 "could not create spare RX mbuf DMA map\n");
1494 bus_dma_tag_destroy(ring->data_tag);
1495 ring->data_tag = NULL;
1499 for (i = 0; i < nfe_rx_ring_count; i++) {
1500 error = bus_dmamap_create(ring->data_tag, 0,
1501 &ring->data[i].map);
1503 if_printf(&sc->arpcom.ac_if,
1504 "could not create %dth RX mbuf DMA mapn", i);
1510 for (j = 0; j < i; ++j)
1511 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1512 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1513 bus_dma_tag_destroy(ring->data_tag);
1514 ring->data_tag = NULL;
1519 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1523 for (i = 0; i < nfe_rx_ring_count; i++) {
1524 struct nfe_rx_data *data = &ring->data[i];
1526 if (data->m != NULL) {
1527 if ((sc->sc_flags & NFE_USE_JUMBO) == 0)
1528 bus_dmamap_unload(ring->data_tag, data->map);
1533 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1535 ring->cur = ring->next = 0;
1539 nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1543 for (i = 0; i < nfe_rx_ring_count; ++i) {
1546 /* XXX should use a function pointer */
1547 if (sc->sc_flags & NFE_USE_JUMBO)
1548 error = nfe_newbuf_jumbo(sc, ring, i, 1);
1550 error = nfe_newbuf_std(sc, ring, i, 1);
1552 if_printf(&sc->arpcom.ac_if,
1553 "could not allocate RX buffer\n");
1557 nfe_set_ready_rxdesc(sc, ring, i);
1559 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1565 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1567 if (ring->data_tag != NULL) {
1568 struct nfe_rx_data *data;
1571 for (i = 0; i < nfe_rx_ring_count; i++) {
1572 data = &ring->data[i];
1574 if (data->m != NULL) {
1575 bus_dmamap_unload(ring->data_tag, data->map);
1578 bus_dmamap_destroy(ring->data_tag, data->map);
1580 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1581 bus_dma_tag_destroy(ring->data_tag);
1584 nfe_jpool_free(sc, ring);
1586 if (ring->jbuf != NULL)
1587 kfree(ring->jbuf, M_DEVBUF);
1588 if (ring->data != NULL)
1589 kfree(ring->data, M_DEVBUF);
1591 if (ring->tag != NULL) {
1594 if (sc->sc_flags & NFE_40BIT_ADDR)
1595 desc = ring->desc64;
1597 desc = ring->desc32;
1599 bus_dmamap_unload(ring->tag, ring->map);
1600 bus_dmamem_free(ring->tag, desc, ring->map);
1601 bus_dma_tag_destroy(ring->tag);
1605 static struct nfe_jbuf *
1606 nfe_jalloc(struct nfe_softc *sc)
1608 struct ifnet *ifp = &sc->arpcom.ac_if;
1609 struct nfe_jbuf *jbuf;
1611 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1613 jbuf = SLIST_FIRST(&sc->rxq.jfreelist);
1615 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext);
1618 if_printf(ifp, "no free jumbo buffer\n");
1621 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1627 nfe_jfree(void *arg)
1629 struct nfe_jbuf *jbuf = arg;
1630 struct nfe_softc *sc = jbuf->sc;
1631 struct nfe_rx_ring *ring = jbuf->ring;
1633 if (&ring->jbuf[jbuf->slot] != jbuf)
1634 panic("%s: free wrong jumbo buffer\n", __func__);
1635 else if (jbuf->inuse == 0)
1636 panic("%s: jumbo buffer already freed\n", __func__);
1638 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1639 atomic_subtract_int(&jbuf->inuse, 1);
1640 if (jbuf->inuse == 0)
1641 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1642 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1648 struct nfe_jbuf *jbuf = arg;
1649 struct nfe_rx_ring *ring = jbuf->ring;
1651 if (&ring->jbuf[jbuf->slot] != jbuf)
1652 panic("%s: ref wrong jumbo buffer\n", __func__);
1653 else if (jbuf->inuse == 0)
1654 panic("%s: jumbo buffer already freed\n", __func__);
1656 atomic_add_int(&jbuf->inuse, 1);
1660 nfe_jpool_alloc(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1662 struct nfe_jbuf *jbuf;
1663 bus_addr_t physaddr;
1668 * Allocate a big chunk of DMA'able memory.
1670 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1671 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1673 NFE_JPOOL_SIZE, 1, NFE_JPOOL_SIZE,
1676 if_printf(&sc->arpcom.ac_if,
1677 "could not create jumbo DMA tag\n");
1681 error = bus_dmamem_alloc(ring->jtag, (void **)&ring->jpool,
1682 BUS_DMA_WAITOK, &ring->jmap);
1684 if_printf(&sc->arpcom.ac_if,
1685 "could not allocate jumbo DMA memory\n");
1686 bus_dma_tag_destroy(ring->jtag);
1691 error = bus_dmamap_load(ring->jtag, ring->jmap, ring->jpool,
1692 NFE_JPOOL_SIZE, nfe_ring_dma_addr, &physaddr,
1695 if_printf(&sc->arpcom.ac_if,
1696 "could not load jumbo DMA map\n");
1697 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1698 bus_dma_tag_destroy(ring->jtag);
1703 /* ..and split it into 9KB chunks */
1704 SLIST_INIT(&ring->jfreelist);
1707 for (i = 0; i < NFE_JPOOL_COUNT; i++) {
1708 jbuf = &ring->jbuf[i];
1715 jbuf->physaddr = physaddr;
1717 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1720 physaddr += NFE_JBYTES;
1727 nfe_jpool_free(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1729 if (ring->jtag != NULL) {
1730 bus_dmamap_unload(ring->jtag, ring->jmap);
1731 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1732 bus_dma_tag_destroy(ring->jtag);
1737 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1739 int i, j, error, descsize;
1742 if (sc->sc_flags & NFE_40BIT_ADDR) {
1743 desc = (void **)&ring->desc64;
1744 descsize = sizeof(struct nfe_desc64);
1746 desc = (void **)&ring->desc32;
1747 descsize = sizeof(struct nfe_desc32);
1751 ring->cur = ring->next = 0;
1753 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1754 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1756 NFE_TX_RING_COUNT * descsize, 1,
1757 NFE_TX_RING_COUNT * descsize,
1760 if_printf(&sc->arpcom.ac_if,
1761 "could not create TX desc DMA map\n");
1765 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1768 if_printf(&sc->arpcom.ac_if,
1769 "could not allocate TX desc DMA memory\n");
1770 bus_dma_tag_destroy(ring->tag);
1775 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1776 NFE_TX_RING_COUNT * descsize,
1777 nfe_ring_dma_addr, &ring->physaddr,
1780 if_printf(&sc->arpcom.ac_if,
1781 "could not load TX desc DMA map\n");
1782 bus_dmamem_free(ring->tag, *desc, ring->map);
1783 bus_dma_tag_destroy(ring->tag);
1788 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1789 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1791 NFE_JBYTES * NFE_MAX_SCATTER,
1792 NFE_MAX_SCATTER, NFE_JBYTES,
1793 0, &ring->data_tag);
1795 if_printf(&sc->arpcom.ac_if,
1796 "could not create TX buf DMA tag\n");
1800 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1801 error = bus_dmamap_create(ring->data_tag, 0,
1802 &ring->data[i].map);
1804 if_printf(&sc->arpcom.ac_if,
1805 "could not create %dth TX buf DMA map\n", i);
1812 for (j = 0; j < i; ++j)
1813 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1814 bus_dma_tag_destroy(ring->data_tag);
1815 ring->data_tag = NULL;
1820 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1824 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1825 struct nfe_tx_data *data = &ring->data[i];
1827 if (sc->sc_flags & NFE_40BIT_ADDR)
1828 ring->desc64[i].flags = 0;
1830 ring->desc32[i].flags = 0;
1832 if (data->m != NULL) {
1833 bus_dmamap_sync(ring->data_tag, data->map,
1834 BUS_DMASYNC_POSTWRITE);
1835 bus_dmamap_unload(ring->data_tag, data->map);
1840 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1843 ring->cur = ring->next = 0;
1847 nfe_init_tx_ring(struct nfe_softc *sc __unused,
1848 struct nfe_tx_ring *ring __unused)
1854 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1856 if (ring->data_tag != NULL) {
1857 struct nfe_tx_data *data;
1860 for (i = 0; i < NFE_TX_RING_COUNT; ++i) {
1861 data = &ring->data[i];
1863 if (data->m != NULL) {
1864 bus_dmamap_unload(ring->data_tag, data->map);
1867 bus_dmamap_destroy(ring->data_tag, data->map);
1870 bus_dma_tag_destroy(ring->data_tag);
1873 if (ring->tag != NULL) {
1876 if (sc->sc_flags & NFE_40BIT_ADDR)
1877 desc = ring->desc64;
1879 desc = ring->desc32;
1881 bus_dmamap_unload(ring->tag, ring->map);
1882 bus_dmamem_free(ring->tag, desc, ring->map);
1883 bus_dma_tag_destroy(ring->tag);
1888 nfe_ifmedia_upd(struct ifnet *ifp)
1890 struct nfe_softc *sc = ifp->if_softc;
1891 struct mii_data *mii = device_get_softc(sc->sc_miibus);
1893 if (mii->mii_instance != 0) {
1894 struct mii_softc *miisc;
1896 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1897 mii_phy_reset(miisc);
1905 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1907 struct nfe_softc *sc = ifp->if_softc;
1908 struct mii_data *mii = device_get_softc(sc->sc_miibus);
1911 ifmr->ifm_status = mii->mii_media_status;
1912 ifmr->ifm_active = mii->mii_media_active;
1916 nfe_setmulti(struct nfe_softc *sc)
1918 struct ifnet *ifp = &sc->arpcom.ac_if;
1919 struct ifmultiaddr *ifma;
1920 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN];
1921 uint32_t filter = NFE_RXFILTER_MAGIC;
1924 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
1925 bzero(addr, ETHER_ADDR_LEN);
1926 bzero(mask, ETHER_ADDR_LEN);
1930 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN);
1931 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN);
1933 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1936 if (ifma->ifma_addr->sa_family != AF_LINK)
1939 maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
1940 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1941 addr[i] &= maddr[i];
1942 mask[i] &= ~maddr[i];
1946 for (i = 0; i < ETHER_ADDR_LEN; i++)
1950 addr[0] |= 0x01; /* make sure multicast bit is set */
1952 NFE_WRITE(sc, NFE_MULTIADDR_HI,
1953 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
1954 NFE_WRITE(sc, NFE_MULTIADDR_LO,
1955 addr[5] << 8 | addr[4]);
1956 NFE_WRITE(sc, NFE_MULTIMASK_HI,
1957 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]);
1958 NFE_WRITE(sc, NFE_MULTIMASK_LO,
1959 mask[5] << 8 | mask[4]);
1961 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M;
1962 NFE_WRITE(sc, NFE_RXFILTER, filter);
1966 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr)
1970 tmp = NFE_READ(sc, NFE_MACADDR_LO);
1971 addr[0] = (tmp >> 8) & 0xff;
1972 addr[1] = (tmp & 0xff);
1974 tmp = NFE_READ(sc, NFE_MACADDR_HI);
1975 addr[2] = (tmp >> 24) & 0xff;
1976 addr[3] = (tmp >> 16) & 0xff;
1977 addr[4] = (tmp >> 8) & 0xff;
1978 addr[5] = (tmp & 0xff);
1982 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr)
1984 NFE_WRITE(sc, NFE_MACADDR_LO,
1985 addr[5] << 8 | addr[4]);
1986 NFE_WRITE(sc, NFE_MACADDR_HI,
1987 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
1993 struct nfe_softc *sc = arg;
1994 struct ifnet *ifp = &sc->arpcom.ac_if;
1995 struct mii_data *mii = device_get_softc(sc->sc_miibus);
1997 lwkt_serialize_enter(ifp->if_serializer);
2000 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
2002 lwkt_serialize_exit(ifp->if_serializer);
2006 nfe_ring_dma_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2011 KASSERT(nseg == 1, ("too many segments, should be 1\n"));
2013 *((uint32_t *)arg) = seg->ds_addr;
2017 nfe_buf_dma_addr(void *arg, bus_dma_segment_t *segs, int nsegs,
2018 bus_size_t mapsz __unused, int error)
2020 struct nfe_dma_ctx *ctx = arg;
2026 KASSERT(nsegs <= ctx->nsegs,
2027 ("too many segments(%d), should be <= %d\n",
2028 nsegs, ctx->nsegs));
2031 for (i = 0; i < nsegs; ++i)
2032 ctx->segs[i] = segs[i];
2036 nfe_newbuf_std(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2039 struct nfe_rx_data *data = &ring->data[idx];
2040 struct nfe_dma_ctx ctx;
2041 bus_dma_segment_t seg;
2046 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2049 m->m_len = m->m_pkthdr.len = MCLBYTES;
2053 error = bus_dmamap_load_mbuf(ring->data_tag, ring->data_tmpmap,
2054 m, nfe_buf_dma_addr, &ctx,
2055 wait ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
2058 if_printf(&sc->arpcom.ac_if, "could map RX mbuf %d\n", error);
2062 /* Unload originally mapped mbuf */
2063 bus_dmamap_unload(ring->data_tag, data->map);
2065 /* Swap this DMA map with tmp DMA map */
2067 data->map = ring->data_tmpmap;
2068 ring->data_tmpmap = map;
2070 /* Caller is assumed to have collected the old mbuf */
2073 nfe_set_paddr_rxdesc(sc, ring, idx, seg.ds_addr);
2075 bus_dmamap_sync(ring->data_tag, data->map, BUS_DMASYNC_PREREAD);
2080 nfe_newbuf_jumbo(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2083 struct nfe_rx_data *data = &ring->data[idx];
2084 struct nfe_jbuf *jbuf;
2087 MGETHDR(m, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA);
2091 jbuf = nfe_jalloc(sc);
2094 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
2095 "-- packet dropped!\n");
2099 m->m_ext.ext_arg = jbuf;
2100 m->m_ext.ext_buf = jbuf->buf;
2101 m->m_ext.ext_free = nfe_jfree;
2102 m->m_ext.ext_ref = nfe_jref;
2103 m->m_ext.ext_size = NFE_JBYTES;
2105 m->m_data = m->m_ext.ext_buf;
2106 m->m_flags |= M_EXT;
2107 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
2109 /* Caller is assumed to have collected the old mbuf */
2112 nfe_set_paddr_rxdesc(sc, ring, idx, jbuf->physaddr);
2114 bus_dmamap_sync(ring->jtag, ring->jmap, BUS_DMASYNC_PREREAD);
2119 nfe_set_paddr_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2120 bus_addr_t physaddr)
2122 if (sc->sc_flags & NFE_40BIT_ADDR) {
2123 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2125 #if defined(__LP64__)
2126 desc64->physaddr[0] = htole32(physaddr >> 32);
2128 desc64->physaddr[1] = htole32(physaddr & 0xffffffff);
2130 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2132 desc32->physaddr = htole32(physaddr);
2137 nfe_set_ready_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx)
2139 if (sc->sc_flags & NFE_40BIT_ADDR) {
2140 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2142 desc64->length = htole16(ring->bufsz);
2143 desc64->flags = htole16(NFE_RX_READY);
2145 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2147 desc32->length = htole16(ring->bufsz);
2148 desc32->flags = htole16(NFE_RX_READY);