2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_ti.c,v 1.25.2.14 2002/02/15 04:20:20 silby Exp $
33 * $DragonFly: src/sys/dev/netif/ti/if_ti.c,v 1.14 2004/07/29 08:46:23 dillon Exp $
35 * $FreeBSD: src/sys/pci/if_ti.c,v 1.25.2.14 2002/02/15 04:20:20 silby Exp $
39 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
40 * Manuals, sample driver and firmware source kits are available
41 * from http://www.alteon.com/support/openkits.
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
49 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
50 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
51 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
52 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
53 * filtering and jumbo (9014 byte) frames. The hardware is largely
54 * controlled by firmware, which must be loaded into the NIC during
57 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
58 * revision, which supports new features such as extended commands,
59 * extended jumbo receive ring desciptors and a mini receive ring.
61 * Alteon Networks is to be commended for releasing such a vast amount
62 * of development material for the Tigon NIC without requiring an NDA
63 * (although they really should have done it a long time ago). With
64 * any luck, the other vendors will finally wise up and follow Alteon's
67 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
68 * this driver by #including it as a C header file. This bloats the
69 * driver somewhat, but it's the easiest method considering that the
70 * driver code and firmware code need to be kept in sync. The source
71 * for the firmware is not provided with the FreeBSD distribution since
72 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
74 * The following people deserve special thanks:
75 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
77 * - Raymond Lee of Netgear, for providing a pair of Netgear
78 * GA620 Tigon 2 boards for testing
79 * - Ulf Zimmermann, for bringing the GA260 to my attention and
80 * convincing me to write this driver.
81 * - Andrew Gallatin for providing FreeBSD/Alpha support.
84 #include <sys/param.h>
85 #include <sys/systm.h>
86 #include <sys/sockio.h>
88 #include <sys/malloc.h>
89 #include <sys/kernel.h>
90 #include <sys/socket.h>
91 #include <sys/queue.h>
94 #include <net/if_arp.h>
95 #include <net/ethernet.h>
96 #include <net/if_dl.h>
97 #include <net/if_media.h>
98 #include <net/if_types.h>
99 #include <net/vlan/if_vlan_var.h>
103 #include <netinet/in_systm.h>
104 #include <netinet/in.h>
105 #include <netinet/ip.h>
107 #include <vm/vm.h> /* for vtophys */
108 #include <vm/pmap.h> /* for vtophys */
109 #include <machine/clock.h> /* for DELAY */
110 #include <machine/bus_memio.h>
111 #include <machine/bus.h>
112 #include <machine/resource.h>
114 #include <sys/rman.h>
116 #include <bus/pci/pcireg.h>
117 #include <bus/pci/pcivar.h>
119 #include "if_tireg.h"
124 * Temporarily disable the checksum offload support for now.
125 * Tests with ftp.freesoftware.com show that after about 12 hours,
126 * the firmware will begin calculating completely bogus TX checksums
127 * and refuse to stop until the interface is reset. Unfortunately,
128 * there isn't enough time to fully debug this before the 4.1
129 * release, so this will need to stay off for now.
132 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
134 #define TI_CSUM_FEATURES 0
138 * Various supported device vendors/types and their names.
141 static struct ti_type ti_devs[] = {
142 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
143 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
144 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
145 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
146 { TC_VENDORID, TC_DEVICEID_3C985,
147 "3Com 3c985-SX Gigabit Ethernet" },
148 { NG_VENDORID, NG_DEVICEID_GA620,
149 "Netgear GA620 1000baseSX Gigabit Ethernet" },
150 { NG_VENDORID, NG_DEVICEID_GA620T,
151 "Netgear GA620 1000baseT Gigabit Ethernet" },
152 { SGI_VENDORID, SGI_DEVICEID_TIGON,
153 "Silicon Graphics Gigabit Ethernet" },
154 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
155 "Farallon PN9000SX Gigabit Ethernet" },
159 static int ti_probe (device_t);
160 static int ti_attach (device_t);
161 static int ti_detach (device_t);
162 static void ti_txeof (struct ti_softc *);
163 static void ti_rxeof (struct ti_softc *);
165 static void ti_stats_update (struct ti_softc *);
166 static int ti_encap (struct ti_softc *, struct mbuf *,
169 static void ti_intr (void *);
170 static void ti_start (struct ifnet *);
171 static int ti_ioctl (struct ifnet *, u_long, caddr_t,
173 static void ti_init (void *);
174 static void ti_init2 (struct ti_softc *);
175 static void ti_stop (struct ti_softc *);
176 static void ti_watchdog (struct ifnet *);
177 static void ti_shutdown (device_t);
178 static int ti_ifmedia_upd (struct ifnet *);
179 static void ti_ifmedia_sts (struct ifnet *, struct ifmediareq *);
181 static u_int32_t ti_eeprom_putbyte (struct ti_softc *, int);
182 static u_int8_t ti_eeprom_getbyte (struct ti_softc *,
184 static int ti_read_eeprom (struct ti_softc *, caddr_t, int, int);
186 static void ti_add_mcast (struct ti_softc *, struct ether_addr *);
187 static void ti_del_mcast (struct ti_softc *, struct ether_addr *);
188 static void ti_setmulti (struct ti_softc *);
190 static void ti_mem (struct ti_softc *, u_int32_t,
192 static void ti_loadfw (struct ti_softc *);
193 static void ti_cmd (struct ti_softc *, struct ti_cmd_desc *);
194 static void ti_cmd_ext (struct ti_softc *, struct ti_cmd_desc *,
196 static void ti_handle_events (struct ti_softc *);
197 static int ti_alloc_jumbo_mem (struct ti_softc *);
198 static void *ti_jalloc (struct ti_softc *);
199 static void ti_jfree (caddr_t, u_int);
200 static void ti_jref (caddr_t, u_int);
201 static int ti_newbuf_std (struct ti_softc *, int, struct mbuf *);
202 static int ti_newbuf_mini (struct ti_softc *, int, struct mbuf *);
203 static int ti_newbuf_jumbo (struct ti_softc *, int, struct mbuf *);
204 static int ti_init_rx_ring_std (struct ti_softc *);
205 static void ti_free_rx_ring_std (struct ti_softc *);
206 static int ti_init_rx_ring_jumbo (struct ti_softc *);
207 static void ti_free_rx_ring_jumbo (struct ti_softc *);
208 static int ti_init_rx_ring_mini (struct ti_softc *);
209 static void ti_free_rx_ring_mini (struct ti_softc *);
210 static void ti_free_tx_ring (struct ti_softc *);
211 static int ti_init_tx_ring (struct ti_softc *);
213 static int ti_64bitslot_war (struct ti_softc *);
214 static int ti_chipinit (struct ti_softc *);
215 static int ti_gibinit (struct ti_softc *);
217 static device_method_t ti_methods[] = {
218 /* Device interface */
219 DEVMETHOD(device_probe, ti_probe),
220 DEVMETHOD(device_attach, ti_attach),
221 DEVMETHOD(device_detach, ti_detach),
222 DEVMETHOD(device_shutdown, ti_shutdown),
226 static driver_t ti_driver = {
229 sizeof(struct ti_softc)
232 static devclass_t ti_devclass;
234 DECLARE_DUMMY_MODULE(if_ti);
235 DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0);
238 * Send an instruction or address to the EEPROM, check for ACK.
240 static u_int32_t ti_eeprom_putbyte(sc, byte)
247 * Make sure we're in TX mode.
249 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
252 * Feed in each bit and stobe the clock.
254 for (i = 0x80; i; i >>= 1) {
256 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
258 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
261 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
263 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
269 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
274 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
275 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
276 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
282 * Read a byte of data stored in the EEPROM at address 'addr.'
283 * We have to send two address bytes since the EEPROM can hold
284 * more than 256 bytes of data.
286 static u_int8_t ti_eeprom_getbyte(sc, addr, dest)
297 * Send write control code to EEPROM.
299 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
300 printf("ti%d: failed to send write command, status: %x\n",
301 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
306 * Send first byte of address of byte we want to read.
308 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
309 printf("ti%d: failed to send address, status: %x\n",
310 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
314 * Send second byte address of byte we want to read.
316 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
317 printf("ti%d: failed to send address, status: %x\n",
318 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
325 * Send read control code to EEPROM.
327 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
328 printf("ti%d: failed to send read command, status: %x\n",
329 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
334 * Start reading bits from EEPROM.
336 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
337 for (i = 0x80; i; i >>= 1) {
338 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
340 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
342 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
349 * No ACK generated for read, so just return byte.
358 * Read a sequence of bytes from the EEPROM.
360 static int ti_read_eeprom(sc, dest, off, cnt)
369 for (i = 0; i < cnt; i++) {
370 err = ti_eeprom_getbyte(sc, off + i, &byte);
380 * NIC memory access function. Can be used to either clear a section
381 * of NIC local memory or (if buf is non-NULL) copy data into it.
383 static void ti_mem(sc, addr, len, buf)
388 int segptr, segsize, cnt;
389 caddr_t ti_winbase, ptr;
393 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW);
400 segsize = TI_WINLEN - (segptr % TI_WINLEN);
401 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
403 bzero((char *)ti_winbase + (segptr &
404 (TI_WINLEN - 1)), segsize);
406 bcopy((char *)ptr, (char *)ti_winbase +
407 (segptr & (TI_WINLEN - 1)), segsize);
418 * Load firmware image into the NIC. Check that the firmware revision
419 * is acceptable and see if we want the firmware for the Tigon 1 or
422 static void ti_loadfw(sc)
425 switch(sc->ti_hwrev) {
427 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
428 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
429 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
430 printf("ti%d: firmware revision mismatch; want "
431 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
432 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
433 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
434 tigonFwReleaseMinor, tigonFwReleaseFix);
437 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen,
438 (caddr_t)tigonFwText);
439 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen,
440 (caddr_t)tigonFwData);
441 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen,
442 (caddr_t)tigonFwRodata);
443 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL);
444 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL);
445 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
447 case TI_HWREV_TIGON_II:
448 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
449 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
450 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
451 printf("ti%d: firmware revision mismatch; want "
452 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
453 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
454 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
455 tigon2FwReleaseMinor, tigon2FwReleaseFix);
458 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen,
459 (caddr_t)tigon2FwText);
460 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen,
461 (caddr_t)tigon2FwData);
462 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
463 (caddr_t)tigon2FwRodata);
464 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL);
465 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL);
466 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
469 printf("ti%d: can't load firmware: unknown hardware rev\n",
478 * Send the NIC a command via the command ring.
480 static void ti_cmd(sc, cmd)
482 struct ti_cmd_desc *cmd;
486 if (sc->ti_rdata->ti_cmd_ring == NULL)
489 index = sc->ti_cmd_saved_prodidx;
490 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
491 TI_INC(index, TI_CMD_RING_CNT);
492 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
493 sc->ti_cmd_saved_prodidx = index;
499 * Send the NIC an extended command. The 'len' parameter specifies the
500 * number of command slots to include after the initial command.
502 static void ti_cmd_ext(sc, cmd, arg, len)
504 struct ti_cmd_desc *cmd;
511 if (sc->ti_rdata->ti_cmd_ring == NULL)
514 index = sc->ti_cmd_saved_prodidx;
515 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
516 TI_INC(index, TI_CMD_RING_CNT);
517 for (i = 0; i < len; i++) {
518 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
519 *(u_int32_t *)(&arg[i * 4]));
520 TI_INC(index, TI_CMD_RING_CNT);
522 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
523 sc->ti_cmd_saved_prodidx = index;
529 * Handle events that have triggered interrupts.
531 static void ti_handle_events(sc)
534 struct ti_event_desc *e;
536 if (sc->ti_rdata->ti_event_ring == NULL)
539 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
540 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
541 switch(e->ti_event) {
542 case TI_EV_LINKSTAT_CHANGED:
543 sc->ti_linkstat = e->ti_code;
544 if (e->ti_code == TI_EV_CODE_LINK_UP)
545 printf("ti%d: 10/100 link up\n", sc->ti_unit);
546 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP)
547 printf("ti%d: gigabit link up\n", sc->ti_unit);
548 else if (e->ti_code == TI_EV_CODE_LINK_DOWN)
549 printf("ti%d: link down\n", sc->ti_unit);
552 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD)
553 printf("ti%d: invalid command\n", sc->ti_unit);
554 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD)
555 printf("ti%d: unknown command\n", sc->ti_unit);
556 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG)
557 printf("ti%d: bad config data\n", sc->ti_unit);
559 case TI_EV_FIRMWARE_UP:
562 case TI_EV_STATS_UPDATED:
565 case TI_EV_RESET_JUMBO_RING:
566 case TI_EV_MCAST_UPDATED:
570 printf("ti%d: unknown event: %d\n",
571 sc->ti_unit, e->ti_event);
574 /* Advance the consumer index. */
575 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
576 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
583 * Memory management for the jumbo receive ring is a pain in the
584 * butt. We need to allocate at least 9018 bytes of space per frame,
585 * _and_ it has to be contiguous (unless you use the extended
586 * jumbo descriptor format). Using malloc() all the time won't
587 * work: malloc() allocates memory in powers of two, which means we
588 * would end up wasting a considerable amount of space by allocating
589 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
590 * to do our own memory management.
592 * The driver needs to allocate a contiguous chunk of memory at boot
593 * time. We then chop this up ourselves into 9K pieces and use them
594 * as external mbuf storage.
596 * One issue here is how much memory to allocate. The jumbo ring has
597 * 256 slots in it, but at 9K per slot than can consume over 2MB of
598 * RAM. This is a bit much, especially considering we also need
599 * RAM for the standard ring and mini ring (on the Tigon 2). To
600 * save space, we only actually allocate enough memory for 64 slots
601 * by default, which works out to between 500 and 600K. This can
602 * be tuned by changing a #define in if_tireg.h.
605 static int ti_alloc_jumbo_mem(sc)
610 struct ti_jpool_entry *entry;
612 /* Grab a big chunk o' storage. */
613 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF,
614 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
616 if (sc->ti_cdata.ti_jumbo_buf == NULL) {
617 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit);
621 SLIST_INIT(&sc->ti_jfree_listhead);
622 SLIST_INIT(&sc->ti_jinuse_listhead);
625 * Now divide it up into 9K pieces and save the addresses
626 * in an array. Note that we play an evil trick here by using
627 * the first few bytes in the buffer to hold the the address
628 * of the softc structure for this interface. This is because
629 * ti_jfree() needs it, but it is called by the mbuf management
630 * code which will not pass it to us explicitly.
632 ptr = sc->ti_cdata.ti_jumbo_buf;
633 for (i = 0; i < TI_JSLOTS; i++) {
635 aptr = (u_int64_t **)ptr;
636 aptr[0] = (u_int64_t *)sc;
637 ptr += sizeof(u_int64_t);
638 sc->ti_cdata.ti_jslots[i].ti_buf = ptr;
639 sc->ti_cdata.ti_jslots[i].ti_inuse = 0;
640 ptr += (TI_JLEN - sizeof(u_int64_t));
641 entry = malloc(sizeof(struct ti_jpool_entry),
644 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM,
646 sc->ti_cdata.ti_jumbo_buf = NULL;
647 printf("ti%d: no memory for jumbo "
648 "buffer queue!\n", sc->ti_unit);
652 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
659 * Allocate a jumbo buffer.
661 static void *ti_jalloc(sc)
664 struct ti_jpool_entry *entry;
666 entry = SLIST_FIRST(&sc->ti_jfree_listhead);
669 printf("ti%d: no free jumbo buffers\n", sc->ti_unit);
673 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
674 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
675 sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1;
676 return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf);
680 * Adjust usage count on a jumbo buffer. In general this doesn't
681 * get used much because our jumbo buffers don't get passed around
682 * too much, but it's implemented for correctness.
684 static void ti_jref(buf, size)
692 /* Extract the softc struct pointer. */
693 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
694 sc = (struct ti_softc *)(aptr[0]);
697 panic("ti_jref: can't find softc pointer!");
699 if (size != TI_JUMBO_FRAMELEN)
700 panic("ti_jref: adjusting refcount of buf of wrong size!");
702 /* calculate the slot this buffer belongs to */
704 i = ((vm_offset_t)aptr
705 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
707 if ((i < 0) || (i >= TI_JSLOTS))
708 panic("ti_jref: asked to reference buffer "
709 "that we don't manage!");
710 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0)
711 panic("ti_jref: buffer already free!");
713 sc->ti_cdata.ti_jslots[i].ti_inuse++;
719 * Release a jumbo buffer.
721 static void ti_jfree(buf, size)
728 struct ti_jpool_entry *entry;
730 /* Extract the softc struct pointer. */
731 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
732 sc = (struct ti_softc *)(aptr[0]);
735 panic("ti_jfree: can't find softc pointer!");
737 if (size != TI_JUMBO_FRAMELEN)
738 panic("ti_jfree: freeing buffer of wrong size!");
740 /* calculate the slot this buffer belongs to */
742 i = ((vm_offset_t)aptr
743 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
745 if ((i < 0) || (i >= TI_JSLOTS))
746 panic("ti_jfree: asked to free buffer that we don't manage!");
747 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0)
748 panic("ti_jfree: buffer already free!");
750 sc->ti_cdata.ti_jslots[i].ti_inuse--;
751 if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) {
752 entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
754 panic("ti_jfree: buffer not in use!");
756 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead,
758 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead,
759 entry, jpool_entries);
768 * Intialize a standard receive ring descriptor.
770 static int ti_newbuf_std(sc, i, m)
775 struct mbuf *m_new = NULL;
776 struct ti_rx_desc *r;
779 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
783 MCLGET(m_new, MB_DONTWAIT);
784 if (!(m_new->m_flags & M_EXT)) {
788 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
791 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
792 m_new->m_data = m_new->m_ext.ext_buf;
795 m_adj(m_new, ETHER_ALIGN);
796 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
797 r = &sc->ti_rdata->ti_rx_std_ring[i];
798 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
799 r->ti_type = TI_BDTYPE_RECV_BD;
801 if (sc->arpcom.ac_if.if_hwassist)
802 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
803 r->ti_len = m_new->m_len;
810 * Intialize a mini receive ring descriptor. This only applies to
813 static int ti_newbuf_mini(sc, i, m)
818 struct mbuf *m_new = NULL;
819 struct ti_rx_desc *r;
822 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
826 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
829 m_new->m_data = m_new->m_pktdat;
830 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
833 m_adj(m_new, ETHER_ALIGN);
834 r = &sc->ti_rdata->ti_rx_mini_ring[i];
835 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
836 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
837 r->ti_type = TI_BDTYPE_RECV_BD;
838 r->ti_flags = TI_BDFLAG_MINI_RING;
839 if (sc->arpcom.ac_if.if_hwassist)
840 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
841 r->ti_len = m_new->m_len;
848 * Initialize a jumbo receive ring descriptor. This allocates
849 * a jumbo buffer from the pool managed internally by the driver.
851 static int ti_newbuf_jumbo(sc, i, m)
856 struct mbuf *m_new = NULL;
857 struct ti_rx_desc *r;
862 /* Allocate the mbuf. */
863 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
868 /* Allocate the jumbo buffer */
872 printf("ti%d: jumbo allocation failed "
873 "-- packet dropped!\n", sc->ti_unit);
877 /* Attach the buffer to the mbuf. */
878 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
879 m_new->m_flags |= M_EXT | M_EXT_OLD;
880 m_new->m_len = m_new->m_pkthdr.len =
881 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
882 m_new->m_ext.ext_nfree.old = ti_jfree;
883 m_new->m_ext.ext_nref.old = ti_jref;
886 m_new->m_data = m_new->m_ext.ext_buf;
887 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
890 m_adj(m_new, ETHER_ALIGN);
891 /* Set up the descriptor. */
892 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
893 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
894 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
895 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
896 r->ti_flags = TI_BDFLAG_JUMBO_RING;
897 if (sc->arpcom.ac_if.if_hwassist)
898 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
899 r->ti_len = m_new->m_len;
906 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
907 * that's 1MB or memory, which is a lot. For now, we fill only the first
908 * 256 ring entries and hope that our CPU is fast enough to keep up with
911 static int ti_init_rx_ring_std(sc)
915 struct ti_cmd_desc cmd;
917 for (i = 0; i < TI_SSLOTS; i++) {
918 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
922 TI_UPDATE_STDPROD(sc, i - 1);
928 static void ti_free_rx_ring_std(sc)
933 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
934 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
935 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
936 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
938 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
939 sizeof(struct ti_rx_desc));
945 static int ti_init_rx_ring_jumbo(sc)
949 struct ti_cmd_desc cmd;
951 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
952 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
956 TI_UPDATE_JUMBOPROD(sc, i - 1);
957 sc->ti_jumbo = i - 1;
962 static void ti_free_rx_ring_jumbo(sc)
967 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
968 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
969 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
970 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
972 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
973 sizeof(struct ti_rx_desc));
979 static int ti_init_rx_ring_mini(sc)
984 for (i = 0; i < TI_MSLOTS; i++) {
985 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
989 TI_UPDATE_MINIPROD(sc, i - 1);
995 static void ti_free_rx_ring_mini(sc)
1000 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1001 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1002 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1003 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1005 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
1006 sizeof(struct ti_rx_desc));
1012 static void ti_free_tx_ring(sc)
1013 struct ti_softc *sc;
1017 if (sc->ti_rdata->ti_tx_ring == NULL)
1020 for (i = 0; i < TI_TX_RING_CNT; i++) {
1021 if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
1022 m_freem(sc->ti_cdata.ti_tx_chain[i]);
1023 sc->ti_cdata.ti_tx_chain[i] = NULL;
1025 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
1026 sizeof(struct ti_tx_desc));
1032 static int ti_init_tx_ring(sc)
1033 struct ti_softc *sc;
1036 sc->ti_tx_saved_considx = 0;
1037 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1042 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1043 * but we have to support the old way too so that Tigon 1 cards will
1046 void ti_add_mcast(sc, addr)
1047 struct ti_softc *sc;
1048 struct ether_addr *addr;
1050 struct ti_cmd_desc cmd;
1052 u_int32_t ext[2] = {0, 0};
1054 m = (u_int16_t *)&addr->octet[0];
1056 switch(sc->ti_hwrev) {
1057 case TI_HWREV_TIGON:
1058 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1059 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1060 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1062 case TI_HWREV_TIGON_II:
1063 ext[0] = htons(m[0]);
1064 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1065 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1068 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1075 void ti_del_mcast(sc, addr)
1076 struct ti_softc *sc;
1077 struct ether_addr *addr;
1079 struct ti_cmd_desc cmd;
1081 u_int32_t ext[2] = {0, 0};
1083 m = (u_int16_t *)&addr->octet[0];
1085 switch(sc->ti_hwrev) {
1086 case TI_HWREV_TIGON:
1087 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1088 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1089 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1091 case TI_HWREV_TIGON_II:
1092 ext[0] = htons(m[0]);
1093 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1094 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1097 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1105 * Configure the Tigon's multicast address filter.
1107 * The actual multicast table management is a bit of a pain, thanks to
1108 * slight brain damage on the part of both Alteon and us. With our
1109 * multicast code, we are only alerted when the multicast address table
1110 * changes and at that point we only have the current list of addresses:
1111 * we only know the current state, not the previous state, so we don't
1112 * actually know what addresses were removed or added. The firmware has
1113 * state, but we can't get our grubby mits on it, and there is no 'delete
1114 * all multicast addresses' command. Hence, we have to maintain our own
1115 * state so we know what addresses have been programmed into the NIC at
1118 static void ti_setmulti(sc)
1119 struct ti_softc *sc;
1122 struct ifmultiaddr *ifma;
1123 struct ti_cmd_desc cmd;
1124 struct ti_mc_entry *mc;
1127 ifp = &sc->arpcom.ac_if;
1129 if (ifp->if_flags & IFF_ALLMULTI) {
1130 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1133 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1136 /* Disable interrupts. */
1137 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1138 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1140 /* First, zot all the existing filters. */
1141 while (sc->ti_mc_listhead.slh_first != NULL) {
1142 mc = sc->ti_mc_listhead.slh_first;
1143 ti_del_mcast(sc, &mc->mc_addr);
1144 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1148 /* Now program new ones. */
1149 for (ifma = ifp->if_multiaddrs.lh_first;
1150 ifma != NULL; ifma = ifma->ifma_link.le_next) {
1151 if (ifma->ifma_addr->sa_family != AF_LINK)
1153 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_INTWAIT);
1154 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1155 (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1156 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1157 ti_add_mcast(sc, &mc->mc_addr);
1160 /* Re-enable interrupts. */
1161 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1167 * Check to see if the BIOS has configured us for a 64 bit slot when
1168 * we aren't actually in one. If we detect this condition, we can work
1169 * around it on the Tigon 2 by setting a bit in the PCI state register,
1170 * but for the Tigon 1 we must give up and abort the interface attach.
1172 static int ti_64bitslot_war(sc)
1173 struct ti_softc *sc;
1175 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1176 CSR_WRITE_4(sc, 0x600, 0);
1177 CSR_WRITE_4(sc, 0x604, 0);
1178 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1179 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1180 if (sc->ti_hwrev == TI_HWREV_TIGON)
1183 TI_SETBIT(sc, TI_PCI_STATE,
1184 TI_PCISTATE_32BIT_BUS);
1194 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1195 * self-test results.
1197 static int ti_chipinit(sc)
1198 struct ti_softc *sc;
1200 u_int32_t cacheline;
1201 u_int32_t pci_writemax = 0;
1203 /* Initialize link to down state. */
1204 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1206 if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM)
1207 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES;
1209 sc->arpcom.ac_if.if_hwassist = 0;
1211 /* Set endianness before we access any non-PCI registers. */
1212 #if BYTE_ORDER == BIG_ENDIAN
1213 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1214 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1216 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1217 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1220 /* Check the ROM failed bit to see if self-tests passed. */
1221 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1222 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit);
1227 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1229 /* Figure out the hardware revision. */
1230 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1231 case TI_REV_TIGON_I:
1232 sc->ti_hwrev = TI_HWREV_TIGON;
1234 case TI_REV_TIGON_II:
1235 sc->ti_hwrev = TI_HWREV_TIGON_II;
1238 printf("ti%d: unsupported chip revision\n", sc->ti_unit);
1242 /* Do special setup for Tigon 2. */
1243 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1244 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1245 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
1246 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1249 /* Set up the PCI state register. */
1250 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1251 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1252 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1255 /* Clear the read/write max DMA parameters. */
1256 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1257 TI_PCISTATE_READ_MAXDMA));
1259 /* Get cache line size. */
1260 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1263 * If the system has set enabled the PCI memory write
1264 * and invalidate command in the command register, set
1265 * the write max parameter accordingly. This is necessary
1266 * to use MWI with the Tigon 2.
1268 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1278 /* Disable PCI memory write and invalidate. */
1280 printf("ti%d: cache line size %d not "
1281 "supported; disabling PCI MWI\n",
1282 sc->ti_unit, cacheline);
1283 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1284 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
1289 #ifdef __brokenalpha__
1291 * From the Alteon sample driver:
1292 * Must insure that we do not cross an 8K (bytes) boundary
1293 * for DMA reads. Our highest limit is 1K bytes. This is a
1294 * restriction on some ALPHA platforms with early revision
1295 * 21174 PCI chipsets, such as the AlphaPC 164lx
1297 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024);
1299 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1302 /* This sets the min dma param all the way up (0xff). */
1303 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1305 /* Configure DMA variables. */
1306 #if BYTE_ORDER == BIG_ENDIAN
1307 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1308 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1309 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1310 TI_OPMODE_DONT_FRAG_JUMBO);
1312 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
1313 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
1314 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB);
1318 * Only allow 1 DMA channel to be active at a time.
1319 * I don't think this is a good idea, but without it
1320 * the firmware racks up lots of nicDmaReadRingFull
1321 * errors. This is not compatible with hardware checksums.
1323 if (sc->arpcom.ac_if.if_hwassist == 0)
1324 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1326 /* Recommended settings from Tigon manual. */
1327 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1328 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1330 if (ti_64bitslot_war(sc)) {
1331 printf("ti%d: bios thinks we're in a 64 bit slot, "
1332 "but we aren't", sc->ti_unit);
1340 * Initialize the general information block and firmware, and
1341 * start the CPU(s) running.
1343 static int ti_gibinit(sc)
1344 struct ti_softc *sc;
1350 ifp = &sc->arpcom.ac_if;
1352 /* Disable interrupts for now. */
1353 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1355 /* Tell the chip where to find the general information block. */
1356 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
1357 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info));
1359 /* Load the firmware into SRAM. */
1362 /* Set up the contents of the general info and ring control blocks. */
1364 /* Set up the event ring and producer pointer. */
1365 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
1367 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring);
1369 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
1370 vtophys(&sc->ti_ev_prodidx);
1371 sc->ti_ev_prodidx.ti_idx = 0;
1372 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
1373 sc->ti_ev_saved_considx = 0;
1375 /* Set up the command ring and producer mailbox. */
1376 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
1378 sc->ti_rdata->ti_cmd_ring =
1379 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING);
1380 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
1382 rcb->ti_max_len = 0;
1383 for (i = 0; i < TI_CMD_RING_CNT; i++) {
1384 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
1386 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
1387 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
1388 sc->ti_cmd_saved_prodidx = 0;
1391 * Assign the address of the stats refresh buffer.
1392 * We re-use the current stats buffer for this to
1395 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
1396 vtophys(&sc->ti_rdata->ti_info.ti_stats);
1398 /* Set up the standard receive ring. */
1399 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
1400 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring);
1401 rcb->ti_max_len = TI_FRAMELEN;
1403 if (sc->arpcom.ac_if.if_hwassist)
1404 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1405 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1406 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1408 /* Set up the jumbo receive ring. */
1409 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
1410 TI_HOSTADDR(rcb->ti_hostaddr) =
1411 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring);
1412 rcb->ti_max_len = TI_JUMBO_FRAMELEN;
1414 if (sc->arpcom.ac_if.if_hwassist)
1415 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1416 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1417 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1420 * Set up the mini ring. Only activated on the
1421 * Tigon 2 but the slot in the config block is
1422 * still there on the Tigon 1.
1424 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
1425 TI_HOSTADDR(rcb->ti_hostaddr) =
1426 vtophys(&sc->ti_rdata->ti_rx_mini_ring);
1427 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
1428 if (sc->ti_hwrev == TI_HWREV_TIGON)
1429 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
1432 if (sc->arpcom.ac_if.if_hwassist)
1433 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1434 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1435 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1438 * Set up the receive return ring.
1440 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
1441 TI_HOSTADDR(rcb->ti_hostaddr) =
1442 vtophys(&sc->ti_rdata->ti_rx_return_ring);
1444 rcb->ti_max_len = TI_RETURN_RING_CNT;
1445 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
1446 vtophys(&sc->ti_return_prodidx);
1449 * Set up the tx ring. Note: for the Tigon 2, we have the option
1450 * of putting the transmit ring in the host's address space and
1451 * letting the chip DMA it instead of leaving the ring in the NIC's
1452 * memory and accessing it through the shared memory region. We
1453 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
1454 * so we have to revert to the shared memory scheme if we detect
1457 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
1458 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1459 sc->ti_rdata->ti_tx_ring_nic =
1460 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW);
1462 bzero((char *)sc->ti_rdata->ti_tx_ring,
1463 TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
1464 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
1465 if (sc->ti_hwrev == TI_HWREV_TIGON)
1468 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
1469 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1470 if (sc->arpcom.ac_if.if_hwassist)
1471 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1472 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1473 rcb->ti_max_len = TI_TX_RING_CNT;
1474 if (sc->ti_hwrev == TI_HWREV_TIGON)
1475 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
1477 TI_HOSTADDR(rcb->ti_hostaddr) =
1478 vtophys(&sc->ti_rdata->ti_tx_ring);
1479 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
1480 vtophys(&sc->ti_tx_considx);
1482 /* Set up tuneables */
1483 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
1484 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
1485 (sc->ti_rx_coal_ticks / 10));
1487 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
1488 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
1489 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
1490 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
1491 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
1492 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
1494 /* Turn interrupts on. */
1495 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
1496 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1499 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
1505 * Probe for a Tigon chip. Check the PCI vendor and device IDs
1506 * against our list and return its name if we find a match.
1508 static int ti_probe(dev)
1515 while(t->ti_name != NULL) {
1516 if ((pci_get_vendor(dev) == t->ti_vid) &&
1517 (pci_get_device(dev) == t->ti_did)) {
1518 device_set_desc(dev, t->ti_name);
1527 static int ti_attach(dev)
1533 struct ti_softc *sc;
1534 int unit, error = 0, rid;
1538 sc = device_get_softc(dev);
1539 unit = device_get_unit(dev);
1540 bzero(sc, sizeof(struct ti_softc));
1541 sc->arpcom.ac_if.if_capabilities = IFCAP_HWCSUM;
1542 sc->arpcom.ac_if.if_capenable = sc->arpcom.ac_if.if_capabilities;
1545 * Map control/status registers.
1547 command = pci_read_config(dev, PCIR_COMMAND, 4);
1548 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1549 pci_write_config(dev, PCIR_COMMAND, command, 4);
1550 command = pci_read_config(dev, PCIR_COMMAND, 4);
1552 if (!(command & PCIM_CMD_MEMEN)) {
1553 printf("ti%d: failed to enable memory mapping!\n", unit);
1559 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1560 0, ~0, 1, RF_ACTIVE);
1562 if (sc->ti_res == NULL) {
1563 printf ("ti%d: couldn't map memory\n", unit);
1568 sc->ti_btag = rman_get_bustag(sc->ti_res);
1569 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
1570 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res);
1573 * XXX FIXME: rman_get_virtual() on the alpha is currently
1574 * broken and returns a physical address instead of a kernel
1575 * virtual address. Consequently, we need to do a little
1576 * extra mangling of the vhandle on the alpha. This should
1577 * eventually be fixed! The whole idea here is to get rid
1578 * of platform dependencies.
1581 if (pci_cvt_to_bwx(sc->ti_vhandle))
1582 sc->ti_vhandle = pci_cvt_to_bwx(sc->ti_vhandle);
1584 sc->ti_vhandle = pci_cvt_to_dense(sc->ti_vhandle);
1585 sc->ti_vhandle = ALPHA_PHYS_TO_K0SEG(sc->ti_vhandle);
1588 /* Allocate interrupt */
1591 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1592 RF_SHAREABLE | RF_ACTIVE);
1594 if (sc->ti_irq == NULL) {
1595 printf("ti%d: couldn't map interrupt\n", unit);
1600 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET,
1601 ti_intr, sc, &sc->ti_intrhand);
1604 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1605 bus_release_resource(dev, SYS_RES_MEMORY,
1606 TI_PCI_LOMEM, sc->ti_res);
1607 printf("ti%d: couldn't set up irq\n", unit);
1613 if (ti_chipinit(sc)) {
1614 printf("ti%d: chip initialization failed\n", sc->ti_unit);
1615 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1616 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1617 bus_release_resource(dev, SYS_RES_MEMORY,
1618 TI_PCI_LOMEM, sc->ti_res);
1623 /* Zero out the NIC's on-board SRAM. */
1624 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
1626 /* Init again -- zeroing memory may have clobbered some registers. */
1627 if (ti_chipinit(sc)) {
1628 printf("ti%d: chip initialization failed\n", sc->ti_unit);
1629 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1630 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1631 bus_release_resource(dev, SYS_RES_MEMORY,
1632 TI_PCI_LOMEM, sc->ti_res);
1638 * Get station address from the EEPROM. Note: the manual states
1639 * that the MAC address is at offset 0x8c, however the data is
1640 * stored as two longwords (since that's how it's loaded into
1641 * the NIC). This means the MAC address is actually preceeded
1642 * by two zero bytes. We need to skip over those.
1644 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1645 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1646 printf("ti%d: failed to read station address\n", unit);
1647 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1648 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1649 bus_release_resource(dev, SYS_RES_MEMORY,
1650 TI_PCI_LOMEM, sc->ti_res);
1655 /* Allocate the general information block and ring buffers. */
1656 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF,
1657 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1659 if (sc->ti_rdata == NULL) {
1660 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1661 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1662 bus_release_resource(dev, SYS_RES_MEMORY,
1663 TI_PCI_LOMEM, sc->ti_res);
1665 printf("ti%d: no memory for list buffers!\n", sc->ti_unit);
1669 bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
1671 /* Try to allocate memory for jumbo buffers. */
1672 if (ti_alloc_jumbo_mem(sc)) {
1673 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit);
1674 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1675 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1676 bus_release_resource(dev, SYS_RES_MEMORY,
1677 TI_PCI_LOMEM, sc->ti_res);
1678 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data),
1685 * We really need a better way to tell a 1000baseTX card
1686 * from a 1000baseSX one, since in theory there could be
1687 * OEMed 1000baseTX cards from lame vendors who aren't
1688 * clever enough to change the PCI ID. For the moment
1689 * though, the AceNIC is the only copper card available.
1691 if (pci_get_vendor(dev) == ALT_VENDORID &&
1692 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
1694 /* Ok, it's not the only copper card available. */
1695 if (pci_get_vendor(dev) == NG_VENDORID &&
1696 pci_get_device(dev) == NG_DEVICEID_GA620T)
1699 /* Set default tuneable values. */
1700 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
1701 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
1702 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
1703 sc->ti_rx_max_coal_bds = 64;
1704 sc->ti_tx_max_coal_bds = 128;
1705 sc->ti_tx_buf_ratio = 21;
1707 /* Set up ifnet structure */
1708 ifp = &sc->arpcom.ac_if;
1710 if_initname(ifp, "ti", sc->ti_unit);
1711 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1712 ifp->if_ioctl = ti_ioctl;
1713 ifp->if_start = ti_start;
1714 ifp->if_watchdog = ti_watchdog;
1715 ifp->if_init = ti_init;
1716 ifp->if_mtu = ETHERMTU;
1717 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1;
1719 /* Set up ifmedia support. */
1720 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
1721 if (sc->ti_copper) {
1723 * Copper cards allow manual 10/100 mode selection,
1724 * but not manual 1000baseTX mode selection. Why?
1725 * Becuase currently there's no way to specify the
1726 * master/slave setting through the firmware interface,
1727 * so Alteon decided to just bag it and handle it
1728 * via autonegotiation.
1730 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1731 ifmedia_add(&sc->ifmedia,
1732 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1733 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
1734 ifmedia_add(&sc->ifmedia,
1735 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
1736 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_TX, 0, NULL);
1737 ifmedia_add(&sc->ifmedia,
1738 IFM_ETHER|IFM_1000_TX|IFM_FDX, 0, NULL);
1740 /* Fiber cards don't support 10/100 modes. */
1741 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1742 ifmedia_add(&sc->ifmedia,
1743 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1745 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1746 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
1749 * Call MI attach routine.
1751 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
1759 static int ti_detach(dev)
1762 struct ti_softc *sc;
1768 sc = device_get_softc(dev);
1769 ifp = &sc->arpcom.ac_if;
1771 ether_ifdetach(ifp);
1774 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1775 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1776 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res);
1778 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF);
1779 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF);
1780 ifmedia_removeall(&sc->ifmedia);
1788 * Frame reception handling. This is called if there's a frame
1789 * on the receive return list.
1791 * Note: we have to be able to handle three possibilities here:
1792 * 1) the frame is from the mini receive ring (can only happen)
1793 * on Tigon 2 boards)
1794 * 2) the frame is from the jumbo recieve ring
1795 * 3) the frame is from the standard receive ring
1798 static void ti_rxeof(sc)
1799 struct ti_softc *sc;
1802 struct ti_cmd_desc cmd;
1804 ifp = &sc->arpcom.ac_if;
1806 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
1807 struct ti_rx_desc *cur_rx;
1809 struct mbuf *m = NULL;
1810 u_int16_t vlan_tag = 0;
1814 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
1815 rxidx = cur_rx->ti_idx;
1816 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
1818 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
1820 vlan_tag = cur_rx->ti_vlan_tag & 0xfff;
1823 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
1824 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
1825 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
1826 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
1827 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1829 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1832 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
1834 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1837 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
1838 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
1839 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
1840 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
1841 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1843 ti_newbuf_mini(sc, sc->ti_mini, m);
1846 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
1848 ti_newbuf_mini(sc, sc->ti_mini, m);
1852 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
1853 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
1854 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
1855 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1857 ti_newbuf_std(sc, sc->ti_std, m);
1860 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
1862 ti_newbuf_std(sc, sc->ti_std, m);
1867 m->m_pkthdr.len = m->m_len = cur_rx->ti_len;
1869 m->m_pkthdr.rcvif = ifp;
1871 if (ifp->if_hwassist) {
1872 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1874 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
1875 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1876 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum;
1880 * If we received a packet with a vlan tag, pass it
1881 * to vlan_input() instead of ether_input().
1884 VLAN_INPUT_TAG(m, vlan_tag);
1885 have_tag = vlan_tag = 0;
1887 (*ifp->if_input)(ifp, m);
1891 /* Only necessary on the Tigon 1. */
1892 if (sc->ti_hwrev == TI_HWREV_TIGON)
1893 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
1894 sc->ti_rx_saved_considx);
1896 TI_UPDATE_STDPROD(sc, sc->ti_std);
1897 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
1898 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
1903 static void ti_txeof(sc)
1904 struct ti_softc *sc;
1906 struct ti_tx_desc *cur_tx = NULL;
1909 ifp = &sc->arpcom.ac_if;
1912 * Go through our tx ring and free mbufs for those
1913 * frames that have been sent.
1915 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
1918 idx = sc->ti_tx_saved_considx;
1919 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1921 CSR_WRITE_4(sc, TI_WINBASE,
1922 TI_TX_RING_BASE + 6144);
1924 CSR_WRITE_4(sc, TI_WINBASE,
1925 TI_TX_RING_BASE + 4096);
1927 CSR_WRITE_4(sc, TI_WINBASE,
1928 TI_TX_RING_BASE + 2048);
1930 CSR_WRITE_4(sc, TI_WINBASE,
1932 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128];
1934 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
1935 if (cur_tx->ti_flags & TI_BDFLAG_END)
1937 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
1938 m_freem(sc->ti_cdata.ti_tx_chain[idx]);
1939 sc->ti_cdata.ti_tx_chain[idx] = NULL;
1942 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
1947 ifp->if_flags &= ~IFF_OACTIVE;
1952 static void ti_intr(xsc)
1955 struct ti_softc *sc;
1959 ifp = &sc->arpcom.ac_if;
1962 /* Avoid this for now -- checking this register is expensive. */
1963 /* Make sure this is really our interrupt. */
1964 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE))
1968 /* Ack interrupt and stop others from occuring. */
1969 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1971 if (ifp->if_flags & IFF_RUNNING) {
1972 /* Check RX return ring producer/consumer */
1975 /* Check TX ring producer/consumer */
1979 ti_handle_events(sc);
1981 /* Re-enable interrupts. */
1982 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1984 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
1990 static void ti_stats_update(sc)
1991 struct ti_softc *sc;
1995 ifp = &sc->arpcom.ac_if;
1997 ifp->if_collisions +=
1998 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
1999 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
2000 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
2001 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
2008 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2009 * pointers to descriptors.
2011 static int ti_encap(sc, m_head, txidx)
2012 struct ti_softc *sc;
2013 struct mbuf *m_head;
2016 struct ti_tx_desc *f = NULL;
2018 u_int32_t frag, cur, cnt = 0;
2019 u_int16_t csum_flags = 0;
2020 struct ifvlan *ifv = NULL;
2022 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2023 m_head->m_pkthdr.rcvif != NULL &&
2024 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2025 ifv = m_head->m_pkthdr.rcvif->if_softc;
2028 cur = frag = *txidx;
2030 if (m_head->m_pkthdr.csum_flags) {
2031 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2032 csum_flags |= TI_BDFLAG_IP_CKSUM;
2033 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2034 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
2035 if (m_head->m_flags & M_LASTFRAG)
2036 csum_flags |= TI_BDFLAG_IP_FRAG_END;
2037 else if (m_head->m_flags & M_FRAG)
2038 csum_flags |= TI_BDFLAG_IP_FRAG;
2041 * Start packing the mbufs in this chain into
2042 * the fragment pointers. Stop when we run out
2043 * of fragments or hit the end of the mbuf chain.
2045 for (m = m_head; m != NULL; m = m->m_next) {
2046 if (m->m_len != 0) {
2047 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2049 CSR_WRITE_4(sc, TI_WINBASE,
2050 TI_TX_RING_BASE + 6144);
2051 else if (frag > 255)
2052 CSR_WRITE_4(sc, TI_WINBASE,
2053 TI_TX_RING_BASE + 4096);
2054 else if (frag > 127)
2055 CSR_WRITE_4(sc, TI_WINBASE,
2056 TI_TX_RING_BASE + 2048);
2058 CSR_WRITE_4(sc, TI_WINBASE,
2060 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128];
2062 f = &sc->ti_rdata->ti_tx_ring[frag];
2063 if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
2065 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t));
2066 f->ti_len = m->m_len;
2067 f->ti_flags = csum_flags;
2070 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
2071 f->ti_vlan_tag = ifv->ifv_tag & 0xfff;
2077 * Sanity check: avoid coming within 16 descriptors
2078 * of the end of the ring.
2080 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
2083 TI_INC(frag, TI_TX_RING_CNT);
2091 if (frag == sc->ti_tx_saved_considx)
2094 if (sc->ti_hwrev == TI_HWREV_TIGON)
2095 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |=
2098 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
2099 sc->ti_cdata.ti_tx_chain[cur] = m_head;
2100 sc->ti_txcnt += cnt;
2108 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2109 * to the mbuf data regions directly in the transmit descriptors.
2111 static void ti_start(ifp)
2114 struct ti_softc *sc;
2115 struct mbuf *m_head = NULL;
2116 u_int32_t prodidx = 0;
2120 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);
2122 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
2123 IF_DEQUEUE(&ifp->if_snd, m_head);
2129 * safety overkill. If this is a fragmented packet chain
2130 * with delayed TCP/UDP checksums, then only encapsulate
2131 * it if we have enough descriptors to handle the entire
2133 * (paranoia -- may not actually be needed)
2135 if (m_head->m_flags & M_FIRSTFRAG &&
2136 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2137 if ((TI_TX_RING_CNT - sc->ti_txcnt) <
2138 m_head->m_pkthdr.csum_data + 16) {
2139 IF_PREPEND(&ifp->if_snd, m_head);
2140 ifp->if_flags |= IFF_OACTIVE;
2146 * Pack the data into the transmit ring. If we
2147 * don't have room, set the OACTIVE flag and wait
2148 * for the NIC to drain the ring.
2150 if (ti_encap(sc, m_head, &prodidx)) {
2151 IF_PREPEND(&ifp->if_snd, m_head);
2152 ifp->if_flags |= IFF_OACTIVE;
2157 * If there's a BPF listener, bounce a copy of this frame
2161 bpf_mtap(ifp, m_head);
2165 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
2168 * Set a timeout in case the chip goes out to lunch.
2175 static void ti_init(xsc)
2178 struct ti_softc *sc = xsc;
2183 /* Cancel pending I/O and flush buffers. */
2186 /* Init the gen info block, ring control blocks and firmware. */
2187 if (ti_gibinit(sc)) {
2188 printf("ti%d: initialization failure\n", sc->ti_unit);
2198 static void ti_init2(sc)
2199 struct ti_softc *sc;
2201 struct ti_cmd_desc cmd;
2204 struct ifmedia *ifm;
2207 ifp = &sc->arpcom.ac_if;
2209 /* Specify MTU and interface index. */
2210 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_dunit);
2211 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
2212 ETHER_HDR_LEN + ETHER_CRC_LEN);
2213 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
2215 /* Load our MAC address. */
2216 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
2217 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0]));
2218 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2]));
2219 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
2221 /* Enable or disable promiscuous mode as needed. */
2222 if (ifp->if_flags & IFF_PROMISC) {
2223 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
2225 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
2228 /* Program multicast filter. */
2232 * If this is a Tigon 1, we should tell the
2233 * firmware to use software packet filtering.
2235 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2236 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
2240 ti_init_rx_ring_std(sc);
2242 /* Init jumbo RX ring. */
2243 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2244 ti_init_rx_ring_jumbo(sc);
2247 * If this is a Tigon 2, we can also configure the
2250 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
2251 ti_init_rx_ring_mini(sc);
2253 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
2254 sc->ti_rx_saved_considx = 0;
2257 ti_init_tx_ring(sc);
2259 /* Tell firmware we're alive. */
2260 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
2262 /* Enable host interrupts. */
2263 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2265 ifp->if_flags |= IFF_RUNNING;
2266 ifp->if_flags &= ~IFF_OACTIVE;
2269 * Make sure to set media properly. We have to do this
2270 * here since we have to issue commands in order to set
2271 * the link negotiation and we can't issue commands until
2272 * the firmware is running.
2275 tmp = ifm->ifm_media;
2276 ifm->ifm_media = ifm->ifm_cur->ifm_media;
2277 ti_ifmedia_upd(ifp);
2278 ifm->ifm_media = tmp;
2284 * Set media options.
2286 static int ti_ifmedia_upd(ifp)
2289 struct ti_softc *sc;
2290 struct ifmedia *ifm;
2291 struct ti_cmd_desc cmd;
2296 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2299 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2301 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2302 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|
2303 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
2304 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
2305 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX|
2306 TI_LNK_AUTONEGENB|TI_LNK_ENB);
2307 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2308 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
2312 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2313 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB);
2314 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
2315 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2316 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
2318 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2319 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
2325 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
2326 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF);
2327 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
2328 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
2329 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
2331 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
2333 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2334 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
2336 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
2338 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2339 TI_CMD_CODE_NEGOTIATE_10_100, 0);
2347 * Report current media status.
2349 static void ti_ifmedia_sts(ifp, ifmr)
2351 struct ifmediareq *ifmr;
2353 struct ti_softc *sc;
2354 u_int32_t media = 0;
2358 ifmr->ifm_status = IFM_AVALID;
2359 ifmr->ifm_active = IFM_ETHER;
2361 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
2364 ifmr->ifm_status |= IFM_ACTIVE;
2366 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
2367 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
2369 ifmr->ifm_active |= IFM_1000_TX;
2371 ifmr->ifm_active |= IFM_1000_SX;
2372 if (media & TI_GLNK_FULL_DUPLEX)
2373 ifmr->ifm_active |= IFM_FDX;
2375 ifmr->ifm_active |= IFM_HDX;
2376 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
2377 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
2378 if (sc->ti_copper) {
2379 if (media & TI_LNK_100MB)
2380 ifmr->ifm_active |= IFM_100_TX;
2381 if (media & TI_LNK_10MB)
2382 ifmr->ifm_active |= IFM_10_T;
2384 if (media & TI_LNK_100MB)
2385 ifmr->ifm_active |= IFM_100_FX;
2386 if (media & TI_LNK_10MB)
2387 ifmr->ifm_active |= IFM_10_FL;
2389 if (media & TI_LNK_FULL_DUPLEX)
2390 ifmr->ifm_active |= IFM_FDX;
2391 if (media & TI_LNK_HALF_DUPLEX)
2392 ifmr->ifm_active |= IFM_HDX;
2398 static int ti_ioctl(ifp, command, data, cr)
2404 struct ti_softc *sc = ifp->if_softc;
2405 struct ifreq *ifr = (struct ifreq *) data;
2406 int s, mask, error = 0;
2407 struct ti_cmd_desc cmd;
2414 error = ether_ioctl(ifp, command, data);
2417 if (ifr->ifr_mtu > TI_JUMBO_MTU)
2420 ifp->if_mtu = ifr->ifr_mtu;
2425 if (ifp->if_flags & IFF_UP) {
2427 * If only the state of the PROMISC flag changed,
2428 * then just use the 'set promisc mode' command
2429 * instead of reinitializing the entire NIC. Doing
2430 * a full re-init means reloading the firmware and
2431 * waiting for it to start up, which may take a
2434 if (ifp->if_flags & IFF_RUNNING &&
2435 ifp->if_flags & IFF_PROMISC &&
2436 !(sc->ti_if_flags & IFF_PROMISC)) {
2437 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2438 TI_CMD_CODE_PROMISC_ENB, 0);
2439 } else if (ifp->if_flags & IFF_RUNNING &&
2440 !(ifp->if_flags & IFF_PROMISC) &&
2441 sc->ti_if_flags & IFF_PROMISC) {
2442 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2443 TI_CMD_CODE_PROMISC_DIS, 0);
2447 if (ifp->if_flags & IFF_RUNNING) {
2451 sc->ti_if_flags = ifp->if_flags;
2456 if (ifp->if_flags & IFF_RUNNING) {
2463 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2466 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2467 if (mask & IFCAP_HWCSUM) {
2468 if (IFCAP_HWCSUM & ifp->if_capenable)
2469 ifp->if_capenable &= ~IFCAP_HWCSUM;
2471 ifp->if_capenable |= IFCAP_HWCSUM;
2472 if (ifp->if_flags & IFF_RUNNING)
2487 static void ti_watchdog(ifp)
2490 struct ti_softc *sc;
2494 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit);
2504 * Stop the adapter and free any mbufs allocated to the
2507 static void ti_stop(sc)
2508 struct ti_softc *sc;
2511 struct ti_cmd_desc cmd;
2513 ifp = &sc->arpcom.ac_if;
2515 /* Disable host interrupts. */
2516 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2518 * Tell firmware we're shutting down.
2520 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
2522 /* Halt and reinitialize. */
2524 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
2527 /* Free the RX lists. */
2528 ti_free_rx_ring_std(sc);
2530 /* Free jumbo RX list. */
2531 ti_free_rx_ring_jumbo(sc);
2533 /* Free mini RX list. */
2534 ti_free_rx_ring_mini(sc);
2536 /* Free TX buffers. */
2537 ti_free_tx_ring(sc);
2539 sc->ti_ev_prodidx.ti_idx = 0;
2540 sc->ti_return_prodidx.ti_idx = 0;
2541 sc->ti_tx_considx.ti_idx = 0;
2542 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
2544 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2550 * Stop all chip I/O so that the kernel's probe routines don't
2551 * get confused by errant DMAs when rebooting.
2553 static void ti_shutdown(dev)
2556 struct ti_softc *sc;
2558 sc = device_get_softc(dev);