sys/net/i4b/layer1/ifpi/i4b_ifpi_pci.c

   1 /*
   2  *   Copyright (c) 1999, 2000 Gary Jennejohn. All rights reserved.
   3  *
   4  *   Redistribution and use in source and binary forms, with or without
   5  *   modification, are permitted provided that the following conditions
   6  *   are met:
   7  *
   8  *   1. Redistributions of source code must retain the above copyright
   9  *      notice, this list of conditions and the following disclaimer.
  10  *   2. Redistributions in binary form must reproduce the above copyright
  11  *      notice, this list of conditions and the following disclaimer in the
  12  *      documentation and/or other materials provided with the distribution.
  13  *   3. Neither the name of the author nor the names of any co-contributors
  14  *      may be used to endorse or promote products derived from this software
  15  *      without specific prior written permission.
  16  *   4. Altered versions must be plainly marked as such, and must not be
  17  *      misrepresented as being the original software and/or documentation.
  18  *
  19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  *   SUCH DAMAGE.
  30  *
  31  *---------------------------------------------------------------------------
  32  *
  33  *      i4b_ifpi_pci.c: AVM Fritz!Card PCI hardware driver
  34  *      --------------------------------------------------
  35  *
  36  *      $Id: i4b_ifpi_pci.c,v 1.4 2000/06/02 11:58:56 hm Exp $
  37  *
  38  * $FreeBSD: src/sys/i4b/layer1/ifpi/i4b_ifpi_pci.c,v 1.6.2.1 2001/08/10 14:08:37 obrien Exp $
  39  * $DragonFly: src/sys/net/i4b/layer1/ifpi/i4b_ifpi_pci.c,v 1.7 2004/05/04 12:03:49 hmp Exp $
  40  *
  41  *      last edit-date: [Fri Jan 12 17:01:26 2001]
  42  *
  43  *---------------------------------------------------------------------------*/
  44
  45 #include "use_ifpi.h"
  46 #include "use_pci.h"
  47 #include "opt_i4b.h"
  48
  49 #if (NIFPI > 0) && (NPCI > 0)
  50
  51 #include <sys/param.h>
  52 #include <sys/kernel.h>
  53 #include <sys/systm.h>
  54 #include <sys/mbuf.h>
  55
  56 #include <machine/bus.h>
  57 #include <sys/bus.h>
  58 #include <sys/rman.h>
  59
  60 #include <bus/pci/pcireg.h>
  61 #include <bus/pci/pcivar.h>
  62
  63 #include <sys/socket.h>
  64 #include <net/if.h>
  65
  66 #include <net/i4b/include/machine/i4b_debug.h>
  67 #include <net/i4b/include/machine/i4b_ioctl.h>
  68 #include <net/i4b/include/machine/i4b_trace.h>
  69
  70 #include "../../include/i4b_global.h"
  71 #include "../../include/i4b_mbuf.h"
  72
  73 #include "../i4b_l1.h"
  74 #include "../isic/i4b_isic.h"
  75 #include "../isic/i4b_isac.h"
  76 #include "../isic/i4b_hscx.h"
  77
  78 #include "i4b_ifpi_ext.h"
  79
  80 #define PCI_AVMA1_VID 0x1244
  81 #define PCI_AVMA1_DID 0x0a00
  82
  83 /* prototypes */
  84 static void avma1pp_disable(device_t);
  85
  86 static void avma1pp_intr(void *);
  87 static void hscx_write_reg(int, u_int, u_int, struct l1_softc *);
  88 static u_char hscx_read_reg(int, u_int, struct l1_softc *);
  89 static u_int hscx_read_reg_int(int, u_int, struct l1_softc *);
  90 static void hscx_read_fifo(int, void *, size_t, struct l1_softc *);
  91 static void hscx_write_fifo(int, void *, size_t, struct l1_softc *);
  92 static void avma1pp_hscx_int_handler(struct l1_softc *);
  93 static void avma1pp_hscx_intr(int, u_int, struct l1_softc *);
  94 static void avma1pp_init_linktab(struct l1_softc *);
  95 static void avma1pp_bchannel_setup(int, int, int, int);
  96 static void avma1pp_bchannel_start(int, int);
  97 static void avma1pp_hscx_init(struct l1_softc *, int, int);
  98 static void avma1pp_bchannel_stat(int, int, bchan_statistics_t *);
  99 static void avma1pp_set_linktab(int, int, drvr_link_t *);
 100 static isdn_link_t * avma1pp_ret_linktab(int, int);
 101 static int avma1pp_pci_probe(device_t);
 102 static int avma1pp_hscx_fifo(l1_bchan_state_t *, struct l1_softc *);
 103 int avma1pp_attach_avma1pp(device_t);
 104 static void ifpi_isac_intr(struct l1_softc *sc);
 105
 106 static device_method_t avma1pp_pci_methods[] = {
 107         /* Device interface */
 108         DEVMETHOD(device_probe,         avma1pp_pci_probe),
 109         DEVMETHOD(device_attach,        avma1pp_attach_avma1pp),
 110         DEVMETHOD(device_shutdown,      avma1pp_disable),
 111
 112         /* bus interface */
 113         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 114         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 115
 116         { 0, 0 }
 117 };
 118
 119 #if 0 /* use what's in l1_softc */
 120 /* a minimal softc for the Fritz!Card PCI */
 121 struct avma1pp_softc
 122 {
 123         bus_space_handle_t      avma1pp_bhandle;
 124         bus_space_tag_t         avma1pp_btag;
 125         void                    *avma1pp_intrhand;
 126         struct resource         *avma1pp_irq;
 127         struct resource         *avma1pp_res;
 128         /* pointer to ifpi_sc */
 129         struct l1_softc *avma1pp_isc;
 130 };
 131 #endif
 132
 133 static driver_t avma1pp_pci_driver = {
 134         "ifpi",
 135         avma1pp_pci_methods,
 136         sizeof(struct l1_softc)
 137 };
 138
 139 static devclass_t avma1pp_pci_devclass;
 140
 141 DRIVER_MODULE(avma1pp, pci, avma1pp_pci_driver, avma1pp_pci_devclass, 0, 0);
 142
 143 /* jump table for multiplex routines */
 144
 145 struct i4b_l1mux_func avma1pp_l1mux_func = {
 146         avma1pp_ret_linktab,
 147         avma1pp_set_linktab,
 148         ifpi_mph_command_req,
 149         ifpi_ph_data_req,
 150         ifpi_ph_activate_req,
 151 };
 152
 153 struct l1_softc *ifpi_scp[IFPI_MAXUNIT];
 154
 155 /*---------------------------------------------------------------------------*
 156  *      AVM PCI Fritz!Card special registers
 157  *---------------------------------------------------------------------------*/
 158
 159 /*
 160  *      register offsets from i/o base
 161  */
 162 #define STAT0_OFFSET            0x02
 163 #define STAT1_OFFSET            0x03
 164 #define ADDR_REG_OFFSET         0x04
 165 /*#define MODREG_OFFSET         0x06
 166 #define VERREG_OFFSET           0x07*/
 167
 168 /* these 2 are used to select an ISAC register set */
 169 #define ISAC_LO_REG_OFFSET      0x04
 170 #define ISAC_HI_REG_OFFSET      0x06
 171
 172 /* offset higher than this goes to the HI register set */
 173 #define MAX_LO_REG_OFFSET       0x2f
 174
 175 /* mask for the offset */
 176 #define ISAC_REGSET_MASK        0x0f
 177
 178 /* the offset from the base to the ISAC registers */
 179 #define ISAC_REG_OFFSET         0x10
 180
 181 /* the offset from the base to the ISAC FIFO */
 182 #define ISAC_FIFO               0x02
 183
 184 /* not really the HSCX, but sort of */
 185 #define HSCX_FIFO               0x00
 186 #define HSCX_STAT               0x04
 187
 188 /*
 189  *      AVM PCI Status Latch 0 read only bits
 190  */
 191 #define ASL_IRQ_ISAC            0x01    /* ISAC  interrupt, active low */
 192 #define ASL_IRQ_HSCX            0x02    /* HSX   interrupt, active low */
 193 #define ASL_IRQ_TIMER           0x04    /* Timer interrupt, active low */
 194 #define ASL_IRQ_BCHAN           ASL_IRQ_HSCX
 195 /* actually active LOW */
 196 #define ASL_IRQ_Pending         (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
 197
 198 /*
 199  *      AVM Status Latch 0 write only bits
 200  */
 201 #define ASL_RESET_ALL           0x01  /* reset siemens IC's, active 1 */
 202 #define ASL_TIMERDISABLE        0x02  /* active high */
 203 #define ASL_TIMERRESET          0x04  /* active high */
 204 #define ASL_ENABLE_INT          0x08  /* active high */
 205 #define ASL_TESTBIT             0x10  /* active high */
 206
 207 /*
 208  *      AVM Status Latch 1 write only bits
 209  */
 210 #define ASL1_INTSEL              0x0f  /* active high */
 211 #define ASL1_ENABLE_IOM          0x80  /* active high */
 212
 213 /*
 214  * "HSCX" mode bits
 215  */
 216 #define  HSCX_MODE_ITF_FLG      0x01
 217 #define  HSCX_MODE_TRANS        0x02
 218 #define  HSCX_MODE_CCR_7        0x04
 219 #define  HSCX_MODE_CCR_16       0x08
 220 #define  HSCX_MODE_TESTLOOP     0x80
 221
 222 /*
 223  * "HSCX" status bits
 224  */
 225 #define  HSCX_STAT_RME          0x01
 226 #define  HSCX_STAT_RDO          0x10
 227 #define  HSCX_STAT_CRCVFRRAB    0x0E
 228 #define  HSCX_STAT_CRCVFR       0x06
 229 #define  HSCX_STAT_RML_MASK     0x3f00
 230
 231 /*
 232  * "HSCX" interrupt bits
 233  */
 234 #define  HSCX_INT_XPR           0x80
 235 #define  HSCX_INT_XDU           0x40
 236 #define  HSCX_INT_RPR           0x20
 237 #define  HSCX_INT_MASK          0xE0
 238
 239 /*
 240  * "HSCX" command bits
 241  */
 242 #define  HSCX_CMD_XRS           0x80
 243 #define  HSCX_CMD_XME           0x01
 244 #define  HSCX_CMD_RRS           0x20
 245 #define  HSCX_CMD_XML_MASK      0x3f00
 246
 247 /*
 248  * Commands and parameters are sent to the "HSCX" as a long, but the
 249  * fields are handled as bytes.
 250  *
 251  * The long contains:
 252  *      (prot << 16)|(txl << 8)|cmd
 253  *
 254  * where:
 255  *      prot = protocol to use
 256  *      txl = transmit length
 257  *      cmd = the command to be executed
 258  *
 259  * The fields are defined as u_char in struct l1_softc.
 260  *
 261  * Macro to coalesce the byte fields into a u_int
 262  */
 263 #define AVMA1PPSETCMDLONG(f) (f) = ((sc->avma1pp_cmd) | (sc->avma1pp_txl << 8) \
 264                                         | (sc->avma1pp_prot << 16))
 265
 266 /*
 267  * to prevent deactivating the "HSCX" when both channels are active we
 268  * define an HSCX_ACTIVE flag which is or'd into the channel's state
 269  * flag in avma1pp_bchannel_setup upon active and cleared upon deactivation.
 270  * It is set high to allow room for new flags.
 271  */
 272 #define HSCX_AVMA1PP_ACTIVE     0x1000
 273
 274 /*---------------------------------------------------------------------------*
 275  *      AVM read fifo routines
 276  *---------------------------------------------------------------------------*/
 277
 278 static void
 279 avma1pp_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 280 {
 281         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 282         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 283
 284         switch (what) {
 285                 case ISIC_WHAT_ISAC:
 286                         bus_space_write_1(btag, bhandle,  ADDR_REG_OFFSET, ISAC_FIFO);
 287                         bus_space_read_multi_1(btag, bhandle,  ISAC_REG_OFFSET, buf, size);
 288                         break;
 289                 case ISIC_WHAT_HSCXA:
 290                         hscx_read_fifo(0, buf, size, sc);
 291                         break;
 292                 case ISIC_WHAT_HSCXB:
 293                         hscx_read_fifo(1, buf, size, sc);
 294                         break;
 295         }
 296 }
 297
 298 static void
 299 hscx_read_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 300 {
 301         u_int32_t *ip;
 302         size_t cnt;
 303         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 304         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 305
 306         bus_space_write_4(btag, bhandle, ADDR_REG_OFFSET, chan);
 307         ip = (u_int32_t *)buf;
 308         cnt = 0;
 309         /* what if len isn't a multiple of sizeof(int) and buf is */
 310         /* too small ???? */
 311         while (cnt < len)
 312         {
 313                 *ip++ = bus_space_read_4(btag, bhandle, ISAC_REG_OFFSET);
 314                 cnt += 4;
 315         }
 316 }
 317
 318 /*---------------------------------------------------------------------------*
 319  *      AVM write fifo routines
 320  *---------------------------------------------------------------------------*/
 321 static void
 322 avma1pp_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 323 {
 324         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 325         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 326
 327         switch (what) {
 328                 case ISIC_WHAT_ISAC:
 329                         bus_space_write_1(btag, bhandle,  ADDR_REG_OFFSET, ISAC_FIFO);
 330                         bus_space_write_multi_1(btag, bhandle,  ISAC_REG_OFFSET, (u_int8_t*)buf, size);
 331                         break;
 332                 case ISIC_WHAT_HSCXA:
 333                         hscx_write_fifo(0, buf, size, sc);
 334                         break;
 335                 case ISIC_WHAT_HSCXB:
 336                         hscx_write_fifo(1, buf, size, sc);
 337                         break;
 338         }
 339 }
 340
 341 static void
 342 hscx_write_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 343 {
 344         u_int32_t *ip;
 345         size_t cnt;
 346         l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
 347         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 348         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 349
 350
 351         sc->avma1pp_cmd &= ~HSCX_CMD_XME;
 352         sc->avma1pp_txl = 0;
 353         if (Bchan->out_mbuf_cur == NULL)
 354         {
 355           if (Bchan->bprot != BPROT_NONE)
 356                  sc->avma1pp_cmd |= HSCX_CMD_XME;
 357         }
 358         if (len != sc->sc_bfifolen)
 359                 sc->avma1pp_txl = len;
 360
 361         cnt = 0; /* borrow cnt */
 362         AVMA1PPSETCMDLONG(cnt);
 363         hscx_write_reg(chan, HSCX_STAT, cnt, sc);
 364
 365         ip = (u_int32_t *)buf;
 366         cnt = 0;
 367         while (cnt < len)
 368         {
 369                 bus_space_write_4(btag, bhandle, ISAC_REG_OFFSET, *ip);
 370                 ip++;
 371                 cnt += 4;
 372         }
 373 }
 374
 375 /*---------------------------------------------------------------------------*
 376  *      AVM write register routines
 377  *---------------------------------------------------------------------------*/
 378
 379 static void
 380 avma1pp_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
 381 {
 382         u_char reg_bank;
 383         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 384         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 385
 386         switch (what) {
 387                 case ISIC_WHAT_ISAC:
 388                         reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
 389 #ifdef AVMA1PCI_DEBUG
 390                         printf("write_reg bank %d  off %ld.. ", (int)reg_bank, (long)offs);
 391 #endif
 392                         /* set the register bank */
 393                         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, reg_bank);
 394                         bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + (offs & ISAC_REGSET_MASK), data);
 395                         break;
 396                 case ISIC_WHAT_HSCXA:
 397                         hscx_write_reg(0, offs, data, sc);
 398                         break;
 399                 case ISIC_WHAT_HSCXB:
 400                         hscx_write_reg(1, offs, data, sc);
 401                         break;
 402         }
 403 }
 404
 405 static void
 406 hscx_write_reg(int chan, u_int off, u_int val, struct l1_softc *sc)
 407 {
 408         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 409         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 410
 411         /* point at the correct channel */
 412         bus_space_write_4(btag, bhandle, ADDR_REG_OFFSET, chan);
 413         bus_space_write_4(btag, bhandle, ISAC_REG_OFFSET + off, val);
 414 }
 415
 416 /*---------------------------------------------------------------------------*
 417  *      AVM read register routines
 418  *---------------------------------------------------------------------------*/
 419 static u_int8_t
 420 avma1pp_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
 421 {
 422         u_char reg_bank;
 423         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 424         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 425
 426         switch (what) {
 427                 case ISIC_WHAT_ISAC:
 428                         reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
 429 #ifdef AVMA1PCI_DEBUG
 430                         printf("read_reg bank %d  off %ld.. ", (int)reg_bank, (long)offs);
 431 #endif
 432                         /* set the register bank */
 433                         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, reg_bank);
 434                         return(bus_space_read_1(btag, bhandle, ISAC_REG_OFFSET +
 435                                 (offs & ISAC_REGSET_MASK)));
 436                 case ISIC_WHAT_HSCXA:
 437                         return hscx_read_reg(0, offs, sc);
 438                 case ISIC_WHAT_HSCXB:
 439                         return hscx_read_reg(1, offs, sc);
 440         }
 441         return 0;
 442 }
 443
 444 static u_char
 445 hscx_read_reg(int chan, u_int off, struct l1_softc *sc)
 446 {
 447         return(hscx_read_reg_int(chan, off, sc) & 0xff);
 448 }
 449
 450 /*
 451  * need to be able to return an int because the RBCH is in the 2nd
 452  * byte.
 453  */
 454 static u_int
 455 hscx_read_reg_int(int chan, u_int off, struct l1_softc *sc)
 456 {
 457         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 458         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 459
 460         /* point at the correct channel */
 461         bus_space_write_4(btag, bhandle, ADDR_REG_OFFSET, chan);
 462         return(bus_space_read_4(btag, bhandle, ISAC_REG_OFFSET + off));
 463 }
 464
 465 /*---------------------------------------------------------------------------*
 466  *      avma1pp_probe - probe for a card
 467  *---------------------------------------------------------------------------*/
 468 static int
 469 avma1pp_pci_probe(dev)
 470         device_t                dev;
 471 {
 472         u_int16_t               did, vid;
 473
 474         vid = pci_get_vendor(dev);
 475         did = pci_get_device(dev);
 476
 477         if ((vid == PCI_AVMA1_VID) && (did == PCI_AVMA1_DID)) {
 478                 device_set_desc(dev, "AVM Fritz!Card PCI");
 479                 return(0);
 480         }
 481
 482         return(ENXIO);
 483 }
 484
 485 /*---------------------------------------------------------------------------*
 486  *      avma1pp_attach_avma1pp - attach Fritz!Card PCI
 487  *---------------------------------------------------------------------------*/
 488 int
 489 avma1pp_attach_avma1pp(device_t dev)
 490 {
 491         struct l1_softc *sc;
 492         u_int v;
 493         int unit, error = 0;
 494         int s;
 495         u_int16_t did, vid;
 496         void *ih = 0;
 497         bus_space_handle_t bhandle;
 498         bus_space_tag_t btag;
 499 #if defined (__FreeBSD__) && __FreeBSD__ > 4
 500         l1_bchan_state_t *chan;
 501 #endif
 502
 503         s = splimp();
 504
 505         vid = pci_get_vendor(dev);
 506         did = pci_get_device(dev);
 507         sc = device_get_softc(dev);
 508         unit = device_get_unit(dev);
 509         bzero(sc, sizeof(struct l1_softc));
 510
 511         /* probably not really required */
 512         if(unit > IFPI_MAXUNIT) {
 513                 printf("avma1pp%d: Error, unit > IFPI_MAXUNIT!\n", unit);
 514                 splx(s);
 515                 return(ENXIO);
 516         }
 517
 518         if ((vid != PCI_AVMA1_VID) && (did != PCI_AVMA1_DID)) {
 519                 printf("avma1pp%d: unknown device!?\n", unit);
 520                 goto fail;
 521         }
 522
 523         ifpi_scp[unit] = sc;
 524
 525         sc->sc_resources.io_rid[0] = PCIR_MAPS+4;
 526         sc->sc_resources.io_base[0] = bus_alloc_resource(dev, SYS_RES_IOPORT,
 527                 &sc->sc_resources.io_rid[0],
 528                 0, ~0, 1, RF_ACTIVE);
 529
 530         if (sc->sc_resources.io_base[0] == NULL) {
 531                 printf("avma1pp%d: couldn't map IO port\n", unit);
 532                 error = ENXIO;
 533                 goto fail;
 534         }
 535
 536         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 537         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 538
 539         /* Allocate interrupt */
 540         sc->sc_resources.irq_rid = 0;
 541         sc->sc_resources.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
 542                 &sc->sc_resources.irq_rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
 543
 544         if (sc->sc_resources.irq == NULL) {
 545                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
 546                 printf("avma1pp%d: couldn't map interrupt\n", unit);
 547                 error = ENXIO;
 548                 goto fail;
 549         }
 550
 551         error = bus_setup_intr(dev, sc->sc_resources.irq, INTR_TYPE_NET, avma1pp_intr, sc, &ih);
 552
 553         if (error) {
 554                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_resources.irq);
 555                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
 556                 printf("avma1pp%d: couldn't set up irq\n", unit);
 557                 goto fail;
 558         }
 559
 560         sc->sc_unit = unit;
 561
 562         /* end of new-bus stuff */
 563
 564         ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
 565
 566         HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
 567         HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
 568
 569         /* setup access routines */
 570
 571         sc->clearirq = NULL;
 572         sc->readreg = avma1pp_read_reg;
 573         sc->writereg = avma1pp_write_reg;
 574
 575         sc->readfifo = avma1pp_read_fifo;
 576         sc->writefifo = avma1pp_write_fifo;
 577
 578         /* setup card type */
 579
 580         sc->sc_cardtyp = CARD_TYPEP_AVMA1PCI;
 581
 582         /* setup IOM bus type */
 583
 584         sc->sc_bustyp = BUS_TYPE_IOM2;
 585
 586         /* set up some other miscellaneous things */
 587         sc->sc_ipac = 0;
 588         sc->sc_bfifolen = HSCX_FIFO_LEN;
 589
 590         /* reset the card */
 591         /* the Linux driver does this to clear any pending ISAC interrupts */
 592         v = 0;
 593         v = ISAC_READ(I_STAR);
 594 #ifdef AVMA1PCI_DEBUG
 595         printf("avma1pp_attach: I_STAR %x...", v);
 596 #endif
 597         v = ISAC_READ(I_MODE);
 598 #ifdef AVMA1PCI_DEBUG
 599         printf("avma1pp_attach: I_MODE %x...", v);
 600 #endif
 601         v = ISAC_READ(I_ADF2);
 602 #ifdef AVMA1PCI_DEBUG
 603         printf("avma1pp_attach: I_ADF2 %x...", v);
 604 #endif
 605         v = ISAC_READ(I_ISTA);
 606 #ifdef AVMA1PCI_DEBUG
 607         printf("avma1pp_attach: I_ISTA %x...", v);
 608 #endif
 609         if (v & ISAC_ISTA_EXI)
 610         {
 611                  v = ISAC_READ(I_EXIR);
 612 #ifdef AVMA1PCI_DEBUG
 613                  printf("avma1pp_attach: I_EXIR %x...", v);
 614 #endif
 615         }
 616         v = ISAC_READ(I_CIRR);
 617 #ifdef AVMA1PCI_DEBUG
 618         printf("avma1pp_attach: I_CIRR %x...", v);
 619 #endif
 620         ISAC_WRITE(I_MASK, 0xff);
 621         /* the Linux driver does this to clear any pending HSCX interrupts */
 622         v = hscx_read_reg_int(0, HSCX_STAT, sc);
 623 #ifdef AVMA1PCI_DEBUG
 624         printf("avma1pp_attach: 0 HSCX_STAT %x...", v);
 625 #endif
 626         v = hscx_read_reg_int(1, HSCX_STAT, sc);
 627 #ifdef AVMA1PCI_DEBUG
 628         printf("avma1pp_attach: 1 HSCX_STAT %x\n", v);
 629 #endif
 630
 631         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
 632         DELAY(SEC_DELAY/100); /* 10 ms */
 633         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_TIMERRESET|ASL_ENABLE_INT|ASL_TIMERDISABLE);
 634         DELAY(SEC_DELAY/100); /* 10 ms */
 635 #ifdef AVMA1PCI_DEBUG
 636         bus_space_write_1(btag, bhandle, STAT1_OFFSET, ASL1_ENABLE_IOM|sc->sc_irq);
 637         DELAY(SEC_DELAY/100); /* 10 ms */
 638         v = bus_space_read_1(btag, bhandle, STAT1_OFFSET);
 639         printf("after reset: S1 %#x\n", v);
 640
 641         v = bus_space_read_4(btag, bhandle, 0);
 642         printf("avma1pp_attach_avma1pp: v %#x\n", v);
 643 #endif
 644
 645    /* from here to the end would normally be done in isic_pciattach */
 646
 647          printf("ifpi%d: ISAC %s (IOM-%c)\n", unit,
 648                 "2085 Version A1/A2 or 2086/2186 Version 1.1",
 649                  sc->sc_bustyp == BUS_TYPE_IOM1 ? '1' : '2');
 650
 651         /* init the ISAC */
 652         ifpi_isac_init(sc);
 653
 654 #if defined (__FreeBSD__) && __FreeBSD__ > 4
 655         /* Init the channel mutexes */
 656         chan = &sc->sc_chan[HSCX_CH_A];
 657         mtx_init(&chan->rx_queue.ifq_mtx, "i4b_avma1pp_rx", MTX_DEF);
 658         mtx_init(&chan->tx_queue.ifq_mtx, "i4b_avma1pp_tx", MTX_DEF);
 659         chan = &sc->sc_chan[HSCX_CH_B];
 660         mtx_init(&chan->rx_queue.ifq_mtx, "i4b_avma1pp_rx", MTX_DEF);
 661         mtx_init(&chan->tx_queue.ifq_mtx, "i4b_avma1pp_tx", MTX_DEF);
 662 #endif
 663
 664         /* init the "HSCX" */
 665         avma1pp_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
 666
 667         avma1pp_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
 668
 669         /* can't use the normal B-Channel stuff */
 670         avma1pp_init_linktab(sc);
 671
 672         /* set trace level */
 673
 674         sc->sc_trace = TRACE_OFF;
 675
 676         sc->sc_state = ISAC_IDLE;
 677
 678         sc->sc_ibuf = NULL;
 679         sc->sc_ib = NULL;
 680         sc->sc_ilen = 0;
 681
 682         sc->sc_obuf = NULL;
 683         sc->sc_op = NULL;
 684         sc->sc_ol = 0;
 685         sc->sc_freeflag = 0;
 686
 687         sc->sc_obuf2 = NULL;
 688         sc->sc_freeflag2 = 0;
 689
 690 #if defined(__DragonFly__) || (defined(__FreeBSD__) && __FreeBSD__ >=3)
 691         callout_handle_init(&sc->sc_T3_callout);
 692         callout_handle_init(&sc->sc_T4_callout);
 693 #endif
 694
 695         /* init higher protocol layers */
 696
 697         i4b_l1_mph_status_ind(L0IFPIUNIT(sc->sc_unit), STI_ATTACH, sc->sc_cardtyp, &avma1pp_l1mux_func);
 698
 699   fail:
 700         splx(s);
 701         return(error);
 702 }
 703
 704 /*
 705  * this is the real interrupt routine
 706  */
 707 static void
 708 avma1pp_hscx_intr(int h_chan, u_int stat, struct l1_softc *sc)
 709 {
 710         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
 711         int activity = -1;
 712         u_int param = 0;
 713
 714         NDBGL1(L1_H_IRQ, "%#x", stat);
 715
 716         if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
 717         {
 718                 chan->stat_XDU++;
 719                 NDBGL1(L1_H_XFRERR, "xmit data underrun");
 720                 /* abort the transmission */
 721                 sc->avma1pp_txl = 0;
 722                 sc->avma1pp_cmd |= HSCX_CMD_XRS;
 723                 AVMA1PPSETCMDLONG(param);
 724                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
 725                 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
 726                 AVMA1PPSETCMDLONG(param);
 727                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
 728
 729                 if (chan->out_mbuf_head != NULL)  /* don't continue to transmit this buffer */
 730                 {
 731                         i4b_Bfreembuf(chan->out_mbuf_head);
 732                         chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
 733                 }
 734         }
 735
 736         /*
 737          * The following is based on examination of the Linux driver.
 738          *
 739          * The logic here is different than with a "real" HSCX; all kinds
 740          * of information (interrupt/status bits) are in stat.
 741          *              HSCX_INT_RPR indicates a receive interrupt
 742          *                      HSCX_STAT_RDO indicates an overrun condition, abort -
 743          *                      otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
 744          *                      HSCX_STAT_RME indicates end-of-frame and apparently any
 745          *                      CRC/framing errors are only reported in this state.
 746          *                              if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
 747          *                                      CRC/framing error
 748          */
 749
 750         if(stat & HSCX_INT_RPR)
 751         {
 752                 int fifo_data_len;
 753                 int error = 0;
 754                 /* always have to read the FIFO, so use a scratch buffer */
 755                 u_char scrbuf[HSCX_FIFO_LEN];
 756
 757                 if(stat & HSCX_STAT_RDO)
 758                 {
 759                         chan->stat_RDO++;
 760                         NDBGL1(L1_H_XFRERR, "receive data overflow");
 761                         error++;
 762                 }
 763
 764                 /*
 765                  * check whether we're receiving data for an inactive B-channel
 766                  * and discard it. This appears to happen for telephony when
 767                  * both B-channels are active and one is deactivated. Since
 768                  * it is not really possible to deactivate the channel in that
 769                  * case (the ASIC seems to deactivate _both_ channels), the
 770                  * "deactivated" channel keeps receiving data which can lead
 771                  * to exhaustion of mbufs and a kernel panic.
 772                  *
 773                  * This is a hack, but it's the only solution I can think of
 774                  * without having the documentation for the ASIC.
 775                  * GJ - 28 Nov 1999
 776                  */
 777                  if (chan->state == HSCX_IDLE)
 778                  {
 779                         NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
 780                         error++;
 781                  }
 782
 783                 fifo_data_len = ((stat & HSCX_STAT_RML_MASK) >> 8);
 784
 785                 if(fifo_data_len == 0)
 786                         fifo_data_len = sc->sc_bfifolen;
 787
 788                 /* ALWAYS read data from HSCX fifo */
 789
 790                 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
 791                 chan->rxcount += fifo_data_len;
 792
 793                 /* all error conditions checked, now decide and take action */
 794
 795                 if(error == 0)
 796                 {
 797                         if(chan->in_mbuf == NULL)
 798                         {
 799                                 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 800                                         panic("L1 avma1pp_hscx_intr: RME, cannot allocate mbuf!\n");
 801                                 chan->in_cbptr = chan->in_mbuf->m_data;
 802                                 chan->in_len = 0;
 803                         }
 804
 805                         if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
 806                         {
 807                                 /* OK to copy the data */
 808                                 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 809                                 chan->in_cbptr += fifo_data_len;
 810                                 chan->in_len += fifo_data_len;
 811
 812                                 /* setup mbuf data length */
 813
 814                                 chan->in_mbuf->m_len = chan->in_len;
 815                                 chan->in_mbuf->m_pkthdr.len = chan->in_len;
 816
 817                                 if(sc->sc_trace & TRACE_B_RX)
 818                                 {
 819                                         i4b_trace_hdr_t hdr;
 820                                         hdr.unit = L0IFPIUNIT(sc->sc_unit);
 821                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 822                                         hdr.dir = FROM_NT;
 823                                         hdr.count = ++sc->sc_trace_bcount;
 824                                         MICROTIME(hdr.time);
 825                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 826                                 }
 827
 828                                 if (stat & HSCX_STAT_RME)
 829                                 {
 830                                   if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
 831                                   {
 832                                          (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 833                                          activity = ACT_RX;
 834
 835                                          /* mark buffer ptr as unused */
 836
 837                                          chan->in_mbuf = NULL;
 838                                          chan->in_cbptr = NULL;
 839                                          chan->in_len = 0;
 840                                   }
 841                                   else
 842                                   {
 843                                                 chan->stat_CRC++;
 844                                                 NDBGL1(L1_H_XFRERR, "CRC/RAB");
 845                                           if (chan->in_mbuf != NULL)
 846                                           {
 847                                                   i4b_Bfreembuf(chan->in_mbuf);
 848                                                   chan->in_mbuf = NULL;
 849                                                   chan->in_cbptr = NULL;
 850                                                   chan->in_len = 0;
 851                                           }
 852                                   }
 853                                 }
 854                         } /* END enough space in mbuf */
 855                         else
 856                         {
 857                                  if(chan->bprot == BPROT_NONE)
 858                                  {
 859                                           /* setup mbuf data length */
 860
 861                                           chan->in_mbuf->m_len = chan->in_len;
 862                                           chan->in_mbuf->m_pkthdr.len = chan->in_len;
 863
 864                                           if(sc->sc_trace & TRACE_B_RX)
 865                                           {
 866                                                         i4b_trace_hdr_t hdr;
 867                                                         hdr.unit = L0IFPIUNIT(sc->sc_unit);
 868                                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 869                                                         hdr.dir = FROM_NT;
 870                                                         hdr.count = ++sc->sc_trace_bcount;
 871                                                         MICROTIME(hdr.time);
 872                                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 873                                                 }
 874
 875                                           if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
 876                                                  activity = ACT_RX;
 877
 878                                           /* move rx'd data to rx queue */
 879
 880 #if defined (__FreeBSD__) && __FreeBSD__ > 4
 881                                           (void) IF_HANDOFF(&chan->rx_queue, chan->in_mbuf, NULL);
 882 #else
 883                                           if(!(IF_QFULL(&chan->rx_queue)))
 884                                           {
 885                                                 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
 886                                           }
 887                                           else
 888                                           {
 889                                                 i4b_Bfreembuf(chan->in_mbuf);
 890                                           }
 891 #endif
 892                                           /* signal upper layer that data are available */
 893                                           (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 894
 895                                           /* alloc new buffer */
 896
 897                                           if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 898                                                  panic("L1 avma1pp_hscx_intr: RPF, cannot allocate new mbuf!\n");
 899
 900                                           /* setup new data ptr */
 901
 902                                           chan->in_cbptr = chan->in_mbuf->m_data;
 903
 904                                           /* OK to copy the data */
 905                                           bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 906
 907                                           chan->in_cbptr += fifo_data_len;
 908                                           chan->in_len = fifo_data_len;
 909
 910                                           chan->rxcount += fifo_data_len;
 911                                         }
 912                                  else
 913                                         {
 914                                           NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
 915                                           chan->in_cbptr = chan->in_mbuf->m_data;
 916                                           chan->in_len = 0;
 917                                         }
 918                           }
 919                 } /* if(error == 0) */
 920                 else
 921                 {
 922                         /* land here for RDO */
 923                         if (chan->in_mbuf != NULL)
 924                         {
 925                                 i4b_Bfreembuf(chan->in_mbuf);
 926                                 chan->in_mbuf = NULL;
 927                                 chan->in_cbptr = NULL;
 928                                 chan->in_len = 0;
 929                         }
 930                         sc->avma1pp_txl = 0;
 931                         sc->avma1pp_cmd |= HSCX_CMD_RRS;
 932                         AVMA1PPSETCMDLONG(param);
 933                         hscx_write_reg(h_chan, HSCX_STAT, param, sc);
 934                         sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
 935                         AVMA1PPSETCMDLONG(param);
 936                         hscx_write_reg(h_chan, HSCX_STAT, param, sc);
 937                 }
 938         }
 939
 940
 941         /* transmit fifo empty, new data can be written to fifo */
 942
 943         if(stat & HSCX_INT_XPR)
 944         {
 945                 /*
 946                  * for a description what is going on here, please have
 947                  * a look at isic_bchannel_start() in i4b_bchan.c !
 948                  */
 949
 950                 NDBGL1(L1_H_IRQ, "unit %d, chan %d - XPR, Tx Fifo Empty!", sc->sc_unit, h_chan);
 951
 952                 if(chan->out_mbuf_cur == NULL)  /* last frame is transmitted */
 953                 {
 954                         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
 955
 956                         if(chan->out_mbuf_head == NULL)
 957                         {
 958                                 chan->state &= ~HSCX_TX_ACTIVE;
 959                                 (*chan->isic_drvr_linktab->bch_tx_queue_empty)(chan->isic_drvr_linktab->unit);
 960                         }
 961                         else
 962                         {
 963                                 chan->state |= HSCX_TX_ACTIVE;
 964                                 chan->out_mbuf_cur = chan->out_mbuf_head;
 965                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
 966                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
 967
 968                                 if(sc->sc_trace & TRACE_B_TX)
 969                                 {
 970                                         i4b_trace_hdr_t hdr;
 971                                         hdr.unit = L0IFPIUNIT(sc->sc_unit);
 972                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 973                                         hdr.dir = FROM_TE;
 974                                         hdr.count = ++sc->sc_trace_bcount;
 975                                         MICROTIME(hdr.time);
 976                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
 977                                 }
 978
 979                                 if(chan->bprot == BPROT_NONE)
 980                                 {
 981                                         if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
 982                                                 activity = ACT_TX;
 983                                 }
 984                                 else
 985                                 {
 986                                         activity = ACT_TX;
 987                                 }
 988                         }
 989                 }
 990
 991                 avma1pp_hscx_fifo(chan, sc);
 992         }
 993
 994         /* call timeout handling routine */
 995
 996         if(activity == ACT_RX || activity == ACT_TX)
 997                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
 998 }
 999
1000 /*
1001  * this is the main routine which checks each channel and then calls
1002  * the real interrupt routine as appropriate
1003  */
1004 static void
1005 avma1pp_hscx_int_handler(struct l1_softc *sc)
1006 {
1007         u_int stat;
1008
1009         /* has to be a u_int because the byte count is in the 2nd byte */
1010         stat = hscx_read_reg_int(0, HSCX_STAT, sc);
1011         if (stat & HSCX_INT_MASK)
1012           avma1pp_hscx_intr(0, stat, sc);
1013         stat = hscx_read_reg_int(1, HSCX_STAT, sc);
1014         if (stat & HSCX_INT_MASK)
1015           avma1pp_hscx_intr(1, stat, sc);
1016 }
1017
1018 static void
1019 avma1pp_disable(device_t dev)
1020 {
1021         struct l1_softc *sc = device_get_softc(dev);
1022         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
1023         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
1024
1025         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
1026 }
1027
1028 static void
1029 avma1pp_intr(void *xsc)
1030 {
1031         u_char stat;
1032         struct l1_softc *sc;
1033         bus_space_handle_t bhandle;
1034         bus_space_tag_t btag;
1035
1036         sc = xsc;
1037         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
1038         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
1039
1040         stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
1041         NDBGL1(L1_H_IRQ, "stat %x", stat);
1042         /* was there an interrupt from this card ? */
1043         if ((stat & ASL_IRQ_Pending) == ASL_IRQ_Pending)
1044                 return; /* no */
1045         /* interrupts are low active */
1046         if (!(stat & ASL_IRQ_TIMER))
1047           NDBGL1(L1_H_IRQ, "timer interrupt ???");
1048         if (!(stat & ASL_IRQ_HSCX))
1049         {
1050           NDBGL1(L1_H_IRQ, "HSCX");
1051                 avma1pp_hscx_int_handler(sc);
1052         }
1053         if (!(stat & ASL_IRQ_ISAC))
1054         {
1055           NDBGL1(L1_H_IRQ, "ISAC");
1056                 ifpi_isac_intr(sc);
1057         }
1058 }
1059
1060 static void
1061 avma1pp_hscx_init(struct l1_softc *sc, int h_chan, int activate)
1062 {
1063         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1064         u_int param = 0;
1065
1066         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1067                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1068
1069         if (activate == 0)
1070         {
1071                 /* only deactivate if both channels are idle */
1072                 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
1073                         sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
1074                 {
1075                         return;
1076                 }
1077                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1078                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1079                 AVMA1PPSETCMDLONG(param);
1080                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1081                 return;
1082         }
1083         if(chan->bprot == BPROT_RHDLC)
1084         {
1085                   NDBGL1(L1_BCHAN, "BPROT_RHDLC");
1086
1087                 /* HDLC Frames, transparent mode 0 */
1088                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1089                 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
1090                 AVMA1PPSETCMDLONG(param);
1091                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1092                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1093                 AVMA1PPSETCMDLONG(param);
1094                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1095                 sc->avma1pp_cmd = 0;
1096         }
1097         else
1098         {
1099                   NDBGL1(L1_BCHAN, "BPROT_NONE??");
1100
1101                 /* Raw Telephony, extended transparent mode 1 */
1102                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1103                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1104                 AVMA1PPSETCMDLONG(param);
1105                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1106                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1107                 AVMA1PPSETCMDLONG(param);
1108                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1109                 sc->avma1pp_cmd = 0;
1110         }
1111 }
1112
1113 static void
1114 avma1pp_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1115 {
1116 #if defined(__DragonFly__) || defined(__FreeBSD__)
1117         struct l1_softc *sc = ifpi_scp[unit];
1118 #else
1119         struct l1_softc *sc = isic_find_sc(unit);
1120 #endif
1121         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1122
1123         int s = SPLI4B();
1124
1125         if(activate == 0)
1126         {
1127                 /* deactivation */
1128                 chan->state = HSCX_IDLE;
1129                 avma1pp_hscx_init(sc, h_chan, activate);
1130         }
1131
1132         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1133                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1134
1135         /* general part */
1136
1137         chan->unit = sc->sc_unit;       /* unit number */
1138         chan->channel = h_chan;         /* B channel */
1139         chan->bprot = bprot;            /* B channel protocol */
1140         chan->state = HSCX_IDLE;        /* B channel state */
1141
1142         /* receiver part */
1143
1144         chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1145
1146         i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1147
1148         chan->rxcount = 0;              /* reset rx counter */
1149
1150         i4b_Bfreembuf(chan->in_mbuf);   /* clean rx mbuf */
1151
1152         chan->in_mbuf = NULL;           /* reset mbuf ptr */
1153         chan->in_cbptr = NULL;          /* reset mbuf curr ptr */
1154         chan->in_len = 0;               /* reset mbuf data len */
1155
1156         /* transmitter part */
1157
1158         chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1159
1160         i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1161
1162         chan->txcount = 0;              /* reset tx counter */
1163
1164         i4b_Bfreembuf(chan->out_mbuf_head);     /* clean tx mbuf */
1165
1166         chan->out_mbuf_head = NULL;     /* reset head mbuf ptr */
1167         chan->out_mbuf_cur = NULL;      /* reset current mbuf ptr */
1168         chan->out_mbuf_cur_ptr = NULL;  /* reset current mbuf data ptr */
1169         chan->out_mbuf_cur_len = 0;     /* reset current mbuf data cnt */
1170
1171         if(activate != 0)
1172         {
1173                 /* activation */
1174                 avma1pp_hscx_init(sc, h_chan, activate);
1175                 chan->state |= HSCX_AVMA1PP_ACTIVE;
1176         }
1177
1178         splx(s);
1179 }
1180
1181 static void
1182 avma1pp_bchannel_start(int unit, int h_chan)
1183 {
1184 #if defined(__DragonFly__) || defined(__FreeBSD__)
1185         struct l1_softc *sc = ifpi_scp[unit];
1186 #else
1187         struct l1_softc *sc = isic_find_sc(unit);
1188 #endif
1189         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1190         int s;
1191         int activity = -1;
1192
1193         s = SPLI4B();                           /* enter critical section */
1194         if(chan->state & HSCX_TX_ACTIVE)        /* already running ? */
1195         {
1196                 splx(s);
1197                 return;                         /* yes, leave */
1198         }
1199
1200         /* get next mbuf from queue */
1201
1202         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1203
1204         if(chan->out_mbuf_head == NULL)         /* queue empty ? */
1205         {
1206                 splx(s);                        /* leave critical section */
1207                 return;                         /* yes, exit */
1208         }
1209
1210         /* init current mbuf values */
1211
1212         chan->out_mbuf_cur = chan->out_mbuf_head;
1213         chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1214         chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1215
1216         /* activity indicator for timeout handling */
1217
1218         if(chan->bprot == BPROT_NONE)
1219         {
1220                 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1221                         activity = ACT_TX;
1222         }
1223         else
1224         {
1225                 activity = ACT_TX;
1226         }
1227
1228         chan->state |= HSCX_TX_ACTIVE;          /* we start transmitting */
1229
1230         if(sc->sc_trace & TRACE_B_TX)   /* if trace, send mbuf to trace dev */
1231         {
1232                 i4b_trace_hdr_t hdr;
1233                 hdr.unit = L0IFPIUNIT(sc->sc_unit);
1234                 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1235                 hdr.dir = FROM_TE;
1236                 hdr.count = ++sc->sc_trace_bcount;
1237                 MICROTIME(hdr.time);
1238                 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1239         }
1240
1241         avma1pp_hscx_fifo(chan, sc);
1242
1243         /* call timeout handling routine */
1244
1245         if(activity == ACT_RX || activity == ACT_TX)
1246                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
1247
1248         splx(s);
1249 }
1250
1251 /*---------------------------------------------------------------------------*
1252  *      return the address of isic drivers linktab
1253  *---------------------------------------------------------------------------*/
1254 static isdn_link_t *
1255 avma1pp_ret_linktab(int unit, int channel)
1256 {
1257 #if defined(__DragonFly__) || defined(__FreeBSD__)
1258         struct l1_softc *sc = ifpi_scp[unit];
1259 #else
1260         struct l1_softc *sc = isic_find_sc(unit);
1261 #endif
1262         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1263
1264         return(&chan->isic_isdn_linktab);
1265 }
1266
1267 /*---------------------------------------------------------------------------*
1268  *      set the driver linktab in the b channel softc
1269  *---------------------------------------------------------------------------*/
1270 static void
1271 avma1pp_set_linktab(int unit, int channel, drvr_link_t *dlt)
1272 {
1273 #if defined(__DragonFly__) || defined(__FreeBSD__)
1274         struct l1_softc *sc = ifpi_scp[unit];
1275 #else
1276         struct l1_softc *sc = isic_find_sc(unit);
1277 #endif
1278         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1279
1280         chan->isic_drvr_linktab = dlt;
1281 }
1282
1283
1284 /*---------------------------------------------------------------------------*
1285  *      initialize our local linktab
1286  *---------------------------------------------------------------------------*/
1287 static void
1288 avma1pp_init_linktab(struct l1_softc *sc)
1289 {
1290         l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1291         isdn_link_t *lt = &chan->isic_isdn_linktab;
1292
1293         /* make sure the hardware driver is known to layer 4 */
1294         /* avoid overwriting if already set */
1295         if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
1296         {
1297                 ctrl_types[CTRL_PASSIVE].set_linktab = avma1pp_set_linktab;
1298                 ctrl_types[CTRL_PASSIVE].get_linktab = avma1pp_ret_linktab;
1299         }
1300
1301         /* local setup */
1302         lt->unit = sc->sc_unit;
1303         lt->channel = HSCX_CH_A;
1304         lt->bch_config = avma1pp_bchannel_setup;
1305         lt->bch_tx_start = avma1pp_bchannel_start;
1306         lt->bch_stat = avma1pp_bchannel_stat;
1307         lt->tx_queue = &chan->tx_queue;
1308
1309         /* used by non-HDLC data transfers, i.e. telephony drivers */
1310         lt->rx_queue = &chan->rx_queue;
1311
1312         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1313         lt->rx_mbuf = &chan->in_mbuf;
1314
1315         chan = &sc->sc_chan[HSCX_CH_B];
1316         lt = &chan->isic_isdn_linktab;
1317
1318         lt->unit = sc->sc_unit;
1319         lt->channel = HSCX_CH_B;
1320         lt->bch_config = avma1pp_bchannel_setup;
1321         lt->bch_tx_start = avma1pp_bchannel_start;
1322         lt->bch_stat = avma1pp_bchannel_stat;
1323         lt->tx_queue = &chan->tx_queue;
1324
1325         /* used by non-HDLC data transfers, i.e. telephony drivers */
1326         lt->rx_queue = &chan->rx_queue;
1327
1328         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1329         lt->rx_mbuf = &chan->in_mbuf;
1330 }
1331
1332 /*
1333  * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1334  */
1335 static void
1336 avma1pp_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
1337 {
1338 #if defined(__DragonFly__) || defined(__FreeBSD__)
1339         struct l1_softc *sc = ifpi_scp[unit];
1340 #else
1341         struct l1_softc *sc = isic_find_sc(unit);
1342 #endif
1343         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1344         int s;
1345
1346         s = SPLI4B();
1347
1348         bsp->outbytes = chan->txcount;
1349         bsp->inbytes = chan->rxcount;
1350
1351         chan->txcount = 0;
1352         chan->rxcount = 0;
1353
1354         splx(s);
1355 }
1356
1357 /*---------------------------------------------------------------------------*
1358  *      fill HSCX fifo with data from the current mbuf
1359  *      Put this here until it can go into i4b_hscx.c
1360  *---------------------------------------------------------------------------*/
1361 static int
1362 avma1pp_hscx_fifo(l1_bchan_state_t *chan, struct l1_softc *sc)
1363 {
1364         int len;
1365         int nextlen;
1366         int i;
1367         int cmd = 0;
1368         /* using a scratch buffer simplifies writing to the FIFO */
1369         u_char scrbuf[HSCX_FIFO_LEN];
1370
1371         len = 0;
1372
1373         /*
1374          * fill the HSCX tx fifo with data from the current mbuf. if
1375          * current mbuf holds less data than HSCX fifo length, try to
1376          * get the next mbuf from (a possible) mbuf chain. if there is
1377          * not enough data in a single mbuf or in a chain, then this
1378          * is the last mbuf and we tell the HSCX that it has to send
1379          * CRC and closing flag
1380          */
1381
1382         while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1383         {
1384                 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1385
1386 #ifdef NOTDEF
1387                 printf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1388                         chan->out_mbuf_head,
1389                         chan->out_mbuf_cur,
1390                         chan->out_mbuf_cur_ptr,
1391                         chan->out_mbuf_cur_len,
1392                         len,
1393                         nextlen);
1394 #endif
1395
1396                 cmd |= HSCX_CMDR_XTF;
1397                 /* collect the data in the scratch buffer */
1398                 for (i = 0; i < nextlen; i++)
1399                         scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1400
1401                 len += nextlen;
1402                 chan->txcount += nextlen;
1403
1404                 chan->out_mbuf_cur_ptr += nextlen;
1405                 chan->out_mbuf_cur_len -= nextlen;
1406
1407                 if(chan->out_mbuf_cur_len == 0)
1408                 {
1409                         if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1410                         {
1411                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1412                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1413
1414                                 if(sc->sc_trace & TRACE_B_TX)
1415                                 {
1416                                         i4b_trace_hdr_t hdr;
1417                                         hdr.unit = L0IFPIUNIT(sc->sc_unit);
1418                                         hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1419                                         hdr.dir = FROM_TE;
1420                                         hdr.count = ++sc->sc_trace_bcount;
1421                                         MICROTIME(hdr.time);
1422                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1423                                 }
1424                         }
1425                         else
1426                         {
1427                                 if (chan->bprot != BPROT_NONE)
1428                                         cmd |= HSCX_CMDR_XME;
1429                                 i4b_Bfreembuf(chan->out_mbuf_head);
1430                                 chan->out_mbuf_head = NULL;
1431                         }
1432                 }
1433         }
1434         /* write what we have from the scratch buf to the HSCX fifo */
1435         if (len != 0)
1436                 HSCX_WRFIFO(chan->channel, scrbuf, len);
1437         return(cmd);
1438 }
1439
1440 /*---------------------------------------------------------------------------*
1441  *      ifpi - ISAC interrupt routine
1442  *---------------------------------------------------------------------------*/
1443 static void
1444 ifpi_isac_intr(struct l1_softc *sc)
1445 {
1446         u_char isac_irq_stat;
1447
1448         for(;;)
1449         {
1450                 /* get isac irq status */
1451                 isac_irq_stat = ISAC_READ(I_ISTA);
1452
1453                 if(isac_irq_stat)
1454                         ifpi_isac_irq(sc, isac_irq_stat); /* isac handler */
1455                 else
1456                         break;
1457         }
1458
1459         ISAC_WRITE(I_MASK, 0xff);
1460
1461         DELAY(100);
1462
1463         ISAC_WRITE(I_MASK, ISAC_IMASK);
1464 }
1465
1466 /*---------------------------------------------------------------------------*
1467  *      ifpi_recover - try to recover from irq lockup
1468  *---------------------------------------------------------------------------*/
1469 void
1470 ifpi_recover(struct l1_softc *sc)
1471 {
1472         u_char byte;
1473
1474         /* get isac irq status */
1475
1476         byte = ISAC_READ(I_ISTA);
1477
1478         NDBGL1(L1_ERROR, "  ISAC: ISTA = 0x%x", byte);
1479
1480         if(byte & ISAC_ISTA_EXI)
1481                 NDBGL1(L1_ERROR, "  ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
1482
1483         if(byte & ISAC_ISTA_CISQ)
1484         {
1485                 byte = ISAC_READ(I_CIRR);
1486
1487                 NDBGL1(L1_ERROR, "  ISAC: CISQ = 0x%x", byte);
1488
1489                 if(byte & ISAC_CIRR_SQC)
1490                         NDBGL1(L1_ERROR, "  ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
1491         }
1492
1493         NDBGL1(L1_ERROR, "  ISAC: IMASK = 0x%x", ISAC_IMASK);
1494
1495         ISAC_WRITE(I_MASK, 0xff);
1496         DELAY(100);
1497         ISAC_WRITE(I_MASK, ISAC_IMASK);
1498 }
1499
1500
1501 #endif /* NIFPI > 0 */