2 * Copyright (c) 1997, 2001 Hellmuth Michaelis. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 *---------------------------------------------------------------------------
27 * i4b_usr_sti.c - USRobotics Sportster ISDN TA intern (Tina-pp)
28 * -------------------------------------------------------------
30 * $FreeBSD: src/sys/i4b/layer1/isic/i4b_usr_sti.c,v 1.5.2.1 2001/08/10 14:08:39 obrien Exp $
31 * $DragonFly: src/sys/net/i4b/layer1/isic/i4b_usr_sti.c,v 1.4 2003/08/07 21:17:26 dillon Exp $
33 * last edit-date: [Wed Jan 24 09:28:12 2001]
35 *---------------------------------------------------------------------------*/
40 #if (NISIC > 0) && defined(USR_STI)
42 #include <sys/param.h>
43 #include <sys/systm.h>
45 #include <machine/bus.h>
48 #include <sys/socket.h>
51 #include <net/i4b/include/machine/i4b_ioctl.h>
52 #include <net/i4b/include/machine/i4b_trace.h>
54 #include "../i4b_l1.h"
58 /*---------------------------------------------------------------------------*
59 * USR Sportster TA intern special registers
60 *---------------------------------------------------------------------------*/
61 #define USR_HSCXA_OFF 0x0000
62 #define USR_HSCXB_OFF 0x4000
63 #define USR_INTL_OFF 0x8000
64 #define USR_ISAC_OFF 0xc000
66 #define USR_RES_BIT 0x80 /* 0 = normal, 1 = reset ISAC/HSCX */
67 #define USR_INTE_BIT 0x40 /* 0 = IRQ disabled, 1 = IRQ's enabled */
68 #define USR_IL_MASK 0x07 /* IRQ level config */
70 static u_char intr_no[] = { 0, 0, 0, 0, 0, 1, 0, 2, 0, 0, 3, 4, 5, 0, 6, 7 };
73 (((reg/4) * 1024) + ((reg%4) * 2))
75 #ifdef USRTA_DEBUG_PORTACCESS
77 #define USRTA_DEBUG(fmt) \
78 if (++debugcntr < 1000) printf fmt;
80 #define USRTA_DEBUG(fmt)
83 /*---------------------------------------------------------------------------*
84 * USRobotics read fifo routine
85 *---------------------------------------------------------------------------*/
87 usrtai_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
90 unsigned int base = 0;
92 USRTA_DEBUG(("usrtai_read_fifo: what %d size %d\n", what, size))
96 base = (unsigned int)ISAC_BASE;
99 base = (unsigned int)HSCX_A_BASE;
101 case ISIC_WHAT_HSCXB:
102 base = (unsigned int)HSCX_B_BASE;
105 printf("usrtai_read_fifo: invalid what %d\n", what);
109 for(;size > 0; size--, offset++)
111 *((u_char *)buf + offset) = inb(base + ADDR(offset));
115 /*---------------------------------------------------------------------------*
116 * USRobotics write fifo routine
117 *---------------------------------------------------------------------------*/
119 usrtai_write_fifo(struct l1_softc *sc, int what, void *data, size_t size)
122 unsigned int base = 0;
124 USRTA_DEBUG(("usrtai_write_fifo: what %d size %d\n", what, size))
128 base = (unsigned int)ISAC_BASE;
130 case ISIC_WHAT_HSCXA:
131 base = (unsigned int)HSCX_A_BASE;
133 case ISIC_WHAT_HSCXB:
134 base = (unsigned int)HSCX_B_BASE;
137 printf("usrtai_write_fifo: invalid what %d\n", what);
142 for(;size > 0; size--, offset++)
144 outb(base + ADDR(offset), *((u_char *)data + offset));
148 /*---------------------------------------------------------------------------*
149 * USRobotics write register routine
150 *---------------------------------------------------------------------------*/
152 usrtai_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
154 unsigned int base = 0;
156 USRTA_DEBUG(("usrtai_write_reg: what %d ADDR(%d) %d data %#x\n", what, offs, ADDR(offs), data))
160 base = (unsigned int)ISAC_BASE;
162 case ISIC_WHAT_HSCXA:
163 base = (unsigned int)HSCX_A_BASE;
165 case ISIC_WHAT_HSCXB:
166 base = (unsigned int)HSCX_B_BASE;
169 printf("usrtai_write_reg invalid what %d\n", what);
173 outb(base + ADDR(offs), (u_char)data);
176 /*---------------------------------------------------------------------------*
177 * USRobotics read register routine
178 *---------------------------------------------------------------------------*/
180 usrtai_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
182 unsigned int base = 0;
185 USRTA_DEBUG(("usrtai_read_reg: what %d ADDR(%d) %d..", what, offs, ADDR(offs)))
189 base = (unsigned int)ISAC_BASE;
191 case ISIC_WHAT_HSCXA:
192 base = (unsigned int)HSCX_A_BASE;
194 case ISIC_WHAT_HSCXB:
195 base = (unsigned int)HSCX_B_BASE;
198 printf("usrtai_read_reg: invalid what %d\n", what);
202 byte = inb(base + ADDR(offs));
203 USRTA_DEBUG(("usrtai_read_reg: got %#x\n", byte))
207 /*---------------------------------------------------------------------------*
208 * allocate an io port - based on code in isa_isic.c
209 *---------------------------------------------------------------------------*/
211 usrtai_alloc_port(device_t dev)
213 size_t unit = device_get_unit(dev);
214 struct l1_softc *sc = &l1_sc[unit];
218 /* 49 io mappings: 1 config and 48x8 registers */
220 /* config at offset 0x8000 */
221 base = sc->sc_port + 0x8000;
222 if (base < 0 || base > 0x0ffff)
224 sc->sc_resources.io_rid[num] = num;
226 bus_set_resource(dev, SYS_RES_IOPORT, num, base, 1);
228 if(!(sc->sc_resources.io_base[num] =
229 bus_alloc_resource(dev, SYS_RES_IOPORT,
230 &sc->sc_resources.io_rid[num],
231 0ul, ~0ul, 1, RF_ACTIVE)))
233 printf("isic%d: Error, failed to reserve io #%dport %#x!\n", unit, num, base);
234 isic_detach_common(dev);
239 /* HSCX A at offset 0 */
241 for (i = 0; i < 16; i++) {
242 if (base+i*1024 < 0 || base+i*1024+8 > 0x0ffff)
244 sc->sc_resources.io_rid[num] = num;
246 bus_set_resource(dev, SYS_RES_IOPORT, num, base+i*1024, 8);
248 if(!(sc->sc_resources.io_base[num] =
249 bus_alloc_resource(dev, SYS_RES_IOPORT,
250 &sc->sc_resources.io_rid[num],
251 0ul, ~0ul, 1, RF_ACTIVE)))
253 printf("isic%d: Error, failed to reserve io #%d port %#x!\n", unit, num, base+i*1024);
254 isic_detach_common(dev);
260 /* HSCX B at offset 0x4000 */
261 base = sc->sc_port + 0x4000;
262 for (i = 0; i < 16; i++) {
263 if (base+i*1024 < 0 || base+i*1024+8 > 0x0ffff)
265 sc->sc_resources.io_rid[num] = num;
267 bus_set_resource(dev, SYS_RES_IOPORT, num, base+i*1024, 8);
269 if(!(sc->sc_resources.io_base[num] =
270 bus_alloc_resource(dev, SYS_RES_IOPORT,
271 &sc->sc_resources.io_rid[num],
272 0ul, ~0ul, 1, RF_ACTIVE)))
274 printf("isic%d: Error, failed to reserve io #%d port %#x!\n", unit, num, base+i*1024);
275 isic_detach_common(dev);
281 /* ISAC at offset 0xc000 */
282 base = sc->sc_port + 0xc000;
283 for (i = 0; i < 16; i++) {
284 if (base+i*1024 < 0 || base+i*1024+8 > 0x0ffff)
286 sc->sc_resources.io_rid[num] = num;
288 bus_set_resource(dev, SYS_RES_IOPORT, num, base+i*1024, 8);
290 if(!(sc->sc_resources.io_base[num] =
291 bus_alloc_resource(dev, SYS_RES_IOPORT,
292 &sc->sc_resources.io_rid[num],
293 0ul, ~0ul, 1, RF_ACTIVE)))
295 printf("isic%d: Error, failed to reserve io #%d port %#x!\n", unit, num, base+i*1024);
296 isic_detach_common(dev);
305 /*---------------------------------------------------------------------------*
306 * isic_probe_usrtai - probe for USR
307 *---------------------------------------------------------------------------*/
309 isic_probe_usrtai(device_t dev)
311 size_t unit = device_get_unit(dev); /* get unit */
312 struct l1_softc *sc = 0; /* pointer to softc */
313 void *ih = 0; /* dummy */
315 /* check max unit range */
317 if(unit >= ISIC_MAXUNIT)
319 printf("isic%d: Error, unit %d >= ISIC_MAXUNIT for USR Sportster TA!\n",
324 sc = &l1_sc[unit]; /* get pointer to softc */
325 sc->sc_unit = unit; /* set unit */
327 /* see if an io base was supplied */
329 if(!(sc->sc_resources.io_base[0] =
330 bus_alloc_resource(dev, SYS_RES_IOPORT,
331 &sc->sc_resources.io_rid[0],
332 0ul, ~0ul, 1, RF_ACTIVE)))
334 printf("isic%d: Could not get iobase for USR Sportster TA!\n",
341 sc->sc_port = rman_get_start(sc->sc_resources.io_base[0]);
343 /* release io base */
345 bus_release_resource(dev, SYS_RES_IOPORT, sc->sc_resources.io_rid[0],
346 sc->sc_resources.io_base[0]);
349 /* check if we got an iobase */
372 printf("isic%d: Error, invalid iobase 0x%x specified for USR Sportster TA!\n",
378 /* allocate all the ports needed */
380 if(usrtai_alloc_port(dev))
382 printf("isic%d: Could not get the ports for USR Sportster TA!\n", unit);
383 isic_detach_common(dev);
389 if(!(sc->sc_resources.irq =
390 bus_alloc_resource(dev, SYS_RES_IRQ,
391 &sc->sc_resources.irq_rid,
392 0ul, ~0ul, 1, RF_ACTIVE)))
394 printf("isic%d: Could not get an irq for USR Sportster TA!\n",unit);
395 isic_detach_common(dev);
399 /* get the irq number */
400 sc->sc_irq = rman_get_start(sc->sc_resources.irq);
402 /* register interrupt routine */
403 bus_setup_intr(dev, sc->sc_resources.irq, INTR_TYPE_NET,
404 (void(*)(void *))(isicintr),
407 /* check IRQ validity */
409 if(intr_no[sc->sc_irq] == 0)
411 printf("isic%d: Error, invalid IRQ [%d] specified for USR Sportster TA!\n",
416 /* setup ISAC access routines */
419 sc->readreg = usrtai_read_reg;
420 sc->writereg = usrtai_write_reg;
422 sc->readfifo = usrtai_read_fifo;
423 sc->writefifo = usrtai_write_fifo;
425 /* setup card type */
427 sc->sc_cardtyp = CARD_TYPEP_USRTA;
429 /* setup IOM bus type */
431 sc->sc_bustyp = BUS_TYPE_IOM2;
434 sc->sc_bfifolen = HSCX_FIFO_LEN;
436 /* setup ISAC and HSCX base addr */
438 ISAC_BASE = (caddr_t)sc->sc_port + USR_ISAC_OFF;
439 HSCX_A_BASE = (caddr_t)sc->sc_port + USR_HSCXA_OFF;
440 HSCX_B_BASE = (caddr_t)sc->sc_port + USR_HSCXB_OFF;
443 * Read HSCX A/B VSTR. Expected value for USR Sportster TA based
444 * boards is 0x05 in the least significant bits.
447 if( ((HSCX_READ(0, H_VSTR) & 0xf) != 0x5) ||
448 ((HSCX_READ(1, H_VSTR) & 0xf) != 0x5) )
450 printf("isic%d: HSCX VSTR test failed for USR Sportster TA\n",
452 printf("isic%d: HSC0: VSTR: %#x\n",
453 unit, HSCX_READ(0, H_VSTR));
454 printf("isic%d: HSC1: VSTR: %#x\n",
455 unit, HSCX_READ(1, H_VSTR));
462 /*---------------------------------------------------------------------------*
463 * isic_attach_usrtai - attach USR
464 *---------------------------------------------------------------------------*/
466 isic_attach_usrtai(device_t dev)
469 size_t unit = device_get_unit(dev); /* get unit */
470 struct l1_softc *sc = 0; /* pointer to softc */
472 sc = &l1_sc[unit]; /* get pointer to softc */
474 /* reset the HSCX and ISAC chips */
476 outb(sc->sc_port + USR_INTL_OFF, USR_RES_BIT);
477 DELAY(SEC_DELAY / 10);
479 outb(sc->sc_port + USR_INTL_OFF, 0x00);
480 DELAY(SEC_DELAY / 10);
484 if((irq = intr_no[sc->sc_irq]) == 0)
486 printf("isic%d: Attach error, invalid IRQ [%d] specified for USR Sportster TA!\n",
491 /* configure and enable irq */
493 outb(sc->sc_port + USR_INTL_OFF, irq | USR_INTE_BIT);
494 DELAY(SEC_DELAY / 10);
499 #endif /* ISIC > 0 */