2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_ti.c,v 1.25.2.14 2002/02/15 04:20:20 silby Exp $
33 * $DragonFly: src/sys/dev/netif/ti/if_ti.c,v 1.5 2003/08/27 09:38:33 rob Exp $
35 * $FreeBSD: src/sys/pci/if_ti.c,v 1.25.2.14 2002/02/15 04:20:20 silby Exp $
39 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
40 * Manuals, sample driver and firmware source kits are available
41 * from http://www.alteon.com/support/openkits.
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
49 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
50 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
51 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
52 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
53 * filtering and jumbo (9014 byte) frames. The hardware is largely
54 * controlled by firmware, which must be loaded into the NIC during
57 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
58 * revision, which supports new features such as extended commands,
59 * extended jumbo receive ring desciptors and a mini receive ring.
61 * Alteon Networks is to be commended for releasing such a vast amount
62 * of development material for the Tigon NIC without requiring an NDA
63 * (although they really should have done it a long time ago). With
64 * any luck, the other vendors will finally wise up and follow Alteon's
67 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
68 * this driver by #including it as a C header file. This bloats the
69 * driver somewhat, but it's the easiest method considering that the
70 * driver code and firmware code need to be kept in sync. The source
71 * for the firmware is not provided with the FreeBSD distribution since
72 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
74 * The following people deserve special thanks:
75 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
77 * - Raymond Lee of Netgear, for providing a pair of Netgear
78 * GA620 Tigon 2 boards for testing
79 * - Ulf Zimmermann, for bringing the GA260 to my attention and
80 * convincing me to write this driver.
81 * - Andrew Gallatin for providing FreeBSD/Alpha support.
84 #include <sys/param.h>
85 #include <sys/systm.h>
86 #include <sys/sockio.h>
88 #include <sys/malloc.h>
89 #include <sys/kernel.h>
90 #include <sys/socket.h>
91 #include <sys/queue.h>
94 #include <net/if_arp.h>
95 #include <net/ethernet.h>
96 #include <net/if_dl.h>
97 #include <net/if_media.h>
98 #include <net/if_types.h>
99 #include <net/vlan/if_vlan_var.h>
103 #include <netinet/in_systm.h>
104 #include <netinet/in.h>
105 #include <netinet/ip.h>
107 #include <vm/vm.h> /* for vtophys */
108 #include <vm/pmap.h> /* for vtophys */
109 #include <machine/clock.h> /* for DELAY */
110 #include <machine/bus_memio.h>
111 #include <machine/bus.h>
112 #include <machine/resource.h>
114 #include <sys/rman.h>
116 #include <bus/pci/pcireg.h>
117 #include <bus/pci/pcivar.h>
119 #include "if_tireg.h"
124 * Temporarily disable the checksum offload support for now.
125 * Tests with ftp.freesoftware.com show that after about 12 hours,
126 * the firmware will begin calculating completely bogus TX checksums
127 * and refuse to stop until the interface is reset. Unfortunately,
128 * there isn't enough time to fully debug this before the 4.1
129 * release, so this will need to stay off for now.
132 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
134 #define TI_CSUM_FEATURES 0
138 * Various supported device vendors/types and their names.
141 static struct ti_type ti_devs[] = {
142 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
143 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
144 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
145 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
146 { TC_VENDORID, TC_DEVICEID_3C985,
147 "3Com 3c985-SX Gigabit Ethernet" },
148 { NG_VENDORID, NG_DEVICEID_GA620,
149 "Netgear GA620 1000baseSX Gigabit Ethernet" },
150 { NG_VENDORID, NG_DEVICEID_GA620T,
151 "Netgear GA620 1000baseT Gigabit Ethernet" },
152 { SGI_VENDORID, SGI_DEVICEID_TIGON,
153 "Silicon Graphics Gigabit Ethernet" },
154 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
155 "Farallon PN9000SX Gigabit Ethernet" },
159 static int ti_probe (device_t);
160 static int ti_attach (device_t);
161 static int ti_detach (device_t);
162 static void ti_txeof (struct ti_softc *);
163 static void ti_rxeof (struct ti_softc *);
165 static void ti_stats_update (struct ti_softc *);
166 static int ti_encap (struct ti_softc *, struct mbuf *,
169 static void ti_intr (void *);
170 static void ti_start (struct ifnet *);
171 static int ti_ioctl (struct ifnet *, u_long, caddr_t);
172 static void ti_init (void *);
173 static void ti_init2 (struct ti_softc *);
174 static void ti_stop (struct ti_softc *);
175 static void ti_watchdog (struct ifnet *);
176 static void ti_shutdown (device_t);
177 static int ti_ifmedia_upd (struct ifnet *);
178 static void ti_ifmedia_sts (struct ifnet *, struct ifmediareq *);
180 static u_int32_t ti_eeprom_putbyte (struct ti_softc *, int);
181 static u_int8_t ti_eeprom_getbyte (struct ti_softc *,
183 static int ti_read_eeprom (struct ti_softc *, caddr_t, int, int);
185 static void ti_add_mcast (struct ti_softc *, struct ether_addr *);
186 static void ti_del_mcast (struct ti_softc *, struct ether_addr *);
187 static void ti_setmulti (struct ti_softc *);
189 static void ti_mem (struct ti_softc *, u_int32_t,
191 static void ti_loadfw (struct ti_softc *);
192 static void ti_cmd (struct ti_softc *, struct ti_cmd_desc *);
193 static void ti_cmd_ext (struct ti_softc *, struct ti_cmd_desc *,
195 static void ti_handle_events (struct ti_softc *);
196 static int ti_alloc_jumbo_mem (struct ti_softc *);
197 static void *ti_jalloc (struct ti_softc *);
198 static void ti_jfree (caddr_t, u_int);
199 static void ti_jref (caddr_t, u_int);
200 static int ti_newbuf_std (struct ti_softc *, int, struct mbuf *);
201 static int ti_newbuf_mini (struct ti_softc *, int, struct mbuf *);
202 static int ti_newbuf_jumbo (struct ti_softc *, int, struct mbuf *);
203 static int ti_init_rx_ring_std (struct ti_softc *);
204 static void ti_free_rx_ring_std (struct ti_softc *);
205 static int ti_init_rx_ring_jumbo (struct ti_softc *);
206 static void ti_free_rx_ring_jumbo (struct ti_softc *);
207 static int ti_init_rx_ring_mini (struct ti_softc *);
208 static void ti_free_rx_ring_mini (struct ti_softc *);
209 static void ti_free_tx_ring (struct ti_softc *);
210 static int ti_init_tx_ring (struct ti_softc *);
212 static int ti_64bitslot_war (struct ti_softc *);
213 static int ti_chipinit (struct ti_softc *);
214 static int ti_gibinit (struct ti_softc *);
216 static device_method_t ti_methods[] = {
217 /* Device interface */
218 DEVMETHOD(device_probe, ti_probe),
219 DEVMETHOD(device_attach, ti_attach),
220 DEVMETHOD(device_detach, ti_detach),
221 DEVMETHOD(device_shutdown, ti_shutdown),
225 static driver_t ti_driver = {
228 sizeof(struct ti_softc)
231 static devclass_t ti_devclass;
233 DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0);
236 * Send an instruction or address to the EEPROM, check for ACK.
238 static u_int32_t ti_eeprom_putbyte(sc, byte)
245 * Make sure we're in TX mode.
247 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
250 * Feed in each bit and stobe the clock.
252 for (i = 0x80; i; i >>= 1) {
254 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
256 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
259 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
261 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
267 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
272 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
273 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
274 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
280 * Read a byte of data stored in the EEPROM at address 'addr.'
281 * We have to send two address bytes since the EEPROM can hold
282 * more than 256 bytes of data.
284 static u_int8_t ti_eeprom_getbyte(sc, addr, dest)
295 * Send write control code to EEPROM.
297 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
298 printf("ti%d: failed to send write command, status: %x\n",
299 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
304 * Send first byte of address of byte we want to read.
306 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
307 printf("ti%d: failed to send address, status: %x\n",
308 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
312 * Send second byte address of byte we want to read.
314 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
315 printf("ti%d: failed to send address, status: %x\n",
316 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
323 * Send read control code to EEPROM.
325 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
326 printf("ti%d: failed to send read command, status: %x\n",
327 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
332 * Start reading bits from EEPROM.
334 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
335 for (i = 0x80; i; i >>= 1) {
336 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
338 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
340 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
347 * No ACK generated for read, so just return byte.
356 * Read a sequence of bytes from the EEPROM.
358 static int ti_read_eeprom(sc, dest, off, cnt)
367 for (i = 0; i < cnt; i++) {
368 err = ti_eeprom_getbyte(sc, off + i, &byte);
378 * NIC memory access function. Can be used to either clear a section
379 * of NIC local memory or (if buf is non-NULL) copy data into it.
381 static void ti_mem(sc, addr, len, buf)
386 int segptr, segsize, cnt;
387 caddr_t ti_winbase, ptr;
391 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW);
398 segsize = TI_WINLEN - (segptr % TI_WINLEN);
399 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
401 bzero((char *)ti_winbase + (segptr &
402 (TI_WINLEN - 1)), segsize);
404 bcopy((char *)ptr, (char *)ti_winbase +
405 (segptr & (TI_WINLEN - 1)), segsize);
416 * Load firmware image into the NIC. Check that the firmware revision
417 * is acceptable and see if we want the firmware for the Tigon 1 or
420 static void ti_loadfw(sc)
423 switch(sc->ti_hwrev) {
425 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
426 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
427 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
428 printf("ti%d: firmware revision mismatch; want "
429 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
430 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
431 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
432 tigonFwReleaseMinor, tigonFwReleaseFix);
435 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen,
436 (caddr_t)tigonFwText);
437 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen,
438 (caddr_t)tigonFwData);
439 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen,
440 (caddr_t)tigonFwRodata);
441 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL);
442 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL);
443 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
445 case TI_HWREV_TIGON_II:
446 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
447 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
448 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
449 printf("ti%d: firmware revision mismatch; want "
450 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
451 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
452 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
453 tigon2FwReleaseMinor, tigon2FwReleaseFix);
456 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen,
457 (caddr_t)tigon2FwText);
458 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen,
459 (caddr_t)tigon2FwData);
460 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
461 (caddr_t)tigon2FwRodata);
462 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL);
463 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL);
464 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
467 printf("ti%d: can't load firmware: unknown hardware rev\n",
476 * Send the NIC a command via the command ring.
478 static void ti_cmd(sc, cmd)
480 struct ti_cmd_desc *cmd;
484 if (sc->ti_rdata->ti_cmd_ring == NULL)
487 index = sc->ti_cmd_saved_prodidx;
488 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
489 TI_INC(index, TI_CMD_RING_CNT);
490 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
491 sc->ti_cmd_saved_prodidx = index;
497 * Send the NIC an extended command. The 'len' parameter specifies the
498 * number of command slots to include after the initial command.
500 static void ti_cmd_ext(sc, cmd, arg, len)
502 struct ti_cmd_desc *cmd;
509 if (sc->ti_rdata->ti_cmd_ring == NULL)
512 index = sc->ti_cmd_saved_prodidx;
513 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
514 TI_INC(index, TI_CMD_RING_CNT);
515 for (i = 0; i < len; i++) {
516 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
517 *(u_int32_t *)(&arg[i * 4]));
518 TI_INC(index, TI_CMD_RING_CNT);
520 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
521 sc->ti_cmd_saved_prodidx = index;
527 * Handle events that have triggered interrupts.
529 static void ti_handle_events(sc)
532 struct ti_event_desc *e;
534 if (sc->ti_rdata->ti_event_ring == NULL)
537 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
538 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
539 switch(e->ti_event) {
540 case TI_EV_LINKSTAT_CHANGED:
541 sc->ti_linkstat = e->ti_code;
542 if (e->ti_code == TI_EV_CODE_LINK_UP)
543 printf("ti%d: 10/100 link up\n", sc->ti_unit);
544 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP)
545 printf("ti%d: gigabit link up\n", sc->ti_unit);
546 else if (e->ti_code == TI_EV_CODE_LINK_DOWN)
547 printf("ti%d: link down\n", sc->ti_unit);
550 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD)
551 printf("ti%d: invalid command\n", sc->ti_unit);
552 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD)
553 printf("ti%d: unknown command\n", sc->ti_unit);
554 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG)
555 printf("ti%d: bad config data\n", sc->ti_unit);
557 case TI_EV_FIRMWARE_UP:
560 case TI_EV_STATS_UPDATED:
563 case TI_EV_RESET_JUMBO_RING:
564 case TI_EV_MCAST_UPDATED:
568 printf("ti%d: unknown event: %d\n",
569 sc->ti_unit, e->ti_event);
572 /* Advance the consumer index. */
573 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
574 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
581 * Memory management for the jumbo receive ring is a pain in the
582 * butt. We need to allocate at least 9018 bytes of space per frame,
583 * _and_ it has to be contiguous (unless you use the extended
584 * jumbo descriptor format). Using malloc() all the time won't
585 * work: malloc() allocates memory in powers of two, which means we
586 * would end up wasting a considerable amount of space by allocating
587 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
588 * to do our own memory management.
590 * The driver needs to allocate a contiguous chunk of memory at boot
591 * time. We then chop this up ourselves into 9K pieces and use them
592 * as external mbuf storage.
594 * One issue here is how much memory to allocate. The jumbo ring has
595 * 256 slots in it, but at 9K per slot than can consume over 2MB of
596 * RAM. This is a bit much, especially considering we also need
597 * RAM for the standard ring and mini ring (on the Tigon 2). To
598 * save space, we only actually allocate enough memory for 64 slots
599 * by default, which works out to between 500 and 600K. This can
600 * be tuned by changing a #define in if_tireg.h.
603 static int ti_alloc_jumbo_mem(sc)
608 struct ti_jpool_entry *entry;
610 /* Grab a big chunk o' storage. */
611 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF,
612 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
614 if (sc->ti_cdata.ti_jumbo_buf == NULL) {
615 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit);
619 SLIST_INIT(&sc->ti_jfree_listhead);
620 SLIST_INIT(&sc->ti_jinuse_listhead);
623 * Now divide it up into 9K pieces and save the addresses
624 * in an array. Note that we play an evil trick here by using
625 * the first few bytes in the buffer to hold the the address
626 * of the softc structure for this interface. This is because
627 * ti_jfree() needs it, but it is called by the mbuf management
628 * code which will not pass it to us explicitly.
630 ptr = sc->ti_cdata.ti_jumbo_buf;
631 for (i = 0; i < TI_JSLOTS; i++) {
633 aptr = (u_int64_t **)ptr;
634 aptr[0] = (u_int64_t *)sc;
635 ptr += sizeof(u_int64_t);
636 sc->ti_cdata.ti_jslots[i].ti_buf = ptr;
637 sc->ti_cdata.ti_jslots[i].ti_inuse = 0;
638 ptr += (TI_JLEN - sizeof(u_int64_t));
639 entry = malloc(sizeof(struct ti_jpool_entry),
642 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM,
644 sc->ti_cdata.ti_jumbo_buf = NULL;
645 printf("ti%d: no memory for jumbo "
646 "buffer queue!\n", sc->ti_unit);
650 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
657 * Allocate a jumbo buffer.
659 static void *ti_jalloc(sc)
662 struct ti_jpool_entry *entry;
664 entry = SLIST_FIRST(&sc->ti_jfree_listhead);
667 printf("ti%d: no free jumbo buffers\n", sc->ti_unit);
671 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
672 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
673 sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1;
674 return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf);
678 * Adjust usage count on a jumbo buffer. In general this doesn't
679 * get used much because our jumbo buffers don't get passed around
680 * too much, but it's implemented for correctness.
682 static void ti_jref(buf, size)
690 /* Extract the softc struct pointer. */
691 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
692 sc = (struct ti_softc *)(aptr[0]);
695 panic("ti_jref: can't find softc pointer!");
697 if (size != TI_JUMBO_FRAMELEN)
698 panic("ti_jref: adjusting refcount of buf of wrong size!");
700 /* calculate the slot this buffer belongs to */
702 i = ((vm_offset_t)aptr
703 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
705 if ((i < 0) || (i >= TI_JSLOTS))
706 panic("ti_jref: asked to reference buffer "
707 "that we don't manage!");
708 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0)
709 panic("ti_jref: buffer already free!");
711 sc->ti_cdata.ti_jslots[i].ti_inuse++;
717 * Release a jumbo buffer.
719 static void ti_jfree(buf, size)
726 struct ti_jpool_entry *entry;
728 /* Extract the softc struct pointer. */
729 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
730 sc = (struct ti_softc *)(aptr[0]);
733 panic("ti_jfree: can't find softc pointer!");
735 if (size != TI_JUMBO_FRAMELEN)
736 panic("ti_jfree: freeing buffer of wrong size!");
738 /* calculate the slot this buffer belongs to */
740 i = ((vm_offset_t)aptr
741 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
743 if ((i < 0) || (i >= TI_JSLOTS))
744 panic("ti_jfree: asked to free buffer that we don't manage!");
745 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0)
746 panic("ti_jfree: buffer already free!");
748 sc->ti_cdata.ti_jslots[i].ti_inuse--;
749 if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) {
750 entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
752 panic("ti_jfree: buffer not in use!");
754 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead,
756 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead,
757 entry, jpool_entries);
766 * Intialize a standard receive ring descriptor.
768 static int ti_newbuf_std(sc, i, m)
773 struct mbuf *m_new = NULL;
774 struct ti_rx_desc *r;
777 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
781 MCLGET(m_new, M_DONTWAIT);
782 if (!(m_new->m_flags & M_EXT)) {
786 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
789 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
790 m_new->m_data = m_new->m_ext.ext_buf;
793 m_adj(m_new, ETHER_ALIGN);
794 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
795 r = &sc->ti_rdata->ti_rx_std_ring[i];
796 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
797 r->ti_type = TI_BDTYPE_RECV_BD;
799 if (sc->arpcom.ac_if.if_hwassist)
800 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
801 r->ti_len = m_new->m_len;
808 * Intialize a mini receive ring descriptor. This only applies to
811 static int ti_newbuf_mini(sc, i, m)
816 struct mbuf *m_new = NULL;
817 struct ti_rx_desc *r;
820 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
824 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
827 m_new->m_data = m_new->m_pktdat;
828 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
831 m_adj(m_new, ETHER_ALIGN);
832 r = &sc->ti_rdata->ti_rx_mini_ring[i];
833 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
834 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
835 r->ti_type = TI_BDTYPE_RECV_BD;
836 r->ti_flags = TI_BDFLAG_MINI_RING;
837 if (sc->arpcom.ac_if.if_hwassist)
838 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
839 r->ti_len = m_new->m_len;
846 * Initialize a jumbo receive ring descriptor. This allocates
847 * a jumbo buffer from the pool managed internally by the driver.
849 static int ti_newbuf_jumbo(sc, i, m)
854 struct mbuf *m_new = NULL;
855 struct ti_rx_desc *r;
860 /* Allocate the mbuf. */
861 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
866 /* Allocate the jumbo buffer */
870 printf("ti%d: jumbo allocation failed "
871 "-- packet dropped!\n", sc->ti_unit);
875 /* Attach the buffer to the mbuf. */
876 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
877 m_new->m_flags |= M_EXT;
878 m_new->m_len = m_new->m_pkthdr.len =
879 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
880 m_new->m_ext.ext_free = ti_jfree;
881 m_new->m_ext.ext_ref = ti_jref;
884 m_new->m_data = m_new->m_ext.ext_buf;
885 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
888 m_adj(m_new, ETHER_ALIGN);
889 /* Set up the descriptor. */
890 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
891 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
892 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
893 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
894 r->ti_flags = TI_BDFLAG_JUMBO_RING;
895 if (sc->arpcom.ac_if.if_hwassist)
896 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
897 r->ti_len = m_new->m_len;
904 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
905 * that's 1MB or memory, which is a lot. For now, we fill only the first
906 * 256 ring entries and hope that our CPU is fast enough to keep up with
909 static int ti_init_rx_ring_std(sc)
913 struct ti_cmd_desc cmd;
915 for (i = 0; i < TI_SSLOTS; i++) {
916 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
920 TI_UPDATE_STDPROD(sc, i - 1);
926 static void ti_free_rx_ring_std(sc)
931 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
932 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
933 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
934 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
936 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
937 sizeof(struct ti_rx_desc));
943 static int ti_init_rx_ring_jumbo(sc)
947 struct ti_cmd_desc cmd;
949 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
950 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
954 TI_UPDATE_JUMBOPROD(sc, i - 1);
955 sc->ti_jumbo = i - 1;
960 static void ti_free_rx_ring_jumbo(sc)
965 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
966 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
967 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
968 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
970 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
971 sizeof(struct ti_rx_desc));
977 static int ti_init_rx_ring_mini(sc)
982 for (i = 0; i < TI_MSLOTS; i++) {
983 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
987 TI_UPDATE_MINIPROD(sc, i - 1);
993 static void ti_free_rx_ring_mini(sc)
998 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
999 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1000 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1001 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1003 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
1004 sizeof(struct ti_rx_desc));
1010 static void ti_free_tx_ring(sc)
1011 struct ti_softc *sc;
1015 if (sc->ti_rdata->ti_tx_ring == NULL)
1018 for (i = 0; i < TI_TX_RING_CNT; i++) {
1019 if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
1020 m_freem(sc->ti_cdata.ti_tx_chain[i]);
1021 sc->ti_cdata.ti_tx_chain[i] = NULL;
1023 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
1024 sizeof(struct ti_tx_desc));
1030 static int ti_init_tx_ring(sc)
1031 struct ti_softc *sc;
1034 sc->ti_tx_saved_considx = 0;
1035 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1040 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1041 * but we have to support the old way too so that Tigon 1 cards will
1044 void ti_add_mcast(sc, addr)
1045 struct ti_softc *sc;
1046 struct ether_addr *addr;
1048 struct ti_cmd_desc cmd;
1050 u_int32_t ext[2] = {0, 0};
1052 m = (u_int16_t *)&addr->octet[0];
1054 switch(sc->ti_hwrev) {
1055 case TI_HWREV_TIGON:
1056 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1057 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1058 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1060 case TI_HWREV_TIGON_II:
1061 ext[0] = htons(m[0]);
1062 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1063 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1066 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1073 void ti_del_mcast(sc, addr)
1074 struct ti_softc *sc;
1075 struct ether_addr *addr;
1077 struct ti_cmd_desc cmd;
1079 u_int32_t ext[2] = {0, 0};
1081 m = (u_int16_t *)&addr->octet[0];
1083 switch(sc->ti_hwrev) {
1084 case TI_HWREV_TIGON:
1085 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1086 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1087 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1089 case TI_HWREV_TIGON_II:
1090 ext[0] = htons(m[0]);
1091 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1092 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1095 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1103 * Configure the Tigon's multicast address filter.
1105 * The actual multicast table management is a bit of a pain, thanks to
1106 * slight brain damage on the part of both Alteon and us. With our
1107 * multicast code, we are only alerted when the multicast address table
1108 * changes and at that point we only have the current list of addresses:
1109 * we only know the current state, not the previous state, so we don't
1110 * actually know what addresses were removed or added. The firmware has
1111 * state, but we can't get our grubby mits on it, and there is no 'delete
1112 * all multicast addresses' command. Hence, we have to maintain our own
1113 * state so we know what addresses have been programmed into the NIC at
1116 static void ti_setmulti(sc)
1117 struct ti_softc *sc;
1120 struct ifmultiaddr *ifma;
1121 struct ti_cmd_desc cmd;
1122 struct ti_mc_entry *mc;
1125 ifp = &sc->arpcom.ac_if;
1127 if (ifp->if_flags & IFF_ALLMULTI) {
1128 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1131 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1134 /* Disable interrupts. */
1135 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1136 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1138 /* First, zot all the existing filters. */
1139 while (sc->ti_mc_listhead.slh_first != NULL) {
1140 mc = sc->ti_mc_listhead.slh_first;
1141 ti_del_mcast(sc, &mc->mc_addr);
1142 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1146 /* Now program new ones. */
1147 for (ifma = ifp->if_multiaddrs.lh_first;
1148 ifma != NULL; ifma = ifma->ifma_link.le_next) {
1149 if (ifma->ifma_addr->sa_family != AF_LINK)
1151 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
1152 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1153 (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1154 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1155 ti_add_mcast(sc, &mc->mc_addr);
1158 /* Re-enable interrupts. */
1159 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1165 * Check to see if the BIOS has configured us for a 64 bit slot when
1166 * we aren't actually in one. If we detect this condition, we can work
1167 * around it on the Tigon 2 by setting a bit in the PCI state register,
1168 * but for the Tigon 1 we must give up and abort the interface attach.
1170 static int ti_64bitslot_war(sc)
1171 struct ti_softc *sc;
1173 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1174 CSR_WRITE_4(sc, 0x600, 0);
1175 CSR_WRITE_4(sc, 0x604, 0);
1176 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1177 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1178 if (sc->ti_hwrev == TI_HWREV_TIGON)
1181 TI_SETBIT(sc, TI_PCI_STATE,
1182 TI_PCISTATE_32BIT_BUS);
1192 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1193 * self-test results.
1195 static int ti_chipinit(sc)
1196 struct ti_softc *sc;
1198 u_int32_t cacheline;
1199 u_int32_t pci_writemax = 0;
1201 /* Initialize link to down state. */
1202 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1204 if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM)
1205 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES;
1207 sc->arpcom.ac_if.if_hwassist = 0;
1209 /* Set endianness before we access any non-PCI registers. */
1210 #if BYTE_ORDER == BIG_ENDIAN
1211 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1212 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1214 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1215 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1218 /* Check the ROM failed bit to see if self-tests passed. */
1219 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1220 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit);
1225 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1227 /* Figure out the hardware revision. */
1228 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1229 case TI_REV_TIGON_I:
1230 sc->ti_hwrev = TI_HWREV_TIGON;
1232 case TI_REV_TIGON_II:
1233 sc->ti_hwrev = TI_HWREV_TIGON_II;
1236 printf("ti%d: unsupported chip revision\n", sc->ti_unit);
1240 /* Do special setup for Tigon 2. */
1241 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1242 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1243 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
1244 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1247 /* Set up the PCI state register. */
1248 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1249 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1250 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1253 /* Clear the read/write max DMA parameters. */
1254 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1255 TI_PCISTATE_READ_MAXDMA));
1257 /* Get cache line size. */
1258 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1261 * If the system has set enabled the PCI memory write
1262 * and invalidate command in the command register, set
1263 * the write max parameter accordingly. This is necessary
1264 * to use MWI with the Tigon 2.
1266 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1276 /* Disable PCI memory write and invalidate. */
1278 printf("ti%d: cache line size %d not "
1279 "supported; disabling PCI MWI\n",
1280 sc->ti_unit, cacheline);
1281 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1282 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
1287 #ifdef __brokenalpha__
1289 * From the Alteon sample driver:
1290 * Must insure that we do not cross an 8K (bytes) boundary
1291 * for DMA reads. Our highest limit is 1K bytes. This is a
1292 * restriction on some ALPHA platforms with early revision
1293 * 21174 PCI chipsets, such as the AlphaPC 164lx
1295 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024);
1297 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1300 /* This sets the min dma param all the way up (0xff). */
1301 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1303 /* Configure DMA variables. */
1304 #if BYTE_ORDER == BIG_ENDIAN
1305 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1306 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1307 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1308 TI_OPMODE_DONT_FRAG_JUMBO);
1310 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
1311 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
1312 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB);
1316 * Only allow 1 DMA channel to be active at a time.
1317 * I don't think this is a good idea, but without it
1318 * the firmware racks up lots of nicDmaReadRingFull
1319 * errors. This is not compatible with hardware checksums.
1321 if (sc->arpcom.ac_if.if_hwassist == 0)
1322 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1324 /* Recommended settings from Tigon manual. */
1325 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1326 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1328 if (ti_64bitslot_war(sc)) {
1329 printf("ti%d: bios thinks we're in a 64 bit slot, "
1330 "but we aren't", sc->ti_unit);
1338 * Initialize the general information block and firmware, and
1339 * start the CPU(s) running.
1341 static int ti_gibinit(sc)
1342 struct ti_softc *sc;
1348 ifp = &sc->arpcom.ac_if;
1350 /* Disable interrupts for now. */
1351 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1353 /* Tell the chip where to find the general information block. */
1354 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
1355 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info));
1357 /* Load the firmware into SRAM. */
1360 /* Set up the contents of the general info and ring control blocks. */
1362 /* Set up the event ring and producer pointer. */
1363 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
1365 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring);
1367 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
1368 vtophys(&sc->ti_ev_prodidx);
1369 sc->ti_ev_prodidx.ti_idx = 0;
1370 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
1371 sc->ti_ev_saved_considx = 0;
1373 /* Set up the command ring and producer mailbox. */
1374 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
1376 sc->ti_rdata->ti_cmd_ring =
1377 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING);
1378 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
1380 rcb->ti_max_len = 0;
1381 for (i = 0; i < TI_CMD_RING_CNT; i++) {
1382 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
1384 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
1385 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
1386 sc->ti_cmd_saved_prodidx = 0;
1389 * Assign the address of the stats refresh buffer.
1390 * We re-use the current stats buffer for this to
1393 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
1394 vtophys(&sc->ti_rdata->ti_info.ti_stats);
1396 /* Set up the standard receive ring. */
1397 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
1398 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring);
1399 rcb->ti_max_len = TI_FRAMELEN;
1401 if (sc->arpcom.ac_if.if_hwassist)
1402 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1403 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1404 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1406 /* Set up the jumbo receive ring. */
1407 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
1408 TI_HOSTADDR(rcb->ti_hostaddr) =
1409 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring);
1410 rcb->ti_max_len = TI_JUMBO_FRAMELEN;
1412 if (sc->arpcom.ac_if.if_hwassist)
1413 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1414 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1415 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1418 * Set up the mini ring. Only activated on the
1419 * Tigon 2 but the slot in the config block is
1420 * still there on the Tigon 1.
1422 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
1423 TI_HOSTADDR(rcb->ti_hostaddr) =
1424 vtophys(&sc->ti_rdata->ti_rx_mini_ring);
1425 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
1426 if (sc->ti_hwrev == TI_HWREV_TIGON)
1427 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
1430 if (sc->arpcom.ac_if.if_hwassist)
1431 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1432 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1433 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1436 * Set up the receive return ring.
1438 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
1439 TI_HOSTADDR(rcb->ti_hostaddr) =
1440 vtophys(&sc->ti_rdata->ti_rx_return_ring);
1442 rcb->ti_max_len = TI_RETURN_RING_CNT;
1443 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
1444 vtophys(&sc->ti_return_prodidx);
1447 * Set up the tx ring. Note: for the Tigon 2, we have the option
1448 * of putting the transmit ring in the host's address space and
1449 * letting the chip DMA it instead of leaving the ring in the NIC's
1450 * memory and accessing it through the shared memory region. We
1451 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
1452 * so we have to revert to the shared memory scheme if we detect
1455 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
1456 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1457 sc->ti_rdata->ti_tx_ring_nic =
1458 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW);
1460 bzero((char *)sc->ti_rdata->ti_tx_ring,
1461 TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
1462 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
1463 if (sc->ti_hwrev == TI_HWREV_TIGON)
1466 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
1467 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1468 if (sc->arpcom.ac_if.if_hwassist)
1469 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1470 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1471 rcb->ti_max_len = TI_TX_RING_CNT;
1472 if (sc->ti_hwrev == TI_HWREV_TIGON)
1473 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
1475 TI_HOSTADDR(rcb->ti_hostaddr) =
1476 vtophys(&sc->ti_rdata->ti_tx_ring);
1477 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
1478 vtophys(&sc->ti_tx_considx);
1480 /* Set up tuneables */
1481 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
1482 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
1483 (sc->ti_rx_coal_ticks / 10));
1485 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
1486 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
1487 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
1488 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
1489 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
1490 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
1492 /* Turn interrupts on. */
1493 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
1494 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1497 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
1503 * Probe for a Tigon chip. Check the PCI vendor and device IDs
1504 * against our list and return its name if we find a match.
1506 static int ti_probe(dev)
1513 while(t->ti_name != NULL) {
1514 if ((pci_get_vendor(dev) == t->ti_vid) &&
1515 (pci_get_device(dev) == t->ti_did)) {
1516 device_set_desc(dev, t->ti_name);
1525 static int ti_attach(dev)
1531 struct ti_softc *sc;
1532 int unit, error = 0, rid;
1536 sc = device_get_softc(dev);
1537 unit = device_get_unit(dev);
1538 bzero(sc, sizeof(struct ti_softc));
1539 sc->arpcom.ac_if.if_capabilities = IFCAP_HWCSUM;
1540 sc->arpcom.ac_if.if_capenable = sc->arpcom.ac_if.if_capabilities;
1543 * Map control/status registers.
1545 command = pci_read_config(dev, PCIR_COMMAND, 4);
1546 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1547 pci_write_config(dev, PCIR_COMMAND, command, 4);
1548 command = pci_read_config(dev, PCIR_COMMAND, 4);
1550 if (!(command & PCIM_CMD_MEMEN)) {
1551 printf("ti%d: failed to enable memory mapping!\n", unit);
1557 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1558 0, ~0, 1, RF_ACTIVE);
1560 if (sc->ti_res == NULL) {
1561 printf ("ti%d: couldn't map memory\n", unit);
1566 sc->ti_btag = rman_get_bustag(sc->ti_res);
1567 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
1568 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res);
1571 * XXX FIXME: rman_get_virtual() on the alpha is currently
1572 * broken and returns a physical address instead of a kernel
1573 * virtual address. Consequently, we need to do a little
1574 * extra mangling of the vhandle on the alpha. This should
1575 * eventually be fixed! The whole idea here is to get rid
1576 * of platform dependencies.
1579 if (pci_cvt_to_bwx(sc->ti_vhandle))
1580 sc->ti_vhandle = pci_cvt_to_bwx(sc->ti_vhandle);
1582 sc->ti_vhandle = pci_cvt_to_dense(sc->ti_vhandle);
1583 sc->ti_vhandle = ALPHA_PHYS_TO_K0SEG(sc->ti_vhandle);
1586 /* Allocate interrupt */
1589 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1590 RF_SHAREABLE | RF_ACTIVE);
1592 if (sc->ti_irq == NULL) {
1593 printf("ti%d: couldn't map interrupt\n", unit);
1598 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET,
1599 ti_intr, sc, &sc->ti_intrhand);
1602 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1603 bus_release_resource(dev, SYS_RES_MEMORY,
1604 TI_PCI_LOMEM, sc->ti_res);
1605 printf("ti%d: couldn't set up irq\n", unit);
1611 if (ti_chipinit(sc)) {
1612 printf("ti%d: chip initialization failed\n", sc->ti_unit);
1613 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1614 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1615 bus_release_resource(dev, SYS_RES_MEMORY,
1616 TI_PCI_LOMEM, sc->ti_res);
1621 /* Zero out the NIC's on-board SRAM. */
1622 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
1624 /* Init again -- zeroing memory may have clobbered some registers. */
1625 if (ti_chipinit(sc)) {
1626 printf("ti%d: chip initialization failed\n", sc->ti_unit);
1627 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1628 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1629 bus_release_resource(dev, SYS_RES_MEMORY,
1630 TI_PCI_LOMEM, sc->ti_res);
1636 * Get station address from the EEPROM. Note: the manual states
1637 * that the MAC address is at offset 0x8c, however the data is
1638 * stored as two longwords (since that's how it's loaded into
1639 * the NIC). This means the MAC address is actually preceeded
1640 * by two zero bytes. We need to skip over those.
1642 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1643 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1644 printf("ti%d: failed to read station address\n", unit);
1645 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1646 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1647 bus_release_resource(dev, SYS_RES_MEMORY,
1648 TI_PCI_LOMEM, sc->ti_res);
1654 * A Tigon chip was detected. Inform the world.
1656 printf("ti%d: Ethernet address: %6D\n", unit,
1657 sc->arpcom.ac_enaddr, ":");
1659 /* Allocate the general information block and ring buffers. */
1660 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF,
1661 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1663 if (sc->ti_rdata == NULL) {
1664 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1665 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1666 bus_release_resource(dev, SYS_RES_MEMORY,
1667 TI_PCI_LOMEM, sc->ti_res);
1669 printf("ti%d: no memory for list buffers!\n", sc->ti_unit);
1673 bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
1675 /* Try to allocate memory for jumbo buffers. */
1676 if (ti_alloc_jumbo_mem(sc)) {
1677 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit);
1678 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1679 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1680 bus_release_resource(dev, SYS_RES_MEMORY,
1681 TI_PCI_LOMEM, sc->ti_res);
1682 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data),
1689 * We really need a better way to tell a 1000baseTX card
1690 * from a 1000baseSX one, since in theory there could be
1691 * OEMed 1000baseTX cards from lame vendors who aren't
1692 * clever enough to change the PCI ID. For the moment
1693 * though, the AceNIC is the only copper card available.
1695 if (pci_get_vendor(dev) == ALT_VENDORID &&
1696 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
1698 /* Ok, it's not the only copper card available. */
1699 if (pci_get_vendor(dev) == NG_VENDORID &&
1700 pci_get_device(dev) == NG_DEVICEID_GA620T)
1703 /* Set default tuneable values. */
1704 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
1705 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
1706 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
1707 sc->ti_rx_max_coal_bds = 64;
1708 sc->ti_tx_max_coal_bds = 128;
1709 sc->ti_tx_buf_ratio = 21;
1711 /* Set up ifnet structure */
1712 ifp = &sc->arpcom.ac_if;
1714 ifp->if_unit = sc->ti_unit;
1715 ifp->if_name = "ti";
1716 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1717 ifp->if_ioctl = ti_ioctl;
1718 ifp->if_output = ether_output;
1719 ifp->if_start = ti_start;
1720 ifp->if_watchdog = ti_watchdog;
1721 ifp->if_init = ti_init;
1722 ifp->if_mtu = ETHERMTU;
1723 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1;
1725 /* Set up ifmedia support. */
1726 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
1727 if (sc->ti_copper) {
1729 * Copper cards allow manual 10/100 mode selection,
1730 * but not manual 1000baseTX mode selection. Why?
1731 * Becuase currently there's no way to specify the
1732 * master/slave setting through the firmware interface,
1733 * so Alteon decided to just bag it and handle it
1734 * via autonegotiation.
1736 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1737 ifmedia_add(&sc->ifmedia,
1738 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1739 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
1740 ifmedia_add(&sc->ifmedia,
1741 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
1742 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_TX, 0, NULL);
1743 ifmedia_add(&sc->ifmedia,
1744 IFM_ETHER|IFM_1000_TX|IFM_FDX, 0, NULL);
1746 /* Fiber cards don't support 10/100 modes. */
1747 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1748 ifmedia_add(&sc->ifmedia,
1749 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1751 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1752 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
1755 * Call MI attach routine.
1757 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1765 static int ti_detach(dev)
1768 struct ti_softc *sc;
1774 sc = device_get_softc(dev);
1775 ifp = &sc->arpcom.ac_if;
1777 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1780 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1781 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1782 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res);
1784 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF);
1785 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF);
1786 ifmedia_removeall(&sc->ifmedia);
1794 * Frame reception handling. This is called if there's a frame
1795 * on the receive return list.
1797 * Note: we have to be able to handle three possibilities here:
1798 * 1) the frame is from the mini receive ring (can only happen)
1799 * on Tigon 2 boards)
1800 * 2) the frame is from the jumbo recieve ring
1801 * 3) the frame is from the standard receive ring
1804 static void ti_rxeof(sc)
1805 struct ti_softc *sc;
1808 struct ti_cmd_desc cmd;
1810 ifp = &sc->arpcom.ac_if;
1812 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
1813 struct ti_rx_desc *cur_rx;
1815 struct ether_header *eh;
1816 struct mbuf *m = NULL;
1817 u_int16_t vlan_tag = 0;
1821 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
1822 rxidx = cur_rx->ti_idx;
1823 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
1825 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
1827 vlan_tag = cur_rx->ti_vlan_tag & 0xfff;
1830 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
1831 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
1832 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
1833 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
1834 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1836 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1839 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
1841 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1844 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
1845 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
1846 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
1847 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
1848 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1850 ti_newbuf_mini(sc, sc->ti_mini, m);
1853 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
1855 ti_newbuf_mini(sc, sc->ti_mini, m);
1859 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
1860 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
1861 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
1862 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1864 ti_newbuf_std(sc, sc->ti_std, m);
1867 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
1869 ti_newbuf_std(sc, sc->ti_std, m);
1874 m->m_pkthdr.len = m->m_len = cur_rx->ti_len;
1876 eh = mtod(m, struct ether_header *);
1877 m->m_pkthdr.rcvif = ifp;
1879 /* Remove header from mbuf and pass it on. */
1880 m_adj(m, sizeof(struct ether_header));
1882 if (ifp->if_hwassist) {
1883 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1885 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
1886 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1887 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum;
1891 * If we received a packet with a vlan tag, pass it
1892 * to vlan_input() instead of ether_input().
1895 VLAN_INPUT_TAG(eh, m, vlan_tag);
1896 have_tag = vlan_tag = 0;
1899 ether_input(ifp, eh, m);
1902 /* Only necessary on the Tigon 1. */
1903 if (sc->ti_hwrev == TI_HWREV_TIGON)
1904 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
1905 sc->ti_rx_saved_considx);
1907 TI_UPDATE_STDPROD(sc, sc->ti_std);
1908 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
1909 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
1914 static void ti_txeof(sc)
1915 struct ti_softc *sc;
1917 struct ti_tx_desc *cur_tx = NULL;
1920 ifp = &sc->arpcom.ac_if;
1923 * Go through our tx ring and free mbufs for those
1924 * frames that have been sent.
1926 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
1929 idx = sc->ti_tx_saved_considx;
1930 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1932 CSR_WRITE_4(sc, TI_WINBASE,
1933 TI_TX_RING_BASE + 6144);
1935 CSR_WRITE_4(sc, TI_WINBASE,
1936 TI_TX_RING_BASE + 4096);
1938 CSR_WRITE_4(sc, TI_WINBASE,
1939 TI_TX_RING_BASE + 2048);
1941 CSR_WRITE_4(sc, TI_WINBASE,
1943 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128];
1945 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
1946 if (cur_tx->ti_flags & TI_BDFLAG_END)
1948 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
1949 m_freem(sc->ti_cdata.ti_tx_chain[idx]);
1950 sc->ti_cdata.ti_tx_chain[idx] = NULL;
1953 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
1958 ifp->if_flags &= ~IFF_OACTIVE;
1963 static void ti_intr(xsc)
1966 struct ti_softc *sc;
1970 ifp = &sc->arpcom.ac_if;
1973 /* Avoid this for now -- checking this register is expensive. */
1974 /* Make sure this is really our interrupt. */
1975 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE))
1979 /* Ack interrupt and stop others from occuring. */
1980 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1982 if (ifp->if_flags & IFF_RUNNING) {
1983 /* Check RX return ring producer/consumer */
1986 /* Check TX ring producer/consumer */
1990 ti_handle_events(sc);
1992 /* Re-enable interrupts. */
1993 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1995 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
2001 static void ti_stats_update(sc)
2002 struct ti_softc *sc;
2006 ifp = &sc->arpcom.ac_if;
2008 ifp->if_collisions +=
2009 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
2010 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
2011 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
2012 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
2019 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2020 * pointers to descriptors.
2022 static int ti_encap(sc, m_head, txidx)
2023 struct ti_softc *sc;
2024 struct mbuf *m_head;
2027 struct ti_tx_desc *f = NULL;
2029 u_int32_t frag, cur, cnt = 0;
2030 u_int16_t csum_flags = 0;
2031 struct ifvlan *ifv = NULL;
2033 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2034 m_head->m_pkthdr.rcvif != NULL &&
2035 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2036 ifv = m_head->m_pkthdr.rcvif->if_softc;
2039 cur = frag = *txidx;
2041 if (m_head->m_pkthdr.csum_flags) {
2042 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2043 csum_flags |= TI_BDFLAG_IP_CKSUM;
2044 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2045 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
2046 if (m_head->m_flags & M_LASTFRAG)
2047 csum_flags |= TI_BDFLAG_IP_FRAG_END;
2048 else if (m_head->m_flags & M_FRAG)
2049 csum_flags |= TI_BDFLAG_IP_FRAG;
2052 * Start packing the mbufs in this chain into
2053 * the fragment pointers. Stop when we run out
2054 * of fragments or hit the end of the mbuf chain.
2056 for (m = m_head; m != NULL; m = m->m_next) {
2057 if (m->m_len != 0) {
2058 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2060 CSR_WRITE_4(sc, TI_WINBASE,
2061 TI_TX_RING_BASE + 6144);
2062 else if (frag > 255)
2063 CSR_WRITE_4(sc, TI_WINBASE,
2064 TI_TX_RING_BASE + 4096);
2065 else if (frag > 127)
2066 CSR_WRITE_4(sc, TI_WINBASE,
2067 TI_TX_RING_BASE + 2048);
2069 CSR_WRITE_4(sc, TI_WINBASE,
2071 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128];
2073 f = &sc->ti_rdata->ti_tx_ring[frag];
2074 if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
2076 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t));
2077 f->ti_len = m->m_len;
2078 f->ti_flags = csum_flags;
2081 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
2082 f->ti_vlan_tag = ifv->ifv_tag & 0xfff;
2088 * Sanity check: avoid coming within 16 descriptors
2089 * of the end of the ring.
2091 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
2094 TI_INC(frag, TI_TX_RING_CNT);
2102 if (frag == sc->ti_tx_saved_considx)
2105 if (sc->ti_hwrev == TI_HWREV_TIGON)
2106 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |=
2109 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
2110 sc->ti_cdata.ti_tx_chain[cur] = m_head;
2111 sc->ti_txcnt += cnt;
2119 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2120 * to the mbuf data regions directly in the transmit descriptors.
2122 static void ti_start(ifp)
2125 struct ti_softc *sc;
2126 struct mbuf *m_head = NULL;
2127 u_int32_t prodidx = 0;
2131 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);
2133 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
2134 IF_DEQUEUE(&ifp->if_snd, m_head);
2140 * safety overkill. If this is a fragmented packet chain
2141 * with delayed TCP/UDP checksums, then only encapsulate
2142 * it if we have enough descriptors to handle the entire
2144 * (paranoia -- may not actually be needed)
2146 if (m_head->m_flags & M_FIRSTFRAG &&
2147 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2148 if ((TI_TX_RING_CNT - sc->ti_txcnt) <
2149 m_head->m_pkthdr.csum_data + 16) {
2150 IF_PREPEND(&ifp->if_snd, m_head);
2151 ifp->if_flags |= IFF_OACTIVE;
2157 * Pack the data into the transmit ring. If we
2158 * don't have room, set the OACTIVE flag and wait
2159 * for the NIC to drain the ring.
2161 if (ti_encap(sc, m_head, &prodidx)) {
2162 IF_PREPEND(&ifp->if_snd, m_head);
2163 ifp->if_flags |= IFF_OACTIVE;
2168 * If there's a BPF listener, bounce a copy of this frame
2172 bpf_mtap(ifp, m_head);
2176 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
2179 * Set a timeout in case the chip goes out to lunch.
2186 static void ti_init(xsc)
2189 struct ti_softc *sc = xsc;
2194 /* Cancel pending I/O and flush buffers. */
2197 /* Init the gen info block, ring control blocks and firmware. */
2198 if (ti_gibinit(sc)) {
2199 printf("ti%d: initialization failure\n", sc->ti_unit);
2209 static void ti_init2(sc)
2210 struct ti_softc *sc;
2212 struct ti_cmd_desc cmd;
2215 struct ifmedia *ifm;
2218 ifp = &sc->arpcom.ac_if;
2220 /* Specify MTU and interface index. */
2221 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit);
2222 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
2223 ETHER_HDR_LEN + ETHER_CRC_LEN);
2224 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
2226 /* Load our MAC address. */
2227 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
2228 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0]));
2229 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2]));
2230 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
2232 /* Enable or disable promiscuous mode as needed. */
2233 if (ifp->if_flags & IFF_PROMISC) {
2234 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
2236 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
2239 /* Program multicast filter. */
2243 * If this is a Tigon 1, we should tell the
2244 * firmware to use software packet filtering.
2246 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2247 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
2251 ti_init_rx_ring_std(sc);
2253 /* Init jumbo RX ring. */
2254 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2255 ti_init_rx_ring_jumbo(sc);
2258 * If this is a Tigon 2, we can also configure the
2261 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
2262 ti_init_rx_ring_mini(sc);
2264 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
2265 sc->ti_rx_saved_considx = 0;
2268 ti_init_tx_ring(sc);
2270 /* Tell firmware we're alive. */
2271 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
2273 /* Enable host interrupts. */
2274 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2276 ifp->if_flags |= IFF_RUNNING;
2277 ifp->if_flags &= ~IFF_OACTIVE;
2280 * Make sure to set media properly. We have to do this
2281 * here since we have to issue commands in order to set
2282 * the link negotiation and we can't issue commands until
2283 * the firmware is running.
2286 tmp = ifm->ifm_media;
2287 ifm->ifm_media = ifm->ifm_cur->ifm_media;
2288 ti_ifmedia_upd(ifp);
2289 ifm->ifm_media = tmp;
2295 * Set media options.
2297 static int ti_ifmedia_upd(ifp)
2300 struct ti_softc *sc;
2301 struct ifmedia *ifm;
2302 struct ti_cmd_desc cmd;
2307 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2310 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2312 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2313 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|
2314 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
2315 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
2316 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX|
2317 TI_LNK_AUTONEGENB|TI_LNK_ENB);
2318 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2319 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
2323 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2324 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB);
2325 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
2326 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2327 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
2329 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2330 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
2336 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
2337 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF);
2338 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
2339 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
2340 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
2342 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
2344 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2345 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
2347 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
2349 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2350 TI_CMD_CODE_NEGOTIATE_10_100, 0);
2358 * Report current media status.
2360 static void ti_ifmedia_sts(ifp, ifmr)
2362 struct ifmediareq *ifmr;
2364 struct ti_softc *sc;
2365 u_int32_t media = 0;
2369 ifmr->ifm_status = IFM_AVALID;
2370 ifmr->ifm_active = IFM_ETHER;
2372 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
2375 ifmr->ifm_status |= IFM_ACTIVE;
2377 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
2378 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
2380 ifmr->ifm_active |= IFM_1000_TX;
2382 ifmr->ifm_active |= IFM_1000_SX;
2383 if (media & TI_GLNK_FULL_DUPLEX)
2384 ifmr->ifm_active |= IFM_FDX;
2386 ifmr->ifm_active |= IFM_HDX;
2387 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
2388 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
2389 if (sc->ti_copper) {
2390 if (media & TI_LNK_100MB)
2391 ifmr->ifm_active |= IFM_100_TX;
2392 if (media & TI_LNK_10MB)
2393 ifmr->ifm_active |= IFM_10_T;
2395 if (media & TI_LNK_100MB)
2396 ifmr->ifm_active |= IFM_100_FX;
2397 if (media & TI_LNK_10MB)
2398 ifmr->ifm_active |= IFM_10_FL;
2400 if (media & TI_LNK_FULL_DUPLEX)
2401 ifmr->ifm_active |= IFM_FDX;
2402 if (media & TI_LNK_HALF_DUPLEX)
2403 ifmr->ifm_active |= IFM_HDX;
2409 static int ti_ioctl(ifp, command, data)
2414 struct ti_softc *sc = ifp->if_softc;
2415 struct ifreq *ifr = (struct ifreq *) data;
2416 int s, mask, error = 0;
2417 struct ti_cmd_desc cmd;
2424 error = ether_ioctl(ifp, command, data);
2427 if (ifr->ifr_mtu > TI_JUMBO_MTU)
2430 ifp->if_mtu = ifr->ifr_mtu;
2435 if (ifp->if_flags & IFF_UP) {
2437 * If only the state of the PROMISC flag changed,
2438 * then just use the 'set promisc mode' command
2439 * instead of reinitializing the entire NIC. Doing
2440 * a full re-init means reloading the firmware and
2441 * waiting for it to start up, which may take a
2444 if (ifp->if_flags & IFF_RUNNING &&
2445 ifp->if_flags & IFF_PROMISC &&
2446 !(sc->ti_if_flags & IFF_PROMISC)) {
2447 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2448 TI_CMD_CODE_PROMISC_ENB, 0);
2449 } else if (ifp->if_flags & IFF_RUNNING &&
2450 !(ifp->if_flags & IFF_PROMISC) &&
2451 sc->ti_if_flags & IFF_PROMISC) {
2452 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2453 TI_CMD_CODE_PROMISC_DIS, 0);
2457 if (ifp->if_flags & IFF_RUNNING) {
2461 sc->ti_if_flags = ifp->if_flags;
2466 if (ifp->if_flags & IFF_RUNNING) {
2473 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2476 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2477 if (mask & IFCAP_HWCSUM) {
2478 if (IFCAP_HWCSUM & ifp->if_capenable)
2479 ifp->if_capenable &= ~IFCAP_HWCSUM;
2481 ifp->if_capenable |= IFCAP_HWCSUM;
2482 if (ifp->if_flags & IFF_RUNNING)
2497 static void ti_watchdog(ifp)
2500 struct ti_softc *sc;
2504 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit);
2514 * Stop the adapter and free any mbufs allocated to the
2517 static void ti_stop(sc)
2518 struct ti_softc *sc;
2521 struct ti_cmd_desc cmd;
2523 ifp = &sc->arpcom.ac_if;
2525 /* Disable host interrupts. */
2526 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2528 * Tell firmware we're shutting down.
2530 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
2532 /* Halt and reinitialize. */
2534 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
2537 /* Free the RX lists. */
2538 ti_free_rx_ring_std(sc);
2540 /* Free jumbo RX list. */
2541 ti_free_rx_ring_jumbo(sc);
2543 /* Free mini RX list. */
2544 ti_free_rx_ring_mini(sc);
2546 /* Free TX buffers. */
2547 ti_free_tx_ring(sc);
2549 sc->ti_ev_prodidx.ti_idx = 0;
2550 sc->ti_return_prodidx.ti_idx = 0;
2551 sc->ti_tx_considx.ti_idx = 0;
2552 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
2554 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2560 * Stop all chip I/O so that the kernel's probe routines don't
2561 * get confused by errant DMAs when rebooting.
2563 static void ti_shutdown(dev)
2566 struct ti_softc *sc;
2568 sc = device_get_softc(dev);