2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $
33 * $DragonFly: src/sys/dev/netif/rl/if_rl.c,v 1.17 2005/02/12 04:00:13 joerg Exp $
35 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $
39 * RealTek 8129/8139 PCI NIC driver
41 * Supports several extremely cheap PCI 10/100 adapters based on
42 * the RealTek chipset. Datasheets can be obtained from
45 * Written by Bill Paul <wpaul@ctr.columbia.edu>
46 * Electrical Engineering Department
47 * Columbia University, New York City
51 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
52 * probably the worst PCI ethernet controller ever made, with the possible
53 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
54 * DMA, but it has a terrible interface that nullifies any performance
55 * gains that bus-master DMA usually offers.
57 * For transmission, the chip offers a series of four TX descriptor
58 * registers. Each transmit frame must be in a contiguous buffer, aligned
59 * on a longword (32-bit) boundary. This means we almost always have to
60 * do mbuf copies in order to transmit a frame, except in the unlikely
61 * case where a) the packet fits into a single mbuf, and b) the packet
62 * is 32-bit aligned within the mbuf's data area. The presence of only
63 * four descriptor registers means that we can never have more than four
64 * packets queued for transmission at any one time.
66 * Reception is not much better. The driver has to allocate a single large
67 * buffer area (up to 64K in size) into which the chip will DMA received
68 * frames. Because we don't know where within this region received packets
69 * will begin or end, we have no choice but to copy data from the buffer
70 * area into mbufs in order to pass the packets up to the higher protocol
73 * It's impossible given this rotten design to really achieve decent
74 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
75 * some equally overmuscled CPU to drive it.
77 * On the bright side, the 8139 does have a built-in PHY, although
78 * rather than using an MDIO serial interface like most other NICs, the
79 * PHY registers are directly accessible through the 8139's register
80 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
83 * The 8129 chip is an older version of the 8139 that uses an external PHY
84 * chip. The 8129 has a serial MDIO interface for accessing the MII where
85 * the 8139 lets you directly access the on-board PHY registers. We need
86 * to select which interface to use depending on the chip type.
89 #include <sys/param.h>
90 #include <sys/endian.h>
91 #include <sys/systm.h>
92 #include <sys/sockio.h>
94 #include <sys/malloc.h>
95 #include <sys/kernel.h>
96 #include <sys/module.h>
97 #include <sys/socket.h>
100 #include <net/ifq_var.h>
101 #include <net/if_arp.h>
102 #include <net/ethernet.h>
103 #include <net/if_dl.h>
104 #include <net/if_media.h>
108 #include <machine/bus_pio.h>
109 #include <machine/bus_memio.h>
110 #include <machine/bus.h>
111 #include <machine/resource.h>
113 #include <sys/rman.h>
115 #include <dev/netif/mii_layer/mii.h>
116 #include <dev/netif/mii_layer/miivar.h>
118 #include <bus/pci/pcireg.h>
119 #include <bus/pci/pcivar.h>
121 /* "controller miibus0" required. See GENERIC if you get errors here. */
122 #include "miibus_if.h"
125 * Default to using PIO access for this driver. On SMP systems,
126 * there appear to be problems with memory mapped mode: it looks like
127 * doing too many memory mapped access back to back in rapid succession
128 * can hang the bus. I'm inclined to blame this on crummy design/construction
129 * on the part of RealTek. Memory mapped mode does appear to work on
130 * uniprocessor systems though.
132 #define RL_USEIOSPACE
134 #include <dev/netif/rl/if_rlreg.h>
137 * Various supported device vendors/types and their names.
139 static struct rl_type {
144 { RT_VENDORID, RT_DEVICEID_8129,
145 "RealTek 8129 10/100BaseTX" },
146 { RT_VENDORID, RT_DEVICEID_8139,
147 "RealTek 8139 10/100BaseTX" },
148 { RT_VENDORID, RT_DEVICEID_8138,
149 "RealTek 8139 10/100BaseTX CardBus" },
150 { ACCTON_VENDORID, ACCTON_DEVICEID_5030,
151 "Accton MPX 5030/5038 10/100BaseTX" },
152 { DELTA_VENDORID, DELTA_DEVICEID_8139,
153 "Delta Electronics 8139 10/100BaseTX" },
154 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139,
155 "Addtron Technolgy 8139 10/100BaseTX" },
156 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS,
157 "D-Link DFE-530TX+ 10/100BaseTX" },
158 { DLINK_VENDORID, DLINK_DEVICEID_690TXD,
159 "D-Link DFE-690TX 10/100BaseTX" },
160 { NORTEL_VENDORID, ACCTON_DEVICEID_5030,
161 "Nortel Networks 10/100BaseTX" },
162 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF,
163 "Peppercon AG ROL/F" },
164 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD,
165 "Corega FEther CB-TXD" },
166 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD,
167 "Corega FEtherII CB-TXD" },
168 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX,
169 "Planex FNW-3800-TX" },
173 static int rl_probe(device_t);
174 static int rl_attach(device_t);
175 static int rl_detach(device_t);
177 static int rl_encap(struct rl_softc *, struct mbuf * );
179 static void rl_rxeof(struct rl_softc *);
180 static void rl_txeof(struct rl_softc *);
181 static void rl_intr(void *);
182 static void rl_tick(void *);
183 static void rl_start(struct ifnet *);
184 static int rl_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
185 static void rl_init(void *);
186 static void rl_stop (struct rl_softc *);
187 static void rl_watchdog(struct ifnet *);
188 static int rl_suspend(device_t);
189 static int rl_resume(device_t);
190 static void rl_shutdown(device_t);
191 static int rl_ifmedia_upd(struct ifnet *);
192 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
194 static void rl_eeprom_putbyte(struct rl_softc *, int);
195 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
196 static void rl_read_eeprom(struct rl_softc *, caddr_t, int, int, int);
197 static void rl_mii_sync(struct rl_softc *);
198 static void rl_mii_send(struct rl_softc *, uint32_t, int);
199 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
200 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
202 static int rl_miibus_readreg(device_t, int, int);
203 static int rl_miibus_writereg(device_t, int, int, int);
204 static void rl_miibus_statchg(device_t);
206 static void rl_setmulti(struct rl_softc *);
207 static void rl_reset(struct rl_softc *);
208 static void rl_list_tx_init(struct rl_softc *);
210 static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int);
211 static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int);
214 #define RL_RES SYS_RES_IOPORT
215 #define RL_RID RL_PCI_LOIO
217 #define RL_RES SYS_RES_MEMORY
218 #define RL_RID RL_PCI_LOMEM
221 static device_method_t rl_methods[] = {
222 /* Device interface */
223 DEVMETHOD(device_probe, rl_probe),
224 DEVMETHOD(device_attach, rl_attach),
225 DEVMETHOD(device_detach, rl_detach),
226 DEVMETHOD(device_suspend, rl_suspend),
227 DEVMETHOD(device_resume, rl_resume),
228 DEVMETHOD(device_shutdown, rl_shutdown),
231 DEVMETHOD(bus_print_child, bus_generic_print_child),
232 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
235 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
236 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
237 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
242 static DEFINE_CLASS_0(rl, rl_driver, rl_methods, sizeof(struct rl_softc));
243 static devclass_t rl_devclass;
245 DECLARE_DUMMY_MODULE(if_rl);
246 DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0);
247 DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0);
248 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
249 MODULE_DEPEND(if_rl, miibus, 1, 1, 1);
252 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) | (x))
255 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) & ~(x))
258 rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
260 struct rl_softc *sc = arg;
262 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF);
266 rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
268 struct rl_softc *sc = arg;
270 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF);
274 * Send a read command and address to the EEPROM, check for ACK.
277 rl_eeprom_putbyte(struct rl_softc *sc, int addr)
281 d = addr | sc->rl_eecmd_read;
284 * Feed in each bit and strobe the clock.
286 for (i = 0x400; i; i >>= 1) {
288 EE_SET(RL_EE_DATAIN);
290 EE_CLR(RL_EE_DATAIN);
300 * Read a word of data stored in the EEPROM at address 'addr.'
303 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
308 /* Enter EEPROM access mode. */
309 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
312 * Send address of word we want to read.
314 rl_eeprom_putbyte(sc, addr);
316 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
319 * Start reading bits from EEPROM.
321 for (i = 0x8000; i; i >>= 1) {
324 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
330 /* Turn off EEPROM access mode. */
331 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
337 * Read a sequence of words from the EEPROM.
340 rl_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt, int swap)
343 u_int16_t word = 0, *ptr;
345 for (i = 0; i < cnt; i++) {
346 rl_eeprom_getword(sc, off + i, &word);
347 ptr = (u_int16_t *)(dest + (i * 2));
357 * MII access routines are provided for the 8129, which
358 * doesn't have a built-in PHY. For the 8139, we fake things
359 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
360 * direct access PHY registers.
363 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) | x)
366 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) & ~x)
369 * Sync the PHYs by setting data bit and strobing the clock 32 times.
372 rl_mii_sync(struct rl_softc *sc)
376 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
378 for (i = 0; i < 32; i++) {
387 * Clock a series of bits through the MII.
390 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
396 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
398 MII_SET(RL_MII_DATAOUT);
400 MII_CLR(RL_MII_DATAOUT);
409 * Read an PHY register through the MII.
412 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
419 * Set up frame for RX.
421 frame->mii_stdelim = RL_MII_STARTDELIM;
422 frame->mii_opcode = RL_MII_READOP;
423 frame->mii_turnaround = 0;
426 CSR_WRITE_2(sc, RL_MII, 0);
436 * Send command/address info.
438 rl_mii_send(sc, frame->mii_stdelim, 2);
439 rl_mii_send(sc, frame->mii_opcode, 2);
440 rl_mii_send(sc, frame->mii_phyaddr, 5);
441 rl_mii_send(sc, frame->mii_regaddr, 5);
444 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
455 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
460 * Now try reading data bits. If the ack failed, we still
461 * need to clock through 16 cycles to keep the PHY(s) in sync.
464 for(i = 0; i < 16; i++) {
471 for (i = 0x8000; i; i >>= 1) {
475 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
476 frame->mii_data |= i;
495 * Write to a PHY register through the MII.
498 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
504 * Set up frame for TX.
507 frame->mii_stdelim = RL_MII_STARTDELIM;
508 frame->mii_opcode = RL_MII_WRITEOP;
509 frame->mii_turnaround = RL_MII_TURNAROUND;
512 * Turn on data output.
518 rl_mii_send(sc, frame->mii_stdelim, 2);
519 rl_mii_send(sc, frame->mii_opcode, 2);
520 rl_mii_send(sc, frame->mii_phyaddr, 5);
521 rl_mii_send(sc, frame->mii_regaddr, 5);
522 rl_mii_send(sc, frame->mii_turnaround, 2);
523 rl_mii_send(sc, frame->mii_data, 16);
542 rl_miibus_readreg(device_t dev, int phy, int reg)
545 struct rl_mii_frame frame;
547 uint16_t rl8139_reg = 0;
549 sc = device_get_softc(dev);
551 if (sc->rl_type == RL_8139) {
552 /* Pretend the internal PHY is only at address 0 */
557 rl8139_reg = RL_BMCR;
560 rl8139_reg = RL_BMSR;
563 rl8139_reg = RL_ANAR;
566 rl8139_reg = RL_ANER;
569 rl8139_reg = RL_LPAR;
576 * Allow the rlphy driver to read the media status
577 * register. If we have a link partner which does not
578 * support NWAY, this is the register which will tell
579 * us the results of parallel detection.
582 rval = CSR_READ_1(sc, RL_MEDIASTAT);
585 device_printf(dev, "bad phy register\n");
588 rval = CSR_READ_2(sc, rl8139_reg);
592 bzero(&frame, sizeof(frame));
594 frame.mii_phyaddr = phy;
595 frame.mii_regaddr = reg;
596 rl_mii_readreg(sc, &frame);
598 return(frame.mii_data);
602 rl_miibus_writereg(device_t dev, int phy, int reg, int data)
605 struct rl_mii_frame frame;
606 u_int16_t rl8139_reg = 0;
608 sc = device_get_softc(dev);
610 if (sc->rl_type == RL_8139) {
611 /* Pretend the internal PHY is only at address 0 */
616 rl8139_reg = RL_BMCR;
619 rl8139_reg = RL_BMSR;
622 rl8139_reg = RL_ANAR;
625 rl8139_reg = RL_ANER;
628 rl8139_reg = RL_LPAR;
634 device_printf(dev, "bad phy register\n");
637 CSR_WRITE_2(sc, rl8139_reg, data);
641 bzero(&frame, sizeof(frame));
643 frame.mii_phyaddr = phy;
644 frame.mii_regaddr = reg;
645 frame.mii_data = data;
647 rl_mii_writereg(sc, &frame);
653 rl_miibus_statchg(device_t dev)
658 * Program the 64-bit multicast hash filter.
661 rl_setmulti(struct rl_softc *sc)
665 uint32_t hashes[2] = { 0, 0 };
666 struct ifmultiaddr *ifma;
670 ifp = &sc->arpcom.ac_if;
672 rxfilt = CSR_READ_4(sc, RL_RXCFG);
674 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
675 rxfilt |= RL_RXCFG_RX_MULTI;
676 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
677 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
678 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
682 /* first, zot all the existing hash bits */
683 CSR_WRITE_4(sc, RL_MAR0, 0);
684 CSR_WRITE_4(sc, RL_MAR4, 0);
686 /* now program new ones */
687 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
688 if (ifma->ifma_addr->sa_family != AF_LINK)
691 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
692 ETHER_ADDR_LEN >> 26);
694 hashes[0] |= (1 << h);
696 hashes[1] |= (1 << (h - 32));
701 rxfilt |= RL_RXCFG_RX_MULTI;
703 rxfilt &= ~RL_RXCFG_RX_MULTI;
705 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
706 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
707 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
711 rl_reset(struct rl_softc *sc)
715 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
717 for (i = 0; i < RL_TIMEOUT; i++) {
719 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
723 device_printf(sc->rl_dev, "reset never completed!\n");
727 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
728 * IDs against our list and return a device name if we find a match.
730 * Return with a value < 0 to give re(4) a change to attach.
733 rl_probe(device_t dev)
736 uint16_t product = pci_get_device(dev);
737 uint16_t vendor = pci_get_vendor(dev);
739 for (t = rl_devs; t->rl_name != NULL; t++) {
740 if (vendor == t->rl_vid && product == t->rl_did) {
741 device_set_desc(dev, t->rl_name);
750 * Attach the interface. Allocate softc structures, do ifmedia
751 * setup and ethernet/BPF attach.
754 rl_attach(device_t dev)
756 uint8_t eaddr[ETHER_ADDR_LEN];
761 int error = 0, rid, i;
763 sc = device_get_softc(dev);
767 * Handle power management nonsense.
770 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
771 uint32_t iobase, membase, irq;
773 /* Save important PCI config data. */
774 iobase = pci_read_config(dev, RL_PCI_LOIO, 4);
775 membase = pci_read_config(dev, RL_PCI_LOMEM, 4);
776 irq = pci_read_config(dev, RL_PCI_INTLINE, 4);
778 /* Reset the power state. */
779 device_printf(dev, "chip is is in D%d power mode "
780 "-- setting to D0\n", pci_get_powerstate(dev));
781 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
783 /* Restore PCI config data. */
784 pci_write_config(dev, RL_PCI_LOIO, iobase, 4);
785 pci_write_config(dev, RL_PCI_LOMEM, membase, 4);
786 pci_write_config(dev, RL_PCI_INTLINE, irq, 4);
790 * Map control/status registers.
792 pci_enable_busmaster(dev);
793 pci_enable_io(dev, RL_RES);
796 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid,
797 0, ~0, 1, RF_ACTIVE);
799 if (sc->rl_res == NULL) {
800 device_printf(dev, "couldn't map ports/memory\n");
805 sc->rl_btag = rman_get_bustag(sc->rl_res);
806 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
809 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
810 RF_SHAREABLE | RF_ACTIVE);
812 if (sc->rl_irq == NULL) {
813 device_printf(dev, "couldn't map interrupt\n");
818 callout_init(&sc->rl_stat_timer);
820 /* Reset the adapter. */
823 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
824 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
825 if (rl_did != 0x8129)
826 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
829 * Get station address from the EEPROM.
831 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0);
832 for (i = 0; i < 3; i++) {
833 eaddr[(i * 2) + 0] = as[i] & 0xff;
834 eaddr[(i * 2) + 1] = as[i] >> 8;
838 * Now read the exact device type from the EEPROM to find
839 * out if it's an 8129 or 8139.
841 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
843 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 ||
844 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 ||
845 rl_did == DLINK_DEVICEID_530TXPLUS || rl_did == RT_DEVICEID_8138 ||
846 rl_did == DLINK_DEVICEID_690TXD ||
847 rl_did == COREGA_DEVICEID_FETHERCBTXD ||
848 rl_did == COREGA_DEVICEID_FETHERIICBTXD ||
849 rl_did == PLANEX_DEVICEID_FNW3800TX)
850 sc->rl_type = RL_8139;
851 else if (rl_did == RT_DEVICEID_8129)
852 sc->rl_type = RL_8129;
854 device_printf(dev, "unknown device ID: %x\n", rl_did);
859 #define RL_NSEG_NEW 32
860 error = bus_dma_tag_create(NULL, /* parent */
861 1, 0, /* alignment, boundary */
862 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
863 BUS_SPACE_MAXADDR, /* highaddr */
864 NULL, NULL, /* filter, filterarg */
865 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
866 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
867 BUS_DMA_ALLOCNOW, /* flags */
871 device_printf(dev, "can't create parent tag\n");
876 * Now allocate a tag for the DMA descriptor lists.
877 * All of our lists are allocated as a contiguous block
880 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
881 1, 0, /* alignment, boundary */
882 BUS_SPACE_MAXADDR, /* lowaddr */
883 BUS_SPACE_MAXADDR, /* highaddr */
884 NULL, NULL, /* filter, filterarg */
885 RL_RXBUFLEN + 1518, 1, /* maxsize, nsegments */
886 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
891 device_printf(dev, "can't create RX tag\n");
896 * Now allocate a chunk of DMA-able memory based on the tag
899 error = bus_dmamem_alloc(sc->rl_tag, (void **)&sc->rl_cdata.rl_rx_buf,
900 BUS_DMA_WAITOK, &sc->rl_cdata.rl_rx_dmamap);
903 device_printf(dev, "can't allocate RX memory!\n");
908 /* Leave a few bytes before the start of the RX ring buffer. */
909 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
910 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
913 if (mii_phy_probe(dev, &sc->rl_miibus, rl_ifmedia_upd,
915 device_printf(dev, "MII without any phy!\n");
920 ifp = &sc->arpcom.ac_if;
922 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
923 ifp->if_mtu = ETHERMTU;
924 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
925 ifp->if_ioctl = rl_ioctl;
926 ifp->if_start = rl_start;
927 ifp->if_watchdog = rl_watchdog;
928 ifp->if_init = rl_init;
929 ifp->if_baudrate = 10000000;
930 ifp->if_capabilities = IFCAP_VLAN_MTU;
931 #ifdef DEVICE_POLLING
932 ifp->if_capabilities |= IFCAP_POLLING;
934 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
935 ifq_set_ready(&ifp->if_snd);
938 * Call MI attach routine.
940 ether_ifattach(ifp, eaddr);
942 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, rl_intr,
943 sc, &sc->rl_intrhand);
946 device_printf(dev, "couldn't set up irq\n");
959 rl_detach(device_t dev)
965 sc = device_get_softc(dev);
966 ifp = &sc->arpcom.ac_if;
970 if (device_is_attached(dev)) {
976 device_delete_child(dev, sc->rl_miibus);
977 bus_generic_detach(dev);
980 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
984 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
986 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
988 if (sc->rl_cdata.rl_rx_buf) {
989 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
990 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
991 sc->rl_cdata.rl_rx_dmamap);
994 bus_dma_tag_destroy(sc->rl_tag);
995 if (sc->rl_parent_tag)
996 bus_dma_tag_destroy(sc->rl_parent_tag);
1002 * Initialize the transmit descriptors.
1005 rl_list_tx_init(struct rl_softc *sc)
1007 struct rl_chain_data *cd;
1011 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1012 cd->rl_tx_chain[i] = NULL;
1014 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
1017 sc->rl_cdata.cur_tx = 0;
1018 sc->rl_cdata.last_tx = 0;
1022 * A frame has been uploaded: pass the resulting mbuf chain up to
1023 * the higher level protocols.
1025 * You know there's something wrong with a PCI bus-master chip design
1026 * when you have to use m_devget().
1028 * The receive operation is badly documented in the datasheet, so I'll
1029 * attempt to document it here. The driver provides a buffer area and
1030 * places its base address in the RX buffer start address register.
1031 * The chip then begins copying frames into the RX buffer. Each frame
1032 * is preceded by a 32-bit RX status word which specifies the length
1033 * of the frame and certain other status bits. Each frame (starting with
1034 * the status word) is also 32-bit aligned. The frame length is in the
1035 * first 16 bits of the status word; the lower 15 bits correspond with
1036 * the 'rx status register' mentioned in the datasheet.
1038 * Note: to make the Alpha happy, the frame payload needs to be aligned
1039 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from
1040 * the ring buffer starting at an address two bytes before the actual
1041 * data location. We can then shave off the first two bytes using m_adj().
1042 * The reason we do this is because m_devget() doesn't let us specify an
1043 * offset into the mbuf storage space, so we have to artificially create
1044 * one. The ring is allocated in such a way that there are a few unused
1045 * bytes of space preceecing it so that it will be safe for us to do the
1046 * 2-byte backstep even if reading from the ring at offset 0.
1049 rl_rxeof(struct rl_softc *sc)
1057 uint16_t cur_rx, limit, max_bytes, rx_bytes = 0;
1059 ifp = &sc->arpcom.ac_if;
1061 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1062 BUS_DMASYNC_POSTREAD);
1064 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1066 /* Do not try to read past this point. */
1067 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1070 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1072 max_bytes = limit - cur_rx;
1074 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1075 #ifdef DEVICE_POLLING
1076 if (ifp->if_flags & IFF_POLLING) {
1077 if (sc->rxcycles <= 0)
1081 #endif /* DEVICE_POLLING */
1082 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1083 rxstat = le32toh(*(uint32_t *)rxbufpos);
1086 * Here's a totally undocumented fact for you. When the
1087 * RealTek chip is in the process of copying a packet into
1088 * RAM for you, the length will be 0xfff0. If you spot a
1089 * packet header with this value, you need to stop. The
1090 * datasheet makes absolutely no mention of this and
1091 * RealTek should be shot for this.
1093 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1096 if ((rxstat & RL_RXSTAT_RXOK) == 0) {
1102 /* No errors; receive the packet. */
1103 total_len = rxstat >> 16;
1104 rx_bytes += total_len + 4;
1107 * XXX The RealTek chip includes the CRC with every
1108 * received frame, and there's no way to turn this
1109 * behavior off (at least, I can't find anything in
1110 * the manual that explains how to do it) so we have
1111 * to trim off the CRC manually.
1113 total_len -= ETHER_CRC_LEN;
1116 * Avoid trying to read more bytes than we know
1117 * the chip has prepared for us.
1119 if (rx_bytes > max_bytes)
1122 rxbufpos = sc->rl_cdata.rl_rx_buf +
1123 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1125 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1126 rxbufpos = sc->rl_cdata.rl_rx_buf;
1128 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1130 if (total_len > wrap) {
1132 * Fool m_devget() into thinking we want to copy
1133 * the whole buffer so we don't end up fragmenting
1136 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1137 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1141 m_adj(m, RL_ETHER_ALIGN);
1142 m_copyback(m, wrap, total_len - wrap,
1143 sc->rl_cdata.rl_rx_buf);
1145 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1147 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1148 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1152 m_adj(m, RL_ETHER_ALIGN);
1153 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1157 * Round up to 32-bit boundary.
1159 cur_rx = (cur_rx + 3) & ~3;
1160 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1167 (*ifp->if_input)(ifp, m);
1172 * A frame was downloaded to the chip. It's safe for us to clean up
1176 rl_txeof(struct rl_softc *sc)
1181 ifp = &sc->arpcom.ac_if;
1184 * Go through our tx list and free mbufs for those
1185 * frames that have been uploaded.
1188 if (RL_LAST_TXMBUF(sc) == NULL)
1190 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1191 if ((txstat & (RL_TXSTAT_TX_OK | RL_TXSTAT_TX_UNDERRUN |
1192 RL_TXSTAT_TXABRT)) == 0)
1195 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1197 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc));
1198 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc));
1199 m_freem(RL_LAST_TXMBUF(sc));
1200 RL_LAST_TXMBUF(sc) = NULL;
1202 if ((txstat & RL_TXSTAT_TX_OK) == 0) {
1206 if ((txstat & RL_TXSTAT_TXABRT) ||
1207 (txstat & RL_TXSTAT_OUTOFWIN))
1208 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1209 oldthresh = sc->rl_txthresh;
1210 /* error recovery */
1214 * If there was a transmit underrun,
1215 * bump the TX threshold.
1217 if (txstat & RL_TXSTAT_TX_UNDERRUN)
1218 sc->rl_txthresh = oldthresh + 32;
1222 RL_INC(sc->rl_cdata.last_tx);
1223 ifp->if_flags &= ~IFF_OACTIVE;
1224 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1226 if (RL_LAST_TXMBUF(sc) == NULL)
1228 else if (ifp->if_timer == 0)
1235 struct rl_softc *sc = xsc;
1236 struct mii_data *mii;
1241 mii = device_get_softc(sc->rl_miibus);
1246 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc);
1249 #ifdef DEVICE_POLLING
1250 static poll_handler_t rl_poll;
1253 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1255 struct rl_softc *sc = ifp->if_softc;
1257 if ((ifp->if_capenable & IFCAP_POLLING) == 0) {
1258 ether_poll_deregister(ifp);
1259 cmd = POLL_DEREGISTER;
1261 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1262 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1266 sc->rxcycles = count;
1269 if (!ifq_is_empty(&ifp->if_snd))
1272 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1275 status = CSR_READ_2(sc, RL_ISR);
1276 if (status == 0xffff)
1279 CSR_WRITE_2(sc, RL_ISR, status);
1282 * XXX check behaviour on receiver stalls.
1285 if (status & RL_ISR_SYSTEM_ERR) {
1291 #endif /* DEVICE_POLLING */
1296 struct rl_softc *sc;
1305 ifp = &sc->arpcom.ac_if;
1306 #ifdef DEVICE_POLLING
1307 if (ifp->if_flags & IFF_POLLING)
1309 if ((ifp->if_capenable & IFCAP_POLLING) &&
1310 ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */
1311 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1315 #endif /* DEVICE_POLLING */
1318 status = CSR_READ_2(sc, RL_ISR);
1319 /* If the card has gone away, the read returns 0xffff. */
1320 if (status == 0xffff)
1324 CSR_WRITE_2(sc, RL_ISR, status);
1326 if ((status & RL_INTRS) == 0)
1329 if (status & RL_ISR_RX_OK)
1332 if (status & RL_ISR_RX_ERR)
1335 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1338 if (status & RL_ISR_SYSTEM_ERR) {
1345 if (!ifq_is_empty(&ifp->if_snd))
1350 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1351 * pointers to the fragment pointers.
1354 rl_encap(struct rl_softc *sc, struct mbuf *m_head)
1356 struct mbuf *m_new = NULL;
1359 * The RealTek is brain damaged and wants longword-aligned
1360 * TX buffers, plus we can only have one fragment buffer
1361 * per packet. We have to copy pretty much all the time.
1363 m_new = m_defrag(m_head, MB_DONTWAIT);
1365 if (m_new == NULL) {
1371 /* Pad frames to at least 60 bytes. */
1372 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1374 * Make security concious people happy: zero out the
1375 * bytes in the pad area, since we don't know what
1376 * this mbuf cluster buffer's previous user might
1379 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
1380 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1381 m_head->m_pkthdr.len +=
1382 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1383 m_head->m_len = m_head->m_pkthdr.len;
1386 RL_CUR_TXMBUF(sc) = m_head;
1392 * Main transmit routine.
1396 rl_start(struct ifnet *ifp)
1398 struct rl_softc *sc;
1399 struct mbuf *m_head = NULL;
1403 while(RL_CUR_TXMBUF(sc) == NULL) {
1404 m_head = ifq_dequeue(&ifp->if_snd);
1408 if (rl_encap(sc, m_head))
1412 * If there's a BPF listener, bounce a copy of this frame
1415 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1418 * Transmit the frame.
1420 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
1421 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
1422 mtod(RL_CUR_TXMBUF(sc), void *),
1423 RL_CUR_TXMBUF(sc)->m_pkthdr.len,
1424 rl_dma_map_txbuf, sc, 0);
1425 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
1426 BUS_DMASYNC_PREREAD);
1427 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1428 RL_TXTHRESH(sc->rl_txthresh) |
1429 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1431 RL_INC(sc->rl_cdata.cur_tx);
1434 * Set a timeout in case the chip goes out to lunch.
1440 * We broke out of the loop because all our TX slots are
1441 * full. Mark the NIC as busy until it drains some of the
1442 * packets from the queue.
1444 if (RL_CUR_TXMBUF(sc) != NULL)
1445 ifp->if_flags |= IFF_OACTIVE;
1451 struct rl_softc *sc = xsc;
1452 struct ifnet *ifp = &sc->arpcom.ac_if;
1453 struct mii_data *mii;
1459 mii = device_get_softc(sc->rl_miibus);
1462 * Cancel pending I/O and free all RX/TX buffers.
1467 * Init our MAC address. Even though the chipset documentation
1468 * doesn't mention it, we need to enter "Config register write enable"
1469 * mode to modify the ID registers.
1471 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1472 CSR_WRITE_STREAM_4(sc, RL_IDR0,
1473 *(uint32_t *)(&sc->arpcom.ac_enaddr[0]));
1474 CSR_WRITE_STREAM_4(sc, RL_IDR4,
1475 *(uint32_t *)(&sc->arpcom.ac_enaddr[4]));
1476 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1478 /* Init the RX buffer pointer register. */
1479 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1480 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf,
1482 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1483 BUS_DMASYNC_PREWRITE);
1485 /* Init TX descriptors. */
1486 rl_list_tx_init(sc);
1489 * Enable transmit and receive.
1491 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1494 * Set the initial TX and RX configuration.
1496 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1497 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1499 /* Set the individual bit to receive frames for this host only. */
1500 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1501 rxcfg |= RL_RXCFG_RX_INDIV;
1503 /* If we want promiscuous mode, set the allframes bit. */
1504 if (ifp->if_flags & IFF_PROMISC) {
1505 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1506 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1508 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1509 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1513 * Set capture broadcast bit to capture broadcast frames.
1515 if (ifp->if_flags & IFF_BROADCAST) {
1516 rxcfg |= RL_RXCFG_RX_BROAD;
1517 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1519 rxcfg &= ~RL_RXCFG_RX_BROAD;
1520 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1524 * Program the multicast filter, if necessary.
1528 #ifdef DEVICE_POLLING
1530 * Only enable interrupts if we are polling, keep them off otherwise.
1532 if (ifp->if_flags & IFF_POLLING)
1533 CSR_WRITE_2(sc, RL_IMR, 0);
1535 #endif /* DEVICE_POLLING */
1537 * Enable interrupts.
1539 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1541 /* Set initial TX threshold */
1542 sc->rl_txthresh = RL_TX_THRESH_INIT;
1544 /* Start RX/TX process. */
1545 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1547 /* Enable receiver and transmitter. */
1548 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1552 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1554 ifp->if_flags |= IFF_RUNNING;
1555 ifp->if_flags &= ~IFF_OACTIVE;
1559 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc);
1563 * Set media options.
1566 rl_ifmedia_upd(struct ifnet *ifp)
1568 struct rl_softc *sc;
1569 struct mii_data *mii;
1572 mii = device_get_softc(sc->rl_miibus);
1579 * Report current media status.
1582 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1584 struct rl_softc *sc = ifp->if_softc;
1585 struct mii_data *mii = device_get_softc(sc->rl_miibus);
1588 ifmr->ifm_active = mii->mii_media_active;
1589 ifmr->ifm_status = mii->mii_media_status;
1593 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1595 struct rl_softc *sc = ifp->if_softc;
1596 struct ifreq *ifr = (struct ifreq *) data;
1597 struct mii_data *mii;
1604 if (ifp->if_flags & IFF_UP) {
1607 if (ifp->if_flags & IFF_RUNNING)
1619 mii = device_get_softc(sc->rl_miibus);
1620 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1623 ifp->if_capenable &= ~IFCAP_POLLING;
1624 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING;
1627 error = ether_ioctl(ifp, command, data);
1637 rl_watchdog(struct ifnet *ifp)
1639 struct rl_softc *sc = ifp->if_softc;
1644 device_printf(sc->rl_dev, "watchdog timeout\n");
1655 * Stop the adapter and free any mbufs allocated to the
1659 rl_stop(struct rl_softc *sc)
1661 struct ifnet *ifp = &sc->arpcom.ac_if;
1666 callout_stop(&sc->rl_stat_timer);
1667 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1668 #ifdef DEVICE_POLLING
1669 ether_poll_deregister(ifp);
1670 #endif /* DEVICE_POLLING */
1672 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1673 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1674 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1677 * Free the TX list buffers.
1679 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1680 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1681 bus_dmamap_unload(sc->rl_tag,
1682 sc->rl_cdata.rl_tx_dmamap[i]);
1683 bus_dmamap_destroy(sc->rl_tag,
1684 sc->rl_cdata.rl_tx_dmamap[i]);
1685 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1686 sc->rl_cdata.rl_tx_chain[i] = NULL;
1687 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1694 * Stop all chip I/O so that the kernel's probe routines don't
1695 * get confused by errant DMAs when rebooting.
1698 rl_shutdown(device_t dev)
1700 struct rl_softc *sc;
1702 sc = device_get_softc(dev);
1708 * Device suspend routine. Stop the interface and save some PCI
1709 * settings in case the BIOS doesn't restore them properly on
1713 rl_suspend(device_t dev)
1715 struct rl_softc *sc = device_get_softc(dev);
1720 for (i = 0; i < 5; i++)
1721 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4);
1722 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
1723 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
1724 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
1725 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
1733 * Device resume routine. Restore some PCI settings in case the BIOS
1734 * doesn't, re-enable busmastering, and restart the interface if
1737 static int rl_resume(device_t dev)
1739 struct rl_softc *sc = device_get_softc(dev);
1740 struct ifnet *ifp = &sc->arpcom.ac_if;
1743 /* better way to do this? */
1744 for (i = 0; i < 5; i++)
1745 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4);
1746 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
1747 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
1748 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
1749 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
1751 /* reenable busmastering */
1752 pci_enable_busmaster(dev);
1753 pci_enable_io(dev, RL_RES);
1755 /* reinitialize interface if necessary */
1756 if (ifp->if_flags & IFF_UP)