2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_ti.c,v 1.25.2.14 2002/02/15 04:20:20 silby Exp $
33 * $DragonFly: src/sys/dev/netif/ti/if_ti.c,v 1.17 2005/02/20 05:45:38 joerg Exp $
35 * $FreeBSD: src/sys/pci/if_ti.c,v 1.25.2.14 2002/02/15 04:20:20 silby Exp $
39 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
40 * Manuals, sample driver and firmware source kits are available
41 * from http://www.alteon.com/support/openkits.
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
49 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
50 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
51 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
52 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
53 * filtering and jumbo (9014 byte) frames. The hardware is largely
54 * controlled by firmware, which must be loaded into the NIC during
57 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
58 * revision, which supports new features such as extended commands,
59 * extended jumbo receive ring desciptors and a mini receive ring.
61 * Alteon Networks is to be commended for releasing such a vast amount
62 * of development material for the Tigon NIC without requiring an NDA
63 * (although they really should have done it a long time ago). With
64 * any luck, the other vendors will finally wise up and follow Alteon's
67 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
68 * this driver by #including it as a C header file. This bloats the
69 * driver somewhat, but it's the easiest method considering that the
70 * driver code and firmware code need to be kept in sync. The source
71 * for the firmware is not provided with the FreeBSD distribution since
72 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
74 * The following people deserve special thanks:
75 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
77 * - Raymond Lee of Netgear, for providing a pair of Netgear
78 * GA620 Tigon 2 boards for testing
79 * - Ulf Zimmermann, for bringing the GA260 to my attention and
80 * convincing me to write this driver.
81 * - Andrew Gallatin for providing FreeBSD/Alpha support.
84 #include <sys/param.h>
85 #include <sys/systm.h>
86 #include <sys/sockio.h>
88 #include <sys/malloc.h>
89 #include <sys/kernel.h>
90 #include <sys/socket.h>
91 #include <sys/queue.h>
94 #include <net/ifq_var.h>
95 #include <net/if_arp.h>
96 #include <net/ethernet.h>
97 #include <net/if_dl.h>
98 #include <net/if_media.h>
99 #include <net/if_types.h>
100 #include <net/vlan/if_vlan_var.h>
104 #include <netinet/in_systm.h>
105 #include <netinet/in.h>
106 #include <netinet/ip.h>
108 #include <vm/vm.h> /* for vtophys */
109 #include <vm/pmap.h> /* for vtophys */
110 #include <machine/clock.h> /* for DELAY */
111 #include <machine/bus_memio.h>
112 #include <machine/bus.h>
113 #include <machine/resource.h>
115 #include <sys/rman.h>
117 #include <bus/pci/pcireg.h>
118 #include <bus/pci/pcivar.h>
120 #include "if_tireg.h"
125 * Temporarily disable the checksum offload support for now.
126 * Tests with ftp.freesoftware.com show that after about 12 hours,
127 * the firmware will begin calculating completely bogus TX checksums
128 * and refuse to stop until the interface is reset. Unfortunately,
129 * there isn't enough time to fully debug this before the 4.1
130 * release, so this will need to stay off for now.
133 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
135 #define TI_CSUM_FEATURES 0
139 * Various supported device vendors/types and their names.
142 static struct ti_type ti_devs[] = {
143 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
144 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
145 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
146 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
147 { TC_VENDORID, TC_DEVICEID_3C985,
148 "3Com 3c985-SX Gigabit Ethernet" },
149 { NG_VENDORID, NG_DEVICEID_GA620,
150 "Netgear GA620 1000baseSX Gigabit Ethernet" },
151 { NG_VENDORID, NG_DEVICEID_GA620T,
152 "Netgear GA620 1000baseT Gigabit Ethernet" },
153 { SGI_VENDORID, SGI_DEVICEID_TIGON,
154 "Silicon Graphics Gigabit Ethernet" },
155 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
156 "Farallon PN9000SX Gigabit Ethernet" },
160 static int ti_probe (device_t);
161 static int ti_attach (device_t);
162 static int ti_detach (device_t);
163 static void ti_txeof (struct ti_softc *);
164 static void ti_rxeof (struct ti_softc *);
166 static void ti_stats_update (struct ti_softc *);
167 static int ti_encap (struct ti_softc *, struct mbuf *,
170 static void ti_intr (void *);
171 static void ti_start (struct ifnet *);
172 static int ti_ioctl (struct ifnet *, u_long, caddr_t,
174 static void ti_init (void *);
175 static void ti_init2 (struct ti_softc *);
176 static void ti_stop (struct ti_softc *);
177 static void ti_watchdog (struct ifnet *);
178 static void ti_shutdown (device_t);
179 static int ti_ifmedia_upd (struct ifnet *);
180 static void ti_ifmedia_sts (struct ifnet *, struct ifmediareq *);
182 static u_int32_t ti_eeprom_putbyte (struct ti_softc *, int);
183 static u_int8_t ti_eeprom_getbyte (struct ti_softc *,
185 static int ti_read_eeprom (struct ti_softc *, caddr_t, int, int);
187 static void ti_add_mcast (struct ti_softc *, struct ether_addr *);
188 static void ti_del_mcast (struct ti_softc *, struct ether_addr *);
189 static void ti_setmulti (struct ti_softc *);
191 static void ti_mem (struct ti_softc *, u_int32_t,
193 static void ti_loadfw (struct ti_softc *);
194 static void ti_cmd (struct ti_softc *, struct ti_cmd_desc *);
195 static void ti_cmd_ext (struct ti_softc *, struct ti_cmd_desc *,
197 static void ti_handle_events (struct ti_softc *);
198 static int ti_alloc_jumbo_mem (struct ti_softc *);
199 static void *ti_jalloc (struct ti_softc *);
200 static void ti_jfree (caddr_t, u_int);
201 static void ti_jref (caddr_t, u_int);
202 static int ti_newbuf_std (struct ti_softc *, int, struct mbuf *);
203 static int ti_newbuf_mini (struct ti_softc *, int, struct mbuf *);
204 static int ti_newbuf_jumbo (struct ti_softc *, int, struct mbuf *);
205 static int ti_init_rx_ring_std (struct ti_softc *);
206 static void ti_free_rx_ring_std (struct ti_softc *);
207 static int ti_init_rx_ring_jumbo (struct ti_softc *);
208 static void ti_free_rx_ring_jumbo (struct ti_softc *);
209 static int ti_init_rx_ring_mini (struct ti_softc *);
210 static void ti_free_rx_ring_mini (struct ti_softc *);
211 static void ti_free_tx_ring (struct ti_softc *);
212 static int ti_init_tx_ring (struct ti_softc *);
214 static int ti_64bitslot_war (struct ti_softc *);
215 static int ti_chipinit (struct ti_softc *);
216 static int ti_gibinit (struct ti_softc *);
218 static device_method_t ti_methods[] = {
219 /* Device interface */
220 DEVMETHOD(device_probe, ti_probe),
221 DEVMETHOD(device_attach, ti_attach),
222 DEVMETHOD(device_detach, ti_detach),
223 DEVMETHOD(device_shutdown, ti_shutdown),
227 static driver_t ti_driver = {
230 sizeof(struct ti_softc)
233 static devclass_t ti_devclass;
235 DECLARE_DUMMY_MODULE(if_ti);
236 DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0);
239 * Send an instruction or address to the EEPROM, check for ACK.
241 static u_int32_t ti_eeprom_putbyte(sc, byte)
248 * Make sure we're in TX mode.
250 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
253 * Feed in each bit and stobe the clock.
255 for (i = 0x80; i; i >>= 1) {
257 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
259 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
262 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
264 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
270 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
275 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
276 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
277 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
283 * Read a byte of data stored in the EEPROM at address 'addr.'
284 * We have to send two address bytes since the EEPROM can hold
285 * more than 256 bytes of data.
287 static u_int8_t ti_eeprom_getbyte(sc, addr, dest)
298 * Send write control code to EEPROM.
300 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
301 printf("ti%d: failed to send write command, status: %x\n",
302 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
307 * Send first byte of address of byte we want to read.
309 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
310 printf("ti%d: failed to send address, status: %x\n",
311 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
315 * Send second byte address of byte we want to read.
317 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
318 printf("ti%d: failed to send address, status: %x\n",
319 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
326 * Send read control code to EEPROM.
328 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
329 printf("ti%d: failed to send read command, status: %x\n",
330 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
335 * Start reading bits from EEPROM.
337 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
338 for (i = 0x80; i; i >>= 1) {
339 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
341 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
343 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
350 * No ACK generated for read, so just return byte.
359 * Read a sequence of bytes from the EEPROM.
361 static int ti_read_eeprom(sc, dest, off, cnt)
370 for (i = 0; i < cnt; i++) {
371 err = ti_eeprom_getbyte(sc, off + i, &byte);
381 * NIC memory access function. Can be used to either clear a section
382 * of NIC local memory or (if buf is non-NULL) copy data into it.
384 static void ti_mem(sc, addr, len, buf)
389 int segptr, segsize, cnt;
390 caddr_t ti_winbase, ptr;
394 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW);
401 segsize = TI_WINLEN - (segptr % TI_WINLEN);
402 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
404 bzero((char *)ti_winbase + (segptr &
405 (TI_WINLEN - 1)), segsize);
407 bcopy((char *)ptr, (char *)ti_winbase +
408 (segptr & (TI_WINLEN - 1)), segsize);
419 * Load firmware image into the NIC. Check that the firmware revision
420 * is acceptable and see if we want the firmware for the Tigon 1 or
423 static void ti_loadfw(sc)
426 switch(sc->ti_hwrev) {
428 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
429 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
430 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
431 printf("ti%d: firmware revision mismatch; want "
432 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
433 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
434 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
435 tigonFwReleaseMinor, tigonFwReleaseFix);
438 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen,
439 (caddr_t)tigonFwText);
440 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen,
441 (caddr_t)tigonFwData);
442 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen,
443 (caddr_t)tigonFwRodata);
444 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL);
445 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL);
446 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
448 case TI_HWREV_TIGON_II:
449 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
450 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
451 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
452 printf("ti%d: firmware revision mismatch; want "
453 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
454 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
455 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
456 tigon2FwReleaseMinor, tigon2FwReleaseFix);
459 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen,
460 (caddr_t)tigon2FwText);
461 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen,
462 (caddr_t)tigon2FwData);
463 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
464 (caddr_t)tigon2FwRodata);
465 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL);
466 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL);
467 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
470 printf("ti%d: can't load firmware: unknown hardware rev\n",
479 * Send the NIC a command via the command ring.
481 static void ti_cmd(sc, cmd)
483 struct ti_cmd_desc *cmd;
487 if (sc->ti_rdata->ti_cmd_ring == NULL)
490 index = sc->ti_cmd_saved_prodidx;
491 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
492 TI_INC(index, TI_CMD_RING_CNT);
493 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
494 sc->ti_cmd_saved_prodidx = index;
500 * Send the NIC an extended command. The 'len' parameter specifies the
501 * number of command slots to include after the initial command.
503 static void ti_cmd_ext(sc, cmd, arg, len)
505 struct ti_cmd_desc *cmd;
512 if (sc->ti_rdata->ti_cmd_ring == NULL)
515 index = sc->ti_cmd_saved_prodidx;
516 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
517 TI_INC(index, TI_CMD_RING_CNT);
518 for (i = 0; i < len; i++) {
519 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
520 *(u_int32_t *)(&arg[i * 4]));
521 TI_INC(index, TI_CMD_RING_CNT);
523 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
524 sc->ti_cmd_saved_prodidx = index;
530 * Handle events that have triggered interrupts.
532 static void ti_handle_events(sc)
535 struct ti_event_desc *e;
537 if (sc->ti_rdata->ti_event_ring == NULL)
540 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
541 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
542 switch(e->ti_event) {
543 case TI_EV_LINKSTAT_CHANGED:
544 sc->ti_linkstat = e->ti_code;
545 if (e->ti_code == TI_EV_CODE_LINK_UP)
546 printf("ti%d: 10/100 link up\n", sc->ti_unit);
547 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP)
548 printf("ti%d: gigabit link up\n", sc->ti_unit);
549 else if (e->ti_code == TI_EV_CODE_LINK_DOWN)
550 printf("ti%d: link down\n", sc->ti_unit);
553 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD)
554 printf("ti%d: invalid command\n", sc->ti_unit);
555 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD)
556 printf("ti%d: unknown command\n", sc->ti_unit);
557 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG)
558 printf("ti%d: bad config data\n", sc->ti_unit);
560 case TI_EV_FIRMWARE_UP:
563 case TI_EV_STATS_UPDATED:
566 case TI_EV_RESET_JUMBO_RING:
567 case TI_EV_MCAST_UPDATED:
571 printf("ti%d: unknown event: %d\n",
572 sc->ti_unit, e->ti_event);
575 /* Advance the consumer index. */
576 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
577 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
584 * Memory management for the jumbo receive ring is a pain in the
585 * butt. We need to allocate at least 9018 bytes of space per frame,
586 * _and_ it has to be contiguous (unless you use the extended
587 * jumbo descriptor format). Using malloc() all the time won't
588 * work: malloc() allocates memory in powers of two, which means we
589 * would end up wasting a considerable amount of space by allocating
590 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
591 * to do our own memory management.
593 * The driver needs to allocate a contiguous chunk of memory at boot
594 * time. We then chop this up ourselves into 9K pieces and use them
595 * as external mbuf storage.
597 * One issue here is how much memory to allocate. The jumbo ring has
598 * 256 slots in it, but at 9K per slot than can consume over 2MB of
599 * RAM. This is a bit much, especially considering we also need
600 * RAM for the standard ring and mini ring (on the Tigon 2). To
601 * save space, we only actually allocate enough memory for 64 slots
602 * by default, which works out to between 500 and 600K. This can
603 * be tuned by changing a #define in if_tireg.h.
606 static int ti_alloc_jumbo_mem(sc)
611 struct ti_jpool_entry *entry;
613 /* Grab a big chunk o' storage. */
614 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF,
615 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
617 if (sc->ti_cdata.ti_jumbo_buf == NULL) {
618 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit);
622 SLIST_INIT(&sc->ti_jfree_listhead);
623 SLIST_INIT(&sc->ti_jinuse_listhead);
626 * Now divide it up into 9K pieces and save the addresses
627 * in an array. Note that we play an evil trick here by using
628 * the first few bytes in the buffer to hold the the address
629 * of the softc structure for this interface. This is because
630 * ti_jfree() needs it, but it is called by the mbuf management
631 * code which will not pass it to us explicitly.
633 ptr = sc->ti_cdata.ti_jumbo_buf;
634 for (i = 0; i < TI_JSLOTS; i++) {
636 aptr = (u_int64_t **)ptr;
637 aptr[0] = (u_int64_t *)sc;
638 ptr += sizeof(u_int64_t);
639 sc->ti_cdata.ti_jslots[i].ti_buf = ptr;
640 sc->ti_cdata.ti_jslots[i].ti_inuse = 0;
641 ptr += (TI_JLEN - sizeof(u_int64_t));
642 entry = malloc(sizeof(struct ti_jpool_entry),
645 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM,
647 sc->ti_cdata.ti_jumbo_buf = NULL;
648 printf("ti%d: no memory for jumbo "
649 "buffer queue!\n", sc->ti_unit);
653 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
660 * Allocate a jumbo buffer.
662 static void *ti_jalloc(sc)
665 struct ti_jpool_entry *entry;
667 entry = SLIST_FIRST(&sc->ti_jfree_listhead);
670 printf("ti%d: no free jumbo buffers\n", sc->ti_unit);
674 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
675 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
676 sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1;
677 return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf);
681 * Adjust usage count on a jumbo buffer. In general this doesn't
682 * get used much because our jumbo buffers don't get passed around
683 * too much, but it's implemented for correctness.
685 static void ti_jref(buf, size)
693 /* Extract the softc struct pointer. */
694 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
695 sc = (struct ti_softc *)(aptr[0]);
698 panic("ti_jref: can't find softc pointer!");
700 if (size != TI_JUMBO_FRAMELEN)
701 panic("ti_jref: adjusting refcount of buf of wrong size!");
703 /* calculate the slot this buffer belongs to */
705 i = ((vm_offset_t)aptr
706 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
708 if ((i < 0) || (i >= TI_JSLOTS))
709 panic("ti_jref: asked to reference buffer "
710 "that we don't manage!");
711 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0)
712 panic("ti_jref: buffer already free!");
714 sc->ti_cdata.ti_jslots[i].ti_inuse++;
720 * Release a jumbo buffer.
722 static void ti_jfree(buf, size)
729 struct ti_jpool_entry *entry;
731 /* Extract the softc struct pointer. */
732 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
733 sc = (struct ti_softc *)(aptr[0]);
736 panic("ti_jfree: can't find softc pointer!");
738 if (size != TI_JUMBO_FRAMELEN)
739 panic("ti_jfree: freeing buffer of wrong size!");
741 /* calculate the slot this buffer belongs to */
743 i = ((vm_offset_t)aptr
744 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
746 if ((i < 0) || (i >= TI_JSLOTS))
747 panic("ti_jfree: asked to free buffer that we don't manage!");
748 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0)
749 panic("ti_jfree: buffer already free!");
751 sc->ti_cdata.ti_jslots[i].ti_inuse--;
752 if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) {
753 entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
755 panic("ti_jfree: buffer not in use!");
757 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead,
759 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead,
760 entry, jpool_entries);
769 * Intialize a standard receive ring descriptor.
771 static int ti_newbuf_std(sc, i, m)
776 struct mbuf *m_new = NULL;
777 struct ti_rx_desc *r;
780 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
784 MCLGET(m_new, MB_DONTWAIT);
785 if (!(m_new->m_flags & M_EXT)) {
789 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
792 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
793 m_new->m_data = m_new->m_ext.ext_buf;
796 m_adj(m_new, ETHER_ALIGN);
797 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
798 r = &sc->ti_rdata->ti_rx_std_ring[i];
799 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
800 r->ti_type = TI_BDTYPE_RECV_BD;
802 if (sc->arpcom.ac_if.if_hwassist)
803 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
804 r->ti_len = m_new->m_len;
811 * Intialize a mini receive ring descriptor. This only applies to
814 static int ti_newbuf_mini(sc, i, m)
819 struct mbuf *m_new = NULL;
820 struct ti_rx_desc *r;
823 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
827 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
830 m_new->m_data = m_new->m_pktdat;
831 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
834 m_adj(m_new, ETHER_ALIGN);
835 r = &sc->ti_rdata->ti_rx_mini_ring[i];
836 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
837 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
838 r->ti_type = TI_BDTYPE_RECV_BD;
839 r->ti_flags = TI_BDFLAG_MINI_RING;
840 if (sc->arpcom.ac_if.if_hwassist)
841 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
842 r->ti_len = m_new->m_len;
849 * Initialize a jumbo receive ring descriptor. This allocates
850 * a jumbo buffer from the pool managed internally by the driver.
852 static int ti_newbuf_jumbo(sc, i, m)
857 struct mbuf *m_new = NULL;
858 struct ti_rx_desc *r;
863 /* Allocate the mbuf. */
864 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
869 /* Allocate the jumbo buffer */
873 printf("ti%d: jumbo allocation failed "
874 "-- packet dropped!\n", sc->ti_unit);
878 /* Attach the buffer to the mbuf. */
879 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
880 m_new->m_flags |= M_EXT | M_EXT_OLD;
881 m_new->m_len = m_new->m_pkthdr.len =
882 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
883 m_new->m_ext.ext_nfree.old = ti_jfree;
884 m_new->m_ext.ext_nref.old = ti_jref;
887 m_new->m_data = m_new->m_ext.ext_buf;
888 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
891 m_adj(m_new, ETHER_ALIGN);
892 /* Set up the descriptor. */
893 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
894 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
895 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
896 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
897 r->ti_flags = TI_BDFLAG_JUMBO_RING;
898 if (sc->arpcom.ac_if.if_hwassist)
899 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
900 r->ti_len = m_new->m_len;
907 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
908 * that's 1MB or memory, which is a lot. For now, we fill only the first
909 * 256 ring entries and hope that our CPU is fast enough to keep up with
912 static int ti_init_rx_ring_std(sc)
916 struct ti_cmd_desc cmd;
918 for (i = 0; i < TI_SSLOTS; i++) {
919 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
923 TI_UPDATE_STDPROD(sc, i - 1);
929 static void ti_free_rx_ring_std(sc)
934 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
935 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
936 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
937 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
939 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
940 sizeof(struct ti_rx_desc));
946 static int ti_init_rx_ring_jumbo(sc)
950 struct ti_cmd_desc cmd;
952 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
953 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
957 TI_UPDATE_JUMBOPROD(sc, i - 1);
958 sc->ti_jumbo = i - 1;
963 static void ti_free_rx_ring_jumbo(sc)
968 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
969 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
970 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
971 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
973 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
974 sizeof(struct ti_rx_desc));
980 static int ti_init_rx_ring_mini(sc)
985 for (i = 0; i < TI_MSLOTS; i++) {
986 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
990 TI_UPDATE_MINIPROD(sc, i - 1);
996 static void ti_free_rx_ring_mini(sc)
1001 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1002 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1003 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1004 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1006 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
1007 sizeof(struct ti_rx_desc));
1013 static void ti_free_tx_ring(sc)
1014 struct ti_softc *sc;
1018 if (sc->ti_rdata->ti_tx_ring == NULL)
1021 for (i = 0; i < TI_TX_RING_CNT; i++) {
1022 if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
1023 m_freem(sc->ti_cdata.ti_tx_chain[i]);
1024 sc->ti_cdata.ti_tx_chain[i] = NULL;
1026 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
1027 sizeof(struct ti_tx_desc));
1033 static int ti_init_tx_ring(sc)
1034 struct ti_softc *sc;
1037 sc->ti_tx_saved_considx = 0;
1038 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1043 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1044 * but we have to support the old way too so that Tigon 1 cards will
1047 void ti_add_mcast(sc, addr)
1048 struct ti_softc *sc;
1049 struct ether_addr *addr;
1051 struct ti_cmd_desc cmd;
1053 u_int32_t ext[2] = {0, 0};
1055 m = (u_int16_t *)&addr->octet[0];
1057 switch(sc->ti_hwrev) {
1058 case TI_HWREV_TIGON:
1059 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1060 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1061 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1063 case TI_HWREV_TIGON_II:
1064 ext[0] = htons(m[0]);
1065 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1066 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1069 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1076 void ti_del_mcast(sc, addr)
1077 struct ti_softc *sc;
1078 struct ether_addr *addr;
1080 struct ti_cmd_desc cmd;
1082 u_int32_t ext[2] = {0, 0};
1084 m = (u_int16_t *)&addr->octet[0];
1086 switch(sc->ti_hwrev) {
1087 case TI_HWREV_TIGON:
1088 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1089 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1090 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1092 case TI_HWREV_TIGON_II:
1093 ext[0] = htons(m[0]);
1094 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1095 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1098 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1106 * Configure the Tigon's multicast address filter.
1108 * The actual multicast table management is a bit of a pain, thanks to
1109 * slight brain damage on the part of both Alteon and us. With our
1110 * multicast code, we are only alerted when the multicast address table
1111 * changes and at that point we only have the current list of addresses:
1112 * we only know the current state, not the previous state, so we don't
1113 * actually know what addresses were removed or added. The firmware has
1114 * state, but we can't get our grubby mits on it, and there is no 'delete
1115 * all multicast addresses' command. Hence, we have to maintain our own
1116 * state so we know what addresses have been programmed into the NIC at
1119 static void ti_setmulti(sc)
1120 struct ti_softc *sc;
1123 struct ifmultiaddr *ifma;
1124 struct ti_cmd_desc cmd;
1125 struct ti_mc_entry *mc;
1128 ifp = &sc->arpcom.ac_if;
1130 if (ifp->if_flags & IFF_ALLMULTI) {
1131 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1134 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1137 /* Disable interrupts. */
1138 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1139 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1141 /* First, zot all the existing filters. */
1142 while (sc->ti_mc_listhead.slh_first != NULL) {
1143 mc = sc->ti_mc_listhead.slh_first;
1144 ti_del_mcast(sc, &mc->mc_addr);
1145 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1149 /* Now program new ones. */
1150 for (ifma = ifp->if_multiaddrs.lh_first;
1151 ifma != NULL; ifma = ifma->ifma_link.le_next) {
1152 if (ifma->ifma_addr->sa_family != AF_LINK)
1154 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_INTWAIT);
1155 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1156 (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1157 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1158 ti_add_mcast(sc, &mc->mc_addr);
1161 /* Re-enable interrupts. */
1162 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1168 * Check to see if the BIOS has configured us for a 64 bit slot when
1169 * we aren't actually in one. If we detect this condition, we can work
1170 * around it on the Tigon 2 by setting a bit in the PCI state register,
1171 * but for the Tigon 1 we must give up and abort the interface attach.
1173 static int ti_64bitslot_war(sc)
1174 struct ti_softc *sc;
1176 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1177 CSR_WRITE_4(sc, 0x600, 0);
1178 CSR_WRITE_4(sc, 0x604, 0);
1179 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1180 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1181 if (sc->ti_hwrev == TI_HWREV_TIGON)
1184 TI_SETBIT(sc, TI_PCI_STATE,
1185 TI_PCISTATE_32BIT_BUS);
1195 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1196 * self-test results.
1198 static int ti_chipinit(sc)
1199 struct ti_softc *sc;
1201 u_int32_t cacheline;
1202 u_int32_t pci_writemax = 0;
1204 /* Initialize link to down state. */
1205 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1207 if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM)
1208 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES;
1210 sc->arpcom.ac_if.if_hwassist = 0;
1212 /* Set endianness before we access any non-PCI registers. */
1213 #if BYTE_ORDER == BIG_ENDIAN
1214 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1215 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1217 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1218 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1221 /* Check the ROM failed bit to see if self-tests passed. */
1222 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1223 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit);
1228 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1230 /* Figure out the hardware revision. */
1231 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1232 case TI_REV_TIGON_I:
1233 sc->ti_hwrev = TI_HWREV_TIGON;
1235 case TI_REV_TIGON_II:
1236 sc->ti_hwrev = TI_HWREV_TIGON_II;
1239 printf("ti%d: unsupported chip revision\n", sc->ti_unit);
1243 /* Do special setup for Tigon 2. */
1244 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1245 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1246 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
1247 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1250 /* Set up the PCI state register. */
1251 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1252 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1253 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1256 /* Clear the read/write max DMA parameters. */
1257 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1258 TI_PCISTATE_READ_MAXDMA));
1260 /* Get cache line size. */
1261 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1264 * If the system has set enabled the PCI memory write
1265 * and invalidate command in the command register, set
1266 * the write max parameter accordingly. This is necessary
1267 * to use MWI with the Tigon 2.
1269 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1279 /* Disable PCI memory write and invalidate. */
1281 printf("ti%d: cache line size %d not "
1282 "supported; disabling PCI MWI\n",
1283 sc->ti_unit, cacheline);
1284 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1285 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
1290 #ifdef __brokenalpha__
1292 * From the Alteon sample driver:
1293 * Must insure that we do not cross an 8K (bytes) boundary
1294 * for DMA reads. Our highest limit is 1K bytes. This is a
1295 * restriction on some ALPHA platforms with early revision
1296 * 21174 PCI chipsets, such as the AlphaPC 164lx
1298 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024);
1300 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1303 /* This sets the min dma param all the way up (0xff). */
1304 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1306 /* Configure DMA variables. */
1307 #if BYTE_ORDER == BIG_ENDIAN
1308 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1309 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1310 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1311 TI_OPMODE_DONT_FRAG_JUMBO);
1313 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
1314 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
1315 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB);
1319 * Only allow 1 DMA channel to be active at a time.
1320 * I don't think this is a good idea, but without it
1321 * the firmware racks up lots of nicDmaReadRingFull
1322 * errors. This is not compatible with hardware checksums.
1324 if (sc->arpcom.ac_if.if_hwassist == 0)
1325 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1327 /* Recommended settings from Tigon manual. */
1328 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1329 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1331 if (ti_64bitslot_war(sc)) {
1332 printf("ti%d: bios thinks we're in a 64 bit slot, "
1333 "but we aren't", sc->ti_unit);
1341 * Initialize the general information block and firmware, and
1342 * start the CPU(s) running.
1344 static int ti_gibinit(sc)
1345 struct ti_softc *sc;
1351 ifp = &sc->arpcom.ac_if;
1353 /* Disable interrupts for now. */
1354 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1356 /* Tell the chip where to find the general information block. */
1357 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
1358 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info));
1360 /* Load the firmware into SRAM. */
1363 /* Set up the contents of the general info and ring control blocks. */
1365 /* Set up the event ring and producer pointer. */
1366 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
1368 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring);
1370 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
1371 vtophys(&sc->ti_ev_prodidx);
1372 sc->ti_ev_prodidx.ti_idx = 0;
1373 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
1374 sc->ti_ev_saved_considx = 0;
1376 /* Set up the command ring and producer mailbox. */
1377 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
1379 sc->ti_rdata->ti_cmd_ring =
1380 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING);
1381 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
1383 rcb->ti_max_len = 0;
1384 for (i = 0; i < TI_CMD_RING_CNT; i++) {
1385 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
1387 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
1388 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
1389 sc->ti_cmd_saved_prodidx = 0;
1392 * Assign the address of the stats refresh buffer.
1393 * We re-use the current stats buffer for this to
1396 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
1397 vtophys(&sc->ti_rdata->ti_info.ti_stats);
1399 /* Set up the standard receive ring. */
1400 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
1401 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring);
1402 rcb->ti_max_len = TI_FRAMELEN;
1404 if (sc->arpcom.ac_if.if_hwassist)
1405 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1406 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1407 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1409 /* Set up the jumbo receive ring. */
1410 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
1411 TI_HOSTADDR(rcb->ti_hostaddr) =
1412 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring);
1413 rcb->ti_max_len = TI_JUMBO_FRAMELEN;
1415 if (sc->arpcom.ac_if.if_hwassist)
1416 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1417 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1418 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1421 * Set up the mini ring. Only activated on the
1422 * Tigon 2 but the slot in the config block is
1423 * still there on the Tigon 1.
1425 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
1426 TI_HOSTADDR(rcb->ti_hostaddr) =
1427 vtophys(&sc->ti_rdata->ti_rx_mini_ring);
1428 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
1429 if (sc->ti_hwrev == TI_HWREV_TIGON)
1430 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
1433 if (sc->arpcom.ac_if.if_hwassist)
1434 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1435 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1436 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1439 * Set up the receive return ring.
1441 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
1442 TI_HOSTADDR(rcb->ti_hostaddr) =
1443 vtophys(&sc->ti_rdata->ti_rx_return_ring);
1445 rcb->ti_max_len = TI_RETURN_RING_CNT;
1446 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
1447 vtophys(&sc->ti_return_prodidx);
1450 * Set up the tx ring. Note: for the Tigon 2, we have the option
1451 * of putting the transmit ring in the host's address space and
1452 * letting the chip DMA it instead of leaving the ring in the NIC's
1453 * memory and accessing it through the shared memory region. We
1454 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
1455 * so we have to revert to the shared memory scheme if we detect
1458 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
1459 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1460 sc->ti_rdata->ti_tx_ring_nic =
1461 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW);
1463 bzero((char *)sc->ti_rdata->ti_tx_ring,
1464 TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
1465 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
1466 if (sc->ti_hwrev == TI_HWREV_TIGON)
1469 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
1470 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1471 if (sc->arpcom.ac_if.if_hwassist)
1472 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1473 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1474 rcb->ti_max_len = TI_TX_RING_CNT;
1475 if (sc->ti_hwrev == TI_HWREV_TIGON)
1476 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
1478 TI_HOSTADDR(rcb->ti_hostaddr) =
1479 vtophys(&sc->ti_rdata->ti_tx_ring);
1480 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
1481 vtophys(&sc->ti_tx_considx);
1483 /* Set up tuneables */
1484 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
1485 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
1486 (sc->ti_rx_coal_ticks / 10));
1488 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
1489 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
1490 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
1491 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
1492 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
1493 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
1495 /* Turn interrupts on. */
1496 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
1497 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1500 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
1506 * Probe for a Tigon chip. Check the PCI vendor and device IDs
1507 * against our list and return its name if we find a match.
1509 static int ti_probe(dev)
1516 while(t->ti_name != NULL) {
1517 if ((pci_get_vendor(dev) == t->ti_vid) &&
1518 (pci_get_device(dev) == t->ti_did)) {
1519 device_set_desc(dev, t->ti_name);
1528 static int ti_attach(dev)
1534 struct ti_softc *sc;
1535 int unit, error = 0, rid;
1539 sc = device_get_softc(dev);
1540 unit = device_get_unit(dev);
1541 bzero(sc, sizeof(struct ti_softc));
1542 sc->arpcom.ac_if.if_capabilities = IFCAP_HWCSUM;
1543 sc->arpcom.ac_if.if_capenable = sc->arpcom.ac_if.if_capabilities;
1546 * Map control/status registers.
1548 command = pci_read_config(dev, PCIR_COMMAND, 4);
1549 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1550 pci_write_config(dev, PCIR_COMMAND, command, 4);
1551 command = pci_read_config(dev, PCIR_COMMAND, 4);
1553 if (!(command & PCIM_CMD_MEMEN)) {
1554 printf("ti%d: failed to enable memory mapping!\n", unit);
1560 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1561 0, ~0, 1, RF_ACTIVE);
1563 if (sc->ti_res == NULL) {
1564 printf ("ti%d: couldn't map memory\n", unit);
1569 sc->ti_btag = rman_get_bustag(sc->ti_res);
1570 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
1571 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res);
1574 * XXX FIXME: rman_get_virtual() on the alpha is currently
1575 * broken and returns a physical address instead of a kernel
1576 * virtual address. Consequently, we need to do a little
1577 * extra mangling of the vhandle on the alpha. This should
1578 * eventually be fixed! The whole idea here is to get rid
1579 * of platform dependencies.
1582 if (pci_cvt_to_bwx(sc->ti_vhandle))
1583 sc->ti_vhandle = pci_cvt_to_bwx(sc->ti_vhandle);
1585 sc->ti_vhandle = pci_cvt_to_dense(sc->ti_vhandle);
1586 sc->ti_vhandle = ALPHA_PHYS_TO_K0SEG(sc->ti_vhandle);
1589 /* Allocate interrupt */
1592 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1593 RF_SHAREABLE | RF_ACTIVE);
1595 if (sc->ti_irq == NULL) {
1596 printf("ti%d: couldn't map interrupt\n", unit);
1601 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET,
1602 ti_intr, sc, &sc->ti_intrhand);
1605 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1606 bus_release_resource(dev, SYS_RES_MEMORY,
1607 TI_PCI_LOMEM, sc->ti_res);
1608 printf("ti%d: couldn't set up irq\n", unit);
1614 if (ti_chipinit(sc)) {
1615 printf("ti%d: chip initialization failed\n", sc->ti_unit);
1616 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1617 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1618 bus_release_resource(dev, SYS_RES_MEMORY,
1619 TI_PCI_LOMEM, sc->ti_res);
1624 /* Zero out the NIC's on-board SRAM. */
1625 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
1627 /* Init again -- zeroing memory may have clobbered some registers. */
1628 if (ti_chipinit(sc)) {
1629 printf("ti%d: chip initialization failed\n", sc->ti_unit);
1630 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1631 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1632 bus_release_resource(dev, SYS_RES_MEMORY,
1633 TI_PCI_LOMEM, sc->ti_res);
1639 * Get station address from the EEPROM. Note: the manual states
1640 * that the MAC address is at offset 0x8c, however the data is
1641 * stored as two longwords (since that's how it's loaded into
1642 * the NIC). This means the MAC address is actually preceeded
1643 * by two zero bytes. We need to skip over those.
1645 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1646 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1647 printf("ti%d: failed to read station address\n", unit);
1648 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1649 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1650 bus_release_resource(dev, SYS_RES_MEMORY,
1651 TI_PCI_LOMEM, sc->ti_res);
1656 /* Allocate the general information block and ring buffers. */
1657 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF,
1658 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1660 if (sc->ti_rdata == NULL) {
1661 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1662 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1663 bus_release_resource(dev, SYS_RES_MEMORY,
1664 TI_PCI_LOMEM, sc->ti_res);
1666 printf("ti%d: no memory for list buffers!\n", sc->ti_unit);
1670 bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
1672 /* Try to allocate memory for jumbo buffers. */
1673 if (ti_alloc_jumbo_mem(sc)) {
1674 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit);
1675 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1676 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1677 bus_release_resource(dev, SYS_RES_MEMORY,
1678 TI_PCI_LOMEM, sc->ti_res);
1679 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data),
1686 * We really need a better way to tell a 1000baseTX card
1687 * from a 1000baseSX one, since in theory there could be
1688 * OEMed 1000baseTX cards from lame vendors who aren't
1689 * clever enough to change the PCI ID. For the moment
1690 * though, the AceNIC is the only copper card available.
1692 if (pci_get_vendor(dev) == ALT_VENDORID &&
1693 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
1695 /* Ok, it's not the only copper card available. */
1696 if (pci_get_vendor(dev) == NG_VENDORID &&
1697 pci_get_device(dev) == NG_DEVICEID_GA620T)
1700 /* Set default tuneable values. */
1701 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
1702 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
1703 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
1704 sc->ti_rx_max_coal_bds = 64;
1705 sc->ti_tx_max_coal_bds = 128;
1706 sc->ti_tx_buf_ratio = 21;
1708 /* Set up ifnet structure */
1709 ifp = &sc->arpcom.ac_if;
1711 if_initname(ifp, "ti", sc->ti_unit);
1712 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1713 ifp->if_ioctl = ti_ioctl;
1714 ifp->if_start = ti_start;
1715 ifp->if_watchdog = ti_watchdog;
1716 ifp->if_init = ti_init;
1717 ifp->if_mtu = ETHERMTU;
1718 ifq_set_maxlen(&ifp->if_snd, TI_TX_RING_CNT - 1);
1719 ifq_set_ready(&ifp->if_snd);
1721 /* Set up ifmedia support. */
1722 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
1723 if (sc->ti_copper) {
1725 * Copper cards allow manual 10/100 mode selection,
1726 * but not manual 1000baseTX mode selection. Why?
1727 * Becuase currently there's no way to specify the
1728 * master/slave setting through the firmware interface,
1729 * so Alteon decided to just bag it and handle it
1730 * via autonegotiation.
1732 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1733 ifmedia_add(&sc->ifmedia,
1734 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1735 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
1736 ifmedia_add(&sc->ifmedia,
1737 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
1738 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL);
1739 ifmedia_add(&sc->ifmedia,
1740 IFM_ETHER|IFM_1000_T | IFM_FDX, 0, NULL);
1742 /* Fiber cards don't support 10/100 modes. */
1743 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1744 ifmedia_add(&sc->ifmedia,
1745 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1747 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1748 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
1751 * Call MI attach routine.
1753 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
1761 static int ti_detach(dev)
1764 struct ti_softc *sc;
1770 sc = device_get_softc(dev);
1771 ifp = &sc->arpcom.ac_if;
1773 ether_ifdetach(ifp);
1776 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1777 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1778 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res);
1780 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF);
1781 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF);
1782 ifmedia_removeall(&sc->ifmedia);
1790 * Frame reception handling. This is called if there's a frame
1791 * on the receive return list.
1793 * Note: we have to be able to handle three possibilities here:
1794 * 1) the frame is from the mini receive ring (can only happen)
1795 * on Tigon 2 boards)
1796 * 2) the frame is from the jumbo recieve ring
1797 * 3) the frame is from the standard receive ring
1800 static void ti_rxeof(sc)
1801 struct ti_softc *sc;
1804 struct ti_cmd_desc cmd;
1806 ifp = &sc->arpcom.ac_if;
1808 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
1809 struct ti_rx_desc *cur_rx;
1811 struct mbuf *m = NULL;
1812 u_int16_t vlan_tag = 0;
1816 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
1817 rxidx = cur_rx->ti_idx;
1818 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
1820 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
1822 vlan_tag = cur_rx->ti_vlan_tag & 0xfff;
1825 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
1826 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
1827 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
1828 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
1829 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1831 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1834 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
1836 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1839 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
1840 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
1841 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
1842 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
1843 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1845 ti_newbuf_mini(sc, sc->ti_mini, m);
1848 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
1850 ti_newbuf_mini(sc, sc->ti_mini, m);
1854 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
1855 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
1856 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
1857 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1859 ti_newbuf_std(sc, sc->ti_std, m);
1862 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
1864 ti_newbuf_std(sc, sc->ti_std, m);
1869 m->m_pkthdr.len = m->m_len = cur_rx->ti_len;
1871 m->m_pkthdr.rcvif = ifp;
1873 if (ifp->if_hwassist) {
1874 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1876 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
1877 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1878 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum;
1882 * If we received a packet with a vlan tag, pass it
1883 * to vlan_input() instead of ether_input().
1886 VLAN_INPUT_TAG(m, vlan_tag);
1887 have_tag = vlan_tag = 0;
1889 (*ifp->if_input)(ifp, m);
1893 /* Only necessary on the Tigon 1. */
1894 if (sc->ti_hwrev == TI_HWREV_TIGON)
1895 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
1896 sc->ti_rx_saved_considx);
1898 TI_UPDATE_STDPROD(sc, sc->ti_std);
1899 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
1900 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
1905 static void ti_txeof(sc)
1906 struct ti_softc *sc;
1908 struct ti_tx_desc *cur_tx = NULL;
1911 ifp = &sc->arpcom.ac_if;
1914 * Go through our tx ring and free mbufs for those
1915 * frames that have been sent.
1917 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
1920 idx = sc->ti_tx_saved_considx;
1921 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1923 CSR_WRITE_4(sc, TI_WINBASE,
1924 TI_TX_RING_BASE + 6144);
1926 CSR_WRITE_4(sc, TI_WINBASE,
1927 TI_TX_RING_BASE + 4096);
1929 CSR_WRITE_4(sc, TI_WINBASE,
1930 TI_TX_RING_BASE + 2048);
1932 CSR_WRITE_4(sc, TI_WINBASE,
1934 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128];
1936 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
1937 if (cur_tx->ti_flags & TI_BDFLAG_END)
1939 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
1940 m_freem(sc->ti_cdata.ti_tx_chain[idx]);
1941 sc->ti_cdata.ti_tx_chain[idx] = NULL;
1944 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
1949 ifp->if_flags &= ~IFF_OACTIVE;
1954 static void ti_intr(xsc)
1957 struct ti_softc *sc;
1961 ifp = &sc->arpcom.ac_if;
1964 /* Avoid this for now -- checking this register is expensive. */
1965 /* Make sure this is really our interrupt. */
1966 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE))
1970 /* Ack interrupt and stop others from occuring. */
1971 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1973 if (ifp->if_flags & IFF_RUNNING) {
1974 /* Check RX return ring producer/consumer */
1977 /* Check TX ring producer/consumer */
1981 ti_handle_events(sc);
1983 /* Re-enable interrupts. */
1984 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1986 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
1992 static void ti_stats_update(sc)
1993 struct ti_softc *sc;
1997 ifp = &sc->arpcom.ac_if;
1999 ifp->if_collisions +=
2000 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
2001 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
2002 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
2003 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
2010 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2011 * pointers to descriptors.
2013 static int ti_encap(sc, m_head, txidx)
2014 struct ti_softc *sc;
2015 struct mbuf *m_head;
2018 struct ti_tx_desc *f = NULL;
2020 u_int32_t frag, cur, cnt = 0;
2021 u_int16_t csum_flags = 0;
2022 struct ifvlan *ifv = NULL;
2024 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2025 m_head->m_pkthdr.rcvif != NULL &&
2026 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2027 ifv = m_head->m_pkthdr.rcvif->if_softc;
2030 cur = frag = *txidx;
2032 if (m_head->m_pkthdr.csum_flags) {
2033 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2034 csum_flags |= TI_BDFLAG_IP_CKSUM;
2035 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2036 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
2037 if (m_head->m_flags & M_LASTFRAG)
2038 csum_flags |= TI_BDFLAG_IP_FRAG_END;
2039 else if (m_head->m_flags & M_FRAG)
2040 csum_flags |= TI_BDFLAG_IP_FRAG;
2043 * Start packing the mbufs in this chain into
2044 * the fragment pointers. Stop when we run out
2045 * of fragments or hit the end of the mbuf chain.
2047 for (m = m_head; m != NULL; m = m->m_next) {
2048 if (m->m_len != 0) {
2049 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2051 CSR_WRITE_4(sc, TI_WINBASE,
2052 TI_TX_RING_BASE + 6144);
2053 else if (frag > 255)
2054 CSR_WRITE_4(sc, TI_WINBASE,
2055 TI_TX_RING_BASE + 4096);
2056 else if (frag > 127)
2057 CSR_WRITE_4(sc, TI_WINBASE,
2058 TI_TX_RING_BASE + 2048);
2060 CSR_WRITE_4(sc, TI_WINBASE,
2062 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128];
2064 f = &sc->ti_rdata->ti_tx_ring[frag];
2065 if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
2067 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t));
2068 f->ti_len = m->m_len;
2069 f->ti_flags = csum_flags;
2072 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
2073 f->ti_vlan_tag = ifv->ifv_tag & 0xfff;
2079 * Sanity check: avoid coming within 16 descriptors
2080 * of the end of the ring.
2082 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
2085 TI_INC(frag, TI_TX_RING_CNT);
2093 if (frag == sc->ti_tx_saved_considx)
2096 if (sc->ti_hwrev == TI_HWREV_TIGON)
2097 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |=
2100 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
2101 sc->ti_cdata.ti_tx_chain[cur] = m_head;
2102 sc->ti_txcnt += cnt;
2110 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2111 * to the mbuf data regions directly in the transmit descriptors.
2113 static void ti_start(ifp)
2116 struct ti_softc *sc;
2117 struct mbuf *m_head = NULL;
2118 u_int32_t prodidx = 0;
2122 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);
2124 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
2125 m_head = ifq_poll(&ifp->if_snd);
2131 * safety overkill. If this is a fragmented packet chain
2132 * with delayed TCP/UDP checksums, then only encapsulate
2133 * it if we have enough descriptors to handle the entire
2135 * (paranoia -- may not actually be needed)
2137 if (m_head->m_flags & M_FIRSTFRAG &&
2138 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2139 if ((TI_TX_RING_CNT - sc->ti_txcnt) <
2140 m_head->m_pkthdr.csum_data + 16) {
2141 ifp->if_flags |= IFF_OACTIVE;
2147 * Pack the data into the transmit ring. If we
2148 * don't have room, set the OACTIVE flag and wait
2149 * for the NIC to drain the ring.
2151 if (ti_encap(sc, m_head, &prodidx)) {
2152 ifp->if_flags |= IFF_OACTIVE;
2156 m_head = ifq_dequeue(&ifp->if_snd);
2157 BPF_MTAP(ifp, m_head);
2161 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
2164 * Set a timeout in case the chip goes out to lunch.
2171 static void ti_init(xsc)
2174 struct ti_softc *sc = xsc;
2179 /* Cancel pending I/O and flush buffers. */
2182 /* Init the gen info block, ring control blocks and firmware. */
2183 if (ti_gibinit(sc)) {
2184 printf("ti%d: initialization failure\n", sc->ti_unit);
2194 static void ti_init2(sc)
2195 struct ti_softc *sc;
2197 struct ti_cmd_desc cmd;
2200 struct ifmedia *ifm;
2203 ifp = &sc->arpcom.ac_if;
2205 /* Specify MTU and interface index. */
2206 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_dunit);
2207 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
2208 ETHER_HDR_LEN + ETHER_CRC_LEN);
2209 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
2211 /* Load our MAC address. */
2212 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
2213 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0]));
2214 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2]));
2215 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
2217 /* Enable or disable promiscuous mode as needed. */
2218 if (ifp->if_flags & IFF_PROMISC) {
2219 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
2221 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
2224 /* Program multicast filter. */
2228 * If this is a Tigon 1, we should tell the
2229 * firmware to use software packet filtering.
2231 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2232 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
2236 ti_init_rx_ring_std(sc);
2238 /* Init jumbo RX ring. */
2239 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2240 ti_init_rx_ring_jumbo(sc);
2243 * If this is a Tigon 2, we can also configure the
2246 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
2247 ti_init_rx_ring_mini(sc);
2249 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
2250 sc->ti_rx_saved_considx = 0;
2253 ti_init_tx_ring(sc);
2255 /* Tell firmware we're alive. */
2256 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
2258 /* Enable host interrupts. */
2259 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2261 ifp->if_flags |= IFF_RUNNING;
2262 ifp->if_flags &= ~IFF_OACTIVE;
2265 * Make sure to set media properly. We have to do this
2266 * here since we have to issue commands in order to set
2267 * the link negotiation and we can't issue commands until
2268 * the firmware is running.
2271 tmp = ifm->ifm_media;
2272 ifm->ifm_media = ifm->ifm_cur->ifm_media;
2273 ti_ifmedia_upd(ifp);
2274 ifm->ifm_media = tmp;
2280 * Set media options.
2282 static int ti_ifmedia_upd(ifp)
2285 struct ti_softc *sc;
2286 struct ifmedia *ifm;
2287 struct ti_cmd_desc cmd;
2292 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2295 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2297 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2298 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|
2299 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
2300 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
2301 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX|
2302 TI_LNK_AUTONEGENB|TI_LNK_ENB);
2303 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2304 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
2308 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2309 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB);
2310 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
2311 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2312 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
2314 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2315 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
2321 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
2322 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF);
2323 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
2324 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
2325 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
2327 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
2329 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2330 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
2332 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
2334 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2335 TI_CMD_CODE_NEGOTIATE_10_100, 0);
2343 * Report current media status.
2345 static void ti_ifmedia_sts(ifp, ifmr)
2347 struct ifmediareq *ifmr;
2349 struct ti_softc *sc;
2350 u_int32_t media = 0;
2354 ifmr->ifm_status = IFM_AVALID;
2355 ifmr->ifm_active = IFM_ETHER;
2357 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
2360 ifmr->ifm_status |= IFM_ACTIVE;
2362 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
2363 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
2365 ifmr->ifm_active |= IFM_1000_T;
2367 ifmr->ifm_active |= IFM_1000_SX;
2368 if (media & TI_GLNK_FULL_DUPLEX)
2369 ifmr->ifm_active |= IFM_FDX;
2371 ifmr->ifm_active |= IFM_HDX;
2372 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
2373 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
2374 if (sc->ti_copper) {
2375 if (media & TI_LNK_100MB)
2376 ifmr->ifm_active |= IFM_100_TX;
2377 if (media & TI_LNK_10MB)
2378 ifmr->ifm_active |= IFM_10_T;
2380 if (media & TI_LNK_100MB)
2381 ifmr->ifm_active |= IFM_100_FX;
2382 if (media & TI_LNK_10MB)
2383 ifmr->ifm_active |= IFM_10_FL;
2385 if (media & TI_LNK_FULL_DUPLEX)
2386 ifmr->ifm_active |= IFM_FDX;
2387 if (media & TI_LNK_HALF_DUPLEX)
2388 ifmr->ifm_active |= IFM_HDX;
2394 static int ti_ioctl(ifp, command, data, cr)
2400 struct ti_softc *sc = ifp->if_softc;
2401 struct ifreq *ifr = (struct ifreq *) data;
2402 int s, mask, error = 0;
2403 struct ti_cmd_desc cmd;
2410 error = ether_ioctl(ifp, command, data);
2413 if (ifr->ifr_mtu > TI_JUMBO_MTU)
2416 ifp->if_mtu = ifr->ifr_mtu;
2421 if (ifp->if_flags & IFF_UP) {
2423 * If only the state of the PROMISC flag changed,
2424 * then just use the 'set promisc mode' command
2425 * instead of reinitializing the entire NIC. Doing
2426 * a full re-init means reloading the firmware and
2427 * waiting for it to start up, which may take a
2430 if (ifp->if_flags & IFF_RUNNING &&
2431 ifp->if_flags & IFF_PROMISC &&
2432 !(sc->ti_if_flags & IFF_PROMISC)) {
2433 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2434 TI_CMD_CODE_PROMISC_ENB, 0);
2435 } else if (ifp->if_flags & IFF_RUNNING &&
2436 !(ifp->if_flags & IFF_PROMISC) &&
2437 sc->ti_if_flags & IFF_PROMISC) {
2438 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2439 TI_CMD_CODE_PROMISC_DIS, 0);
2443 if (ifp->if_flags & IFF_RUNNING) {
2447 sc->ti_if_flags = ifp->if_flags;
2452 if (ifp->if_flags & IFF_RUNNING) {
2459 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2462 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2463 if (mask & IFCAP_HWCSUM) {
2464 if (IFCAP_HWCSUM & ifp->if_capenable)
2465 ifp->if_capenable &= ~IFCAP_HWCSUM;
2467 ifp->if_capenable |= IFCAP_HWCSUM;
2468 if (ifp->if_flags & IFF_RUNNING)
2483 static void ti_watchdog(ifp)
2486 struct ti_softc *sc;
2490 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit);
2500 * Stop the adapter and free any mbufs allocated to the
2503 static void ti_stop(sc)
2504 struct ti_softc *sc;
2507 struct ti_cmd_desc cmd;
2509 ifp = &sc->arpcom.ac_if;
2511 /* Disable host interrupts. */
2512 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2514 * Tell firmware we're shutting down.
2516 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
2518 /* Halt and reinitialize. */
2520 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
2523 /* Free the RX lists. */
2524 ti_free_rx_ring_std(sc);
2526 /* Free jumbo RX list. */
2527 ti_free_rx_ring_jumbo(sc);
2529 /* Free mini RX list. */
2530 ti_free_rx_ring_mini(sc);
2532 /* Free TX buffers. */
2533 ti_free_tx_ring(sc);
2535 sc->ti_ev_prodidx.ti_idx = 0;
2536 sc->ti_return_prodidx.ti_idx = 0;
2537 sc->ti_tx_considx.ti_idx = 0;
2538 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
2540 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2546 * Stop all chip I/O so that the kernel's probe routines don't
2547 * get confused by errant DMAs when rebooting.
2549 static void ti_shutdown(dev)
2552 struct ti_softc *sc;
2554 sc = device_get_softc(dev);