1 /* $OpenBSD: if_nfe.c,v 1.63 2006/06/17 18:00:43 brad Exp $ */
2 /* $DragonFly: src/sys/dev/netif/nfe/if_nfe.c,v 1.36 2008/07/12 06:01:37 sephe Exp $ */
5 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
7 * This code is derived from software contributed to The DragonFly Project
8 * by Sepherosa Ziehau <sepherosa@gmail.com> and
9 * Matthew Dillon <dillon@apollo.backplane.com>
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
21 * 3. Neither the name of The DragonFly Project nor the names of its
22 * contributors may be used to endorse or promote products derived
23 * from this software without specific, prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
28 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
29 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
30 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
31 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
33 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
34 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
35 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr>
41 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org>
43 * Permission to use, copy, modify, and distribute this software for any
44 * purpose with or without fee is hereby granted, provided that the above
45 * copyright notice and this permission notice appear in all copies.
47 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
48 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
49 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
50 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
51 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
52 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
53 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
56 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */
58 #include "opt_polling.h"
59 #include "opt_ethernet.h"
61 #include <sys/param.h>
62 #include <sys/endian.h>
63 #include <sys/kernel.h>
65 #include <sys/interrupt.h>
68 #include <sys/serialize.h>
69 #include <sys/socket.h>
70 #include <sys/sockio.h>
71 #include <sys/sysctl.h>
73 #include <net/ethernet.h>
76 #include <net/if_arp.h>
77 #include <net/if_dl.h>
78 #include <net/if_media.h>
79 #include <net/ifq_var.h>
80 #include <net/if_types.h>
81 #include <net/if_var.h>
82 #include <net/vlan/if_vlan_var.h>
83 #include <net/vlan/if_vlan_ether.h>
85 #include <bus/pci/pcireg.h>
86 #include <bus/pci/pcivar.h>
87 #include <bus/pci/pcidevs.h>
89 #include <dev/netif/mii_layer/mii.h>
90 #include <dev/netif/mii_layer/miivar.h>
92 #include "miibus_if.h"
94 #include <dev/netif/nfe/if_nfereg.h>
95 #include <dev/netif/nfe/if_nfevar.h>
98 #define NFE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
100 static int nfe_probe(device_t);
101 static int nfe_attach(device_t);
102 static int nfe_detach(device_t);
103 static void nfe_shutdown(device_t);
104 static int nfe_resume(device_t);
105 static int nfe_suspend(device_t);
107 static int nfe_miibus_readreg(device_t, int, int);
108 static void nfe_miibus_writereg(device_t, int, int, int);
109 static void nfe_miibus_statchg(device_t);
111 #ifdef DEVICE_POLLING
112 static void nfe_poll(struct ifnet *, enum poll_cmd, int);
114 static void nfe_intr(void *);
115 static int nfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
116 static int nfe_rxeof(struct nfe_softc *);
117 static int nfe_txeof(struct nfe_softc *);
118 static int nfe_encap(struct nfe_softc *, struct nfe_tx_ring *,
120 static void nfe_start(struct ifnet *);
121 static void nfe_watchdog(struct ifnet *);
122 static void nfe_init(void *);
123 static void nfe_stop(struct nfe_softc *);
124 static struct nfe_jbuf *nfe_jalloc(struct nfe_softc *);
125 static void nfe_jfree(void *);
126 static void nfe_jref(void *);
127 static int nfe_jpool_alloc(struct nfe_softc *, struct nfe_rx_ring *);
128 static void nfe_jpool_free(struct nfe_softc *, struct nfe_rx_ring *);
129 static int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
130 static void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
131 static int nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
132 static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
133 static int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
134 static void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
135 static int nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
136 static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
137 static int nfe_ifmedia_upd(struct ifnet *);
138 static void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
139 static void nfe_setmulti(struct nfe_softc *);
140 static void nfe_get_macaddr(struct nfe_softc *, uint8_t *);
141 static void nfe_set_macaddr(struct nfe_softc *, const uint8_t *);
142 static void nfe_powerup(device_t);
143 static void nfe_mac_reset(struct nfe_softc *);
144 static void nfe_tick(void *);
145 static void nfe_ring_dma_addr(void *, bus_dma_segment_t *, int, int);
146 static void nfe_buf_dma_addr(void *, bus_dma_segment_t *, int, bus_size_t,
148 static void nfe_set_paddr_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
150 static void nfe_set_ready_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
152 static int nfe_newbuf_std(struct nfe_softc *, struct nfe_rx_ring *, int,
154 static int nfe_newbuf_jumbo(struct nfe_softc *, struct nfe_rx_ring *, int,
156 static void nfe_enable_intrs(struct nfe_softc *);
157 static void nfe_disable_intrs(struct nfe_softc *);
159 static int nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS);
164 static int nfe_debug = 0;
165 static int nfe_rx_ring_count = NFE_RX_RING_DEF_COUNT;
166 static int nfe_imtime = 0; /* Disable interrupt moderation */
168 TUNABLE_INT("hw.nfe.rx_ring_count", &nfe_rx_ring_count);
169 TUNABLE_INT("hw.nfe.imtimer", &nfe_imtime);
170 TUNABLE_INT("hw.nfe.debug", &nfe_debug);
172 #define DPRINTF(sc, fmt, ...) do { \
173 if ((sc)->sc_debug) { \
174 if_printf(&(sc)->arpcom.ac_if, \
179 #define DPRINTFN(sc, lv, fmt, ...) do { \
180 if ((sc)->sc_debug >= (lv)) { \
181 if_printf(&(sc)->arpcom.ac_if, \
186 #else /* !NFE_DEBUG */
188 #define DPRINTF(sc, fmt, ...)
189 #define DPRINTFN(sc, lv, fmt, ...)
191 #endif /* NFE_DEBUG */
195 bus_dma_segment_t *segs;
198 static const struct nfe_dev {
203 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN,
204 "NVIDIA nForce Fast Ethernet" },
206 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN,
207 "NVIDIA nForce2 Fast Ethernet" },
209 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1,
210 "NVIDIA nForce3 Gigabit Ethernet" },
212 /* XXX TGEN the next chip can also be found in the nForce2 Ultra 400Gb
213 chipset, and possibly also the 400R; it might be both nForce2- and
214 nForce3-based boards can use the same MCPs (= southbridges) */
215 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2,
216 "NVIDIA nForce3 Gigabit Ethernet" },
218 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3,
219 "NVIDIA nForce3 Gigabit Ethernet" },
221 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4,
222 "NVIDIA nForce3 Gigabit Ethernet" },
224 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5,
225 "NVIDIA nForce3 Gigabit Ethernet" },
227 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1,
228 "NVIDIA CK804 Gigabit Ethernet" },
230 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2,
231 "NVIDIA CK804 Gigabit Ethernet" },
233 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1,
234 "NVIDIA MCP04 Gigabit Ethernet" },
236 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2,
237 "NVIDIA MCP04 Gigabit Ethernet" },
239 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1,
240 "NVIDIA MCP51 Gigabit Ethernet" },
242 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2,
243 "NVIDIA MCP51 Gigabit Ethernet" },
245 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1,
246 "NVIDIA MCP55 Gigabit Ethernet" },
248 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2,
249 "NVIDIA MCP55 Gigabit Ethernet" },
251 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1,
252 "NVIDIA MCP61 Gigabit Ethernet" },
254 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2,
255 "NVIDIA MCP61 Gigabit Ethernet" },
257 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3,
258 "NVIDIA MCP61 Gigabit Ethernet" },
260 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4,
261 "NVIDIA MCP61 Gigabit Ethernet" },
263 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1,
264 "NVIDIA MCP65 Gigabit Ethernet" },
266 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2,
267 "NVIDIA MCP65 Gigabit Ethernet" },
269 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3,
270 "NVIDIA MCP65 Gigabit Ethernet" },
272 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4,
273 "NVIDIA MCP65 Gigabit Ethernet" },
275 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1,
276 "NVIDIA MCP67 Gigabit Ethernet" },
278 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2,
279 "NVIDIA MCP67 Gigabit Ethernet" },
281 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3,
282 "NVIDIA MCP67 Gigabit Ethernet" },
284 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4,
285 "NVIDIA MCP67 Gigabit Ethernet" },
287 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1,
288 "NVIDIA MCP73 Gigabit Ethernet" },
290 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2,
291 "NVIDIA MCP73 Gigabit Ethernet" },
293 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3,
294 "NVIDIA MCP73 Gigabit Ethernet" },
296 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4,
297 "NVIDIA MCP73 Gigabit Ethernet" },
299 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1,
300 "NVIDIA MCP77 Gigabit Ethernet" },
302 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2,
303 "NVIDIA MCP77 Gigabit Ethernet" },
305 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3,
306 "NVIDIA MCP77 Gigabit Ethernet" },
308 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4,
309 "NVIDIA MCP77 Gigabit Ethernet" },
311 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1,
312 "NVIDIA MCP79 Gigabit Ethernet" },
314 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2,
315 "NVIDIA MCP79 Gigabit Ethernet" },
317 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3,
318 "NVIDIA MCP79 Gigabit Ethernet" },
320 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4,
321 "NVIDIA MCP79 Gigabit Ethernet" },
326 static device_method_t nfe_methods[] = {
327 /* Device interface */
328 DEVMETHOD(device_probe, nfe_probe),
329 DEVMETHOD(device_attach, nfe_attach),
330 DEVMETHOD(device_detach, nfe_detach),
331 DEVMETHOD(device_suspend, nfe_suspend),
332 DEVMETHOD(device_resume, nfe_resume),
333 DEVMETHOD(device_shutdown, nfe_shutdown),
336 DEVMETHOD(bus_print_child, bus_generic_print_child),
337 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
340 DEVMETHOD(miibus_readreg, nfe_miibus_readreg),
341 DEVMETHOD(miibus_writereg, nfe_miibus_writereg),
342 DEVMETHOD(miibus_statchg, nfe_miibus_statchg),
347 static driver_t nfe_driver = {
350 sizeof(struct nfe_softc)
353 static devclass_t nfe_devclass;
355 DECLARE_DUMMY_MODULE(if_nfe);
356 MODULE_DEPEND(if_nfe, miibus, 1, 1, 1);
357 DRIVER_MODULE(if_nfe, pci, nfe_driver, nfe_devclass, 0, 0);
358 DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, 0, 0);
361 nfe_probe(device_t dev)
363 const struct nfe_dev *n;
366 vid = pci_get_vendor(dev);
367 did = pci_get_device(dev);
368 for (n = nfe_devices; n->desc != NULL; ++n) {
369 if (vid == n->vid && did == n->did) {
370 struct nfe_softc *sc = device_get_softc(dev);
373 case PCI_PRODUCT_NVIDIA_NFORCE_LAN:
374 case PCI_PRODUCT_NVIDIA_NFORCE2_LAN:
375 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN1:
376 sc->sc_caps = NFE_NO_PWRCTL |
379 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2:
380 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3:
381 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4:
382 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5:
383 sc->sc_caps = NFE_JUMBO_SUP |
388 case PCI_PRODUCT_NVIDIA_MCP51_LAN1:
389 case PCI_PRODUCT_NVIDIA_MCP51_LAN2:
390 sc->sc_caps = NFE_FIX_EADDR;
392 case PCI_PRODUCT_NVIDIA_MCP61_LAN1:
393 case PCI_PRODUCT_NVIDIA_MCP61_LAN2:
394 case PCI_PRODUCT_NVIDIA_MCP61_LAN3:
395 case PCI_PRODUCT_NVIDIA_MCP61_LAN4:
396 case PCI_PRODUCT_NVIDIA_MCP67_LAN1:
397 case PCI_PRODUCT_NVIDIA_MCP67_LAN2:
398 case PCI_PRODUCT_NVIDIA_MCP67_LAN3:
399 case PCI_PRODUCT_NVIDIA_MCP67_LAN4:
400 case PCI_PRODUCT_NVIDIA_MCP73_LAN1:
401 case PCI_PRODUCT_NVIDIA_MCP73_LAN2:
402 case PCI_PRODUCT_NVIDIA_MCP73_LAN3:
403 case PCI_PRODUCT_NVIDIA_MCP73_LAN4:
404 sc->sc_caps |= NFE_40BIT_ADDR;
406 case PCI_PRODUCT_NVIDIA_CK804_LAN1:
407 case PCI_PRODUCT_NVIDIA_CK804_LAN2:
408 case PCI_PRODUCT_NVIDIA_MCP04_LAN1:
409 case PCI_PRODUCT_NVIDIA_MCP04_LAN2:
410 sc->sc_caps = NFE_JUMBO_SUP |
416 case PCI_PRODUCT_NVIDIA_MCP65_LAN1:
417 case PCI_PRODUCT_NVIDIA_MCP65_LAN2:
418 case PCI_PRODUCT_NVIDIA_MCP65_LAN3:
419 case PCI_PRODUCT_NVIDIA_MCP65_LAN4:
420 sc->sc_caps = NFE_JUMBO_SUP |
423 case PCI_PRODUCT_NVIDIA_MCP55_LAN1:
424 case PCI_PRODUCT_NVIDIA_MCP55_LAN2:
425 sc->sc_caps = NFE_JUMBO_SUP |
431 case PCI_PRODUCT_NVIDIA_MCP77_LAN1:
432 case PCI_PRODUCT_NVIDIA_MCP77_LAN2:
433 case PCI_PRODUCT_NVIDIA_MCP77_LAN3:
434 case PCI_PRODUCT_NVIDIA_MCP77_LAN4:
435 case PCI_PRODUCT_NVIDIA_MCP79_LAN1:
436 case PCI_PRODUCT_NVIDIA_MCP79_LAN2:
437 case PCI_PRODUCT_NVIDIA_MCP79_LAN3:
438 case PCI_PRODUCT_NVIDIA_MCP79_LAN4:
439 sc->sc_caps = NFE_40BIT_ADDR |
444 device_set_desc(dev, n->desc);
445 device_set_async_attach(dev, TRUE);
453 nfe_attach(device_t dev)
455 struct nfe_softc *sc = device_get_softc(dev);
456 struct ifnet *ifp = &sc->arpcom.ac_if;
457 uint8_t eaddr[ETHER_ADDR_LEN];
460 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
461 lwkt_serialize_init(&sc->sc_jbuf_serializer);
464 * Initialize sysctl variables
466 sc->sc_rx_ring_count = nfe_rx_ring_count;
467 sc->sc_debug = nfe_debug;
468 if (nfe_imtime < 0) {
469 sc->sc_flags |= NFE_F_DYN_IM;
470 sc->sc_imtime = -nfe_imtime;
472 sc->sc_imtime = nfe_imtime;
474 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
476 sc->sc_mem_rid = PCIR_BAR(0);
478 if (sc->sc_caps & NFE_40BIT_ADDR)
479 sc->rxtxctl_desc = NFE_RXTX_DESC_V3;
480 else if (sc->sc_caps & NFE_JUMBO_SUP)
481 sc->rxtxctl_desc = NFE_RXTX_DESC_V2;
484 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
487 mem = pci_read_config(dev, sc->sc_mem_rid, 4);
488 irq = pci_read_config(dev, PCIR_INTLINE, 4);
490 device_printf(dev, "chip is in D%d power mode "
491 "-- setting to D0\n", pci_get_powerstate(dev));
493 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
495 pci_write_config(dev, sc->sc_mem_rid, mem, 4);
496 pci_write_config(dev, PCIR_INTLINE, irq, 4);
498 #endif /* !BURN_BRIDGE */
500 /* Enable bus mastering */
501 pci_enable_busmaster(dev);
503 /* Allocate IO memory */
504 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
505 &sc->sc_mem_rid, RF_ACTIVE);
506 if (sc->sc_mem_res == NULL) {
507 device_printf(dev, "cound not allocate io memory\n");
510 sc->sc_memh = rman_get_bushandle(sc->sc_mem_res);
511 sc->sc_memt = rman_get_bustag(sc->sc_mem_res);
515 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
517 RF_SHAREABLE | RF_ACTIVE);
518 if (sc->sc_irq_res == NULL) {
519 device_printf(dev, "could not allocate irq\n");
525 NFE_WRITE(sc, NFE_WOL_CTL, 0);
527 if ((sc->sc_caps & NFE_NO_PWRCTL) == 0)
530 nfe_get_macaddr(sc, eaddr);
533 * Allocate Tx and Rx rings.
535 error = nfe_alloc_tx_ring(sc, &sc->txq);
537 device_printf(dev, "could not allocate Tx ring\n");
541 error = nfe_alloc_rx_ring(sc, &sc->rxq);
543 device_printf(dev, "could not allocate Rx ring\n");
550 sysctl_ctx_init(&sc->sc_sysctl_ctx);
551 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
552 SYSCTL_STATIC_CHILDREN(_hw),
554 device_get_nameunit(dev),
556 if (sc->sc_sysctl_tree == NULL) {
557 device_printf(dev, "can't add sysctl node\n");
561 SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
562 SYSCTL_CHILDREN(sc->sc_sysctl_tree),
563 OID_AUTO, "imtimer", CTLTYPE_INT | CTLFLAG_RW,
564 sc, 0, nfe_sysctl_imtime, "I",
565 "Interrupt moderation time (usec). "
566 "0 to disable interrupt moderation.");
567 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
568 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
569 "rx_ring_count", CTLFLAG_RD, &sc->sc_rx_ring_count,
571 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
572 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
573 "debug", CTLFLAG_RW, &sc->sc_debug,
574 0, "control debugging printfs");
576 error = mii_phy_probe(dev, &sc->sc_miibus, nfe_ifmedia_upd,
579 device_printf(dev, "MII without any phy\n");
584 ifp->if_mtu = ETHERMTU;
585 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
586 ifp->if_ioctl = nfe_ioctl;
587 ifp->if_start = nfe_start;
588 #ifdef DEVICE_POLLING
589 ifp->if_poll = nfe_poll;
591 ifp->if_watchdog = nfe_watchdog;
592 ifp->if_init = nfe_init;
593 ifq_set_maxlen(&ifp->if_snd, NFE_IFQ_MAXLEN);
594 ifq_set_ready(&ifp->if_snd);
596 ifp->if_capabilities = IFCAP_VLAN_MTU;
598 if (sc->sc_caps & NFE_HW_VLAN)
599 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
602 if (sc->sc_caps & NFE_HW_CSUM) {
603 ifp->if_capabilities |= IFCAP_HWCSUM;
604 ifp->if_hwassist = NFE_CSUM_FEATURES;
607 sc->sc_caps &= ~NFE_HW_CSUM;
609 ifp->if_capenable = ifp->if_capabilities;
611 callout_init(&sc->sc_tick_ch);
613 ether_ifattach(ifp, eaddr, NULL);
615 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, nfe_intr, sc,
616 &sc->sc_ih, ifp->if_serializer);
618 device_printf(dev, "could not setup intr\n");
623 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->sc_irq_res));
624 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
633 nfe_detach(device_t dev)
635 struct nfe_softc *sc = device_get_softc(dev);
637 if (device_is_attached(dev)) {
638 struct ifnet *ifp = &sc->arpcom.ac_if;
640 lwkt_serialize_enter(ifp->if_serializer);
642 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_ih);
643 lwkt_serialize_exit(ifp->if_serializer);
648 if (sc->sc_miibus != NULL)
649 device_delete_child(dev, sc->sc_miibus);
650 bus_generic_detach(dev);
652 if (sc->sc_sysctl_tree != NULL)
653 sysctl_ctx_free(&sc->sc_sysctl_ctx);
655 if (sc->sc_irq_res != NULL) {
656 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
660 if (sc->sc_mem_res != NULL) {
661 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
665 nfe_free_tx_ring(sc, &sc->txq);
666 nfe_free_rx_ring(sc, &sc->rxq);
672 nfe_shutdown(device_t dev)
674 struct nfe_softc *sc = device_get_softc(dev);
675 struct ifnet *ifp = &sc->arpcom.ac_if;
677 lwkt_serialize_enter(ifp->if_serializer);
679 lwkt_serialize_exit(ifp->if_serializer);
683 nfe_suspend(device_t dev)
685 struct nfe_softc *sc = device_get_softc(dev);
686 struct ifnet *ifp = &sc->arpcom.ac_if;
688 lwkt_serialize_enter(ifp->if_serializer);
690 lwkt_serialize_exit(ifp->if_serializer);
696 nfe_resume(device_t dev)
698 struct nfe_softc *sc = device_get_softc(dev);
699 struct ifnet *ifp = &sc->arpcom.ac_if;
701 lwkt_serialize_enter(ifp->if_serializer);
702 if (ifp->if_flags & IFF_UP)
704 lwkt_serialize_exit(ifp->if_serializer);
710 nfe_miibus_statchg(device_t dev)
712 struct nfe_softc *sc = device_get_softc(dev);
713 struct mii_data *mii = device_get_softc(sc->sc_miibus);
714 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET;
716 phy = NFE_READ(sc, NFE_PHY_IFACE);
717 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T);
719 seed = NFE_READ(sc, NFE_RNDSEED);
720 seed &= ~NFE_SEED_MASK;
722 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) {
723 phy |= NFE_PHY_HDX; /* half-duplex */
724 misc |= NFE_MISC1_HDX;
727 switch (IFM_SUBTYPE(mii->mii_media_active)) {
728 case IFM_1000_T: /* full-duplex only */
729 link |= NFE_MEDIA_1000T;
730 seed |= NFE_SEED_1000T;
731 phy |= NFE_PHY_1000T;
734 link |= NFE_MEDIA_100TX;
735 seed |= NFE_SEED_100TX;
736 phy |= NFE_PHY_100TX;
739 link |= NFE_MEDIA_10T;
740 seed |= NFE_SEED_10T;
744 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */
746 NFE_WRITE(sc, NFE_PHY_IFACE, phy);
747 NFE_WRITE(sc, NFE_MISC1, misc);
748 NFE_WRITE(sc, NFE_LINKSPEED, link);
752 nfe_miibus_readreg(device_t dev, int phy, int reg)
754 struct nfe_softc *sc = device_get_softc(dev);
758 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
760 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
761 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
765 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);
767 for (ntries = 0; ntries < 1000; ntries++) {
769 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
772 if (ntries == 1000) {
773 DPRINTFN(sc, 2, "timeout waiting for PHY %s\n", "");
777 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) {
778 DPRINTFN(sc, 2, "could not read PHY %s\n", "");
782 val = NFE_READ(sc, NFE_PHY_DATA);
783 if (val != 0xffffffff && val != 0)
784 sc->mii_phyaddr = phy;
786 DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val);
792 nfe_miibus_writereg(device_t dev, int phy, int reg, int val)
794 struct nfe_softc *sc = device_get_softc(dev);
798 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
800 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
801 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
805 NFE_WRITE(sc, NFE_PHY_DATA, val);
806 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;
807 NFE_WRITE(sc, NFE_PHY_CTL, ctl);
809 for (ntries = 0; ntries < 1000; ntries++) {
811 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
817 DPRINTFN(sc, 2, "could not write to PHY %s\n", "");
821 #ifdef DEVICE_POLLING
824 nfe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
826 struct nfe_softc *sc = ifp->if_softc;
828 ASSERT_SERIALIZED(ifp->if_serializer);
832 nfe_disable_intrs(sc);
835 case POLL_DEREGISTER:
836 nfe_enable_intrs(sc);
839 case POLL_AND_CHECK_STATUS:
842 if (ifp->if_flags & IFF_RUNNING) {
855 struct nfe_softc *sc = arg;
856 struct ifnet *ifp = &sc->arpcom.ac_if;
859 r = NFE_READ(sc, NFE_IRQ_STATUS);
861 return; /* not for us */
862 NFE_WRITE(sc, NFE_IRQ_STATUS, r);
864 DPRINTFN(sc, 5, "%s: interrupt register %x\n", __func__, r);
866 if (r & NFE_IRQ_LINK) {
867 NFE_READ(sc, NFE_PHY_STATUS);
868 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
869 DPRINTF(sc, "link state changed %s\n", "");
872 if (ifp->if_flags & IFF_RUNNING) {
879 ret |= nfe_txeof(sc);
881 if (sc->sc_flags & NFE_F_DYN_IM) {
882 if (ret && (sc->sc_flags & NFE_F_IRQ_TIMER) == 0) {
884 * Assume that using hardware timer could reduce
885 * the interrupt rate.
887 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_IMTIMER);
888 sc->sc_flags |= NFE_F_IRQ_TIMER;
889 } else if (!ret && (sc->sc_flags & NFE_F_IRQ_TIMER)) {
891 * Nothing needs to be processed, fall back to
892 * use TX/RX interrupts.
894 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_NOIMTIMER);
895 sc->sc_flags &= ~NFE_F_IRQ_TIMER;
902 nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
904 struct nfe_softc *sc = ifp->if_softc;
905 struct ifreq *ifr = (struct ifreq *)data;
906 struct mii_data *mii;
907 int error = 0, mask, jumbo_cap;
911 if ((sc->sc_caps & NFE_JUMBO_SUP) && sc->rxq.jbuf != NULL)
916 if ((jumbo_cap && ifr->ifr_mtu > NFE_JUMBO_MTU) ||
917 (!jumbo_cap && ifr->ifr_mtu > ETHERMTU)) {
919 } else if (ifp->if_mtu != ifr->ifr_mtu) {
920 ifp->if_mtu = ifr->ifr_mtu;
921 if (ifp->if_flags & IFF_RUNNING)
926 if (ifp->if_flags & IFF_UP) {
928 * If only the PROMISC or ALLMULTI flag changes, then
929 * don't do a full re-init of the chip, just update
932 if ((ifp->if_flags & IFF_RUNNING) &&
933 ((ifp->if_flags ^ sc->sc_if_flags) &
934 (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
937 if (!(ifp->if_flags & IFF_RUNNING))
941 if (ifp->if_flags & IFF_RUNNING)
944 sc->sc_if_flags = ifp->if_flags;
948 if (ifp->if_flags & IFF_RUNNING)
953 mii = device_get_softc(sc->sc_miibus);
954 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
957 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) & IFCAP_HWCSUM;
958 if (mask && (ifp->if_capabilities & IFCAP_HWCSUM)) {
959 ifp->if_capenable ^= mask;
960 if (IFCAP_TXCSUM & ifp->if_capenable)
961 ifp->if_hwassist = NFE_CSUM_FEATURES;
963 ifp->if_hwassist = 0;
965 if (ifp->if_flags & IFF_RUNNING)
970 error = ether_ioctl(ifp, cmd, data);
977 nfe_rxeof(struct nfe_softc *sc)
979 struct ifnet *ifp = &sc->arpcom.ac_if;
980 struct nfe_rx_ring *ring = &sc->rxq;
982 #ifdef ETHER_INPUT_CHAIN
983 struct mbuf_chain chain[MAXCPU];
987 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
989 #ifdef ETHER_INPUT_CHAIN
990 ether_input_chain_init(chain);
994 struct nfe_rx_data *data = &ring->data[ring->cur];
999 if (sc->sc_caps & NFE_40BIT_ADDR) {
1000 struct nfe_desc64 *desc64 = &ring->desc64[ring->cur];
1002 flags = le16toh(desc64->flags);
1003 len = le16toh(desc64->length) & 0x3fff;
1005 struct nfe_desc32 *desc32 = &ring->desc32[ring->cur];
1007 flags = le16toh(desc32->flags);
1008 len = le16toh(desc32->length) & 0x3fff;
1011 if (flags & NFE_RX_READY)
1016 if ((sc->sc_caps & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
1017 if (!(flags & NFE_RX_VALID_V1))
1020 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) {
1021 flags &= ~NFE_RX_ERROR;
1022 len--; /* fix buffer length */
1025 if (!(flags & NFE_RX_VALID_V2))
1028 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) {
1029 flags &= ~NFE_RX_ERROR;
1030 len--; /* fix buffer length */
1034 if (flags & NFE_RX_ERROR) {
1041 if (sc->sc_flags & NFE_F_USE_JUMBO)
1042 error = nfe_newbuf_jumbo(sc, ring, ring->cur, 0);
1044 error = nfe_newbuf_std(sc, ring, ring->cur, 0);
1051 m->m_pkthdr.len = m->m_len = len;
1052 m->m_pkthdr.rcvif = ifp;
1054 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
1055 (flags & NFE_RX_CSUMOK)) {
1056 if (flags & NFE_RX_IP_CSUMOK_V2) {
1057 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1062 (NFE_RX_UDP_CSUMOK_V2 | NFE_RX_TCP_CSUMOK_V2)) {
1063 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1065 CSUM_FRAG_NOT_CHECKED;
1066 m->m_pkthdr.csum_data = 0xffff;
1071 #ifdef ETHER_INPUT_CHAIN
1073 ether_input_chain2(ifp, m, chain);
1075 ether_input_chain(ifp, m, chain);
1078 ifp->if_input(ifp, m);
1081 nfe_set_ready_rxdesc(sc, ring, ring->cur);
1082 sc->rxq.cur = (sc->rxq.cur + 1) % sc->sc_rx_ring_count;
1086 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1087 #ifdef ETHER_INPUT_CHAIN
1088 ether_input_dispatch(chain);
1095 nfe_txeof(struct nfe_softc *sc)
1097 struct ifnet *ifp = &sc->arpcom.ac_if;
1098 struct nfe_tx_ring *ring = &sc->txq;
1099 struct nfe_tx_data *data = NULL;
1101 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
1102 while (ring->next != ring->cur) {
1105 if (sc->sc_caps & NFE_40BIT_ADDR)
1106 flags = le16toh(ring->desc64[ring->next].flags);
1108 flags = le16toh(ring->desc32[ring->next].flags);
1110 if (flags & NFE_TX_VALID)
1113 data = &ring->data[ring->next];
1115 if ((sc->sc_caps & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
1116 if (!(flags & NFE_TX_LASTFRAG_V1) && data->m == NULL)
1119 if ((flags & NFE_TX_ERROR_V1) != 0) {
1120 if_printf(ifp, "tx v1 error 0x%4b\n", flags,
1127 if (!(flags & NFE_TX_LASTFRAG_V2) && data->m == NULL)
1130 if ((flags & NFE_TX_ERROR_V2) != 0) {
1131 if_printf(ifp, "tx v2 error 0x%4b\n", flags,
1139 if (data->m == NULL) { /* should not get there */
1141 "last fragment bit w/o associated mbuf!\n");
1145 /* last fragment of the mbuf chain transmitted */
1146 bus_dmamap_sync(ring->data_tag, data->map,
1147 BUS_DMASYNC_POSTWRITE);
1148 bus_dmamap_unload(ring->data_tag, data->map);
1155 KKASSERT(ring->queued >= 0);
1156 ring->next = (ring->next + 1) % NFE_TX_RING_COUNT;
1159 if (data != NULL) { /* at least one slot freed */
1160 ifp->if_flags &= ~IFF_OACTIVE;
1168 nfe_encap(struct nfe_softc *sc, struct nfe_tx_ring *ring, struct mbuf *m0)
1170 struct nfe_dma_ctx ctx;
1171 bus_dma_segment_t segs[NFE_MAX_SCATTER];
1172 struct nfe_tx_data *data, *data_map;
1174 struct nfe_desc64 *desc64 = NULL;
1175 struct nfe_desc32 *desc32 = NULL;
1180 data = &ring->data[ring->cur];
1182 data_map = data; /* Remember who owns the DMA map */
1184 ctx.nsegs = NFE_MAX_SCATTER;
1186 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
1187 nfe_buf_dma_addr, &ctx, BUS_DMA_NOWAIT);
1188 if (error && error != EFBIG) {
1189 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
1193 if (error) { /* error == EFBIG */
1196 m_new = m_defrag(m0, MB_DONTWAIT);
1197 if (m_new == NULL) {
1198 if_printf(&sc->arpcom.ac_if,
1199 "could not defrag TX mbuf\n");
1206 ctx.nsegs = NFE_MAX_SCATTER;
1208 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
1209 nfe_buf_dma_addr, &ctx,
1212 if_printf(&sc->arpcom.ac_if,
1213 "could not map defraged TX mbuf\n");
1220 if (ring->queued + ctx.nsegs >= NFE_TX_RING_COUNT - 1) {
1221 bus_dmamap_unload(ring->data_tag, map);
1226 /* setup h/w VLAN tagging */
1227 if (m0->m_flags & M_VLANTAG)
1228 vtag = m0->m_pkthdr.ether_vlantag;
1230 if (sc->arpcom.ac_if.if_capenable & IFCAP_TXCSUM) {
1231 if (m0->m_pkthdr.csum_flags & CSUM_IP)
1232 flags |= NFE_TX_IP_CSUM;
1233 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
1234 flags |= NFE_TX_TCP_CSUM;
1238 * XXX urm. somebody is unaware of how hardware works. You
1239 * absolutely CANNOT set NFE_TX_VALID on the next descriptor in
1240 * the ring until the entire chain is actually *VALID*. Otherwise
1241 * the hardware may encounter a partially initialized chain that
1242 * is marked as being ready to go when it in fact is not ready to
1246 for (i = 0; i < ctx.nsegs; i++) {
1247 j = (ring->cur + i) % NFE_TX_RING_COUNT;
1248 data = &ring->data[j];
1250 if (sc->sc_caps & NFE_40BIT_ADDR) {
1251 desc64 = &ring->desc64[j];
1252 #if defined(__LP64__)
1253 desc64->physaddr[0] =
1254 htole32(segs[i].ds_addr >> 32);
1256 desc64->physaddr[1] =
1257 htole32(segs[i].ds_addr & 0xffffffff);
1258 desc64->length = htole16(segs[i].ds_len - 1);
1259 desc64->vtag = htole32(vtag);
1260 desc64->flags = htole16(flags);
1262 desc32 = &ring->desc32[j];
1263 desc32->physaddr = htole32(segs[i].ds_addr);
1264 desc32->length = htole16(segs[i].ds_len - 1);
1265 desc32->flags = htole16(flags);
1268 /* csum flags and vtag belong to the first fragment only */
1269 flags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_CSUM);
1273 KKASSERT(ring->queued <= NFE_TX_RING_COUNT);
1276 /* the whole mbuf chain has been DMA mapped, fix last descriptor */
1277 if (sc->sc_caps & NFE_40BIT_ADDR) {
1278 desc64->flags |= htole16(NFE_TX_LASTFRAG_V2);
1280 if (sc->sc_caps & NFE_JUMBO_SUP)
1281 flags = NFE_TX_LASTFRAG_V2;
1283 flags = NFE_TX_LASTFRAG_V1;
1284 desc32->flags |= htole16(flags);
1288 * Set NFE_TX_VALID backwards so the hardware doesn't see the
1289 * whole mess until the first descriptor in the map is flagged.
1291 for (i = ctx.nsegs - 1; i >= 0; --i) {
1292 j = (ring->cur + i) % NFE_TX_RING_COUNT;
1293 if (sc->sc_caps & NFE_40BIT_ADDR) {
1294 desc64 = &ring->desc64[j];
1295 desc64->flags |= htole16(NFE_TX_VALID);
1297 desc32 = &ring->desc32[j];
1298 desc32->flags |= htole16(NFE_TX_VALID);
1301 ring->cur = (ring->cur + ctx.nsegs) % NFE_TX_RING_COUNT;
1303 /* Exchange DMA map */
1304 data_map->map = data->map;
1308 bus_dmamap_sync(ring->data_tag, map, BUS_DMASYNC_PREWRITE);
1316 nfe_start(struct ifnet *ifp)
1318 struct nfe_softc *sc = ifp->if_softc;
1319 struct nfe_tx_ring *ring = &sc->txq;
1323 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
1327 m0 = ifq_dequeue(&ifp->if_snd, NULL);
1331 ETHER_BPF_MTAP(ifp, m0);
1333 if (nfe_encap(sc, ring, m0) != 0) {
1334 ifp->if_flags |= IFF_OACTIVE;
1341 * `m0' may be freed in nfe_encap(), so
1342 * it should not be touched any more.
1345 if (count == 0) /* nothing sent */
1348 /* Sync TX descriptor ring */
1349 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1352 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl);
1355 * Set a timeout in case the chip goes out to lunch.
1361 nfe_watchdog(struct ifnet *ifp)
1363 struct nfe_softc *sc = ifp->if_softc;
1365 if (ifp->if_flags & IFF_RUNNING) {
1366 if_printf(ifp, "watchdog timeout - lost interrupt recovered\n");
1371 if_printf(ifp, "watchdog timeout\n");
1373 nfe_init(ifp->if_softc);
1381 struct nfe_softc *sc = xsc;
1382 struct ifnet *ifp = &sc->arpcom.ac_if;
1388 if ((sc->sc_caps & NFE_NO_PWRCTL) == 0)
1393 * Switching between jumbo frames and normal frames should
1394 * be done _after_ nfe_stop() but _before_ nfe_init_rx_ring().
1396 if (ifp->if_mtu > ETHERMTU) {
1397 sc->sc_flags |= NFE_F_USE_JUMBO;
1398 sc->rxq.bufsz = NFE_JBYTES;
1400 if_printf(ifp, "use jumbo frames\n");
1402 sc->sc_flags &= ~NFE_F_USE_JUMBO;
1403 sc->rxq.bufsz = MCLBYTES;
1405 if_printf(ifp, "use non-jumbo frames\n");
1408 error = nfe_init_tx_ring(sc, &sc->txq);
1414 error = nfe_init_rx_ring(sc, &sc->rxq);
1420 NFE_WRITE(sc, NFE_TX_POLL, 0);
1421 NFE_WRITE(sc, NFE_STATUS, 0);
1423 sc->rxtxctl = NFE_RXTX_BIT2 | sc->rxtxctl_desc;
1425 if (ifp->if_capenable & IFCAP_RXCSUM)
1426 sc->rxtxctl |= NFE_RXTX_RXCSUM;
1429 * Although the adapter is capable of stripping VLAN tags from received
1430 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on
1431 * purpose. This will be done in software by our network stack.
1433 if (sc->sc_caps & NFE_HW_VLAN)
1434 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT;
1436 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl);
1438 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1440 if (sc->sc_caps & NFE_HW_VLAN)
1441 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE);
1443 NFE_WRITE(sc, NFE_SETUP_R6, 0);
1445 /* set MAC address */
1446 nfe_set_macaddr(sc, sc->arpcom.ac_enaddr);
1448 /* tell MAC where rings are in memory */
1450 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32);
1452 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff);
1454 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32);
1456 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff);
1458 NFE_WRITE(sc, NFE_RING_SIZE,
1459 (sc->sc_rx_ring_count - 1) << 16 |
1460 (NFE_TX_RING_COUNT - 1));
1462 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz);
1464 /* force MAC to wakeup */
1465 tmp = NFE_READ(sc, NFE_PWR_STATE);
1466 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP);
1468 tmp = NFE_READ(sc, NFE_PWR_STATE);
1469 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID);
1471 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC);
1472 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC);
1473 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC);
1475 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */
1476 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC);
1478 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC);
1480 sc->rxtxctl &= ~NFE_RXTX_BIT2;
1481 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1483 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl);
1488 nfe_ifmedia_upd(ifp);
1491 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START);
1494 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START);
1496 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1498 #ifdef DEVICE_POLLING
1499 if ((ifp->if_flags & IFF_POLLING))
1500 nfe_disable_intrs(sc);
1503 nfe_enable_intrs(sc);
1505 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
1507 ifp->if_flags |= IFF_RUNNING;
1508 ifp->if_flags &= ~IFF_OACTIVE;
1511 * If we had stuff in the tx ring before its all cleaned out now
1512 * so we are not going to get an interrupt, jump-start any pending
1519 nfe_stop(struct nfe_softc *sc)
1521 struct ifnet *ifp = &sc->arpcom.ac_if;
1522 uint32_t rxtxctl = sc->rxtxctl_desc | NFE_RXTX_BIT2;
1525 callout_stop(&sc->sc_tick_ch);
1528 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1529 sc->sc_flags &= ~NFE_F_IRQ_TIMER;
1531 #define WAITMAX 50000
1536 NFE_WRITE(sc, NFE_TX_CTL, 0);
1537 for (i = 0; i < WAITMAX; ++i) {
1539 if ((NFE_READ(sc, NFE_TX_STATUS) & NFE_TX_STATUS_BUSY) == 0)
1543 if_printf(ifp, "can't stop TX\n");
1549 NFE_WRITE(sc, NFE_RX_CTL, 0);
1550 for (i = 0; i < WAITMAX; ++i) {
1552 if ((NFE_READ(sc, NFE_RX_STATUS) & NFE_RX_STATUS_BUSY) == 0)
1556 if_printf(ifp, "can't stop RX\n");
1561 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | rxtxctl);
1563 NFE_WRITE(sc, NFE_RXTX_CTL, rxtxctl);
1565 /* Disable interrupts */
1566 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
1568 /* Reset Tx and Rx rings */
1569 nfe_reset_tx_ring(sc, &sc->txq);
1570 nfe_reset_rx_ring(sc, &sc->rxq);
1574 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1576 int i, j, error, descsize;
1579 if (sc->sc_caps & NFE_40BIT_ADDR) {
1580 desc = (void **)&ring->desc64;
1581 descsize = sizeof(struct nfe_desc64);
1583 desc = (void **)&ring->desc32;
1584 descsize = sizeof(struct nfe_desc32);
1587 ring->bufsz = MCLBYTES;
1588 ring->cur = ring->next = 0;
1590 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1591 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1593 sc->sc_rx_ring_count * descsize, 1,
1594 BUS_SPACE_MAXSIZE_32BIT,
1597 if_printf(&sc->arpcom.ac_if,
1598 "could not create desc RX DMA tag\n");
1602 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1605 if_printf(&sc->arpcom.ac_if,
1606 "could not allocate RX desc DMA memory\n");
1607 bus_dma_tag_destroy(ring->tag);
1612 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1613 sc->sc_rx_ring_count * descsize,
1614 nfe_ring_dma_addr, &ring->physaddr,
1617 if_printf(&sc->arpcom.ac_if,
1618 "could not load RX desc DMA map\n");
1619 bus_dmamem_free(ring->tag, *desc, ring->map);
1620 bus_dma_tag_destroy(ring->tag);
1625 if (sc->sc_caps & NFE_JUMBO_SUP) {
1627 kmalloc(sizeof(struct nfe_jbuf) * NFE_JPOOL_COUNT(sc),
1628 M_DEVBUF, M_WAITOK | M_ZERO);
1630 error = nfe_jpool_alloc(sc, ring);
1632 if_printf(&sc->arpcom.ac_if,
1633 "could not allocate jumbo frames\n");
1634 kfree(ring->jbuf, M_DEVBUF);
1636 /* Allow jumbo frame allocation to fail */
1640 ring->data = kmalloc(sizeof(struct nfe_rx_data) * sc->sc_rx_ring_count,
1641 M_DEVBUF, M_WAITOK | M_ZERO);
1643 error = bus_dma_tag_create(NULL, 1, 0,
1644 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1646 MCLBYTES, 1, BUS_SPACE_MAXSIZE_32BIT,
1647 BUS_DMA_ALLOCNOW, &ring->data_tag);
1649 if_printf(&sc->arpcom.ac_if,
1650 "could not create RX mbuf DMA tag\n");
1654 /* Create a spare RX mbuf DMA map */
1655 error = bus_dmamap_create(ring->data_tag, 0, &ring->data_tmpmap);
1657 if_printf(&sc->arpcom.ac_if,
1658 "could not create spare RX mbuf DMA map\n");
1659 bus_dma_tag_destroy(ring->data_tag);
1660 ring->data_tag = NULL;
1664 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1665 error = bus_dmamap_create(ring->data_tag, 0,
1666 &ring->data[i].map);
1668 if_printf(&sc->arpcom.ac_if,
1669 "could not create %dth RX mbuf DMA mapn", i);
1675 for (j = 0; j < i; ++j)
1676 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1677 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1678 bus_dma_tag_destroy(ring->data_tag);
1679 ring->data_tag = NULL;
1684 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1688 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1689 struct nfe_rx_data *data = &ring->data[i];
1691 if (data->m != NULL) {
1692 if ((sc->sc_flags & NFE_F_USE_JUMBO) == 0)
1693 bus_dmamap_unload(ring->data_tag, data->map);
1698 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1700 ring->cur = ring->next = 0;
1704 nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1708 for (i = 0; i < sc->sc_rx_ring_count; ++i) {
1711 /* XXX should use a function pointer */
1712 if (sc->sc_flags & NFE_F_USE_JUMBO)
1713 error = nfe_newbuf_jumbo(sc, ring, i, 1);
1715 error = nfe_newbuf_std(sc, ring, i, 1);
1717 if_printf(&sc->arpcom.ac_if,
1718 "could not allocate RX buffer\n");
1722 nfe_set_ready_rxdesc(sc, ring, i);
1724 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1730 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1732 if (ring->data_tag != NULL) {
1733 struct nfe_rx_data *data;
1736 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1737 data = &ring->data[i];
1739 if (data->m != NULL) {
1740 bus_dmamap_unload(ring->data_tag, data->map);
1743 bus_dmamap_destroy(ring->data_tag, data->map);
1745 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1746 bus_dma_tag_destroy(ring->data_tag);
1749 nfe_jpool_free(sc, ring);
1751 if (ring->jbuf != NULL)
1752 kfree(ring->jbuf, M_DEVBUF);
1753 if (ring->data != NULL)
1754 kfree(ring->data, M_DEVBUF);
1756 if (ring->tag != NULL) {
1759 if (sc->sc_caps & NFE_40BIT_ADDR)
1760 desc = ring->desc64;
1762 desc = ring->desc32;
1764 bus_dmamap_unload(ring->tag, ring->map);
1765 bus_dmamem_free(ring->tag, desc, ring->map);
1766 bus_dma_tag_destroy(ring->tag);
1770 static struct nfe_jbuf *
1771 nfe_jalloc(struct nfe_softc *sc)
1773 struct ifnet *ifp = &sc->arpcom.ac_if;
1774 struct nfe_jbuf *jbuf;
1776 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1778 jbuf = SLIST_FIRST(&sc->rxq.jfreelist);
1780 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext);
1783 if_printf(ifp, "no free jumbo buffer\n");
1786 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1792 nfe_jfree(void *arg)
1794 struct nfe_jbuf *jbuf = arg;
1795 struct nfe_softc *sc = jbuf->sc;
1796 struct nfe_rx_ring *ring = jbuf->ring;
1798 if (&ring->jbuf[jbuf->slot] != jbuf)
1799 panic("%s: free wrong jumbo buffer\n", __func__);
1800 else if (jbuf->inuse == 0)
1801 panic("%s: jumbo buffer already freed\n", __func__);
1803 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1804 atomic_subtract_int(&jbuf->inuse, 1);
1805 if (jbuf->inuse == 0)
1806 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1807 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1813 struct nfe_jbuf *jbuf = arg;
1814 struct nfe_rx_ring *ring = jbuf->ring;
1816 if (&ring->jbuf[jbuf->slot] != jbuf)
1817 panic("%s: ref wrong jumbo buffer\n", __func__);
1818 else if (jbuf->inuse == 0)
1819 panic("%s: jumbo buffer already freed\n", __func__);
1821 atomic_add_int(&jbuf->inuse, 1);
1825 nfe_jpool_alloc(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1827 struct nfe_jbuf *jbuf;
1828 bus_addr_t physaddr;
1833 * Allocate a big chunk of DMA'able memory.
1835 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1836 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1838 NFE_JPOOL_SIZE(sc), 1,
1839 BUS_SPACE_MAXSIZE_32BIT,
1842 if_printf(&sc->arpcom.ac_if,
1843 "could not create jumbo DMA tag\n");
1847 error = bus_dmamem_alloc(ring->jtag, (void **)&ring->jpool,
1848 BUS_DMA_WAITOK, &ring->jmap);
1850 if_printf(&sc->arpcom.ac_if,
1851 "could not allocate jumbo DMA memory\n");
1852 bus_dma_tag_destroy(ring->jtag);
1857 error = bus_dmamap_load(ring->jtag, ring->jmap, ring->jpool,
1859 nfe_ring_dma_addr, &physaddr, BUS_DMA_WAITOK);
1861 if_printf(&sc->arpcom.ac_if,
1862 "could not load jumbo DMA map\n");
1863 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1864 bus_dma_tag_destroy(ring->jtag);
1869 /* ..and split it into 9KB chunks */
1870 SLIST_INIT(&ring->jfreelist);
1873 for (i = 0; i < NFE_JPOOL_COUNT(sc); i++) {
1874 jbuf = &ring->jbuf[i];
1881 jbuf->physaddr = physaddr;
1883 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1886 physaddr += NFE_JBYTES;
1893 nfe_jpool_free(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1895 if (ring->jtag != NULL) {
1896 bus_dmamap_unload(ring->jtag, ring->jmap);
1897 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1898 bus_dma_tag_destroy(ring->jtag);
1903 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1905 int i, j, error, descsize;
1908 if (sc->sc_caps & NFE_40BIT_ADDR) {
1909 desc = (void **)&ring->desc64;
1910 descsize = sizeof(struct nfe_desc64);
1912 desc = (void **)&ring->desc32;
1913 descsize = sizeof(struct nfe_desc32);
1917 ring->cur = ring->next = 0;
1919 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1920 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1922 NFE_TX_RING_COUNT * descsize, 1,
1923 BUS_SPACE_MAXSIZE_32BIT,
1926 if_printf(&sc->arpcom.ac_if,
1927 "could not create TX desc DMA map\n");
1931 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1934 if_printf(&sc->arpcom.ac_if,
1935 "could not allocate TX desc DMA memory\n");
1936 bus_dma_tag_destroy(ring->tag);
1941 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1942 NFE_TX_RING_COUNT * descsize,
1943 nfe_ring_dma_addr, &ring->physaddr,
1946 if_printf(&sc->arpcom.ac_if,
1947 "could not load TX desc DMA map\n");
1948 bus_dmamem_free(ring->tag, *desc, ring->map);
1949 bus_dma_tag_destroy(ring->tag);
1954 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1955 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1957 NFE_JBYTES, NFE_MAX_SCATTER,
1958 BUS_SPACE_MAXSIZE_32BIT,
1959 BUS_DMA_ALLOCNOW, &ring->data_tag);
1961 if_printf(&sc->arpcom.ac_if,
1962 "could not create TX buf DMA tag\n");
1966 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1967 error = bus_dmamap_create(ring->data_tag, 0,
1968 &ring->data[i].map);
1970 if_printf(&sc->arpcom.ac_if,
1971 "could not create %dth TX buf DMA map\n", i);
1978 for (j = 0; j < i; ++j)
1979 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1980 bus_dma_tag_destroy(ring->data_tag);
1981 ring->data_tag = NULL;
1986 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1990 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1991 struct nfe_tx_data *data = &ring->data[i];
1993 if (sc->sc_caps & NFE_40BIT_ADDR)
1994 ring->desc64[i].flags = 0;
1996 ring->desc32[i].flags = 0;
1998 if (data->m != NULL) {
1999 bus_dmamap_sync(ring->data_tag, data->map,
2000 BUS_DMASYNC_POSTWRITE);
2001 bus_dmamap_unload(ring->data_tag, data->map);
2006 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
2009 ring->cur = ring->next = 0;
2013 nfe_init_tx_ring(struct nfe_softc *sc __unused,
2014 struct nfe_tx_ring *ring __unused)
2020 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
2022 if (ring->data_tag != NULL) {
2023 struct nfe_tx_data *data;
2026 for (i = 0; i < NFE_TX_RING_COUNT; ++i) {
2027 data = &ring->data[i];
2029 if (data->m != NULL) {
2030 bus_dmamap_unload(ring->data_tag, data->map);
2033 bus_dmamap_destroy(ring->data_tag, data->map);
2036 bus_dma_tag_destroy(ring->data_tag);
2039 if (ring->tag != NULL) {
2042 if (sc->sc_caps & NFE_40BIT_ADDR)
2043 desc = ring->desc64;
2045 desc = ring->desc32;
2047 bus_dmamap_unload(ring->tag, ring->map);
2048 bus_dmamem_free(ring->tag, desc, ring->map);
2049 bus_dma_tag_destroy(ring->tag);
2054 nfe_ifmedia_upd(struct ifnet *ifp)
2056 struct nfe_softc *sc = ifp->if_softc;
2057 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2059 if (mii->mii_instance != 0) {
2060 struct mii_softc *miisc;
2062 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2063 mii_phy_reset(miisc);
2071 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2073 struct nfe_softc *sc = ifp->if_softc;
2074 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2077 ifmr->ifm_status = mii->mii_media_status;
2078 ifmr->ifm_active = mii->mii_media_active;
2082 nfe_setmulti(struct nfe_softc *sc)
2084 struct ifnet *ifp = &sc->arpcom.ac_if;
2085 struct ifmultiaddr *ifma;
2086 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN];
2087 uint32_t filter = NFE_RXFILTER_MAGIC;
2090 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
2091 bzero(addr, ETHER_ADDR_LEN);
2092 bzero(mask, ETHER_ADDR_LEN);
2096 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN);
2097 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN);
2099 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2102 if (ifma->ifma_addr->sa_family != AF_LINK)
2105 maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
2106 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2107 addr[i] &= maddr[i];
2108 mask[i] &= ~maddr[i];
2112 for (i = 0; i < ETHER_ADDR_LEN; i++)
2116 addr[0] |= 0x01; /* make sure multicast bit is set */
2118 NFE_WRITE(sc, NFE_MULTIADDR_HI,
2119 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2120 NFE_WRITE(sc, NFE_MULTIADDR_LO,
2121 addr[5] << 8 | addr[4]);
2122 NFE_WRITE(sc, NFE_MULTIMASK_HI,
2123 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]);
2124 NFE_WRITE(sc, NFE_MULTIMASK_LO,
2125 mask[5] << 8 | mask[4]);
2127 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M;
2128 NFE_WRITE(sc, NFE_RXFILTER, filter);
2132 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr)
2136 lo = NFE_READ(sc, NFE_MACADDR_LO);
2137 hi = NFE_READ(sc, NFE_MACADDR_HI);
2138 if (sc->sc_caps & NFE_FIX_EADDR) {
2139 addr[0] = (lo >> 8) & 0xff;
2140 addr[1] = (lo & 0xff);
2142 addr[2] = (hi >> 24) & 0xff;
2143 addr[3] = (hi >> 16) & 0xff;
2144 addr[4] = (hi >> 8) & 0xff;
2145 addr[5] = (hi & 0xff);
2147 addr[0] = (hi & 0xff);
2148 addr[1] = (hi >> 8) & 0xff;
2149 addr[2] = (hi >> 16) & 0xff;
2150 addr[3] = (hi >> 24) & 0xff;
2152 addr[4] = (lo & 0xff);
2153 addr[5] = (lo >> 8) & 0xff;
2158 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr)
2160 NFE_WRITE(sc, NFE_MACADDR_LO,
2161 addr[5] << 8 | addr[4]);
2162 NFE_WRITE(sc, NFE_MACADDR_HI,
2163 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2169 struct nfe_softc *sc = arg;
2170 struct ifnet *ifp = &sc->arpcom.ac_if;
2171 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2173 lwkt_serialize_enter(ifp->if_serializer);
2176 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
2178 lwkt_serialize_exit(ifp->if_serializer);
2182 nfe_ring_dma_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2187 KASSERT(nseg == 1, ("too many segments, should be 1\n"));
2189 *((uint32_t *)arg) = seg->ds_addr;
2193 nfe_buf_dma_addr(void *arg, bus_dma_segment_t *segs, int nsegs,
2194 bus_size_t mapsz __unused, int error)
2196 struct nfe_dma_ctx *ctx = arg;
2202 KASSERT(nsegs <= ctx->nsegs,
2203 ("too many segments(%d), should be <= %d\n",
2204 nsegs, ctx->nsegs));
2207 for (i = 0; i < nsegs; ++i)
2208 ctx->segs[i] = segs[i];
2212 nfe_newbuf_std(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2215 struct nfe_rx_data *data = &ring->data[idx];
2216 struct nfe_dma_ctx ctx;
2217 bus_dma_segment_t seg;
2222 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2225 m->m_len = m->m_pkthdr.len = MCLBYTES;
2229 error = bus_dmamap_load_mbuf(ring->data_tag, ring->data_tmpmap,
2230 m, nfe_buf_dma_addr, &ctx,
2231 wait ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
2234 if_printf(&sc->arpcom.ac_if, "could map RX mbuf %d\n", error);
2238 /* Unload originally mapped mbuf */
2239 bus_dmamap_unload(ring->data_tag, data->map);
2241 /* Swap this DMA map with tmp DMA map */
2243 data->map = ring->data_tmpmap;
2244 ring->data_tmpmap = map;
2246 /* Caller is assumed to have collected the old mbuf */
2249 nfe_set_paddr_rxdesc(sc, ring, idx, seg.ds_addr);
2251 bus_dmamap_sync(ring->data_tag, data->map, BUS_DMASYNC_PREREAD);
2256 nfe_newbuf_jumbo(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2259 struct nfe_rx_data *data = &ring->data[idx];
2260 struct nfe_jbuf *jbuf;
2263 MGETHDR(m, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA);
2267 jbuf = nfe_jalloc(sc);
2270 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
2271 "-- packet dropped!\n");
2275 m->m_ext.ext_arg = jbuf;
2276 m->m_ext.ext_buf = jbuf->buf;
2277 m->m_ext.ext_free = nfe_jfree;
2278 m->m_ext.ext_ref = nfe_jref;
2279 m->m_ext.ext_size = NFE_JBYTES;
2281 m->m_data = m->m_ext.ext_buf;
2282 m->m_flags |= M_EXT;
2283 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
2285 /* Caller is assumed to have collected the old mbuf */
2288 nfe_set_paddr_rxdesc(sc, ring, idx, jbuf->physaddr);
2290 bus_dmamap_sync(ring->jtag, ring->jmap, BUS_DMASYNC_PREREAD);
2295 nfe_set_paddr_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2296 bus_addr_t physaddr)
2298 if (sc->sc_caps & NFE_40BIT_ADDR) {
2299 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2301 #if defined(__LP64__)
2302 desc64->physaddr[0] = htole32(physaddr >> 32);
2304 desc64->physaddr[1] = htole32(physaddr & 0xffffffff);
2306 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2308 desc32->physaddr = htole32(physaddr);
2313 nfe_set_ready_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx)
2315 if (sc->sc_caps & NFE_40BIT_ADDR) {
2316 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2318 desc64->length = htole16(ring->bufsz);
2319 desc64->flags = htole16(NFE_RX_READY);
2321 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2323 desc32->length = htole16(ring->bufsz);
2324 desc32->flags = htole16(NFE_RX_READY);
2329 nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS)
2331 struct nfe_softc *sc = arg1;
2332 struct ifnet *ifp = &sc->arpcom.ac_if;
2336 lwkt_serialize_enter(ifp->if_serializer);
2338 flags = sc->sc_flags & ~NFE_F_DYN_IM;
2340 if (sc->sc_flags & NFE_F_DYN_IM)
2343 error = sysctl_handle_int(oidp, &v, 0, req);
2344 if (error || req->newptr == NULL)
2348 flags |= NFE_F_DYN_IM;
2352 if (v != sc->sc_imtime || (flags ^ sc->sc_flags)) {
2353 int old_imtime = sc->sc_imtime;
2354 uint32_t old_flags = sc->sc_flags;
2357 sc->sc_flags = flags;
2358 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
2360 if ((ifp->if_flags & (IFF_POLLING | IFF_RUNNING))
2362 if (old_imtime * sc->sc_imtime == 0 ||
2363 (old_flags ^ sc->sc_flags)) {
2366 NFE_WRITE(sc, NFE_IMTIMER,
2367 NFE_IMTIME(sc->sc_imtime));
2372 lwkt_serialize_exit(ifp->if_serializer);
2377 nfe_powerup(device_t dev)
2379 struct nfe_softc *sc = device_get_softc(dev);
2384 * Bring MAC and PHY out of low power state
2387 pwr_state = NFE_READ(sc, NFE_PWR_STATE2) & ~NFE_PWRUP_MASK;
2389 did = pci_get_device(dev);
2390 if ((did == PCI_PRODUCT_NVIDIA_MCP51_LAN1 ||
2391 did == PCI_PRODUCT_NVIDIA_MCP51_LAN2) &&
2392 pci_get_revid(dev) >= 0xa3)
2393 pwr_state |= NFE_PWRUP_REV_A3;
2395 NFE_WRITE(sc, NFE_PWR_STATE2, pwr_state);
2399 nfe_mac_reset(struct nfe_softc *sc)
2401 uint32_t rxtxctl = sc->rxtxctl_desc | NFE_RXTX_BIT2;
2402 uint32_t macaddr_hi, macaddr_lo, tx_poll;
2404 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | rxtxctl);
2406 /* Save several registers for later restoration */
2407 macaddr_hi = NFE_READ(sc, NFE_MACADDR_HI);
2408 macaddr_lo = NFE_READ(sc, NFE_MACADDR_LO);
2409 tx_poll = NFE_READ(sc, NFE_TX_POLL);
2411 NFE_WRITE(sc, NFE_MAC_RESET, NFE_RESET_ASSERT);
2414 NFE_WRITE(sc, NFE_MAC_RESET, 0);
2417 /* Restore saved registers */
2418 NFE_WRITE(sc, NFE_MACADDR_HI, macaddr_hi);
2419 NFE_WRITE(sc, NFE_MACADDR_LO, macaddr_lo);
2420 NFE_WRITE(sc, NFE_TX_POLL, tx_poll);
2422 NFE_WRITE(sc, NFE_RXTX_CTL, rxtxctl);
2426 nfe_enable_intrs(struct nfe_softc *sc)
2429 * NFE_IMTIMER generates a periodic interrupt via NFE_IRQ_TIMER.
2430 * It is unclear how wide the timer is. Base programming does
2431 * not seem to effect NFE_IRQ_TX_DONE or NFE_IRQ_RX_DONE so
2432 * we don't get any interrupt moderation. TX moderation is
2433 * possible by using the timer interrupt instead of TX_DONE.
2435 * It is unclear whether there are other bits that can be
2436 * set to make the NFE device actually do interrupt moderation
2439 * For now set a 128uS interval as a placemark, but don't use
2442 if (sc->sc_imtime == 0)
2443 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME_DEFAULT);
2445 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME(sc->sc_imtime));
2447 /* Enable interrupts */
2448 NFE_WRITE(sc, NFE_IRQ_MASK, sc->sc_irq_enable);
2450 if (sc->sc_irq_enable & NFE_IRQ_TIMER)
2451 sc->sc_flags |= NFE_F_IRQ_TIMER;
2453 sc->sc_flags &= ~NFE_F_IRQ_TIMER;
2457 nfe_disable_intrs(struct nfe_softc *sc)
2459 /* Disable interrupts */
2460 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
2461 sc->sc_flags &= ~NFE_F_IRQ_TIMER;