2 * Copyright (c) 1999 Cameron Grant <gandalf@vilnya.demon.co.uk>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
26 * $FreeBSD: src/sys/dev/sound/pci/t4dwave.c,v 1.9.2.11 2002/10/22 08:27:13 cognet Exp $
27 * $DragonFly: src/sys/dev/sound/pci/t4dwave.c,v 1.3 2003/08/07 21:17:13 dillon Exp $
30 #include <dev/sound/pcm/sound.h>
31 #include <dev/sound/pcm/ac97.h>
32 #include <dev/sound/pci/t4dwave.h>
34 #include <bus/pci/pcireg.h>
35 #include <bus/pci/pcivar.h>
37 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/t4dwave.c,v 1.3 2003/08/07 21:17:13 dillon Exp $");
38 /* -------------------------------------------------------------------- */
40 #define TDX_PCI_ID 0x20001023
41 #define TNX_PCI_ID 0x20011023
42 #define ALI_PCI_ID 0x545110b9
43 #define SPA_PCI_ID 0x70181039
45 #define TR_DEFAULT_BUFSZ 0x1000
46 #define TR_TIMEOUT_CDC 0xffff
47 #define TR_MAXPLAYCH 4
51 /* channel registers */
53 u_int32_t cso, alpha, fms, fmc, ec;
57 u_int32_t gvsel, pan, vol, ctrl;
58 u_int32_t active:1, was_active:1;
60 struct snd_dbuf *buffer;
61 struct pcm_channel *channel;
62 struct tr_info *parent;
67 u_int32_t active:1, was_active:1;
68 struct snd_dbuf *buffer;
69 struct pcm_channel *channel;
70 struct tr_info *parent;
73 /* device private data */
79 bus_space_handle_t sh;
80 bus_dma_tag_t parent_dmat;
82 struct resource *reg, *irq;
83 int regtype, regid, irqid;
91 struct tr_chinfo chinfo[TR_MAXPLAYCH];
92 struct tr_rchinfo recchinfo;
95 /* -------------------------------------------------------------------- */
97 static u_int32_t tr_recfmt[] = {
99 AFMT_STEREO | AFMT_U8,
101 AFMT_STEREO | AFMT_S8,
103 AFMT_STEREO | AFMT_S16_LE,
105 AFMT_STEREO | AFMT_U16_LE,
108 static struct pcmchan_caps tr_reccaps = {4000, 48000, tr_recfmt, 0};
110 static u_int32_t tr_playfmt[] = {
112 AFMT_STEREO | AFMT_U8,
114 AFMT_STEREO | AFMT_S8,
116 AFMT_STEREO | AFMT_S16_LE,
118 AFMT_STEREO | AFMT_U16_LE,
121 static struct pcmchan_caps tr_playcaps = {4000, 48000, tr_playfmt, 0};
123 /* -------------------------------------------------------------------- */
128 tr_rd(struct tr_info *tr, int regno, int size)
132 return bus_space_read_1(tr->st, tr->sh, regno);
134 return bus_space_read_2(tr->st, tr->sh, regno);
136 return bus_space_read_4(tr->st, tr->sh, regno);
143 tr_wr(struct tr_info *tr, int regno, u_int32_t data, int size)
147 bus_space_write_1(tr->st, tr->sh, regno, data);
150 bus_space_write_2(tr->st, tr->sh, regno, data);
153 bus_space_write_4(tr->st, tr->sh, regno, data);
158 /* -------------------------------------------------------------------- */
162 tr_rdcd(kobj_t obj, void *devinfo, int regno)
164 struct tr_info *tr = (struct tr_info *)devinfo;
169 treg=SPA_REG_CODECRD;
174 treg=TDX_REG_CODECWR;
176 treg=TDX_REG_CODECRD;
180 treg=TDX_REG_CODECRD;
184 treg=(regno & 0x100)? TNX_REG_CODEC2RD : TNX_REG_CODEC1RD;
188 printf("!!! tr_rdcd defaulted !!!\n");
195 snd_mtxlock(tr->lock);
196 if (tr->type == ALI_PCI_ID) {
197 u_int32_t chk1, chk2;
199 for (i = TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--)
200 j = tr_rd(tr, treg, 4);
202 chk1 = tr_rd(tr, 0xc8, 4);
203 chk2 = tr_rd(tr, 0xc8, 4);
204 for (i = TR_TIMEOUT_CDC; (i > 0) && (chk1 == chk2);
206 chk2 = tr_rd(tr, 0xc8, 4);
209 if (tr->type != ALI_PCI_ID || i > 0) {
210 tr_wr(tr, treg, regno | trw, 4);
212 for (i=TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--)
213 j=tr_rd(tr, treg, 4);
215 snd_mtxunlock(tr->lock);
216 if (i == 0) printf("codec timeout during read of register %x\n", regno);
217 return (j >> TR_CDC_DATA) & 0xffff;
221 tr_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
223 struct tr_info *tr = (struct tr_info *)devinfo;
228 treg=SPA_REG_CODECWR;
233 treg=TDX_REG_CODECWR;
237 treg=TNX_REG_CODECWR;
238 trw=TNX_CDC_RWSTAT | ((regno & 0x100)? TNX_CDC_SEC : 0);
241 printf("!!! tr_wrcd defaulted !!!");
249 printf("tr_wrcd: reg %x was %x", regno, tr_rdcd(devinfo, regno));
252 snd_mtxlock(tr->lock);
253 if (tr->type == ALI_PCI_ID) {
255 for (i = TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--)
256 j = tr_rd(tr, treg, 4);
258 u_int32_t chk1, chk2;
259 chk1 = tr_rd(tr, 0xc8, 4);
260 chk2 = tr_rd(tr, 0xc8, 4);
261 for (i = TR_TIMEOUT_CDC; (i > 0) && (chk1 == chk2);
263 chk2 = tr_rd(tr, 0xc8, 4);
266 if (tr->type != ALI_PCI_ID || i > 0) {
267 for (i=TR_TIMEOUT_CDC; (i>0) && (j & trw); i--)
268 j=tr_rd(tr, treg, 4);
269 if (tr->type == ALI_PCI_ID && tr->rev > 0x01)
271 tr_wr(tr, treg, (data << TR_CDC_DATA) | regno | trw, 4);
274 printf(" - wrote %x, now %x\n", data, tr_rdcd(devinfo, regno));
276 snd_mtxunlock(tr->lock);
277 if (i==0) printf("codec timeout writing %x, data %x\n", regno, data);
278 return (i > 0)? 0 : -1;
281 static kobj_method_t tr_ac97_methods[] = {
282 KOBJMETHOD(ac97_read, tr_rdcd),
283 KOBJMETHOD(ac97_write, tr_wrcd),
286 AC97_DECLARE(tr_ac97);
288 /* -------------------------------------------------------------------- */
289 /* playback channel interrupts */
293 tr_testint(struct tr_chinfo *ch)
295 struct tr_info *tr = ch->parent;
298 bank = (ch->index & 0x20) ? 1 : 0;
299 chan = ch->index & 0x1f;
300 return tr_rd(tr, bank? TR_REG_ADDRINTB : TR_REG_ADDRINTA, 4) & (1 << chan);
305 tr_clrint(struct tr_chinfo *ch)
307 struct tr_info *tr = ch->parent;
310 bank = (ch->index & 0x20) ? 1 : 0;
311 chan = ch->index & 0x1f;
312 tr_wr(tr, bank? TR_REG_ADDRINTB : TR_REG_ADDRINTA, 1 << chan, 4);
316 tr_enaint(struct tr_chinfo *ch, int enable)
318 struct tr_info *tr = ch->parent;
322 snd_mtxlock(tr->lock);
323 bank = (ch->index & 0x20) ? 1 : 0;
324 chan = ch->index & 0x1f;
325 reg = bank? TR_REG_INTENB : TR_REG_INTENA;
327 i = tr_rd(tr, reg, 4);
329 i |= (enable? 1 : 0) << chan;
332 tr_wr(tr, reg, i, 4);
333 snd_mtxunlock(tr->lock);
336 /* playback channels */
339 tr_selch(struct tr_chinfo *ch)
341 struct tr_info *tr = ch->parent;
344 i = tr_rd(tr, TR_REG_CIR, 4);
346 i |= ch->index & 0x3f;
347 tr_wr(tr, TR_REG_CIR, i, 4);
351 tr_startch(struct tr_chinfo *ch)
353 struct tr_info *tr = ch->parent;
356 bank = (ch->index & 0x20) ? 1 : 0;
357 chan = ch->index & 0x1f;
358 tr_wr(tr, bank? TR_REG_STARTB : TR_REG_STARTA, 1 << chan, 4);
362 tr_stopch(struct tr_chinfo *ch)
364 struct tr_info *tr = ch->parent;
367 bank = (ch->index & 0x20) ? 1 : 0;
368 chan = ch->index & 0x1f;
369 tr_wr(tr, bank? TR_REG_STOPB : TR_REG_STOPA, 1 << chan, 4);
373 tr_wrch(struct tr_chinfo *ch)
375 struct tr_info *tr = ch->parent;
376 u_int32_t cr[TR_CHN_REGS], i;
378 ch->gvsel &= 0x00000001;
379 ch->fmc &= 0x00000003;
380 ch->fms &= 0x0000000f;
381 ch->ctrl &= 0x0000000f;
382 ch->pan &= 0x0000007f;
383 ch->rvol &= 0x0000007f;
384 ch->cvol &= 0x0000007f;
385 ch->vol &= 0x000000ff;
386 ch->ec &= 0x00000fff;
387 ch->alpha &= 0x00000fff;
388 ch->delta &= 0x0000ffff;
389 ch->lba &= 0x3fffffff;
392 cr[3]=(ch->fmc<<14) | (ch->rvol<<7) | (ch->cvol);
393 cr[4]=(ch->gvsel<<31) | (ch->pan<<24) | (ch->vol<<16) | (ch->ctrl<<12) | (ch->ec);
399 ch->cso &= 0x0000ffff;
400 ch->eso &= 0x0000ffff;
401 cr[0]=(ch->cso<<16) | (ch->alpha<<4) | (ch->fms);
402 cr[2]=(ch->eso<<16) | (ch->delta);
405 ch->cso &= 0x00ffffff;
406 ch->eso &= 0x00ffffff;
407 cr[0]=((ch->delta & 0xff)<<24) | (ch->cso);
408 cr[2]=((ch->delta>>8)<<24) | (ch->eso);
409 cr[3]|=(ch->alpha<<20) | (ch->fms<<16) | (ch->fmc<<14);
412 snd_mtxlock(tr->lock);
414 for (i=0; i<TR_CHN_REGS; i++)
415 tr_wr(tr, TR_REG_CHNBASE+(i<<2), cr[i], 4);
416 snd_mtxunlock(tr->lock);
420 tr_rdch(struct tr_chinfo *ch)
422 struct tr_info *tr = ch->parent;
425 snd_mtxlock(tr->lock);
428 cr[i]=tr_rd(tr, TR_REG_CHNBASE+(i<<2), 4);
429 snd_mtxunlock(tr->lock);
432 ch->lba= (cr[1] & 0x3fffffff);
433 ch->fmc= (cr[3] & 0x0000c000) >> 14;
434 ch->rvol= (cr[3] & 0x00003f80) >> 7;
435 ch->cvol= (cr[3] & 0x0000007f);
436 ch->gvsel= (cr[4] & 0x80000000) >> 31;
437 ch->pan= (cr[4] & 0x7f000000) >> 24;
438 ch->vol= (cr[4] & 0x00ff0000) >> 16;
439 ch->ctrl= (cr[4] & 0x0000f000) >> 12;
440 ch->ec= (cr[4] & 0x00000fff);
445 ch->cso= (cr[0] & 0xffff0000) >> 16;
446 ch->alpha= (cr[0] & 0x0000fff0) >> 4;
447 ch->fms= (cr[0] & 0x0000000f);
448 ch->eso= (cr[2] & 0xffff0000) >> 16;
449 ch->delta= (cr[2] & 0x0000ffff);
452 ch->cso= (cr[0] & 0x00ffffff);
453 ch->eso= (cr[2] & 0x00ffffff);
454 ch->delta= ((cr[2] & 0xff000000) >> 16) | ((cr[0] & 0xff000000) >> 24);
455 ch->alpha= (cr[3] & 0xfff00000) >> 20;
456 ch->fms= (cr[3] & 0x000f0000) >> 16;
462 tr_fmttobits(u_int32_t fmt)
467 bits |= (fmt & AFMT_SIGNED)? 0x2 : 0;
468 bits |= (fmt & AFMT_STEREO)? 0x4 : 0;
469 bits |= (fmt & AFMT_16BIT)? 0x8 : 0;
474 /* -------------------------------------------------------------------- */
475 /* channel interface */
478 trpchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
480 struct tr_info *tr = devinfo;
481 struct tr_chinfo *ch;
483 KASSERT(dir == PCMDIR_PLAY, ("trpchan_init: bad direction"));
484 ch = &tr->chinfo[tr->playchns];
485 ch->index = tr->playchns++;
489 if (sndbuf_alloc(ch->buffer, tr->parent_dmat, tr->bufsz) == -1)
496 trpchan_setformat(kobj_t obj, void *data, u_int32_t format)
498 struct tr_chinfo *ch = data;
500 ch->ctrl = tr_fmttobits(format) | 0x01;
506 trpchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
508 struct tr_chinfo *ch = data;
510 ch->delta = (speed << 12) / 48000;
511 return (ch->delta * 48000) >> 12;
515 trpchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
517 struct tr_chinfo *ch = data;
519 sndbuf_resize(ch->buffer, 2, blocksize);
524 trpchan_trigger(kobj_t obj, void *data, int go)
526 struct tr_chinfo *ch = data;
528 if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD)
531 if (go == PCMTRIG_START) {
536 ch->lba = vtophys(sndbuf_getbuf(ch->buffer));
538 ch->eso = (sndbuf_getsize(ch->buffer) / sndbuf_getbps(ch->buffer)) - 1;
539 ch->rvol = ch->cvol = 0x7f;
557 trpchan_getptr(kobj_t obj, void *data)
559 struct tr_chinfo *ch = data;
562 return ch->cso * sndbuf_getbps(ch->buffer);
565 static struct pcmchan_caps *
566 trpchan_getcaps(kobj_t obj, void *data)
571 static kobj_method_t trpchan_methods[] = {
572 KOBJMETHOD(channel_init, trpchan_init),
573 KOBJMETHOD(channel_setformat, trpchan_setformat),
574 KOBJMETHOD(channel_setspeed, trpchan_setspeed),
575 KOBJMETHOD(channel_setblocksize, trpchan_setblocksize),
576 KOBJMETHOD(channel_trigger, trpchan_trigger),
577 KOBJMETHOD(channel_getptr, trpchan_getptr),
578 KOBJMETHOD(channel_getcaps, trpchan_getcaps),
581 CHANNEL_DECLARE(trpchan);
583 /* -------------------------------------------------------------------- */
584 /* rec channel interface */
587 trrchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
589 struct tr_info *tr = devinfo;
590 struct tr_rchinfo *ch;
592 KASSERT(dir == PCMDIR_REC, ("trrchan_init: bad direction"));
597 if (sndbuf_alloc(ch->buffer, tr->parent_dmat, tr->bufsz) == -1)
604 trrchan_setformat(kobj_t obj, void *data, u_int32_t format)
606 struct tr_rchinfo *ch = data;
607 struct tr_info *tr = ch->parent;
610 bits = tr_fmttobits(format);
611 /* set # of samples between interrupts */
612 i = (sndbuf_runsz(ch->buffer) >> ((bits & 0x08)? 1 : 0)) - 1;
613 tr_wr(tr, TR_REG_SBBL, i | (i << 16), 4);
614 /* set sample format */
615 i = 0x18 | (bits << 4);
616 tr_wr(tr, TR_REG_SBCTRL, i, 1);
623 trrchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
625 struct tr_rchinfo *ch = data;
626 struct tr_info *tr = ch->parent;
629 ch->delta = (48000 << 12) / speed;
630 tr_wr(tr, TR_REG_SBDELTA, ch->delta, 2);
632 /* return closest possible speed */
633 return (48000 << 12) / ch->delta;
637 trrchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
639 struct tr_rchinfo *ch = data;
641 sndbuf_resize(ch->buffer, 2, blocksize);
647 trrchan_trigger(kobj_t obj, void *data, int go)
649 struct tr_rchinfo *ch = data;
650 struct tr_info *tr = ch->parent;
653 if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD)
656 if (go == PCMTRIG_START) {
657 /* set up dma mode regs */
658 tr_wr(tr, TR_REG_DMAR15, 0, 1);
659 i = tr_rd(tr, TR_REG_DMAR11, 1) & 0x03;
660 tr_wr(tr, TR_REG_DMAR11, i | 0x54, 1);
661 /* set up base address */
662 tr_wr(tr, TR_REG_DMAR0, vtophys(sndbuf_getbuf(ch->buffer)), 4);
663 /* set up buffer size */
664 i = tr_rd(tr, TR_REG_DMAR4, 4) & ~0x00ffffff;
665 tr_wr(tr, TR_REG_DMAR4, i | (sndbuf_runsz(ch->buffer) - 1), 4);
667 tr_wr(tr, TR_REG_SBCTRL, tr_rd(tr, TR_REG_SBCTRL, 1) | 1, 1);
670 tr_wr(tr, TR_REG_SBCTRL, tr_rd(tr, TR_REG_SBCTRL, 1) & ~7, 1);
679 trrchan_getptr(kobj_t obj, void *data)
681 struct tr_rchinfo *ch = data;
682 struct tr_info *tr = ch->parent;
684 /* return current byte offset of channel */
685 return tr_rd(tr, TR_REG_DMAR0, 4) - vtophys(sndbuf_getbuf(ch->buffer));
688 static struct pcmchan_caps *
689 trrchan_getcaps(kobj_t obj, void *data)
694 static kobj_method_t trrchan_methods[] = {
695 KOBJMETHOD(channel_init, trrchan_init),
696 KOBJMETHOD(channel_setformat, trrchan_setformat),
697 KOBJMETHOD(channel_setspeed, trrchan_setspeed),
698 KOBJMETHOD(channel_setblocksize, trrchan_setblocksize),
699 KOBJMETHOD(channel_trigger, trrchan_trigger),
700 KOBJMETHOD(channel_getptr, trrchan_getptr),
701 KOBJMETHOD(channel_getcaps, trrchan_getcaps),
704 CHANNEL_DECLARE(trrchan);
706 /* -------------------------------------------------------------------- */
707 /* The interrupt handler */
712 struct tr_info *tr = (struct tr_info *)p;
713 struct tr_chinfo *ch;
714 u_int32_t active, mask, bufhalf, chnum, intsrc;
717 intsrc = tr_rd(tr, TR_REG_MISCINT, 4);
718 if (intsrc & TR_INT_ADDR) {
722 active = tr_rd(tr, (chnum < 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, 4);
723 bufhalf = tr_rd(tr, (chnum < 32)? TR_REG_CSPF_A : TR_REG_CSPF_B, 4);
727 tmp = (bufhalf & mask)? 1 : 0;
728 if (chnum < tr->playchns) {
729 ch = &tr->chinfo[chnum];
730 /* printf("%d @ %d, ", chnum, trpchan_getptr(NULL, ch)); */
731 if (ch->bufhalf != tmp) {
732 chn_intr(ch->channel);
739 } while (chnum & 31);
743 tr_wr(tr, (chnum <= 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, active, 4);
746 if (intsrc & TR_INT_SB) {
747 chn_intr(tr->recchinfo.channel);
748 tr_rd(tr, TR_REG_SBR9, 1);
749 tr_rd(tr, TR_REG_SBR10, 1);
753 /* -------------------------------------------------------------------- */
756 * Probe and attach the card
760 tr_init(struct tr_info *tr)
764 tr_wr(tr, SPA_REG_GPIO, 0, 4);
765 tr_wr(tr, SPA_REG_CODECST, SPA_RST_OFF, 4);
768 tr_wr(tr, TDX_REG_CODECST, TDX_CDC_ON, 4);
771 tr_wr(tr, TNX_REG_CODECST, TNX_CDC_ON, 4);
775 tr_wr(tr, TR_REG_CIR, TR_CIR_MIDENA | TR_CIR_ADDRENA, 4);
780 tr_pci_probe(device_t dev)
782 switch (pci_get_devid(dev)) {
784 device_set_desc(dev, "SiS 7018");
787 device_set_desc(dev, "Acer Labs M5451");
790 device_set_desc(dev, "Trident 4DWave DX");
793 device_set_desc(dev, "Trident 4DWave NX");
801 tr_pci_attach(device_t dev)
805 struct ac97_info *codec = 0;
807 char status[SND_STATUSLEN];
809 if ((tr = malloc(sizeof(*tr), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) {
810 device_printf(dev, "cannot allocate softc\n");
814 tr->type = pci_get_devid(dev);
815 tr->rev = pci_get_revid(dev);
816 tr->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc");
818 data = pci_read_config(dev, PCIR_COMMAND, 2);
819 data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
820 pci_write_config(dev, PCIR_COMMAND, data, 2);
821 data = pci_read_config(dev, PCIR_COMMAND, 2);
823 tr->regid = PCIR_MAPS;
824 tr->regtype = SYS_RES_IOPORT;
825 tr->reg = bus_alloc_resource(dev, tr->regtype, &tr->regid, 0, ~0, 1, RF_ACTIVE);
827 tr->st = rman_get_bustag(tr->reg);
828 tr->sh = rman_get_bushandle(tr->reg);
830 device_printf(dev, "unable to map register space\n");
834 tr->bufsz = pcm_getbuffersize(dev, 4096, TR_DEFAULT_BUFSZ, 65536);
836 if (tr_init(tr) == -1) {
837 device_printf(dev, "unable to initialize the card\n");
842 codec = AC97_CREATE(dev, tr, tr_ac97);
843 if (codec == NULL) goto bad;
844 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad;
847 tr->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &tr->irqid,
848 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
849 if (!tr->irq || snd_setup_intr(dev, tr->irq, INTR_MPSAFE, tr_intr, tr, &tr->ih)) {
850 device_printf(dev, "unable to map interrupt\n");
854 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
855 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
856 /*highaddr*/BUS_SPACE_MAXADDR,
857 /*filter*/NULL, /*filterarg*/NULL,
858 /*maxsize*/tr->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff,
859 /*flags*/0, &tr->parent_dmat) != 0) {
860 device_printf(dev, "unable to create dma tag\n");
864 snprintf(status, 64, "at io 0x%lx irq %ld",
865 rman_get_start(tr->reg), rman_get_start(tr->irq));
867 if (pcm_register(dev, tr, TR_MAXPLAYCH, 1)) goto bad;
868 pcm_addchan(dev, PCMDIR_REC, &trrchan_class, tr);
869 for (i = 0; i < TR_MAXPLAYCH; i++)
870 pcm_addchan(dev, PCMDIR_PLAY, &trpchan_class, tr);
871 pcm_setstatus(dev, status);
876 if (codec) ac97_destroy(codec);
877 if (tr->reg) bus_release_resource(dev, tr->regtype, tr->regid, tr->reg);
878 if (tr->ih) bus_teardown_intr(dev, tr->irq, tr->ih);
879 if (tr->irq) bus_release_resource(dev, SYS_RES_IRQ, tr->irqid, tr->irq);
880 if (tr->parent_dmat) bus_dma_tag_destroy(tr->parent_dmat);
881 if (tr->lock) snd_mtxfree(tr->lock);
887 tr_pci_detach(device_t dev)
892 r = pcm_unregister(dev);
896 tr = pcm_getdevinfo(dev);
897 bus_release_resource(dev, tr->regtype, tr->regid, tr->reg);
898 bus_teardown_intr(dev, tr->irq, tr->ih);
899 bus_release_resource(dev, SYS_RES_IRQ, tr->irqid, tr->irq);
900 bus_dma_tag_destroy(tr->parent_dmat);
901 snd_mtxfree(tr->lock);
908 tr_pci_suspend(device_t dev)
913 tr = pcm_getdevinfo(dev);
915 for (i = 0; i < tr->playchns; i++) {
916 tr->chinfo[i].was_active = tr->chinfo[i].active;
917 if (tr->chinfo[i].active) {
918 trpchan_trigger(NULL, &tr->chinfo[i], PCMTRIG_STOP);
922 tr->recchinfo.was_active = tr->recchinfo.active;
923 if (tr->recchinfo.active) {
924 trrchan_trigger(NULL, &tr->recchinfo, PCMTRIG_STOP);
931 tr_pci_resume(device_t dev)
936 tr = pcm_getdevinfo(dev);
938 if (tr_init(tr) == -1) {
939 device_printf(dev, "unable to initialize the card\n");
943 if (mixer_reinit(dev) == -1) {
944 device_printf(dev, "unable to initialize the mixer\n");
948 for (i = 0; i < tr->playchns; i++) {
949 if (tr->chinfo[i].was_active) {
950 trpchan_trigger(NULL, &tr->chinfo[i], PCMTRIG_START);
954 if (tr->recchinfo.was_active) {
955 trrchan_trigger(NULL, &tr->recchinfo, PCMTRIG_START);
961 static device_method_t tr_methods[] = {
962 /* Device interface */
963 DEVMETHOD(device_probe, tr_pci_probe),
964 DEVMETHOD(device_attach, tr_pci_attach),
965 DEVMETHOD(device_detach, tr_pci_detach),
966 DEVMETHOD(device_suspend, tr_pci_suspend),
967 DEVMETHOD(device_resume, tr_pci_resume),
971 static driver_t tr_driver = {
977 DRIVER_MODULE(snd_t4dwave, pci, tr_driver, pcm_devclass, 0, 0);
978 MODULE_DEPEND(snd_t4dwave, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
979 MODULE_VERSION(snd_t4dwave, 1);