2 * Copyright (c) 1990 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
37 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
38 * $DragonFly: src/sys/i386/isa/Attic/clock.c,v 1.16 2004/08/02 23:20:30 dillon Exp $
42 * Routines to handle clock hardware.
46 * inittodr, settodr and support routines written
47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
54 #include "opt_clock.h"
56 #include <sys/param.h>
57 #include <sys/systm.h>
59 #include <sys/kernel.h>
64 #include <sys/sysctl.h>
66 #include <sys/systimer.h>
67 #include <sys/globaldata.h>
68 #include <sys/thread2.h>
69 #include <sys/systimer.h>
71 #include <machine/clock.h>
72 #ifdef CLK_CALIBRATION_LOOP
74 #include <machine/cputypes.h>
75 #include <machine/frame.h>
76 #include <machine/ipl.h>
77 #include <machine/limits.h>
78 #include <machine/md_var.h>
79 #include <machine/psl.h>
81 #include <machine/segments.h>
83 #if defined(SMP) || defined(APIC_IO)
84 #include <machine/smp.h>
85 #endif /* SMP || APIC_IO */
86 #include <machine/specialreg.h>
88 #include <i386/isa/icu.h>
89 #include <bus/isa/i386/isa.h>
90 #include <bus/isa/rtc.h>
91 #include <i386/isa/timerreg.h>
93 #include <i386/isa/intr_machdep.h>
96 #include <bus/mca/i386/mca_machdep.h>
100 #include <i386/isa/intr_machdep.h>
101 /* The interrupt triggered by the 8254 (timer) chip */
103 static u_long read_intr_count (int vec);
104 static void setup_8254_mixed_mode (void);
106 static void i8254_restore(void);
109 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
110 * can use a simple formula for leap years.
112 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
113 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
116 #define TIMER_FREQ 1193182
119 #define TIMER_SELX TIMER_SEL2
120 #define TIMER_CNTRX TIMER_CNTR2
122 int adjkerntz; /* local offset from GMT in seconds */
123 int disable_rtc_set; /* disable resettodr() if != 0 */
124 volatile u_int idelayed;
125 int statclock_disable = 1; /* we don't use the statclock right now */
126 u_int stat_imask = SWI_CLOCK_MASK;
127 u_int cputimer_freq = TIMER_FREQ;
129 int64_t cputimer_freq64_usec = ((int64_t)TIMER_FREQ << 32) / 1000000;
130 int64_t cputimer_freq64_nsec = ((int64_t)TIMER_FREQ << 32) / 1000000000LL;
132 int64_t cputimer_freq64_usec = (1000000LL << 32) / TIMER_FREQ;
133 int64_t cputimer_freq64_nsec = (1000000000LL << 32) / TIMER_FREQ;
136 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
138 enum tstate { RELEASED, ACQUIRED };
139 enum tstate timer0_state;
140 enum tstate timer1_state;
141 enum tstate timer2_state;
143 static int beeping = 0;
144 static u_int clk_imask = HWI_MASK | SWI_MASK;
145 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
146 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
147 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
148 static u_int tsc_present;
151 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped
152 * counting as of this interrupt. We use timer1 in free-running mode (not
153 * generating any interrupts) as our main counter. Each cpu has timeouts
157 clkintr(struct intrframe frame)
159 static sysclock_t timer1_count;
160 struct globaldata *gd = mycpu;
161 struct globaldata *gscan;
165 * SWSTROBE mode is a one-shot, the timer is no longer running
170 * XXX this could be done more efficiently by using a bitmask?
172 timer1_count = cputimer_count();
173 for (n = 0; n < ncpus; ++n) {
174 gscan = globaldata_find(n);
175 if (gscan->gd_nextclock == 0)
178 lwkt_send_ipiq(gscan, (ipifunc_t)systimer_intr, &timer1_count);
180 systimer_intr(&timer1_count, &frame);
184 /* Reset clock interrupt by asserting bit 7 of port 0x61 */
186 outb(0x61, inb(0x61) | 0x80);
195 acquire_timer2(int mode)
197 /* Timer2 is being used for time count operation */
200 if (timer2_state != RELEASED)
202 timer2_state = ACQUIRED;
205 * This access to the timer registers is as atomic as possible
206 * because it is a single instruction. We could do better if we
209 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
217 if (timer2_state != ACQUIRED)
219 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
220 timer2_state = RELEASED;
225 * This routine receives statistical clock interrupts from the RTC.
226 * As explained above, these occur at 128 interrupts per second.
227 * When profiling, we receive interrupts at a rate of 1024 Hz.
229 * This does not actually add as much overhead as it sounds, because
230 * when the statistical clock is active, the hardclock driver no longer
231 * needs to keep (inaccurate) statistics on its own. This decouples
232 * statistics gathering from scheduling interrupts.
234 * The RTC chip requires that we read status register C (RTC_INTR)
235 * to acknowledge an interrupt, before it will generate the next one.
236 * Under high interrupt load, rtcintr() can be indefinitely delayed and
237 * the clock can tick immediately after the read from RTC_INTR. In this
238 * case, the mc146818A interrupt signal will not drop for long enough
239 * to register with the 8259 PIC. If an interrupt is missed, the stat
240 * clock will halt, considerably degrading system performance. This is
241 * why we use 'while' rather than a more straightforward 'if' below.
242 * Stat clock ticks can still be lost, causing minor loss of accuracy
243 * in the statistics, but the stat clock will no longer stop.
246 rtcintr(struct intrframe frame)
248 while (rtcin(RTC_INTR) & RTCIR_PERIOD)
250 /* statclock(&frame); no longer used */
257 DB_SHOW_COMMAND(rtc, rtc)
259 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
260 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
261 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
262 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
267 * Convert a frequency to a cpu timer count.
270 cputimer_fromhz(int freq)
272 return(cputimer_freq / freq + 1);
276 cputimer_fromus(int us)
278 return((int64_t)cputimer_freq * us / 1000000);
282 * Return the current cpu timer count as a 32 bit integer.
287 static sysclock_t cputimer_base;
288 static __uint16_t cputimer_last;
293 outb(TIMER_MODE, TIMER_SELX | TIMER_LATCH);
294 count = (__uint8_t)inb(TIMER_CNTRX); /* get countdown */
295 count |= ((__uint8_t)inb(TIMER_CNTRX) << 8);
296 count = -count; /* -> countup */
297 if (count < cputimer_last) /* rollover */
298 cputimer_base += 0x00010000;
299 ret = cputimer_base | count;
300 cputimer_last = count;
306 * Reload for the next timeout. It is possible for the reload value
307 * to be 0 or negative, indicating that an immediate timer interrupt
308 * is desired. For now make the minimum 2 ticks.
311 cputimer_intr_reload(sysclock_t reload)
319 if (timer0_running) {
320 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */
321 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */
322 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */
323 if (reload < count) {
324 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
325 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
326 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
331 reload = 0; /* full count */
332 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
333 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
334 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
340 * Wait "n" microseconds.
341 * Relies on timer 1 counting down from (cputimer_freq / hz)
342 * Note: timer had better have been programmed before this is first used!
347 int delta, prev_tick, tick, ticks_left;
352 static int state = 0;
356 for (n1 = 1; n1 <= 10000000; n1 *= 10)
361 printf("DELAY(%d)...", n);
364 * Guard against the timer being uninitialized if we are called
365 * early for console i/o.
367 if (timer0_state == RELEASED)
371 * Read the counter first, so that the rest of the setup overhead is
372 * counted. Guess the initial overhead is 20 usec (on most systems it
373 * takes about 1.5 usec for each of the i/o's in getit(). The loop
374 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The
375 * multiplications and divisions to scale the count take a while).
377 prev_tick = cputimer_count();
378 n -= 0; /* XXX actually guess no initial overhead */
380 * Calculate (n * (cputimer_freq / 1e6)) without using floating point
381 * and without any avoidable overflows.
385 } else if (n < 256) {
387 * Use fixed point to avoid a slow division by 1000000.
388 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest.
389 * 2^15 is the first power of 2 that gives exact results
390 * for n between 0 and 256.
392 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15;
395 * Don't bother using fixed point, although gcc-2.7.2
396 * generates particularly poor code for the long long
397 * division, since even the slow way will complete long
398 * before the delay is up (unless we're interrupted).
400 ticks_left = ((u_int)n * (long long)cputimer_freq + 999999)
404 while (ticks_left > 0) {
405 tick = cputimer_count();
409 delta = tick - prev_tick;
417 printf(" %d calls to getit() at %d usec each\n",
418 getit_calls, (n + 5) / getit_calls);
423 sysbeepstop(void *chan)
425 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
431 sysbeep(int pitch, int period)
433 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
436 * Nobody else is using timer2, we do not need the clock lock
438 outb(TIMER_CNTR2, pitch);
439 outb(TIMER_CNTR2, (pitch>>8));
441 /* enable counter2 output to speaker */
442 outb(IO_PPI, inb(IO_PPI) | 3);
444 timeout(sysbeepstop, (void *)NULL, period);
450 * RTC support routines
463 val = inb(IO_RTC + 1);
470 writertc(u_char reg, u_char val)
478 outb(IO_RTC + 1, val);
479 inb(0x84); /* XXX work around wrong order in rtcin() */
486 return(bcd2bin(rtcin(port)));
490 calibrate_clocks(void)
493 u_int count, prev_count, tot_count;
494 int sec, start_sec, timeout;
497 printf("Calibrating clock(s) ... ");
498 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
502 /* Read the mc146818A seconds counter. */
504 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
505 sec = rtcin(RTC_SEC);
512 /* Wait for the mC146818A seconds counter to change. */
515 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
516 sec = rtcin(RTC_SEC);
517 if (sec != start_sec)
524 /* Start keeping track of the i8254 counter. */
525 prev_count = cputimer_count();
531 old_tsc = 0; /* shut up gcc */
534 * Wait for the mc146818A seconds counter to change. Read the i8254
535 * counter for each iteration since this is convenient and only
536 * costs a few usec of inaccuracy. The timing of the final reads
537 * of the counters almost matches the timing of the initial reads,
538 * so the main cause of inaccuracy is the varying latency from
539 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
540 * rtcin(RTC_SEC) that returns a changed seconds count. The
541 * maximum inaccuracy from this cause is < 10 usec on 486's.
545 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
546 sec = rtcin(RTC_SEC);
547 count = cputimer_count();
548 tot_count += (int)(count - prev_count);
550 if (sec != start_sec)
557 * Read the cpu cycle counter. The timing considerations are
558 * similar to those for the i8254 clock.
561 tsc_freq = rdtsc() - old_tsc;
564 printf("TSC clock: %u Hz, ", tsc_freq);
565 printf("i8254 clock: %u Hz\n", tot_count);
569 printf("failed, using default i8254 clock of %u Hz\n", cputimer_freq);
570 return (cputimer_freq);
576 timer0_state = ACQUIRED;
577 timer1_state = ACQUIRED;
579 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
580 outb(TIMER_CNTR0, 2); /* lsb */
581 outb(TIMER_CNTR0, 0); /* msb */
582 outb(TIMER_MODE, TIMER_SELX | TIMER_RATEGEN | TIMER_16BIT);
583 outb(TIMER_CNTRX, 0); /* lsb */
584 outb(TIMER_CNTRX, 0); /* msb */
585 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */
592 /* Restore all of the RTC's "status" (actually, control) registers. */
593 writertc(RTC_STATUSB, RTCSB_24HR);
594 writertc(RTC_STATUSA, rtc_statusa);
595 writertc(RTC_STATUSB, rtc_statusb);
599 * Restore all the timers.
601 * This function is called from apm_default_resume() / pmtimer to restore
602 * all the timers. We also have to restore our timebases, especially on
603 * MP systems, because cputimer_count() counter's delta may have grown
604 * too large for nanouptime() and friends to handle.
610 i8254_restore(); /* restore timer_freq and hz */
611 rtc_restore(); /* reenable RTC interrupts */
617 * Initialize 8254 timer 0 early so that it can be used in DELAY().
625 * Can we use the TSC?
627 if (cpu_feature & CPUID_TSC)
633 * Initial RTC state, don't do anything unexpected
635 writertc(RTC_STATUSA, rtc_statusa);
636 writertc(RTC_STATUSB, RTCSB_24HR);
639 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
640 * generate an interrupt, which we will ignore for now.
642 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
643 * (so it counts a full 2^16 and repeats). We will use this timer
647 freq = calibrate_clocks();
648 #ifdef CLK_CALIBRATION_LOOP
651 "Press a key on the console to abort clock calibration\n");
652 while (cncheckc() == -1)
658 * Use the calibrated i8254 frequency if it seems reasonable.
659 * Otherwise use the default, and don't use the calibrated i586
662 delta = freq > cputimer_freq ?
663 freq - cputimer_freq : cputimer_freq - freq;
664 if (delta < cputimer_freq / 100) {
665 #ifndef CLK_USE_I8254_CALIBRATION
668 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
669 freq = cputimer_freq;
671 cputimer_freq = freq;
672 cputimer_freq64_usec = (1000000LL << 32) / freq;
673 cputimer_freq64_nsec = (1000000000LL << 32) / freq;
677 "%d Hz differs from default of %d Hz by more than 1%%\n",
678 freq, cputimer_freq);
682 #ifndef CLK_USE_TSC_CALIBRATION
686 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
690 if (tsc_present && tsc_freq == 0) {
692 * Calibration of the i586 clock relative to the mc146818A
693 * clock failed. Do a less accurate calibration relative
694 * to the i8254 clock.
696 u_int64_t old_tsc = rdtsc();
699 tsc_freq = rdtsc() - old_tsc;
700 #ifdef CLK_USE_TSC_CALIBRATION
702 printf("TSC clock: %u Hz (Method B)\n", tsc_freq);
708 * We can not use the TSC in SMP mode, until we figure out a
709 * cheap (impossible), reliable and precise (yeah right!) way
710 * to synchronize the TSCs of all the CPUs.
711 * Curse Intel for leaving the counter out of the I/O APIC.
716 * We can not use the TSC if we support APM. Precise timekeeping
717 * on an APM'ed machine is at best a fools pursuit, since
718 * any and all of the time spent in various SMM code can't
719 * be reliably accounted for. Reading the RTC is your only
720 * source of reliable time info. The i8254 looses too of course
721 * but we need to have some kind of time...
722 * We don't know at this point whether APM is going to be used
723 * or not, nor when it might be activated. Play it safe.
726 #endif /* NAPM > 0 */
728 #endif /* !defined(SMP) */
732 * Initialize the time of day register, based on the time base which is, e.g.
736 inittodr(time_t base)
738 unsigned long sec, days;
750 /* Look if we have a RTC present and the time is valid */
751 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
754 /* wait for time update to complete */
755 /* If RTCSA_TUP is zero, we have at least 244us before next update */
757 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
763 #ifdef USE_RTC_CENTURY
764 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
766 year = readrtc(RTC_YEAR) + 1900;
774 month = readrtc(RTC_MONTH);
775 for (m = 1; m < month; m++)
776 days += daysinmonth[m-1];
777 if ((month > 2) && LEAPYEAR(year))
779 days += readrtc(RTC_DAY) - 1;
781 for (y = 1970; y < year; y++)
782 days += DAYSPERYEAR + LEAPYEAR(y);
783 sec = ((( days * 24 +
784 readrtc(RTC_HRS)) * 60 +
785 readrtc(RTC_MIN)) * 60 +
787 /* sec now contains the number of seconds, since Jan 1 1970,
788 in the local time zone */
790 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
792 y = time_second - sec;
793 if (y <= -2 || y >= 2) {
794 /* badly off, adjust it */
803 printf("Invalid time in real time clock.\n");
804 printf("Check and reset the date immediately!\n");
808 * Write system time back to RTC
825 /* Disable RTC updates and interrupts. */
826 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
828 /* Calculate local time to put in RTC */
830 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
832 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
833 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
834 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
836 /* We have now the days since 01-01-1970 in tm */
837 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
838 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
840 y++, m = DAYSPERYEAR + LEAPYEAR(y))
843 /* Now we have the years in y and the day-of-the-year in tm */
844 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
845 #ifdef USE_RTC_CENTURY
846 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
852 if (m == 1 && LEAPYEAR(y))
859 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
860 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
862 /* Reenable RTC updates and interrupts. */
863 writertc(RTC_STATUSB, rtc_statusb);
869 * Start both clocks running. DragonFly note: the stat clock is no longer
870 * used. Instead, 8254 based systimers are used for all major clock
871 * interrupts. statclock_disable is set by default.
879 struct intrec *clkdesc;
882 if (statclock_disable) {
884 * The stat interrupt mask is different without the
885 * statistics clock. Also, don't set the interrupt
886 * flag which would normally cause the RTC to generate
889 stat_imask = HWI_MASK | SWI_MASK;
890 rtc_statusb = RTCSB_24HR;
892 /* Setting stathz to nonzero early helps avoid races. */
893 stathz = RTC_NOPROFRATE;
894 profhz = RTC_PROFRATE;
897 /* Finish initializing 8253 timer 0. */
900 apic_8254_intr = isa_apic_irq(0);
902 if (apic_8254_intr >= 0 ) {
903 if (apic_int_type(0, 0) == 3)
906 /* look for ExtInt on pin 0 */
907 if (apic_int_type(0, 0) == 3) {
908 apic_8254_intr = apic_irq(0, 0);
909 setup_8254_mixed_mode();
911 panic("APIC_IO: Cannot route 8254 interrupt to CPU");
914 clkdesc = inthand_add("clk", apic_8254_intr, (inthand2_t *)clkintr,
915 NULL, &clk_imask, INTR_EXCL | INTR_FAST);
916 INTREN(1 << apic_8254_intr);
920 inthand_add("clk", 0, (inthand2_t *)clkintr, NULL, &clk_imask,
921 INTR_EXCL | INTR_FAST);
926 /* Initialize RTC. */
927 writertc(RTC_STATUSA, rtc_statusa);
928 writertc(RTC_STATUSB, RTCSB_24HR);
930 if (statclock_disable == 0) {
931 diag = rtcin(RTC_DIAG);
933 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
936 if (isa_apic_irq(8) != 8)
937 panic("APIC RTC != 8");
940 inthand_add("rtc", 8, (inthand2_t *)rtcintr, NULL, &stat_imask,
941 INTR_EXCL | INTR_FAST);
949 writertc(RTC_STATUSB, rtc_statusb);
953 if (apic_8254_trial) {
955 int lastcnt = read_intr_count(apic_8254_intr);
958 * XXX this assumes the 8254 is the cpu timer. Force an
959 * 8254 Timer0 interrupt and wait 1/100s for it to happen,
960 * then see if we got it.
962 printf("APIC_IO: Testing 8254 interrupt delivery\n");
963 cputimer_intr_reload(2); /* XXX assumes 8254 */
964 base = cputimer_count();
965 while (cputimer_count() - base < cputimer_freq / 100)
967 if (read_intr_count(apic_8254_intr) - lastcnt == 0) {
969 * The MP table is broken.
970 * The 8254 was not connected to the specified pin
972 * Workaround: Limited variant of mixed mode.
974 INTRDIS(1 << apic_8254_intr);
975 inthand_remove(clkdesc);
976 printf("APIC_IO: Broken MP table detected: "
977 "8254 is not connected to "
978 "IOAPIC #%d intpin %d\n",
979 int_to_apicintpin[apic_8254_intr].ioapic,
980 int_to_apicintpin[apic_8254_intr].int_pin);
982 * Revoke current ISA IRQ 0 assignment and
983 * configure a fallback interrupt routing from
984 * the 8254 Timer via the 8259 PIC to the
985 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
986 * We reuse the low level interrupt handler number.
988 if (apic_irq(0, 0) < 0) {
989 revoke_apic_irq(apic_8254_intr);
990 assign_apic_irq(0, 0, apic_8254_intr);
992 apic_8254_intr = apic_irq(0, 0);
993 setup_8254_mixed_mode();
994 inthand_add("clk", apic_8254_intr,
995 (inthand2_t *)clkintr,
996 NULL, &clk_imask, INTR_EXCL | INTR_FAST);
997 INTREN(1 << apic_8254_intr);
1001 if (apic_int_type(0, 0) != 3 ||
1002 int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
1003 int_to_apicintpin[apic_8254_intr].int_pin != 0) {
1004 printf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1005 int_to_apicintpin[apic_8254_intr].ioapic,
1006 int_to_apicintpin[apic_8254_intr].int_pin);
1009 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
1017 read_intr_count(int vec)
1020 up = intr_countp[vec];
1027 setup_8254_mixed_mode()
1030 * Allow 8254 timer to INTerrupt 8259:
1031 * re-initialize master 8259:
1032 * reset; prog 4 bytes, single ICU, edge triggered
1034 outb(IO_ICU1, 0x13);
1035 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */
1036 outb(IO_ICU1 + 1, 0x00); /* ignore slave */
1037 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
1038 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
1040 /* program IO APIC for type 3 INT on INT0 */
1041 if (ext_int_setup(0, 0) < 0)
1042 panic("8254 redirect via APIC pin0 impossible!");
1047 setstatclockrate(int newhz)
1049 if (newhz == RTC_PROFRATE)
1050 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1052 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1053 writertc(RTC_STATUSA, rtc_statusa);
1058 tsc_get_timecount(struct timecounter *tc)
1064 #ifdef KERN_TIMESTAMP
1065 #define KERN_TIMESTAMP_SIZE 16384
1066 static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1067 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1068 sizeof(tsc), "LU", "Kernel timestamps");
1074 tsc[i] = (u_int32_t)rdtsc();
1077 if (i >= KERN_TIMESTAMP_SIZE)
1079 tsc[i] = 0; /* mark last entry */
1081 #endif /* KERN_TIMESTAMP */
1088 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS)
1095 count = cputimer_count();
1101 snprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval);
1102 return(SYSCTL_OUT(req, buf, strlen(buf) + 1));
1105 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254");
1106 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &cputimer_freq, 0, "");
1107 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD,
1108 0, 0, hw_i8254_timestamp, "A", "");