2 * Copyright (c) 1990 William Jolitz.
3 * Copyright (c) 1991 The Regents of the University of California.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by the University of
17 * California, Berkeley and its contributors.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
35 * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $
36 * $DragonFly: src/sys/i386/isa/Attic/npx.c,v 1.22 2005/01/31 23:44:35 joerg Exp $
40 #include "opt_debug_npx.h"
41 #include "opt_math_emulate.h"
43 #include <sys/param.h>
44 #include <sys/systm.h>
46 #include <sys/kernel.h>
47 #include <sys/malloc.h>
48 #include <sys/module.h>
49 #include <sys/sysctl.h>
51 #include <machine/bus.h>
54 #include <sys/syslog.h>
56 #include <sys/signalvar.h>
57 #include <sys/thread2.h>
60 #include <machine/asmacros.h>
62 #include <machine/cputypes.h>
63 #include <machine/frame.h>
64 #include <machine/ipl.h>
65 #include <machine/md_var.h>
66 #include <machine/pcb.h>
67 #include <machine/psl.h>
69 #include <machine/clock.h>
71 #include <machine/resource.h>
72 #include <machine/specialreg.h>
73 #include <machine/segments.h>
74 #include <machine/globaldata.h>
77 #include <i386/isa/icu.h>
78 #include <i386/isa/intr_machdep.h>
79 #include <bus/isa/i386/isa.h>
83 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
86 /* Configuration flags. */
87 #define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0)
88 #define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1)
89 #define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2)
90 #define NPX_PREFER_EMULATOR (1 << 3)
94 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr)))
95 #define fnclex() __asm("fnclex")
96 #define fninit() __asm("fninit")
97 #define fnop() __asm("fnop")
98 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr)))
99 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
100 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr)))
101 #define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop")
102 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr)))
103 #ifndef CPU_DISABLE_SSE
104 #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr)))
105 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
107 #define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
108 : : "n" (CR0_TS) : "ax")
109 #define stop_emulating() __asm("clts")
111 #else /* not __GNUC__ */
113 void fldcw (caddr_t addr);
117 void fnsave (caddr_t addr);
118 void fnstcw (caddr_t addr);
119 void fnstsw (caddr_t addr);
120 void fp_divide_by_0 (void);
121 void frstor (caddr_t addr);
122 #ifndef CPU_DISABLE_SSE
123 void fxsave (caddr_t addr);
124 void fxrstor (caddr_t addr);
126 void start_emulating (void);
127 void stop_emulating (void);
129 #endif /* __GNUC__ */
131 #ifndef CPU_DISABLE_SSE
132 #define GET_FPU_EXSW_PTR(td) \
134 &(td)->td_savefpu->sv_xmm.sv_ex_sw : \
135 &(td)->td_savefpu->sv_87.sv_ex_sw)
136 #else /* CPU_DISABLE_SSE */
137 #define GET_FPU_EXSW_PTR(td) \
138 (&(td)->td_savefpu->sv_87.sv_ex_sw)
139 #endif /* CPU_DISABLE_SSE */
141 typedef u_char bool_t;
143 static int npx_attach (device_t dev);
144 void npx_intr (void *);
145 static void npx_identify (driver_t *driver, device_t parent);
146 static int npx_probe (device_t dev);
147 static int npx_probe1 (device_t dev);
148 static void fpusave (union savefpu *);
149 static void fpurstor (union savefpu *);
151 int hw_float; /* XXX currently just alias for npx_exists */
153 SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint,
154 CTLFLAG_RD, &hw_float, 0,
155 "Floatingpoint instructions executed in hardware");
156 #if (defined(I586_CPU) || defined(I686_CPU)) && !defined(CPU_DISABLE_SSE)
158 SYSCTL_INT(_kern, OID_AUTO, mmxopt, CTLFLAG_RD, &mmxopt, 0,
159 "MMX/XMM optimized bcopy/copyin/copyout support");
163 static u_int npx0_imask = SWI_CLOCK_MASK;
164 static struct gate_descriptor npx_idt_probeintr;
165 static int npx_intrno;
166 static volatile u_int npx_intrs_while_probing;
167 static volatile u_int npx_traps_while_probing;
170 static bool_t npx_ex16;
171 static bool_t npx_exists;
172 static bool_t npx_irq13;
173 static int npx_irq; /* irq number */
177 * Special interrupt handlers. Someday intr0-intr15 will be used to count
178 * interrupts. We'll still need a special exception 16 handler. The busy
179 * latch stuff in probeintr() can be moved to npxprobe().
185 .type " __XSTRING(CNAME(probeintr)) ",@function \n\
186 " __XSTRING(CNAME(probeintr)) ": \n\
188 incl " __XSTRING(CNAME(npx_intrs_while_probing)) " \n\
190 movb $0x20,%al # EOI (asm in strings loses cpp features) \n\
191 outb %al,$0xa0 # IO_ICU2 \n\
192 outb %al,$0x20 # IO_ICU1 \n\
194 outb %al,$0xf0 # clear BUSY# latch \n\
203 .type " __XSTRING(CNAME(probetrap)) ",@function \n\
204 " __XSTRING(CNAME(probetrap)) ": \n\
206 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\
213 * Identify routine. Create a connection point on our parent for probing.
216 npx_identify(driver_t *driver, device_t parent)
220 child = BUS_ADD_CHILD(parent, 0, "npx", 0);
222 panic("npx_identify");
226 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait
227 * whether the device exists or not (XXX should be elsewhere). Set flags
228 * to tell npxattach() what to do. Modify device struct if npx doesn't
229 * need to use interrupts. Return 1 if device exists.
232 npx_probe(device_t dev)
236 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0)
238 return npx_probe1(dev);
244 u_char save_icu1_mask;
245 u_char save_icu2_mask;
246 struct gate_descriptor save_idt_npxintr;
247 struct gate_descriptor save_idt_npxtrap;
249 * This routine is now just a wrapper for npxprobe1(), to install
250 * special npx interrupt and trap handlers, to enable npx interrupts
251 * and to disable other interrupts. Someday isa_configure() will
252 * install suitable handlers and run with interrupts enabled so we
253 * won't need to do so much here.
255 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0)
257 npx_intrno = NRSVIDT + npx_irq;
258 save_eflags = read_eflags();
260 save_icu1_mask = inb(IO_ICU1 + 1);
261 save_icu2_mask = inb(IO_ICU2 + 1);
262 save_idt_npxintr = idt[npx_intrno];
263 save_idt_npxtrap = idt[16];
264 outb(IO_ICU1 + 1, ~IRQ_SLAVE);
265 outb(IO_ICU2 + 1, ~(1 << (npx_irq - 8)));
266 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
267 setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
268 npx_idt_probeintr = idt[npx_intrno];
270 result = npx_probe1(dev);
272 outb(IO_ICU1 + 1, save_icu1_mask);
273 outb(IO_ICU2 + 1, save_icu2_mask);
274 idt[npx_intrno] = save_idt_npxintr;
275 idt[16] = save_idt_npxtrap;
276 write_eflags(save_eflags);
283 npx_probe1(device_t dev)
291 * Partially reset the coprocessor, if any. Some BIOS's don't reset
292 * it after a warm boot.
294 outb(0xf1, 0); /* full reset on some systems, NOP on others */
295 outb(0xf0, 0); /* clear BUSY# latch */
297 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT
298 * instructions. We must set the CR0_MP bit and use the CR0_TS
299 * bit to control the trap, because setting the CR0_EM bit does
300 * not cause WAIT instructions to trap. It's important to trap
301 * WAIT instructions - otherwise the "wait" variants of no-wait
302 * control instructions would degenerate to the "no-wait" variants
303 * after FP context switches but work correctly otherwise. It's
304 * particularly important to trap WAITs when there is no NPX -
305 * otherwise the "wait" variants would always degenerate.
307 * Try setting CR0_NE to get correct error reporting on 486DX's.
308 * Setting it should fail or do nothing on lesser processors.
310 load_cr0(rcr0() | CR0_MP | CR0_NE);
312 * But don't trap while we're probing.
316 * Finish resetting the coprocessor, if any. If there is an error
317 * pending, then we may get a bogus IRQ13, but probeintr() will handle
318 * it OK. Bogus halts have never been observed, but we enabled
319 * IRQ13 and cleared the BUSY# latch early to handle them anyway.
325 * Exception 16 MUST work for SMP.
328 npx_ex16 = hw_float = npx_exists = 1;
329 device_set_desc(dev, "math processor");
333 device_set_desc(dev, "math processor");
336 * Don't use fwait here because it might hang.
337 * Don't use fnop here because it usually hangs if there is no FPU.
339 DELAY(1000); /* wait for any IRQ13 */
341 if (npx_intrs_while_probing != 0)
342 printf("fninit caused %u bogus npx interrupt(s)\n",
343 npx_intrs_while_probing);
344 if (npx_traps_while_probing != 0)
345 printf("fninit caused %u bogus npx trap(s)\n",
346 npx_traps_while_probing);
349 * Check for a status of mostly zero.
353 if ((status & 0xb8ff) == 0) {
355 * Good, now check for a proper control word.
359 if ((control & 0x1f3f) == 0x033f) {
360 hw_float = npx_exists = 1;
362 * We have an npx, now divide by 0 to see if exception
365 control &= ~(1 << 2); /* enable divide by 0 trap */
367 npx_traps_while_probing = npx_intrs_while_probing = 0;
369 if (npx_traps_while_probing != 0) {
371 * Good, exception 16 works.
376 if (npx_intrs_while_probing != 0) {
381 * Bad, we are stuck with IRQ13.
385 * npxattach would be too late to set npx0_imask
387 npx0_imask |= (1 << npx_irq);
390 * We allocate these resources permanently,
391 * so there is no need to keep track of them.
394 r = bus_alloc_resource(dev, SYS_RES_IOPORT,
395 &rid, IO_NPX, IO_NPX,
396 IO_NPXSIZE, RF_ACTIVE);
398 panic("npx: can't get ports");
400 r = bus_alloc_resource(dev, SYS_RES_IRQ,
401 &rid, npx_irq, npx_irq,
404 panic("npx: can't get IRQ");
405 BUS_SETUP_INTR(device_get_parent(dev),
406 dev, r, INTR_TYPE_MISC,
409 panic("npx: can't create intr");
414 * Worse, even IRQ13 is broken. Use emulator.
419 * Probe failed, but we want to get to npxattach to initialize the
420 * emulator and say that it has been installed. XXX handle devices
421 * that aren't really devices better.
428 * Attach routine - announce which it is, and wire into system
431 npx_attach(device_t dev)
435 if (resource_int_value("npx", 0, "flags", &flags) != 0)
439 device_printf(dev, "flags 0x%x ", flags);
441 device_printf(dev, "using IRQ 13 interface\n");
443 #if defined(MATH_EMULATE)
445 if (!(flags & NPX_PREFER_EMULATOR))
446 device_printf(dev, "INT 16 interface\n");
448 device_printf(dev, "FPU exists, but flags request "
450 hw_float = npx_exists = 0;
452 } else if (npx_exists) {
453 device_printf(dev, "error reporting broken; using 387 emulator\n");
454 hw_float = npx_exists = 0;
456 device_printf(dev, "387 emulator\n");
459 device_printf(dev, "INT 16 interface\n");
460 if (flags & NPX_PREFER_EMULATOR) {
461 device_printf(dev, "emulator requested, but none compiled "
462 "into kernel, using FPU\n");
465 device_printf(dev, "no 387 emulator in kernel and no FPU!\n");
468 npxinit(__INITIAL_NPXCW__);
470 #if (defined(I586_CPU) || defined(I686_CPU)) && !defined(CPU_DISABLE_SSE)
472 * The asm_mmx_*() routines actually use XMM as well, so only
473 * enable them if we have SSE2 and are using FXSR (fxsave/fxrstore).
475 TUNABLE_INT_FETCH("kern.mmxopt", &mmxopt);
476 if ((cpu_feature & CPUID_MMX) && (cpu_feature & CPUID_SSE) &&
477 (cpu_feature & CPUID_SSE2) &&
478 npx_ex16 && npx_exists && mmxopt && cpu_fxsr
480 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY) == 0) {
481 bcopy_vector = (void **)asm_xmm_bcopy;
482 ovbcopy_vector = (void **)asm_xmm_bcopy;
483 memcpy_vector = (void **)asm_xmm_memcpy;
484 printf("Using XMM optimized bcopy/copyin/copyout\n");
486 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BZERO) == 0) {
489 } else if ((cpu_feature & CPUID_MMX) && (cpu_feature & CPUID_SSE) &&
490 npx_ex16 && npx_exists && mmxopt && cpu_fxsr
492 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY) == 0) {
493 bcopy_vector = (void **)asm_mmx_bcopy;
494 ovbcopy_vector = (void **)asm_mmx_bcopy;
495 memcpy_vector = (void **)asm_mmx_memcpy;
496 printf("Using MMX optimized bcopy/copyin/copyout\n");
498 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BZERO) == 0) {
504 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists &&
505 timezero("i586_bzero()", i586_bzero) <
506 timezero("bzero()", bzero) * 4 / 5) {
507 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) {
508 bcopy_vector = i586_bcopy;
509 ovbcopy_vector = i586_bcopy;
511 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO))
513 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) {
514 copyin_vector = i586_copyin;
515 copyout_vector = i586_copyout;
519 return (0); /* XXX unused */
523 * Initialize the floating point unit.
526 npxinit(u_short control)
528 static union savefpu dummy;
533 * fninit has the same h/w bugs as fnsave. Use the detoxified
534 * fnsave to throw away any junk in the fpu. npxsave() initializes
535 * the fpu and sets npxthread = NULL as important side effects.
541 fpusave(curthread->td_savefpu);
542 mdcpu->gd_npxthread = NULL;
548 * Free coprocessor (if we have it).
551 npxexit(struct proc *p)
553 if (p->p_thread == mdcpu->gd_npxthread)
554 npxsave(curthread->td_savefpu);
557 u_int masked_exceptions;
560 curthread->td_savefpu->sv_87.sv_env.en_cw
561 & curthread->td_savefpu->sv_87.sv_env.en_sw & 0x7f;
563 * Log exceptions that would have trapped with the old
564 * control word (overflow, divide by 0, and invalid operand).
566 if (masked_exceptions & 0x0d)
568 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n",
569 p->p_pid, p->p_comm, masked_exceptions);
575 * The following mechanism is used to ensure that the FPE_... value
576 * that is passed as a trapcode to the signal handler of the user
577 * process does not have more than one bit set.
579 * Multiple bits may be set if the user process modifies the control
580 * word while a status word bit is already set. While this is a sign
581 * of bad coding, we have no choise than to narrow them down to one
582 * bit, since we must not send a trapcode that is not exactly one of
585 * The mechanism has a static table with 127 entries. Each combination
586 * of the 7 FPU status word exception bits directly translates to a
587 * position in this table, where a single FPE_... value is stored.
588 * This FPE_... value stored there is considered the "most important"
589 * of the exception bits and will be sent as the signal code. The
590 * precedence of the bits is based upon Intel Document "Numerical
591 * Applications", Chapter "Special Computational Situations".
593 * The macro to choose one of these values does these steps: 1) Throw
594 * away status word bits that cannot be masked. 2) Throw away the bits
595 * currently masked in the control word, assuming the user isn't
596 * interested in them anymore. 3) Reinsert status word bit 7 (stack
597 * fault) if it is set, which cannot be masked but must be presered.
598 * 4) Use the remaining bits to point into the trapcode table.
600 * The 6 maskable bits in order of their preference, as stated in the
601 * above referenced Intel manual:
602 * 1 Invalid operation (FP_X_INV)
605 * 1c Operand of unsupported format
607 * 2 QNaN operand (not an exception, irrelavant here)
608 * 3 Any other invalid-operation not mentioned above or zero divide
609 * (FP_X_INV, FP_X_DZ)
610 * 4 Denormal operand (FP_X_DNML)
611 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
612 * 6 Inexact result (FP_X_IMP)
614 static char fpetable[128] = {
616 FPE_FLTINV, /* 1 - INV */
617 FPE_FLTUND, /* 2 - DNML */
618 FPE_FLTINV, /* 3 - INV | DNML */
619 FPE_FLTDIV, /* 4 - DZ */
620 FPE_FLTINV, /* 5 - INV | DZ */
621 FPE_FLTDIV, /* 6 - DNML | DZ */
622 FPE_FLTINV, /* 7 - INV | DNML | DZ */
623 FPE_FLTOVF, /* 8 - OFL */
624 FPE_FLTINV, /* 9 - INV | OFL */
625 FPE_FLTUND, /* A - DNML | OFL */
626 FPE_FLTINV, /* B - INV | DNML | OFL */
627 FPE_FLTDIV, /* C - DZ | OFL */
628 FPE_FLTINV, /* D - INV | DZ | OFL */
629 FPE_FLTDIV, /* E - DNML | DZ | OFL */
630 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
631 FPE_FLTUND, /* 10 - UFL */
632 FPE_FLTINV, /* 11 - INV | UFL */
633 FPE_FLTUND, /* 12 - DNML | UFL */
634 FPE_FLTINV, /* 13 - INV | DNML | UFL */
635 FPE_FLTDIV, /* 14 - DZ | UFL */
636 FPE_FLTINV, /* 15 - INV | DZ | UFL */
637 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
638 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
639 FPE_FLTOVF, /* 18 - OFL | UFL */
640 FPE_FLTINV, /* 19 - INV | OFL | UFL */
641 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
642 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
643 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
644 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
645 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
646 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
647 FPE_FLTRES, /* 20 - IMP */
648 FPE_FLTINV, /* 21 - INV | IMP */
649 FPE_FLTUND, /* 22 - DNML | IMP */
650 FPE_FLTINV, /* 23 - INV | DNML | IMP */
651 FPE_FLTDIV, /* 24 - DZ | IMP */
652 FPE_FLTINV, /* 25 - INV | DZ | IMP */
653 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
654 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
655 FPE_FLTOVF, /* 28 - OFL | IMP */
656 FPE_FLTINV, /* 29 - INV | OFL | IMP */
657 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
658 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
659 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
660 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
661 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
662 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
663 FPE_FLTUND, /* 30 - UFL | IMP */
664 FPE_FLTINV, /* 31 - INV | UFL | IMP */
665 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
666 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
667 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
668 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
669 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
670 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
671 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
672 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
673 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
674 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
675 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
676 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
677 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
678 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
679 FPE_FLTSUB, /* 40 - STK */
680 FPE_FLTSUB, /* 41 - INV | STK */
681 FPE_FLTUND, /* 42 - DNML | STK */
682 FPE_FLTSUB, /* 43 - INV | DNML | STK */
683 FPE_FLTDIV, /* 44 - DZ | STK */
684 FPE_FLTSUB, /* 45 - INV | DZ | STK */
685 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
686 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
687 FPE_FLTOVF, /* 48 - OFL | STK */
688 FPE_FLTSUB, /* 49 - INV | OFL | STK */
689 FPE_FLTUND, /* 4A - DNML | OFL | STK */
690 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
691 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
692 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
693 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
694 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
695 FPE_FLTUND, /* 50 - UFL | STK */
696 FPE_FLTSUB, /* 51 - INV | UFL | STK */
697 FPE_FLTUND, /* 52 - DNML | UFL | STK */
698 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
699 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
700 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
701 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
702 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
703 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
704 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
705 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
706 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
707 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
708 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
709 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
710 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
711 FPE_FLTRES, /* 60 - IMP | STK */
712 FPE_FLTSUB, /* 61 - INV | IMP | STK */
713 FPE_FLTUND, /* 62 - DNML | IMP | STK */
714 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
715 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
716 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
717 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
718 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
719 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
720 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
721 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
722 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
723 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
724 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
725 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
726 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
727 FPE_FLTUND, /* 70 - UFL | IMP | STK */
728 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
729 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
730 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
731 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
732 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
733 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
734 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
735 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
736 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
737 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
738 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
739 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
740 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
741 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
742 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
746 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
748 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now
749 * depend on longjmp() restoring a usable state. Restoring the state
750 * or examining it might fail if we didn't clear exceptions.
752 * The error code chosen will be one of the FPE_... macros. It will be
753 * sent as the second argument to old BSD-style signal handlers and as
754 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
756 * XXX the FP state is not preserved across signal handlers. So signal
757 * handlers cannot afford to do FP unless they preserve the state or
758 * longjmp() out. Both preserving the state and longjmp()ing may be
759 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable
760 * solution for signals other than SIGFPE.
762 * The MP lock is not held on entry (see i386/i386/exception.s) and
763 * should not be held on exit.
766 npx_intr(void *dummy)
770 struct intrframe *frame;
773 if (mdcpu->gd_npxthread == NULL || !npx_exists) {
775 printf("npxintr: npxthread = %p, curthread = %p, npx_exists = %d\n",
776 mdcpu->gd_npxthread, curthread, npx_exists);
777 panic("npxintr from nowhere");
779 if (mdcpu->gd_npxthread != curthread) {
781 printf("npxintr: npxthread = %p, curthread = %p, npx_exists = %d\n",
782 mdcpu->gd_npxthread, curthread, npx_exists);
783 panic("npxintr from non-current process");
786 exstat = GET_FPU_EXSW_PTR(curthread);
795 * Pass exception to process.
797 frame = (struct intrframe *)&dummy; /* XXX */
798 if ((ISPL(frame->if_cs) == SEL_UPL) || (frame->if_eflags & PSL_VM)) {
800 * Interrupt is essentially a trap, so we can afford to call
801 * the SIGFPE handler (if any) as soon as the interrupt
804 * XXX little or nothing is gained from this, and plenty is
805 * lost - the interrupt frame has to contain the trap frame
806 * (this is otherwise only necessary for the rescheduling trap
807 * in doreti, and the frame for that could easily be set up
808 * just before it is used).
810 curproc->p_md.md_regs = INTR_TO_TRAPFRAME(frame);
812 * Encode the appropriate code for detailed information on
816 fpetable[(*exstat & ~control & 0x3f) | (*exstat & 0x40)];
817 trapsignal(curproc, SIGFPE, code);
820 * Nested interrupt. These losers occur when:
821 * o an IRQ13 is bogusly generated at a bogus time, e.g.:
822 * o immediately after an fnsave or frstor of an
824 * o a couple of 386 instructions after
825 * "fstpl _memvar" causes a stack overflow.
826 * These are especially nasty when combined with a
828 * o an IRQ13 occurs at the same time as another higher-
829 * priority interrupt.
831 * Treat them like a true async interrupt.
833 psignal(curproc, SIGFPE);
839 * Implement the device not available (DNA) exception. gd_npxthread had
840 * better be NULL. Restore the current thread's FP state and set gd_npxthread
850 if (mdcpu->gd_npxthread != NULL) {
851 printf("npxdna: npxthread = %p, curthread = %p\n",
852 mdcpu->gd_npxthread, curthread);
856 * The setting of gd_npxthread and the call to fpurstor() must not
857 * be preempted by an interrupt thread or we will take an npxdna
858 * trap and potentially save our current fpstate (which is garbage)
859 * and then restore the garbage rather then the originally saved
865 * Record new context early in case frstor causes an IRQ13.
867 mdcpu->gd_npxthread = curthread;
868 exstat = GET_FPU_EXSW_PTR(curthread);
871 * The following frstor may cause an IRQ13 when the state being
872 * restored has a pending error. The error will appear to have been
873 * triggered by the current (npx) user instruction even when that
874 * instruction is a no-wait instruction that should not trigger an
875 * error (e.g., fnclex). On at least one 486 system all of the
876 * no-wait instructions are broken the same as frstor, so our
877 * treatment does not amplify the breakage. On at least one
878 * 386/Cyrix 387 system, fnclex works correctly while frstor and
879 * fnsave are broken, so our treatment breaks fnclex if it is the
880 * first FPU instruction after a context switch.
882 fpurstor(curthread->td_savefpu);
889 * Wrapper for the fnsave instruction to handle h/w bugs. If there is an error
890 * pending, then fnsave generates a bogus IRQ13 on some systems. Force
891 * any IRQ13 to be handled immediately, and then ignore it. This routine is
892 * often called at splhigh so it must not use many system services. In
893 * particular, it's much easier to install a special handler than to
894 * guarantee that it's safe to use npxintr() and its supporting code.
896 * WARNING! This call is made during a switch and the MP lock will be
897 * setup for the new target thread rather then the current thread, so we
898 * cannot do anything here that depends on the *_mplock() functions as
899 * we may trip over their assertions.
901 * WARNING! When using fxsave we MUST fninit after saving the FP state. The
902 * kernel will always assume that the FP state is 'safe' (will not cause
903 * exceptions) for mmx/xmm use if npxthread is NULL. The kernel must still
904 * setup a custom save area before actually using the FP unit, but it will
905 * not bother calling fninit. This greatly improves kernel performance when
906 * it wishes to use the FP unit.
909 npxsave(union savefpu *addr)
911 #if defined(SMP) || !defined(CPU_DISABLE_SSE)
916 mdcpu->gd_npxthread = NULL;
921 #else /* !SMP and CPU_DISABLE_SSE */
925 u_char old_icu1_mask;
926 u_char old_icu2_mask;
927 struct gate_descriptor save_idt_npxintr;
930 save_eflags = read_eflags();
932 old_icu1_mask = inb(IO_ICU1 + 1);
933 old_icu2_mask = inb(IO_ICU2 + 1);
934 save_idt_npxintr = idt[npx_intrno];
935 outb(IO_ICU1 + 1, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask));
936 outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8));
937 idt[npx_intrno] = npx_idt_probeintr;
943 mdcpu->gd_npxthread = NULL;
945 icu1_mask = inb(IO_ICU1 + 1); /* masks may have changed */
946 icu2_mask = inb(IO_ICU2 + 1);
948 (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask));
950 (icu2_mask & ~(npx0_imask >> 8))
951 | (old_icu2_mask & (npx0_imask >> 8)));
952 idt[npx_intrno] = save_idt_npxintr;
953 write_eflags(save_eflags); /* back to usual state */
959 fpusave(union savefpu *addr)
961 #ifndef CPU_DISABLE_SSE
970 fpurstor(union savefpu *addr)
972 #ifndef CPU_DISABLE_SSE
980 static device_method_t npx_methods[] = {
981 /* Device interface */
982 DEVMETHOD(device_identify, npx_identify),
983 DEVMETHOD(device_probe, npx_probe),
984 DEVMETHOD(device_attach, npx_attach),
985 DEVMETHOD(device_detach, bus_generic_detach),
986 DEVMETHOD(device_shutdown, bus_generic_shutdown),
987 DEVMETHOD(device_suspend, bus_generic_suspend),
988 DEVMETHOD(device_resume, bus_generic_resume),
993 static driver_t npx_driver = {
999 static devclass_t npx_devclass;
1002 * We prefer to attach to the root nexus so that the usual case (exception 16)
1003 * doesn't describe the processor as being `on isa'.
1005 DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0);