2 * Copyright (c) 1999,2000,2001 Jonathan Lemon
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * $FreeBSD: src/sys/dev/gx/if_gx.c,v 1.2.2.3 2001/12/14 19:51:39 jlemon Exp $
30 * $DragonFly: src/sys/dev/netif/gx/Attic/if_gx.c,v 1.5 2004/01/06 01:40:48 dillon Exp $
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/sockio.h>
37 #include <sys/malloc.h>
38 #include <sys/kernel.h>
39 #include <sys/socket.h>
40 #include <sys/queue.h>
43 #include <net/if_arp.h>
44 #include <net/ethernet.h>
45 #include <net/if_dl.h>
46 #include <net/if_media.h>
49 #include <net/if_types.h>
50 #include <net/vlan/if_vlan_var.h>
52 #include <netinet/in_systm.h>
53 #include <netinet/in.h>
54 #include <netinet/ip.h>
55 #include <netinet/tcp.h>
56 #include <netinet/udp.h>
58 #include <vm/vm.h> /* for vtophys */
59 #include <vm/pmap.h> /* for vtophys */
60 #include <machine/clock.h> /* for DELAY */
61 #include <machine/bus_memio.h>
62 #include <machine/bus.h>
63 #include <machine/resource.h>
67 #include <bus/pci/pcireg.h>
68 #include <bus/pci/pcivar.h>
70 #include "../mii_layer/mii.h"
71 #include "../mii_layer/miivar.h"
76 #include "miibus_if.h"
78 #define TUNABLE_TX_INTR_DELAY 100
79 #define TUNABLE_RX_INTR_DELAY 100
81 #define GX_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
84 * Various supported device vendors/types and their names.
90 u_int32_t version_ipg;
94 static struct gx_device gx_devs[] = {
95 { INTEL_VENDORID, DEVICEID_WISEMAN,
96 GXF_FORCE_TBI | GXF_OLD_REGS,
97 10 | 2 << 10 | 10 << 20,
98 "Intel Gigabit Ethernet (82542)" },
99 { INTEL_VENDORID, DEVICEID_LIVINGOOD_FIBER,
100 GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
101 6 | 8 << 10 | 6 << 20,
102 "Intel Gigabit Ethernet (82543GC-F)" },
103 { INTEL_VENDORID, DEVICEID_LIVINGOOD_COPPER,
104 GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
105 8 | 8 << 10 | 6 << 20,
106 "Intel Gigabit Ethernet (82543GC-T)" },
109 { INTEL_VENDORID, DEVICEID_CORDOVA_FIBER,
110 GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
111 6 | 8 << 10 | 6 << 20,
112 "Intel Gigabit Ethernet (82544EI-F)" },
113 { INTEL_VENDORID, DEVICEID_CORDOVA_COPPER,
114 GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
115 8 | 8 << 10 | 6 << 20,
116 "Intel Gigabit Ethernet (82544EI-T)" },
117 { INTEL_VENDORID, DEVICEID_CORDOVA2_COPPER,
118 GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
119 8 | 8 << 10 | 6 << 20,
120 "Intel Gigabit Ethernet (82544GC-T)" },
125 static struct gx_regs new_regs = {
126 GX_RX_RING_BASE, GX_RX_RING_LEN,
127 GX_RX_RING_HEAD, GX_RX_RING_TAIL,
128 GX_RX_INTR_DELAY, GX_RX_DMA_CTRL,
130 GX_TX_RING_BASE, GX_TX_RING_LEN,
131 GX_TX_RING_HEAD, GX_TX_RING_TAIL,
132 GX_TX_INTR_DELAY, GX_TX_DMA_CTRL,
134 static struct gx_regs old_regs = {
135 GX_RX_OLD_RING_BASE, GX_RX_OLD_RING_LEN,
136 GX_RX_OLD_RING_HEAD, GX_RX_OLD_RING_TAIL,
137 GX_RX_OLD_INTR_DELAY, GX_RX_OLD_DMA_CTRL,
139 GX_TX_OLD_RING_BASE, GX_TX_OLD_RING_LEN,
140 GX_TX_OLD_RING_HEAD, GX_TX_OLD_RING_TAIL,
141 GX_TX_OLD_INTR_DELAY, GX_TX_OLD_DMA_CTRL,
144 static int gx_probe(device_t dev);
145 static int gx_attach(device_t dev);
146 static int gx_detach(device_t dev);
147 static void gx_shutdown(device_t dev);
149 static void gx_intr(void *xsc);
150 static void gx_init(void *xsc);
152 static struct gx_device *gx_match(device_t dev);
153 static void gx_eeprom_getword(struct gx_softc *gx, int addr,
155 static int gx_read_eeprom(struct gx_softc *gx, caddr_t dest, int off,
157 static int gx_ifmedia_upd(struct ifnet *ifp);
158 static void gx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
159 static int gx_miibus_readreg(device_t dev, int phy, int reg);
160 static void gx_miibus_writereg(device_t dev, int phy, int reg, int value);
161 static void gx_miibus_statchg(device_t dev);
162 static int gx_ioctl(struct ifnet *ifp, u_long command, caddr_t data);
163 static void gx_setmulti(struct gx_softc *gx);
164 static void gx_reset(struct gx_softc *gx);
165 static void gx_phy_reset(struct gx_softc *gx);
166 static void gx_release(struct gx_softc *gx);
167 static void gx_stop(struct gx_softc *gx);
168 static void gx_watchdog(struct ifnet *ifp);
169 static void gx_start(struct ifnet *ifp);
171 static int gx_init_rx_ring(struct gx_softc *gx);
172 static void gx_free_rx_ring(struct gx_softc *gx);
173 static int gx_init_tx_ring(struct gx_softc *gx);
174 static void gx_free_tx_ring(struct gx_softc *gx);
176 static device_method_t gx_methods[] = {
177 /* Device interface */
178 DEVMETHOD(device_probe, gx_probe),
179 DEVMETHOD(device_attach, gx_attach),
180 DEVMETHOD(device_detach, gx_detach),
181 DEVMETHOD(device_shutdown, gx_shutdown),
184 DEVMETHOD(miibus_readreg, gx_miibus_readreg),
185 DEVMETHOD(miibus_writereg, gx_miibus_writereg),
186 DEVMETHOD(miibus_statchg, gx_miibus_statchg),
191 static driver_t gx_driver = {
194 sizeof(struct gx_softc)
197 static devclass_t gx_devclass;
199 DECLARE_DUMMY_MODULE(if_gx);
200 MODULE_DEPEND(if_gx, miibus, 1, 1, 1);
201 DRIVER_MODULE(if_gx, pci, gx_driver, gx_devclass, 0, 0);
202 DRIVER_MODULE(miibus, gx, miibus_driver, miibus_devclass, 0, 0);
204 static struct gx_device *
205 gx_match(device_t dev)
209 for (i = 0; gx_devs[i].name != NULL; i++) {
210 if ((pci_get_vendor(dev) == gx_devs[i].vendor) &&
211 (pci_get_device(dev) == gx_devs[i].device))
212 return (&gx_devs[i]);
218 gx_probe(device_t dev)
220 struct gx_device *gx_dev;
222 gx_dev = gx_match(dev);
226 device_set_desc(dev, gx_dev->name);
231 gx_attach(device_t dev)
234 struct gx_device *gx_dev;
242 gx = device_get_softc(dev);
243 bzero(gx, sizeof(struct gx_softc));
246 gx_dev = gx_match(dev);
247 gx->gx_vflags = gx_dev->version_flags;
248 gx->gx_ipg = gx_dev->version_ipg;
250 mtx_init(&gx->gx_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
255 * Map control/status registers.
257 command = pci_read_config(dev, PCIR_COMMAND, 4);
258 command |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
259 if (gx->gx_vflags & GXF_ENABLE_MWI)
260 command |= PCIM_CMD_MWIEN;
261 pci_write_config(dev, PCIR_COMMAND, command, 4);
262 command = pci_read_config(dev, PCIR_COMMAND, 4);
264 /* XXX check cache line size? */
266 if ((command & PCIM_CMD_MEMEN) == 0) {
267 device_printf(dev, "failed to enable memory mapping!\n");
273 gx->gx_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
274 0, ~0, 1, RF_ACTIVE);
276 /* support PIO mode */
278 gx->gx_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
279 0, ~0, 1, RF_ACTIVE);
282 if (gx->gx_res == NULL) {
283 device_printf(dev, "couldn't map memory\n");
288 gx->gx_btag = rman_get_bustag(gx->gx_res);
289 gx->gx_bhandle = rman_get_bushandle(gx->gx_res);
291 /* Allocate interrupt */
293 gx->gx_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
294 RF_SHAREABLE | RF_ACTIVE);
296 if (gx->gx_irq == NULL) {
297 device_printf(dev, "couldn't map interrupt\n");
302 error = bus_setup_intr(dev, gx->gx_irq, INTR_TYPE_NET,
303 gx_intr, gx, &gx->gx_intrhand);
305 device_printf(dev, "couldn't setup irq\n");
309 /* compensate for different register mappings */
310 if (gx->gx_vflags & GXF_OLD_REGS)
311 gx->gx_reg = old_regs;
313 gx->gx_reg = new_regs;
315 if (gx_read_eeprom(gx, (caddr_t)&gx->arpcom.ac_enaddr,
317 device_printf(dev, "failed to read station address\n");
321 device_printf(dev, "Ethernet address: %6D\n",
322 gx->arpcom.ac_enaddr, ":");
324 /* Allocate the ring buffers. */
325 gx->gx_rdata = contigmalloc(sizeof(struct gx_ring_data), M_DEVBUF,
326 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
328 if (gx->gx_rdata == NULL) {
329 device_printf(dev, "no memory for list buffers!\n");
333 bzero(gx->gx_rdata, sizeof(struct gx_ring_data));
335 /* Set default tuneable values. */
336 gx->gx_tx_intr_delay = TUNABLE_TX_INTR_DELAY;
337 gx->gx_rx_intr_delay = TUNABLE_RX_INTR_DELAY;
339 /* Set up ifnet structure */
340 ifp = &gx->arpcom.ac_if;
342 if_initname(ifp, "gx", device_get_unit(dev));
343 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
344 ifp->if_ioctl = gx_ioctl;
345 ifp->if_output = ether_output;
346 ifp->if_start = gx_start;
347 ifp->if_watchdog = gx_watchdog;
348 ifp->if_init = gx_init;
349 ifp->if_mtu = ETHERMTU;
350 ifp->if_snd.ifq_maxlen = GX_TX_RING_CNT - 1;
352 /* see if we can enable hardware checksumming */
353 if (gx->gx_vflags & GXF_CSUM) {
354 ifp->if_capabilities = IFCAP_HWCSUM;
355 ifp->if_capenable = ifp->if_capabilities;
358 /* figure out transciever type */
359 if (gx->gx_vflags & GXF_FORCE_TBI ||
360 CSR_READ_4(gx, GX_STATUS) & GX_STAT_TBIMODE)
363 if (gx->gx_tbimode) {
364 /* SERDES transceiver */
365 ifmedia_init(&gx->gx_media, IFM_IMASK, gx_ifmedia_upd,
367 ifmedia_add(&gx->gx_media,
368 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
369 ifmedia_add(&gx->gx_media, IFM_ETHER|IFM_AUTO, 0, NULL);
370 ifmedia_set(&gx->gx_media, IFM_ETHER|IFM_AUTO);
372 /* GMII/MII transceiver */
374 if (mii_phy_probe(dev, &gx->gx_miibus, gx_ifmedia_upd,
376 device_printf(dev, "GMII/MII, PHY not detected\n");
383 * Call MI attach routines.
385 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
399 gx_release(struct gx_softc *gx)
402 bus_generic_detach(gx->gx_dev);
404 device_delete_child(gx->gx_dev, gx->gx_miibus);
407 bus_teardown_intr(gx->gx_dev, gx->gx_irq, gx->gx_intrhand);
409 bus_release_resource(gx->gx_dev, SYS_RES_IRQ, 0, gx->gx_irq);
411 bus_release_resource(gx->gx_dev, SYS_RES_MEMORY,
412 GX_PCI_LOMEM, gx->gx_res);
418 struct gx_softc *gx = (struct gx_softc *)xsc;
427 ifp = &gx->arpcom.ac_if;
432 /* Disable host interrupts, halt chip. */
435 /* disable I/O, flush RX/TX FIFOs, and free RX/TX buffers */
438 /* Load our MAC address, invalidate other 15 RX addresses. */
439 m = (u_int16_t *)&gx->arpcom.ac_enaddr[0];
440 CSR_WRITE_4(gx, GX_RX_ADDR_BASE, (m[1] << 16) | m[0]);
441 CSR_WRITE_4(gx, GX_RX_ADDR_BASE + 4, m[2] | GX_RA_VALID);
442 for (i = 1; i < 16; i++)
443 CSR_WRITE_8(gx, GX_RX_ADDR_BASE + i * 8, (u_quad_t)0);
445 /* Program multicast filter. */
454 if (gx->gx_vflags & GXF_DMA) {
455 /* set up DMA control */
456 CSR_WRITE_4(gx, gx->gx_reg.r_rx_dma_ctrl, 0x00010000);
457 CSR_WRITE_4(gx, gx->gx_reg.r_tx_dma_ctrl, 0x00000000);
460 /* enable receiver */
461 ctrl = GX_RXC_ENABLE | GX_RXC_RX_THOLD_EIGHTH | GX_RXC_RX_BSIZE_2K;
462 ctrl |= GX_RXC_BCAST_ACCEPT;
464 /* Enable or disable promiscuous mode as needed. */
465 if (ifp->if_flags & IFF_PROMISC)
466 ctrl |= GX_RXC_UNI_PROMISC;
468 /* This is required if we want to accept jumbo frames */
469 if (ifp->if_mtu > ETHERMTU)
470 ctrl |= GX_RXC_LONG_PKT_ENABLE;
472 /* setup receive checksum control */
473 if (ifp->if_capenable & IFCAP_RXCSUM)
474 CSR_WRITE_4(gx, GX_RX_CSUM_CONTROL,
475 GX_CSUM_TCP/* | GX_CSUM_IP*/);
477 /* setup transmit checksum control */
478 if (ifp->if_capenable & IFCAP_TXCSUM)
479 ifp->if_hwassist = GX_CSUM_FEATURES;
481 ctrl |= GX_RXC_STRIP_ETHERCRC; /* not on 82542? */
482 CSR_WRITE_4(gx, GX_RX_CONTROL, ctrl);
484 /* enable transmitter */
485 ctrl = GX_TXC_ENABLE | GX_TXC_PAD_SHORT_PKTS | GX_TXC_COLL_RETRY_16;
487 /* XXX we should support half-duplex here too... */
488 ctrl |= GX_TXC_COLL_TIME_FDX;
490 CSR_WRITE_4(gx, GX_TX_CONTROL, ctrl);
493 * set up recommended IPG times, which vary depending on chip type:
494 * IPG transmit time: 80ns
495 * IPG receive time 1: 20ns
496 * IPG receive time 2: 80ns
498 CSR_WRITE_4(gx, GX_TX_IPG, gx->gx_ipg);
500 /* set up 802.3x MAC flow control address -- 01:80:c2:00:00:01 */
501 CSR_WRITE_4(gx, GX_FLOW_CTRL_BASE, 0x00C28001);
502 CSR_WRITE_4(gx, GX_FLOW_CTRL_BASE+4, 0x00000100);
504 /* set up 802.3x MAC flow control type -- 88:08 */
505 CSR_WRITE_4(gx, GX_FLOW_CTRL_TYPE, 0x8808);
507 /* Set up tuneables */
508 CSR_WRITE_4(gx, gx->gx_reg.r_rx_delay, gx->gx_rx_intr_delay);
509 CSR_WRITE_4(gx, gx->gx_reg.r_tx_delay, gx->gx_tx_intr_delay);
512 * Configure chip for correct operation.
514 ctrl = GX_CTRL_DUPLEX;
515 #if BYTE_ORDER == BIG_ENDIAN
516 ctrl |= GX_CTRL_BIGENDIAN;
518 ctrl |= GX_CTRL_VLAN_ENABLE;
520 if (gx->gx_tbimode) {
522 * It seems that TXCW must be initialized from the EEPROM
526 * should probably read the eeprom and re-insert the
529 #define TXCONFIG_WORD 0x000001A0
530 CSR_WRITE_4(gx, GX_TX_CONFIG, TXCONFIG_WORD);
532 /* turn on hardware autonegotiate */
533 GX_SETBIT(gx, GX_TX_CONFIG, GX_TXCFG_AUTONEG);
536 * Auto-detect speed from PHY, instead of using direct
537 * indication. The SLU bit doesn't force the link, but
538 * must be present for ASDE to work.
541 ctrl |= GX_CTRL_SET_LINK_UP | GX_CTRL_AUTOSPEED;
545 * Take chip out of reset and start it running.
547 CSR_WRITE_4(gx, GX_CTRL, ctrl);
549 /* Turn interrupts on. */
550 CSR_WRITE_4(gx, GX_INT_MASK_SET, GX_INT_WANTED);
552 ifp->if_flags |= IFF_RUNNING;
553 ifp->if_flags &= ~IFF_OACTIVE;
556 * Set the current media.
558 if (gx->gx_miibus != NULL) {
559 mii_mediachg(device_get_softc(gx->gx_miibus));
562 tmp = ifm->ifm_media;
563 ifm->ifm_media = ifm->ifm_cur->ifm_media;
565 ifm->ifm_media = tmp;
570 * Have the LINK0 flag force the link in TBI mode.
572 if (gx->gx_tbimode && ifp->if_flags & IFF_LINK0) {
573 GX_CLRBIT(gx, GX_TX_CONFIG, GX_TXCFG_AUTONEG);
574 GX_SETBIT(gx, GX_CTRL, GX_CTRL_SET_LINK_UP);
578 printf("66mhz: %s 64bit: %s\n",
579 CSR_READ_4(gx, GX_STATUS) & GX_STAT_PCI66 ? "yes" : "no",
580 CSR_READ_4(gx, GX_STATUS) & GX_STAT_BUS64 ? "yes" : "no");
588 * Stop all chip I/O so that the kernel's probe routines don't
589 * get confused by errant DMAs when rebooting.
592 gx_shutdown(device_t dev)
596 gx = device_get_softc(dev);
602 gx_detach(device_t dev)
610 gx = device_get_softc(dev);
611 ifp = &gx->arpcom.ac_if;
614 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
617 ifmedia_removeall(&gx->gx_media);
620 contigfree(gx->gx_rdata, sizeof(struct gx_ring_data), M_DEVBUF);
623 mtx_destroy(&gx->gx_mtx);
630 gx_eeprom_getword(struct gx_softc *gx, int addr, u_int16_t *dest)
636 addr = (GX_EE_OPC_READ << GX_EE_ADDR_SIZE) |
637 (addr & ((1 << GX_EE_ADDR_SIZE) - 1));
639 base = CSR_READ_4(gx, GX_EEPROM_CTRL);
640 base &= ~(GX_EE_DATA_OUT | GX_EE_DATA_IN | GX_EE_CLOCK);
641 base |= GX_EE_SELECT;
643 CSR_WRITE_4(gx, GX_EEPROM_CTRL, base);
645 for (x = 1 << ((GX_EE_OPC_SIZE + GX_EE_ADDR_SIZE) - 1); x; x >>= 1) {
646 reg = base | (addr & x ? GX_EE_DATA_IN : 0);
647 CSR_WRITE_4(gx, GX_EEPROM_CTRL, reg);
649 CSR_WRITE_4(gx, GX_EEPROM_CTRL, reg | GX_EE_CLOCK);
651 CSR_WRITE_4(gx, GX_EEPROM_CTRL, reg);
655 for (x = 1 << 15; x; x >>= 1) {
656 CSR_WRITE_4(gx, GX_EEPROM_CTRL, base | GX_EE_CLOCK);
658 reg = CSR_READ_4(gx, GX_EEPROM_CTRL);
659 if (reg & GX_EE_DATA_OUT)
661 CSR_WRITE_4(gx, GX_EEPROM_CTRL, base);
665 CSR_WRITE_4(gx, GX_EEPROM_CTRL, base & ~GX_EE_SELECT);
672 gx_read_eeprom(struct gx_softc *gx, caddr_t dest, int off, int cnt)
677 word = (u_int16_t *)dest;
678 for (i = 0; i < cnt; i ++) {
679 gx_eeprom_getword(gx, off + i, word);
689 gx_ifmedia_upd(struct ifnet *ifp)
693 struct mii_data *mii;
697 if (gx->gx_tbimode) {
699 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
701 switch (IFM_SUBTYPE(ifm->ifm_media)) {
703 GX_SETBIT(gx, GX_CTRL, GX_CTRL_LINK_RESET);
704 GX_SETBIT(gx, GX_TX_CONFIG, GX_TXCFG_AUTONEG);
705 GX_CLRBIT(gx, GX_CTRL, GX_CTRL_LINK_RESET);
708 device_printf(gx->gx_dev,
709 "manual config not supported yet.\n");
711 GX_CLRBIT(gx, GX_TX_CONFIG, GX_TXCFG_AUTONEG);
712 config = /* bit symbols for 802.3z */0;
713 ctrl |= GX_CTRL_SET_LINK_UP;
714 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
715 ctrl |= GX_CTRL_DUPLEX;
725 * 1000TX half duplex does not work.
727 if (IFM_TYPE(ifm->ifm_media) == IFM_ETHER &&
728 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_TX &&
729 (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) == 0)
731 mii = device_get_softc(gx->gx_miibus);
738 * Report current media status.
741 gx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
744 struct mii_data *mii;
749 if (gx->gx_tbimode) {
750 ifmr->ifm_status = IFM_AVALID;
751 ifmr->ifm_active = IFM_ETHER;
753 status = CSR_READ_4(gx, GX_STATUS);
754 if ((status & GX_STAT_LINKUP) == 0)
757 ifmr->ifm_status |= IFM_ACTIVE;
758 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
760 mii = device_get_softc(gx->gx_miibus);
762 if ((mii->mii_media_active & (IFM_1000_TX | IFM_HDX)) ==
763 (IFM_1000_TX | IFM_HDX))
764 mii->mii_media_active = IFM_ETHER | IFM_NONE;
765 ifmr->ifm_active = mii->mii_media_active;
766 ifmr->ifm_status = mii->mii_media_status;
771 gx_mii_shiftin(struct gx_softc *gx, int data, int length)
776 * Set up default GPIO direction + PHY data out.
778 reg = CSR_READ_4(gx, GX_CTRL);
779 reg &= ~(GX_CTRL_GPIO_DIR_MASK | GX_CTRL_PHY_IO | GX_CTRL_PHY_CLK);
780 reg |= GX_CTRL_GPIO_DIR | GX_CTRL_PHY_IO_DIR;
783 * Shift in data to PHY.
785 for (x = 1 << (length - 1); x; x >>= 1) {
787 reg |= GX_CTRL_PHY_IO;
789 reg &= ~GX_CTRL_PHY_IO;
790 CSR_WRITE_4(gx, GX_CTRL, reg);
792 CSR_WRITE_4(gx, GX_CTRL, reg | GX_CTRL_PHY_CLK);
794 CSR_WRITE_4(gx, GX_CTRL, reg);
800 gx_mii_shiftout(struct gx_softc *gx)
807 * Set up default GPIO direction + PHY data in.
809 reg = CSR_READ_4(gx, GX_CTRL);
810 reg &= ~(GX_CTRL_GPIO_DIR_MASK | GX_CTRL_PHY_IO | GX_CTRL_PHY_CLK);
811 reg |= GX_CTRL_GPIO_DIR;
813 CSR_WRITE_4(gx, GX_CTRL, reg);
815 CSR_WRITE_4(gx, GX_CTRL, reg | GX_CTRL_PHY_CLK);
817 CSR_WRITE_4(gx, GX_CTRL, reg);
820 * Shift out data from PHY.
823 for (x = 1 << 15; x; x >>= 1) {
824 CSR_WRITE_4(gx, GX_CTRL, reg | GX_CTRL_PHY_CLK);
826 if (CSR_READ_4(gx, GX_CTRL) & GX_CTRL_PHY_IO)
828 CSR_WRITE_4(gx, GX_CTRL, reg);
831 CSR_WRITE_4(gx, GX_CTRL, reg | GX_CTRL_PHY_CLK);
833 CSR_WRITE_4(gx, GX_CTRL, reg);
840 gx_miibus_readreg(device_t dev, int phy, int reg)
844 gx = device_get_softc(dev);
850 * Note: Cordova has a MDIC register. livingood and < have mii bits
853 gx_mii_shiftin(gx, GX_PHY_PREAMBLE, GX_PHY_PREAMBLE_LEN);
854 gx_mii_shiftin(gx, (GX_PHY_SOF << 12) | (GX_PHY_OP_READ << 10) |
855 (phy << 5) | reg, GX_PHY_READ_LEN);
856 return (gx_mii_shiftout(gx));
860 gx_miibus_writereg(device_t dev, int phy, int reg, int value)
864 gx = device_get_softc(dev);
868 gx_mii_shiftin(gx, GX_PHY_PREAMBLE, GX_PHY_PREAMBLE_LEN);
869 gx_mii_shiftin(gx, (GX_PHY_SOF << 30) | (GX_PHY_OP_WRITE << 28) |
870 (phy << 23) | (reg << 18) | (GX_PHY_TURNAROUND << 16) |
871 (value & 0xffff), GX_PHY_WRITE_LEN);
875 gx_miibus_statchg(device_t dev)
878 struct mii_data *mii;
881 gx = device_get_softc(dev);
886 * Set flow control behavior to mirror what PHY negotiated.
888 mii = device_get_softc(gx->gx_miibus);
893 reg = CSR_READ_4(gx, GX_CTRL);
894 if (mii->mii_media_active & IFM_FLAG0)
895 reg |= GX_CTRL_RX_FLOWCTRL;
897 reg &= ~GX_CTRL_RX_FLOWCTRL;
898 if (mii->mii_media_active & IFM_FLAG1)
899 reg |= GX_CTRL_TX_FLOWCTRL;
901 reg &= ~GX_CTRL_TX_FLOWCTRL;
902 CSR_WRITE_4(gx, GX_CTRL, reg);
909 gx_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
911 struct gx_softc *gx = ifp->if_softc;
912 struct ifreq *ifr = (struct ifreq *)data;
913 struct mii_data *mii;
914 int s, mask, error = 0;
922 error = ether_ioctl(ifp, command, data);
925 if (ifr->ifr_mtu > GX_MAX_MTU) {
928 ifp->if_mtu = ifr->ifr_mtu;
933 if ((ifp->if_flags & IFF_UP) == 0) {
935 } else if (ifp->if_flags & IFF_RUNNING &&
936 ((ifp->if_flags & IFF_PROMISC) !=
937 (gx->gx_if_flags & IFF_PROMISC))) {
938 if (ifp->if_flags & IFF_PROMISC)
939 GX_SETBIT(gx, GX_RX_CONTROL, GX_RXC_UNI_PROMISC);
941 GX_CLRBIT(gx, GX_RX_CONTROL, GX_RXC_UNI_PROMISC);
945 gx->gx_if_flags = ifp->if_flags;
949 if (ifp->if_flags & IFF_RUNNING)
954 if (gx->gx_miibus != NULL) {
955 mii = device_get_softc(gx->gx_miibus);
956 error = ifmedia_ioctl(ifp, ifr,
957 &mii->mii_media, command);
959 error = ifmedia_ioctl(ifp, ifr, &gx->gx_media, command);
963 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
964 if (mask & IFCAP_HWCSUM) {
965 if (IFCAP_HWCSUM & ifp->if_capenable)
966 ifp->if_capenable &= ~IFCAP_HWCSUM;
968 ifp->if_capenable |= IFCAP_HWCSUM;
969 if (ifp->if_flags & IFF_RUNNING)
984 gx_phy_reset(struct gx_softc *gx)
988 GX_SETBIT(gx, GX_CTRL, GX_CTRL_SET_LINK_UP);
991 * PHY reset is active low.
993 reg = CSR_READ_4(gx, GX_CTRL_EXT);
994 reg &= ~(GX_CTRLX_GPIO_DIR_MASK | GX_CTRLX_PHY_RESET);
995 reg |= GX_CTRLX_GPIO_DIR;
997 CSR_WRITE_4(gx, GX_CTRL_EXT, reg | GX_CTRLX_PHY_RESET);
999 CSR_WRITE_4(gx, GX_CTRL_EXT, reg);
1001 CSR_WRITE_4(gx, GX_CTRL_EXT, reg | GX_CTRLX_PHY_RESET);
1005 /* post-livingood (cordova) only */
1006 GX_SETBIT(gx, GX_CTRL, 0x80000000);
1008 GX_CLRBIT(gx, GX_CTRL, 0x80000000);
1013 gx_reset(struct gx_softc *gx)
1016 /* Disable host interrupts. */
1017 CSR_WRITE_4(gx, GX_INT_MASK_CLR, GX_INT_ALL);
1019 /* reset chip (THWAP!) */
1020 GX_SETBIT(gx, GX_CTRL, GX_CTRL_DEVICE_RESET);
1025 gx_stop(struct gx_softc *gx)
1029 ifp = &gx->arpcom.ac_if;
1031 /* reset and flush transmitter */
1032 CSR_WRITE_4(gx, GX_TX_CONTROL, GX_TXC_RESET);
1034 /* reset and flush receiver */
1035 CSR_WRITE_4(gx, GX_RX_CONTROL, GX_RXC_RESET);
1039 GX_SETBIT(gx, GX_CTRL, GX_CTRL_LINK_RESET);
1041 /* Free the RX lists. */
1042 gx_free_rx_ring(gx);
1044 /* Free TX buffers. */
1045 gx_free_tx_ring(gx);
1047 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1051 gx_watchdog(struct ifnet *ifp)
1053 struct gx_softc *gx;
1057 device_printf(gx->gx_dev, "watchdog timeout -- resetting\n");
1065 * Intialize a receive ring descriptor.
1068 gx_newbuf(struct gx_softc *gx, int idx, struct mbuf *m)
1070 struct mbuf *m_new = NULL;
1071 struct gx_rx_desc *r;
1074 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1075 if (m_new == NULL) {
1076 device_printf(gx->gx_dev,
1077 "mbuf allocation failed -- packet dropped\n");
1080 MCLGET(m_new, M_DONTWAIT);
1081 if ((m_new->m_flags & M_EXT) == 0) {
1082 device_printf(gx->gx_dev,
1083 "cluster allocation failed -- packet dropped\n");
1087 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1089 m->m_len = m->m_pkthdr.len = MCLBYTES;
1090 m->m_data = m->m_ext.ext_buf;
1097 * this will _NOT_ work for large MTU's; it will overwrite
1098 * the end of the buffer. E.g.: take this out for jumbograms,
1099 * but then that breaks alignment.
1101 if (gx->arpcom.ac_if.if_mtu <= ETHERMTU)
1102 m_adj(m_new, ETHER_ALIGN);
1104 gx->gx_cdata.gx_rx_chain[idx] = m_new;
1105 r = &gx->gx_rdata->gx_rx_ring[idx];
1106 r->rx_addr = vtophys(mtod(m_new, caddr_t));
1113 * The receive ring can have up to 64K descriptors, which at 2K per mbuf
1114 * cluster, could add up to 128M of memory. Due to alignment constraints,
1115 * the number of descriptors must be a multiple of 8. For now, we
1116 * allocate 256 entries and hope that our CPU is fast enough to keep up
1120 gx_init_rx_ring(struct gx_softc *gx)
1124 for (i = 0; i < GX_RX_RING_CNT; i++) {
1125 error = gx_newbuf(gx, i, NULL);
1130 /* bring receiver out of reset state, leave disabled */
1131 CSR_WRITE_4(gx, GX_RX_CONTROL, 0);
1133 /* set up ring registers */
1134 CSR_WRITE_8(gx, gx->gx_reg.r_rx_base,
1135 (u_quad_t)vtophys(gx->gx_rdata->gx_rx_ring));
1137 CSR_WRITE_4(gx, gx->gx_reg.r_rx_length,
1138 GX_RX_RING_CNT * sizeof(struct gx_rx_desc));
1139 CSR_WRITE_4(gx, gx->gx_reg.r_rx_head, 0);
1140 CSR_WRITE_4(gx, gx->gx_reg.r_rx_tail, GX_RX_RING_CNT - 1);
1141 gx->gx_rx_tail_idx = 0;
1147 gx_free_rx_ring(struct gx_softc *gx)
1152 mp = gx->gx_cdata.gx_rx_chain;
1153 for (i = 0; i < GX_RX_RING_CNT; i++, mp++) {
1159 bzero((void *)gx->gx_rdata->gx_rx_ring,
1160 GX_RX_RING_CNT * sizeof(struct gx_rx_desc));
1162 /* release any partially-received packet chain */
1163 if (gx->gx_pkthdr != NULL) {
1164 m_freem(gx->gx_pkthdr);
1165 gx->gx_pkthdr = NULL;
1170 gx_init_tx_ring(struct gx_softc *gx)
1173 /* bring transmitter out of reset state, leave disabled */
1174 CSR_WRITE_4(gx, GX_TX_CONTROL, 0);
1176 /* set up ring registers */
1177 CSR_WRITE_8(gx, gx->gx_reg.r_tx_base,
1178 (u_quad_t)vtophys(gx->gx_rdata->gx_tx_ring));
1179 CSR_WRITE_4(gx, gx->gx_reg.r_tx_length,
1180 GX_TX_RING_CNT * sizeof(struct gx_tx_desc));
1181 CSR_WRITE_4(gx, gx->gx_reg.r_tx_head, 0);
1182 CSR_WRITE_4(gx, gx->gx_reg.r_tx_tail, 0);
1183 gx->gx_tx_head_idx = 0;
1184 gx->gx_tx_tail_idx = 0;
1187 /* set up initial TX context */
1188 gx->gx_txcontext = GX_TXCONTEXT_NONE;
1194 gx_free_tx_ring(struct gx_softc *gx)
1199 mp = gx->gx_cdata.gx_tx_chain;
1200 for (i = 0; i < GX_TX_RING_CNT; i++, mp++) {
1206 bzero((void *)&gx->gx_rdata->gx_tx_ring,
1207 GX_TX_RING_CNT * sizeof(struct gx_tx_desc));
1211 gx_setmulti(struct gx_softc *gx)
1215 /* wipe out the multicast table */
1216 for (i = 1; i < 128; i++)
1217 CSR_WRITE_4(gx, GX_MULTICAST_BASE + i * 4, 0);
1221 gx_rxeof(struct gx_softc *gx)
1223 struct ether_header *eh;
1224 struct gx_rx_desc *rx;
1226 int idx, staterr, len;
1229 gx->gx_rx_interrupts++;
1231 ifp = &gx->arpcom.ac_if;
1232 idx = gx->gx_rx_tail_idx;
1234 while (gx->gx_rdata->gx_rx_ring[idx].rx_staterr & GX_RXSTAT_COMPLETED) {
1236 rx = &gx->gx_rdata->gx_rx_ring[idx];
1237 m = gx->gx_cdata.gx_rx_chain[idx];
1239 * gx_newbuf overwrites status and length bits, so we
1240 * make a copy of them here.
1243 staterr = rx->rx_staterr;
1245 if (staterr & GX_INPUT_ERROR)
1248 if (gx_newbuf(gx, idx, NULL) == ENOBUFS)
1251 GX_INC(idx, GX_RX_RING_CNT);
1253 if (staterr & GX_RXSTAT_INEXACT_MATCH) {
1255 * multicast packet, must verify against
1256 * multicast address.
1260 if ((staterr & GX_RXSTAT_END_OF_PACKET) == 0) {
1261 if (gx->gx_pkthdr == NULL) {
1263 m->m_pkthdr.len = len;
1265 gx->gx_pktnextp = &m->m_next;
1268 m->m_flags &= ~M_PKTHDR;
1269 gx->gx_pkthdr->m_pkthdr.len += len;
1270 *(gx->gx_pktnextp) = m;
1271 gx->gx_pktnextp = &m->m_next;
1276 if (gx->gx_pkthdr == NULL) {
1278 m->m_pkthdr.len = len;
1281 m->m_flags &= ~M_PKTHDR;
1282 gx->gx_pkthdr->m_pkthdr.len += len;
1283 *(gx->gx_pktnextp) = m;
1285 gx->gx_pkthdr = NULL;
1289 eh = mtod(m, struct ether_header *);
1290 m->m_pkthdr.rcvif = ifp;
1292 /* Remove header from mbuf and pass it on. */
1293 m_adj(m, sizeof(struct ether_header));
1295 #define IP_CSMASK (GX_RXSTAT_IGNORE_CSUM | GX_RXSTAT_HAS_IP_CSUM)
1296 #define TCP_CSMASK \
1297 (GX_RXSTAT_IGNORE_CSUM | GX_RXSTAT_HAS_TCP_CSUM | GX_RXERR_TCP_CSUM)
1298 if (ifp->if_capenable & IFCAP_RXCSUM) {
1301 * Intel Erratum #23 indicates that the Receive IP
1302 * Checksum offload feature has been completely
1305 if ((staterr & IP_CSUM_MASK) == GX_RXSTAT_HAS_IP_CSUM) {
1306 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1307 if ((staterr & GX_RXERR_IP_CSUM) == 0)
1308 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1311 if ((staterr & TCP_CSMASK) == GX_RXSTAT_HAS_TCP_CSUM) {
1312 m->m_pkthdr.csum_flags |=
1313 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1314 m->m_pkthdr.csum_data = 0xffff;
1318 * If we received a packet with a vlan tag, pass it
1319 * to vlan_input() instead of ether_input().
1321 if (staterr & GX_RXSTAT_VLAN_PKT) {
1322 VLAN_INPUT_TAG(eh, m, rx->rx_special);
1325 ether_input(ifp, eh, m);
1330 gx_newbuf(gx, idx, m);
1334 * this isn't quite right. Suppose we have a packet that
1335 * spans 5 descriptors (9K split into 2K buffers). If
1336 * the 3rd descriptor sets an error, we need to ignore
1337 * the last two. The way things stand now, the last two
1338 * will be accepted as a single packet.
1340 * we don't worry about this -- the chip may not set an
1341 * error in this case, and the checksum of the upper layers
1342 * will catch the error.
1344 if (gx->gx_pkthdr != NULL) {
1345 m_freem(gx->gx_pkthdr);
1346 gx->gx_pkthdr = NULL;
1348 GX_INC(idx, GX_RX_RING_CNT);
1351 gx->gx_rx_tail_idx = idx;
1353 idx = GX_RX_RING_CNT - 1;
1354 CSR_WRITE_4(gx, gx->gx_reg.r_rx_tail, idx);
1358 gx_txeof(struct gx_softc *gx)
1363 gx->gx_tx_interrupts++;
1365 ifp = &gx->arpcom.ac_if;
1366 idx = gx->gx_tx_head_idx;
1370 * If the system chipset performs I/O write buffering, it is
1371 * possible for the PIO read of the head descriptor to bypass the
1372 * memory write of the descriptor, resulting in reading a descriptor
1373 * which has not been updated yet.
1376 struct gx_tx_desc_old *tx;
1378 tx = (struct gx_tx_desc_old *)&gx->gx_rdata->gx_tx_ring[idx];
1381 if ((tx->tx_command & GX_TXOLD_END_OF_PKT) == 0) {
1382 GX_INC(idx, GX_TX_RING_CNT);
1386 if ((tx->tx_status & GX_TXSTAT_DONE) == 0)
1391 m_freem(gx->gx_cdata.gx_tx_chain[idx]);
1392 gx->gx_cdata.gx_tx_chain[idx] = NULL;
1396 GX_INC(idx, GX_TX_RING_CNT);
1397 gx->gx_tx_head_idx = idx;
1400 if (gx->gx_txcnt == 0)
1401 ifp->if_flags &= ~IFF_OACTIVE;
1407 struct gx_softc *gx;
1413 ifp = &gx->arpcom.ac_if;
1417 gx->gx_interrupts++;
1419 /* Disable host interrupts. */
1420 CSR_WRITE_4(gx, GX_INT_MASK_CLR, GX_INT_ALL);
1423 * find out why we're being bothered.
1424 * reading this register automatically clears all bits.
1426 intr = CSR_READ_4(gx, GX_INT_READ);
1428 /* Check RX return ring producer/consumer */
1429 if (intr & (GX_INT_RCV_TIMER | GX_INT_RCV_THOLD | GX_INT_RCV_OVERRUN))
1432 /* Check TX ring producer/consumer */
1433 if (intr & (GX_INT_XMIT_DONE | GX_INT_XMIT_EMPTY))
1437 * handle other interrupts here.
1441 * Link change interrupts are not reliable; the interrupt may
1442 * not be generated if the link is lost. However, the register
1443 * read is reliable, so check that. Use SEQ errors to possibly
1444 * indicate that the link has changed.
1446 if (intr & GX_INT_LINK_CHANGE) {
1447 if ((CSR_READ_4(gx, GX_STATUS) & GX_STAT_LINKUP) == 0) {
1448 device_printf(gx->gx_dev, "link down\n");
1450 device_printf(gx->gx_dev, "link up\n");
1454 /* Turn interrupts on. */
1455 CSR_WRITE_4(gx, GX_INT_MASK_SET, GX_INT_WANTED);
1457 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
1464 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
1465 * pointers to descriptors.
1468 gx_encap(struct gx_softc *gx, struct mbuf *m_head)
1470 struct gx_tx_desc_data *tx = NULL;
1471 struct gx_tx_desc_ctx *tctx;
1473 int idx, cnt, csumopts, txcontext;
1474 struct ifvlan *ifv = NULL;
1476 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1477 m_head->m_pkthdr.rcvif != NULL &&
1478 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
1479 ifv = m_head->m_pkthdr.rcvif->if_softc;
1482 idx = gx->gx_tx_tail_idx;
1483 txcontext = gx->gx_txcontext;
1486 * Insure we have at least 4 descriptors pre-allocated.
1488 if (cnt >= GX_TX_RING_CNT - 4)
1492 * Set up the appropriate offload context if necessary.
1495 if (m_head->m_pkthdr.csum_flags) {
1496 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1497 csumopts |= GX_TXTCP_OPT_IP_CSUM;
1498 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) {
1499 csumopts |= GX_TXTCP_OPT_TCP_CSUM;
1500 txcontext = GX_TXCONTEXT_TCPIP;
1501 } else if (m_head->m_pkthdr.csum_flags & CSUM_UDP) {
1502 csumopts |= GX_TXTCP_OPT_TCP_CSUM;
1503 txcontext = GX_TXCONTEXT_UDPIP;
1504 } else if (txcontext == GX_TXCONTEXT_NONE)
1505 txcontext = GX_TXCONTEXT_TCPIP;
1506 if (txcontext == gx->gx_txcontext)
1509 tctx = (struct gx_tx_desc_ctx *)&gx->gx_rdata->gx_tx_ring[idx];
1510 tctx->tx_ip_csum_start = ETHER_HDR_LEN;
1511 tctx->tx_ip_csum_end = ETHER_HDR_LEN + sizeof(struct ip) - 1;
1512 tctx->tx_ip_csum_offset =
1513 ETHER_HDR_LEN + offsetof(struct ip, ip_sum);
1514 tctx->tx_tcp_csum_start = ETHER_HDR_LEN + sizeof(struct ip);
1515 tctx->tx_tcp_csum_end = 0;
1516 if (txcontext == GX_TXCONTEXT_TCPIP)
1517 tctx->tx_tcp_csum_offset = ETHER_HDR_LEN +
1518 sizeof(struct ip) + offsetof(struct tcphdr, th_sum);
1520 tctx->tx_tcp_csum_offset = ETHER_HDR_LEN +
1521 sizeof(struct ip) + offsetof(struct udphdr, uh_sum);
1522 tctx->tx_command = GX_TXCTX_EXTENSION | GX_TXCTX_INT_DELAY;
1524 tctx->tx_status = 0;
1525 GX_INC(idx, GX_TX_RING_CNT);
1531 * Start packing the mbufs in this chain into the transmit
1532 * descriptors. Stop when we run out of descriptors or hit
1533 * the end of the mbuf chain.
1535 for (m = m_head; m != NULL; m = m->m_next) {
1539 if (cnt == GX_TX_RING_CNT) {
1540 printf("overflow(2): %d, %d\n", cnt, GX_TX_RING_CNT);
1544 tx = (struct gx_tx_desc_data *)&gx->gx_rdata->gx_tx_ring[idx];
1545 tx->tx_addr = vtophys(mtod(m, vm_offset_t));
1547 tx->tx_len = m->m_len;
1548 if (gx->arpcom.ac_if.if_hwassist) {
1550 tx->tx_command = GX_TXTCP_EXTENSION;
1551 tx->tx_options = csumopts;
1554 * This is really a struct gx_tx_desc_old.
1558 GX_INC(idx, GX_TX_RING_CNT);
1563 tx->tx_command |= GX_TXTCP_REPORT_STATUS | GX_TXTCP_INT_DELAY |
1564 GX_TXTCP_ETHER_CRC | GX_TXTCP_END_OF_PKT;
1566 tx->tx_command |= GX_TXTCP_VLAN_ENABLE;
1567 tx->tx_vlan = ifv->ifv_tag;
1570 gx->gx_tx_tail_idx = idx;
1571 gx->gx_txcontext = txcontext;
1572 idx = GX_PREV(idx, GX_TX_RING_CNT);
1573 gx->gx_cdata.gx_tx_chain[idx] = m_head;
1575 CSR_WRITE_4(gx, gx->gx_reg.r_tx_tail, gx->gx_tx_tail_idx);
1582 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1583 * to the mbuf data regions directly in the transmit descriptors.
1586 gx_start(struct ifnet *ifp)
1588 struct gx_softc *gx;
1589 struct mbuf *m_head;
1597 IF_DEQUEUE(&ifp->if_snd, m_head);
1602 * Pack the data into the transmit ring. If we
1603 * don't have room, set the OACTIVE flag and wait
1604 * for the NIC to drain the ring.
1606 if (gx_encap(gx, m_head) != 0) {
1607 IF_PREPEND(&ifp->if_snd, m_head);
1608 ifp->if_flags |= IFF_OACTIVE;
1613 * If there's a BPF listener, bounce a copy of this frame
1617 bpf_mtap(ifp, m_head);
1620 * Set a timeout in case the chip goes out to lunch.