2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $
33 * $DragonFly: src/sys/dev/netif/rl/if_rl.c,v 1.7 2004/01/06 01:40:48 dillon Exp $
35 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $
39 * RealTek 8129/8139 PCI NIC driver
41 * Supports several extremely cheap PCI 10/100 adapters based on
42 * the RealTek chipset. Datasheets can be obtained from
45 * Written by Bill Paul <wpaul@ctr.columbia.edu>
46 * Electrical Engineering Department
47 * Columbia University, New York City
51 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
52 * probably the worst PCI ethernet controller ever made, with the possible
53 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
54 * DMA, but it has a terrible interface that nullifies any performance
55 * gains that bus-master DMA usually offers.
57 * For transmission, the chip offers a series of four TX descriptor
58 * registers. Each transmit frame must be in a contiguous buffer, aligned
59 * on a longword (32-bit) boundary. This means we almost always have to
60 * do mbuf copies in order to transmit a frame, except in the unlikely
61 * case where a) the packet fits into a single mbuf, and b) the packet
62 * is 32-bit aligned within the mbuf's data area. The presence of only
63 * four descriptor registers means that we can never have more than four
64 * packets queued for transmission at any one time.
66 * Reception is not much better. The driver has to allocate a single large
67 * buffer area (up to 64K in size) into which the chip will DMA received
68 * frames. Because we don't know where within this region received packets
69 * will begin or end, we have no choice but to copy data from the buffer
70 * area into mbufs in order to pass the packets up to the higher protocol
73 * It's impossible given this rotten design to really achieve decent
74 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
75 * some equally overmuscled CPU to drive it.
77 * On the bright side, the 8139 does have a built-in PHY, although
78 * rather than using an MDIO serial interface like most other NICs, the
79 * PHY registers are directly accessible through the 8139's register
80 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
83 * The 8129 chip is an older version of the 8139 that uses an external PHY
84 * chip. The 8129 has a serial MDIO interface for accessing the MII where
85 * the 8139 lets you directly access the on-board PHY registers. We need
86 * to select which interface to use depending on the chip type.
89 #include <sys/param.h>
90 #include <sys/systm.h>
91 #include <sys/sockio.h>
93 #include <sys/malloc.h>
94 #include <sys/kernel.h>
95 #include <sys/socket.h>
98 #include <net/if_arp.h>
99 #include <net/ethernet.h>
100 #include <net/if_dl.h>
101 #include <net/if_media.h>
105 #include <vm/vm.h> /* for vtophys */
106 #include <vm/pmap.h> /* for vtophys */
107 #include <machine/clock.h> /* for DELAY */
108 #include <machine/bus_pio.h>
109 #include <machine/bus_memio.h>
110 #include <machine/bus.h>
111 #include <machine/resource.h>
113 #include <sys/rman.h>
115 #include "../mii_layer/mii.h"
116 #include "../mii_layer/miivar.h"
118 #include <bus/pci/pcireg.h>
119 #include <bus/pci/pcivar.h>
121 /* "controller miibus0" required. See GENERIC if you get errors here. */
122 #include "miibus_if.h"
125 * Default to using PIO access for this driver. On SMP systems,
126 * there appear to be problems with memory mapped mode: it looks like
127 * doing too many memory mapped access back to back in rapid succession
128 * can hang the bus. I'm inclined to blame this on crummy design/construction
129 * on the part of RealTek. Memory mapped mode does appear to work on
130 * uniprocessor systems though.
132 #define RL_USEIOSPACE
134 #include "if_rlreg.h"
137 * Various supported device vendors/types and their names.
139 static struct rl_type rl_devs[] = {
140 { RT_VENDORID, RT_DEVICEID_8129,
141 "RealTek 8129 10/100BaseTX" },
142 { RT_VENDORID, RT_DEVICEID_8139,
143 "RealTek 8139 10/100BaseTX" },
144 { ACCTON_VENDORID, ACCTON_DEVICEID_5030,
145 "Accton MPX 5030/5038 10/100BaseTX" },
146 { DELTA_VENDORID, DELTA_DEVICEID_8139,
147 "Delta Electronics 8139 10/100BaseTX" },
148 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139,
149 "Addtron Technolgy 8139 10/100BaseTX" },
150 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS,
151 "D-Link DFE-530TX+ 10/100BaseTX" },
152 { NORTEL_VENDORID, ACCTON_DEVICEID_5030,
153 "Nortel Networks 10/100BaseTX" },
154 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF,
155 "Peppercon AG ROL/F" },
159 static int rl_probe (device_t);
160 static int rl_attach (device_t);
161 static int rl_detach (device_t);
163 static int rl_encap (struct rl_softc *, struct mbuf * );
165 static void rl_rxeof (struct rl_softc *);
166 static void rl_txeof (struct rl_softc *);
167 static void rl_intr (void *);
168 static void rl_tick (void *);
169 static void rl_start (struct ifnet *);
170 static int rl_ioctl (struct ifnet *, u_long, caddr_t);
171 static void rl_init (void *);
172 static void rl_stop (struct rl_softc *);
173 static void rl_watchdog (struct ifnet *);
174 static int rl_suspend (device_t);
175 static int rl_resume (device_t);
176 static void rl_shutdown (device_t);
177 static int rl_ifmedia_upd (struct ifnet *);
178 static void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
180 static void rl_eeprom_putbyte (struct rl_softc *, int);
181 static void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *);
182 static void rl_read_eeprom (struct rl_softc *, caddr_t,
184 static void rl_mii_sync (struct rl_softc *);
185 static void rl_mii_send (struct rl_softc *, u_int32_t, int);
186 static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *);
187 static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *);
189 static int rl_miibus_readreg (device_t, int, int);
190 static int rl_miibus_writereg (device_t, int, int, int);
191 static void rl_miibus_statchg (device_t);
193 static u_int8_t rl_calchash (caddr_t);
194 static void rl_setmulti (struct rl_softc *);
195 static void rl_reset (struct rl_softc *);
196 static int rl_list_tx_init (struct rl_softc *);
199 #define RL_RES SYS_RES_IOPORT
200 #define RL_RID RL_PCI_LOIO
202 #define RL_RES SYS_RES_MEMORY
203 #define RL_RID RL_PCI_LOMEM
206 static device_method_t rl_methods[] = {
207 /* Device interface */
208 DEVMETHOD(device_probe, rl_probe),
209 DEVMETHOD(device_attach, rl_attach),
210 DEVMETHOD(device_detach, rl_detach),
211 DEVMETHOD(device_suspend, rl_suspend),
212 DEVMETHOD(device_resume, rl_resume),
213 DEVMETHOD(device_shutdown, rl_shutdown),
216 DEVMETHOD(bus_print_child, bus_generic_print_child),
217 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
220 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
221 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
222 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
227 static driver_t rl_driver = {
230 sizeof(struct rl_softc)
233 static devclass_t rl_devclass;
235 DECLARE_DUMMY_MODULE(if_rl);
236 DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0);
237 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
240 CSR_WRITE_1(sc, RL_EECMD, \
241 CSR_READ_1(sc, RL_EECMD) | x)
244 CSR_WRITE_1(sc, RL_EECMD, \
245 CSR_READ_1(sc, RL_EECMD) & ~x)
248 * Send a read command and address to the EEPROM, check for ACK.
250 static void rl_eeprom_putbyte(sc, addr)
256 d = addr | RL_EECMD_READ;
259 * Feed in each bit and strobe the clock.
261 for (i = 0x400; i; i >>= 1) {
263 EE_SET(RL_EE_DATAIN);
265 EE_CLR(RL_EE_DATAIN);
278 * Read a word of data stored in the EEPROM at address 'addr.'
280 static void rl_eeprom_getword(sc, addr, dest)
288 /* Enter EEPROM access mode. */
289 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
292 * Send address of word we want to read.
294 rl_eeprom_putbyte(sc, addr);
296 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
299 * Start reading bits from EEPROM.
301 for (i = 0x8000; i; i >>= 1) {
304 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
310 /* Turn off EEPROM access mode. */
311 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
319 * Read a sequence of words from the EEPROM.
321 static void rl_read_eeprom(sc, dest, off, cnt, swap)
329 u_int16_t word = 0, *ptr;
331 for (i = 0; i < cnt; i++) {
332 rl_eeprom_getword(sc, off + i, &word);
333 ptr = (u_int16_t *)(dest + (i * 2));
345 * MII access routines are provided for the 8129, which
346 * doesn't have a built-in PHY. For the 8139, we fake things
347 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
348 * direct access PHY registers.
351 CSR_WRITE_1(sc, RL_MII, \
352 CSR_READ_1(sc, RL_MII) | x)
355 CSR_WRITE_1(sc, RL_MII, \
356 CSR_READ_1(sc, RL_MII) & ~x)
359 * Sync the PHYs by setting data bit and strobing the clock 32 times.
361 static void rl_mii_sync(sc)
366 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
368 for (i = 0; i < 32; i++) {
379 * Clock a series of bits through the MII.
381 static void rl_mii_send(sc, bits, cnt)
390 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
392 MII_SET(RL_MII_DATAOUT);
394 MII_CLR(RL_MII_DATAOUT);
404 * Read an PHY register through the MII.
406 static int rl_mii_readreg(sc, frame)
408 struct rl_mii_frame *frame;
416 * Set up frame for RX.
418 frame->mii_stdelim = RL_MII_STARTDELIM;
419 frame->mii_opcode = RL_MII_READOP;
420 frame->mii_turnaround = 0;
423 CSR_WRITE_2(sc, RL_MII, 0);
433 * Send command/address info.
435 rl_mii_send(sc, frame->mii_stdelim, 2);
436 rl_mii_send(sc, frame->mii_opcode, 2);
437 rl_mii_send(sc, frame->mii_phyaddr, 5);
438 rl_mii_send(sc, frame->mii_regaddr, 5);
441 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
452 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
457 * Now try reading data bits. If the ack failed, we still
458 * need to clock through 16 cycles to keep the PHY(s) in sync.
461 for(i = 0; i < 16; i++) {
470 for (i = 0x8000; i; i >>= 1) {
474 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
475 frame->mii_data |= i;
497 * Write to a PHY register through the MII.
499 static int rl_mii_writereg(sc, frame)
501 struct rl_mii_frame *frame;
508 * Set up frame for TX.
511 frame->mii_stdelim = RL_MII_STARTDELIM;
512 frame->mii_opcode = RL_MII_WRITEOP;
513 frame->mii_turnaround = RL_MII_TURNAROUND;
516 * Turn on data output.
522 rl_mii_send(sc, frame->mii_stdelim, 2);
523 rl_mii_send(sc, frame->mii_opcode, 2);
524 rl_mii_send(sc, frame->mii_phyaddr, 5);
525 rl_mii_send(sc, frame->mii_regaddr, 5);
526 rl_mii_send(sc, frame->mii_turnaround, 2);
527 rl_mii_send(sc, frame->mii_data, 16);
545 static int rl_miibus_readreg(dev, phy, reg)
550 struct rl_mii_frame frame;
552 u_int16_t rl8139_reg = 0;
554 sc = device_get_softc(dev);
556 if (sc->rl_type == RL_8139) {
557 /* Pretend the internal PHY is only at address 0 */
562 rl8139_reg = RL_BMCR;
565 rl8139_reg = RL_BMSR;
568 rl8139_reg = RL_ANAR;
571 rl8139_reg = RL_ANER;
574 rl8139_reg = RL_LPAR;
581 * Allow the rlphy driver to read the media status
582 * register. If we have a link partner which does not
583 * support NWAY, this is the register which will tell
584 * us the results of parallel detection.
587 rval = CSR_READ_1(sc, RL_MEDIASTAT);
591 printf("rl%d: bad phy register\n", sc->rl_unit);
594 rval = CSR_READ_2(sc, rl8139_reg);
598 bzero((char *)&frame, sizeof(frame));
600 frame.mii_phyaddr = phy;
601 frame.mii_regaddr = reg;
602 rl_mii_readreg(sc, &frame);
604 return(frame.mii_data);
607 static int rl_miibus_writereg(dev, phy, reg, data)
612 struct rl_mii_frame frame;
613 u_int16_t rl8139_reg = 0;
615 sc = device_get_softc(dev);
617 if (sc->rl_type == RL_8139) {
618 /* Pretend the internal PHY is only at address 0 */
623 rl8139_reg = RL_BMCR;
626 rl8139_reg = RL_BMSR;
629 rl8139_reg = RL_ANAR;
632 rl8139_reg = RL_ANER;
635 rl8139_reg = RL_LPAR;
642 printf("rl%d: bad phy register\n", sc->rl_unit);
645 CSR_WRITE_2(sc, rl8139_reg, data);
649 bzero((char *)&frame, sizeof(frame));
651 frame.mii_phyaddr = phy;
652 frame.mii_regaddr = reg;
653 frame.mii_data = data;
655 rl_mii_writereg(sc, &frame);
660 static void rl_miibus_statchg(dev)
667 * Calculate CRC of a multicast group address, return the upper 6 bits.
669 static u_int8_t rl_calchash(addr)
672 u_int32_t crc, carry;
676 /* Compute CRC for the address value. */
677 crc = 0xFFFFFFFF; /* initial value */
679 for (i = 0; i < 6; i++) {
681 for (j = 0; j < 8; j++) {
682 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
686 crc = (crc ^ 0x04c11db6) | carry;
690 /* return the filter bit position */
695 * Program the 64-bit multicast hash filter.
697 static void rl_setmulti(sc)
702 u_int32_t hashes[2] = { 0, 0 };
703 struct ifmultiaddr *ifma;
707 ifp = &sc->arpcom.ac_if;
709 rxfilt = CSR_READ_4(sc, RL_RXCFG);
711 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
712 rxfilt |= RL_RXCFG_RX_MULTI;
713 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
714 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
715 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
719 /* first, zot all the existing hash bits */
720 CSR_WRITE_4(sc, RL_MAR0, 0);
721 CSR_WRITE_4(sc, RL_MAR4, 0);
723 /* now program new ones */
724 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
725 ifma = ifma->ifma_link.le_next) {
726 if (ifma->ifma_addr->sa_family != AF_LINK)
728 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
730 hashes[0] |= (1 << h);
732 hashes[1] |= (1 << (h - 32));
737 rxfilt |= RL_RXCFG_RX_MULTI;
739 rxfilt &= ~RL_RXCFG_RX_MULTI;
741 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
742 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
743 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
748 static void rl_reset(sc)
753 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
755 for (i = 0; i < RL_TIMEOUT; i++) {
757 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
761 printf("rl%d: reset never completed!\n", sc->rl_unit);
767 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
768 * IDs against our list and return a device name if we find a match.
770 static int rl_probe(dev)
777 while(t->rl_name != NULL) {
778 if ((pci_get_vendor(dev) == t->rl_vid) &&
779 (pci_get_device(dev) == t->rl_did)) {
780 device_set_desc(dev, t->rl_name);
790 * Attach the interface. Allocate softc structures, do ifmedia
791 * setup and ethernet/BPF attach.
793 static int rl_attach(dev)
797 u_char eaddr[ETHER_ADDR_LEN];
801 u_int16_t rl_did = 0;
802 int unit, error = 0, rid;
806 sc = device_get_softc(dev);
807 unit = device_get_unit(dev);
808 bzero(sc, sizeof(struct rl_softc));
811 * Handle power management nonsense.
814 command = pci_read_config(dev, RL_PCI_CAPID, 4) & 0x000000FF;
815 if (command == 0x01) {
817 command = pci_read_config(dev, RL_PCI_PWRMGMTCTRL, 4);
818 if (command & RL_PSTATE_MASK) {
819 u_int32_t iobase, membase, irq;
821 /* Save important PCI config data. */
822 iobase = pci_read_config(dev, RL_PCI_LOIO, 4);
823 membase = pci_read_config(dev, RL_PCI_LOMEM, 4);
824 irq = pci_read_config(dev, RL_PCI_INTLINE, 4);
826 /* Reset the power state. */
827 printf("rl%d: chip is is in D%d power mode "
828 "-- setting to D0\n", unit, command & RL_PSTATE_MASK);
829 command &= 0xFFFFFFFC;
830 pci_write_config(dev, RL_PCI_PWRMGMTCTRL, command, 4);
832 /* Restore PCI config data. */
833 pci_write_config(dev, RL_PCI_LOIO, iobase, 4);
834 pci_write_config(dev, RL_PCI_LOMEM, membase, 4);
835 pci_write_config(dev, RL_PCI_INTLINE, irq, 4);
840 * Map control/status registers.
842 command = pci_read_config(dev, PCIR_COMMAND, 4);
843 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
844 pci_write_config(dev, PCIR_COMMAND, command, 4);
845 command = pci_read_config(dev, PCIR_COMMAND, 4);
848 if (!(command & PCIM_CMD_PORTEN)) {
849 printf("rl%d: failed to enable I/O ports!\n", unit);
854 if (!(command & PCIM_CMD_MEMEN)) {
855 printf("rl%d: failed to enable memory mapping!\n", unit);
862 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid,
863 0, ~0, 1, RF_ACTIVE);
865 if (sc->rl_res == NULL) {
866 printf ("rl%d: couldn't map ports/memory\n", unit);
871 sc->rl_btag = rman_get_bustag(sc->rl_res);
872 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
875 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
876 RF_SHAREABLE | RF_ACTIVE);
878 if (sc->rl_irq == NULL) {
879 printf("rl%d: couldn't map interrupt\n", unit);
880 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
885 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET,
886 rl_intr, sc, &sc->rl_intrhand);
889 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
890 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
891 printf("rl%d: couldn't set up irq\n", unit);
895 callout_handle_init(&sc->rl_stat_ch);
897 /* Reset the adapter. */
901 * Get station address from the EEPROM.
903 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0);
906 * A RealTek chip was detected. Inform the world.
908 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":");
911 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
914 * Now read the exact device type from the EEPROM to find
915 * out if it's an 8129 or 8139.
917 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
919 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 ||
920 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 ||
921 rl_did == DLINK_DEVICEID_530TXPLUS)
922 sc->rl_type = RL_8139;
923 else if (rl_did == RT_DEVICEID_8129)
924 sc->rl_type = RL_8129;
926 printf("rl%d: unknown device ID: %x\n", unit, rl_did);
927 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
928 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
929 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
934 sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 1518, M_DEVBUF,
935 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
937 if (sc->rl_cdata.rl_rx_buf == NULL) {
938 printf("rl%d: no memory for list buffers!\n", unit);
939 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
940 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
941 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
946 /* Leave a few bytes before the start of the RX ring buffer. */
947 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
948 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
951 if (mii_phy_probe(dev, &sc->rl_miibus,
952 rl_ifmedia_upd, rl_ifmedia_sts)) {
953 printf("rl%d: MII without any phy!\n", sc->rl_unit);
954 contigfree(sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN + 1518,
956 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
957 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
958 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
959 free(sc->rl_cdata.rl_rx_buf, M_DEVBUF);
964 ifp = &sc->arpcom.ac_if;
966 if_initname(ifp, "rl", unit);
967 ifp->if_mtu = ETHERMTU;
968 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
969 ifp->if_ioctl = rl_ioctl;
970 ifp->if_output = ether_output;
971 ifp->if_start = rl_start;
972 ifp->if_watchdog = rl_watchdog;
973 ifp->if_init = rl_init;
974 ifp->if_baudrate = 10000000;
975 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
978 * Call MI attach routine.
980 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
987 static int rl_detach(dev)
996 sc = device_get_softc(dev);
997 ifp = &sc->arpcom.ac_if;
999 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1002 bus_generic_detach(dev);
1003 device_delete_child(dev, sc->rl_miibus);
1005 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1006 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1007 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1009 contigfree(sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN + 1518, M_DEVBUF);
1017 * Initialize the transmit descriptors.
1019 static int rl_list_tx_init(sc)
1020 struct rl_softc *sc;
1022 struct rl_chain_data *cd;
1026 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1027 cd->rl_tx_chain[i] = NULL;
1029 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000);
1032 sc->rl_cdata.cur_tx = 0;
1033 sc->rl_cdata.last_tx = 0;
1039 * A frame has been uploaded: pass the resulting mbuf chain up to
1040 * the higher level protocols.
1042 * You know there's something wrong with a PCI bus-master chip design
1043 * when you have to use m_devget().
1045 * The receive operation is badly documented in the datasheet, so I'll
1046 * attempt to document it here. The driver provides a buffer area and
1047 * places its base address in the RX buffer start address register.
1048 * The chip then begins copying frames into the RX buffer. Each frame
1049 * is preceeded by a 32-bit RX status word which specifies the length
1050 * of the frame and certain other status bits. Each frame (starting with
1051 * the status word) is also 32-bit aligned. The frame length is in the
1052 * first 16 bits of the status word; the lower 15 bits correspond with
1053 * the 'rx status register' mentioned in the datasheet.
1055 * Note: to make the Alpha happy, the frame payload needs to be aligned
1056 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from
1057 * the ring buffer starting at an address two bytes before the actual
1058 * data location. We can then shave off the first two bytes using m_adj().
1059 * The reason we do this is because m_devget() doesn't let us specify an
1060 * offset into the mbuf storage space, so we have to artificially create
1061 * one. The ring is allocated in such a way that there are a few unused
1062 * bytes of space preceecing it so that it will be safe for us to do the
1063 * 2-byte backstep even if reading from the ring at offset 0.
1065 static void rl_rxeof(sc)
1066 struct rl_softc *sc;
1068 struct ether_header *eh;
1077 u_int16_t rx_bytes = 0, max_bytes;
1079 ifp = &sc->arpcom.ac_if;
1081 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1083 /* Do not try to read past this point. */
1084 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1087 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1089 max_bytes = limit - cur_rx;
1091 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1092 #ifdef DEVICE_POLLING
1093 if (ifp->if_ipending & IFF_POLLING) {
1094 if (sc->rxcycles <= 0)
1098 #endif /* DEVICE_POLLING */
1099 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1100 rxstat = *(u_int32_t *)rxbufpos;
1103 * Here's a totally undocumented fact for you. When the
1104 * RealTek chip is in the process of copying a packet into
1105 * RAM for you, the length will be 0xfff0. If you spot a
1106 * packet header with this value, you need to stop. The
1107 * datasheet makes absolutely no mention of this and
1108 * RealTek should be shot for this.
1110 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1113 if (!(rxstat & RL_RXSTAT_RXOK)) {
1119 /* No errors; receive the packet. */
1120 total_len = rxstat >> 16;
1121 rx_bytes += total_len + 4;
1124 * XXX The RealTek chip includes the CRC with every
1125 * received frame, and there's no way to turn this
1126 * behavior off (at least, I can't find anything in
1127 * the manual that explains how to do it) so we have
1128 * to trim off the CRC manually.
1130 total_len -= ETHER_CRC_LEN;
1133 * Avoid trying to read more bytes than we know
1134 * the chip has prepared for us.
1136 if (rx_bytes > max_bytes)
1139 rxbufpos = sc->rl_cdata.rl_rx_buf +
1140 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN);
1142 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1143 rxbufpos = sc->rl_cdata.rl_rx_buf;
1145 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1147 if (total_len > wrap) {
1149 * Fool m_devget() into thinking we want to copy
1150 * the whole buffer so we don't end up fragmenting
1153 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1154 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1158 m_adj(m, RL_ETHER_ALIGN);
1159 m_copyback(m, wrap, total_len - wrap,
1160 sc->rl_cdata.rl_rx_buf);
1162 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1164 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1165 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1169 m_adj(m, RL_ETHER_ALIGN);
1170 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1174 * Round up to 32-bit boundary.
1176 cur_rx = (cur_rx + 3) & ~3;
1177 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1182 eh = mtod(m, struct ether_header *);
1185 /* Remove header from mbuf and pass it on. */
1186 m_adj(m, sizeof(struct ether_header));
1187 ether_input(ifp, eh, m);
1194 * A frame was downloaded to the chip. It's safe for us to clean up
1197 static void rl_txeof(sc)
1198 struct rl_softc *sc;
1203 ifp = &sc->arpcom.ac_if;
1206 * Go through our tx list and free mbufs for those
1207 * frames that have been uploaded.
1210 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1211 if (!(txstat & (RL_TXSTAT_TX_OK|
1212 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1215 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1217 if (RL_LAST_TXMBUF(sc) != NULL) {
1218 m_freem(RL_LAST_TXMBUF(sc));
1219 RL_LAST_TXMBUF(sc) = NULL;
1221 if (txstat & RL_TXSTAT_TX_OK)
1226 if ((txstat & RL_TXSTAT_TXABRT) ||
1227 (txstat & RL_TXSTAT_OUTOFWIN))
1228 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1229 oldthresh = sc->rl_txthresh;
1230 /* error recovery */
1234 * If there was a transmit underrun,
1235 * bump the TX threshold.
1237 if (txstat & RL_TXSTAT_TX_UNDERRUN)
1238 sc->rl_txthresh = oldthresh + 32;
1241 RL_INC(sc->rl_cdata.last_tx);
1242 ifp->if_flags &= ~IFF_OACTIVE;
1243 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1246 (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) ? 0 : 5;
1251 static void rl_tick(xsc)
1254 struct rl_softc *sc;
1255 struct mii_data *mii;
1261 mii = device_get_softc(sc->rl_miibus);
1267 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1272 #ifdef DEVICE_POLLING
1273 static poll_handler_t rl_poll;
1276 rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count)
1278 struct rl_softc *sc = ifp->if_softc;
1280 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1281 CSR_WRITE_4(sc, RL_IMR, RL_INTRS);
1285 sc->rxcycles = count;
1288 if (ifp->if_snd.ifq_head != NULL)
1291 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1294 status = CSR_READ_2(sc, RL_ISR);
1296 CSR_WRITE_2(sc, RL_ISR, status);
1299 * XXX check behaviour on receiver stalls.
1302 if (status & RL_ISR_SYSTEM_ERR) {
1308 #endif /* DEVICE_POLLING */
1310 static void rl_intr(arg)
1313 struct rl_softc *sc;
1319 if (sc->suspended) {
1323 ifp = &sc->arpcom.ac_if;
1324 #ifdef DEVICE_POLLING
1325 if (ifp->if_ipending & IFF_POLLING)
1327 if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */
1328 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1332 #endif /* DEVICE_POLLING */
1336 status = CSR_READ_2(sc, RL_ISR);
1338 CSR_WRITE_2(sc, RL_ISR, status);
1340 if ((status & RL_INTRS) == 0)
1343 if (status & RL_ISR_RX_OK)
1346 if (status & RL_ISR_RX_ERR)
1349 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1352 if (status & RL_ISR_SYSTEM_ERR) {
1358 if (ifp->if_snd.ifq_head != NULL)
1365 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1366 * pointers to the fragment pointers.
1368 static int rl_encap(sc, m_head)
1369 struct rl_softc *sc;
1370 struct mbuf *m_head;
1372 struct mbuf *m_new = NULL;
1375 * The RealTek is brain damaged and wants longword-aligned
1376 * TX buffers, plus we can only have one fragment buffer
1377 * per packet. We have to copy pretty much all the time.
1380 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1383 if (m_head->m_pkthdr.len > MHLEN) {
1384 MCLGET(m_new, M_DONTWAIT);
1385 if (!(m_new->m_flags & M_EXT)) {
1390 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1391 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1395 /* Pad frames to at least 60 bytes. */
1396 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1398 * Make security concious people happy: zero out the
1399 * bytes in the pad area, since we don't know what
1400 * this mbuf cluster buffer's previous user might
1403 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
1404 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1405 m_head->m_pkthdr.len +=
1406 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1407 m_head->m_len = m_head->m_pkthdr.len;
1410 RL_CUR_TXMBUF(sc) = m_head;
1416 * Main transmit routine.
1419 static void rl_start(ifp)
1422 struct rl_softc *sc;
1423 struct mbuf *m_head = NULL;
1427 while(RL_CUR_TXMBUF(sc) == NULL) {
1428 IF_DEQUEUE(&ifp->if_snd, m_head);
1432 if (rl_encap(sc, m_head)) {
1433 IF_PREPEND(&ifp->if_snd, m_head);
1434 ifp->if_flags |= IFF_OACTIVE;
1439 * If there's a BPF listener, bounce a copy of this frame
1443 bpf_mtap(ifp, RL_CUR_TXMBUF(sc));
1446 * Transmit the frame.
1448 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc),
1449 vtophys(mtod(RL_CUR_TXMBUF(sc), caddr_t)));
1450 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1451 RL_TXTHRESH(sc->rl_txthresh) |
1452 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1454 RL_INC(sc->rl_cdata.cur_tx);
1458 * We broke out of the loop because all our TX slots are
1459 * full. Mark the NIC as busy until it drains some of the
1460 * packets from the queue.
1462 if (RL_CUR_TXMBUF(sc) != NULL)
1463 ifp->if_flags |= IFF_OACTIVE;
1466 * Set a timeout in case the chip goes out to lunch.
1473 static void rl_init(xsc)
1476 struct rl_softc *sc = xsc;
1477 struct ifnet *ifp = &sc->arpcom.ac_if;
1478 struct mii_data *mii;
1480 u_int32_t rxcfg = 0;
1484 mii = device_get_softc(sc->rl_miibus);
1487 * Cancel pending I/O and free all RX/TX buffers.
1491 /* Init our MAC address */
1492 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1493 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]);
1496 /* Init the RX buffer pointer register. */
1497 CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf));
1499 /* Init TX descriptors. */
1500 rl_list_tx_init(sc);
1503 * Enable transmit and receive.
1505 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1508 * Set the initial TX and RX configuration.
1510 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1511 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1513 /* Set the individual bit to receive frames for this host only. */
1514 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1515 rxcfg |= RL_RXCFG_RX_INDIV;
1517 /* If we want promiscuous mode, set the allframes bit. */
1518 if (ifp->if_flags & IFF_PROMISC) {
1519 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1520 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1522 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1523 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1527 * Set capture broadcast bit to capture broadcast frames.
1529 if (ifp->if_flags & IFF_BROADCAST) {
1530 rxcfg |= RL_RXCFG_RX_BROAD;
1531 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1533 rxcfg &= ~RL_RXCFG_RX_BROAD;
1534 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1538 * Program the multicast filter, if necessary.
1542 #ifdef DEVICE_POLLING
1544 * Only enable interrupts if we are polling, keep them off otherwise.
1546 if (ifp->if_ipending & IFF_POLLING)
1547 CSR_WRITE_2(sc, RL_IMR, 0);
1549 #endif /* DEVICE_POLLING */
1551 * Enable interrupts.
1553 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1555 /* Set initial TX threshold */
1556 sc->rl_txthresh = RL_TX_THRESH_INIT;
1558 /* Start RX/TX process. */
1559 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1561 /* Enable receiver and transmitter. */
1562 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1566 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1568 ifp->if_flags |= IFF_RUNNING;
1569 ifp->if_flags &= ~IFF_OACTIVE;
1573 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1579 * Set media options.
1581 static int rl_ifmedia_upd(ifp)
1584 struct rl_softc *sc;
1585 struct mii_data *mii;
1588 mii = device_get_softc(sc->rl_miibus);
1595 * Report current media status.
1597 static void rl_ifmedia_sts(ifp, ifmr)
1599 struct ifmediareq *ifmr;
1601 struct rl_softc *sc;
1602 struct mii_data *mii;
1605 mii = device_get_softc(sc->rl_miibus);
1608 ifmr->ifm_active = mii->mii_media_active;
1609 ifmr->ifm_status = mii->mii_media_status;
1614 static int rl_ioctl(ifp, command, data)
1619 struct rl_softc *sc = ifp->if_softc;
1620 struct ifreq *ifr = (struct ifreq *) data;
1621 struct mii_data *mii;
1630 error = ether_ioctl(ifp, command, data);
1633 if (ifp->if_flags & IFF_UP) {
1636 if (ifp->if_flags & IFF_RUNNING)
1648 mii = device_get_softc(sc->rl_miibus);
1649 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1661 static void rl_watchdog(ifp)
1664 struct rl_softc *sc;
1668 printf("rl%d: watchdog timeout\n", sc->rl_unit);
1679 * Stop the adapter and free any mbufs allocated to the
1682 static void rl_stop(sc)
1683 struct rl_softc *sc;
1688 ifp = &sc->arpcom.ac_if;
1691 untimeout(rl_tick, sc, sc->rl_stat_ch);
1692 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1693 #ifdef DEVICE_POLLING
1694 ether_poll_deregister(ifp);
1695 #endif /* DEVICE_POLLING */
1697 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1698 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1701 * Free the TX list buffers.
1703 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1704 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1705 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1706 sc->rl_cdata.rl_tx_chain[i] = NULL;
1707 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000);
1716 * Stop all chip I/O so that the kernel's probe routines don't
1717 * get confused by errant DMAs when rebooting.
1719 static void rl_shutdown(dev)
1722 struct rl_softc *sc;
1724 sc = device_get_softc(dev);
1732 * Device suspend routine. Stop the interface and save some PCI
1733 * settings in case the BIOS doesn't restore them properly on
1736 static int rl_suspend(dev)
1740 struct rl_softc *sc;
1742 sc = device_get_softc(dev);
1746 for (i = 0; i < 5; i++)
1747 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
1748 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
1749 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
1750 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
1751 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
1759 * Device resume routine. Restore some PCI settings in case the BIOS
1760 * doesn't, re-enable busmastering, and restart the interface if
1763 static int rl_resume(dev)
1767 struct rl_softc *sc;
1770 sc = device_get_softc(dev);
1771 ifp = &sc->arpcom.ac_if;
1773 /* better way to do this? */
1774 for (i = 0; i < 5; i++)
1775 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
1776 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
1777 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
1778 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
1779 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
1781 /* reenable busmastering */
1782 pci_enable_busmaster(dev);
1783 pci_enable_io(dev, RL_RES);
1785 /* reinitialize interface if necessary */
1786 if (ifp->if_flags & IFF_UP)