sys/dev/netif/sk/if_sk.c

   1 /*      $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ */
   2
   3 /*
   4  * Copyright (c) 1997, 1998, 1999, 2000
   5  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by Bill Paul.
  18  * 4. Neither the name of the author nor the names of any co-contributors
  19  *    may be used to endorse or promote products derived from this software
  20  *    without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  32  * THE POSSIBILITY OF SUCH DAMAGE.
  33  *
  34  * $FreeBSD: src/sys/pci/if_sk.c,v 1.19.2.9 2003/03/05 18:42:34 njl Exp $
  35  * $DragonFly: src/sys/dev/netif/sk/if_sk.c,v 1.8 2003/11/12 22:43:07 dillon Exp $
  36  *
  37  * $FreeBSD: src/sys/pci/if_sk.c,v 1.19.2.9 2003/03/05 18:42:34 njl Exp $
  38  */
  39
  40 /*
  41  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
  42  *
  43  * Permission to use, copy, modify, and distribute this software for any
  44  * purpose with or without fee is hereby granted, provided that the above
  45  * copyright notice and this permission notice appear in all copies.
  46  *
  47  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  48  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  49  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  50  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  51  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  52  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  53  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  54  */
  55
  56 /*
  57  * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
  58  * the SK-984x series adapters, both single port and dual port.
  59  * References:
  60  *      The XaQti XMAC II datasheet,
  61  *  http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  62  *      The SysKonnect GEnesis manual, http://www.syskonnect.com
  63  *
  64  * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the
  65  * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
  66  * convenience to others until Vitesse corrects this problem:
  67  *
  68  * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  69  *
  70  * Written by Bill Paul <wpaul@ee.columbia.edu>
  71  * Department of Electrical Engineering
  72  * Columbia University, New York City
  73  */
  74
  75 /*
  76  * The SysKonnect gigabit ethernet adapters consist of two main
  77  * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
  78  * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
  79  * components and a PHY while the GEnesis controller provides a PCI
  80  * interface with DMA support. Each card may have between 512K and
  81  * 2MB of SRAM on board depending on the configuration.
  82  *
  83  * The SysKonnect GEnesis controller can have either one or two XMAC
  84  * chips connected to it, allowing single or dual port NIC configurations.
  85  * SysKonnect has the distinction of being the only vendor on the market
  86  * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
  87  * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
  88  * XMAC registers. This driver takes advantage of these features to allow
  89  * both XMACs to operate as independent interfaces.
  90  */
  91
  92 #include <sys/param.h>
  93 #include <sys/systm.h>
  94 #include <sys/sockio.h>
  95 #include <sys/mbuf.h>
  96 #include <sys/malloc.h>
  97 #include <sys/kernel.h>
  98 #include <sys/socket.h>
  99 #include <sys/queue.h>
 100
 101 #include <net/if.h>
 102 #include <net/if_arp.h>
 103 #include <net/ethernet.h>
 104 #include <net/if_dl.h>
 105 #include <net/if_media.h>
 106
 107 #include <net/bpf.h>
 108
 109 #include <vm/vm.h>              /* for vtophys */
 110 #include <vm/pmap.h>            /* for vtophys */
 111 #include <machine/clock.h>      /* for DELAY */
 112 #include <machine/bus_pio.h>
 113 #include <machine/bus_memio.h>
 114 #include <machine/bus.h>
 115 #include <machine/resource.h>
 116 #include <sys/bus.h>
 117 #include <sys/rman.h>
 118
 119 #include "../mii_layer/mii.h"
 120 #include "../mii_layer/miivar.h"
 121 #include "../mii_layer/brgphyreg.h"
 122
 123 #include <bus/pci/pcireg.h>
 124 #include <bus/pci/pcivar.h>
 125
 126 #if 0
 127 #define SK_USEIOSPACE
 128 #endif
 129
 130 #include "if_skreg.h"
 131 #include "xmaciireg.h"
 132 #include "yukonreg.h"
 133
 134 /* "controller miibus0" required.  See GENERIC if you get errors here. */
 135 #include "miibus_if.h"
 136
 137 static struct sk_type sk_devs[] = {
 138         {
 139                 VENDORID_SK,
 140                 DEVICEID_SK_V1,
 141                 "SysKonnect Gigabit Ethernet (V1.0)"
 142         },
 143         {
 144                 VENDORID_SK,
 145                 DEVICEID_SK_V2,
 146                 "SysKonnect Gigabit Ethernet (V2.0)"
 147         },
 148         {
 149                 VENDORID_MARVELL,
 150                 DEVICEID_SK_V2,
 151                 "Marvell Gigabit Ethernet"
 152         },
 153         {
 154                 VENDORID_3COM,
 155                 DEVICEID_3COM_3C940,
 156                 "3Com 3C940 Gigabit Ethernet"
 157         },
 158         { 0, 0, NULL }
 159 };
 160
 161 static int skc_probe            (device_t);
 162 static int skc_attach           (device_t);
 163 static int skc_detach           (device_t);
 164 static void skc_shutdown        (device_t);
 165 static int sk_probe             (device_t);
 166 static int sk_attach            (device_t);
 167 static int sk_detach            (device_t);
 168 static void sk_tick             (void *);
 169 static void sk_intr             (void *);
 170 static void sk_intr_bcom        (struct sk_if_softc *);
 171 static void sk_intr_xmac        (struct sk_if_softc *);
 172 static void sk_intr_yukon       (struct sk_if_softc *);
 173 static void sk_rxeof            (struct sk_if_softc *);
 174 static void sk_txeof            (struct sk_if_softc *);
 175 static int sk_encap             (struct sk_if_softc *, struct mbuf *,
 176                                         u_int32_t *);
 177 static void sk_start            (struct ifnet *);
 178 static int sk_ioctl             (struct ifnet *, u_long, caddr_t);
 179 static void sk_init             (void *);
 180 static void sk_init_xmac        (struct sk_if_softc *);
 181 static void sk_init_yukon       (struct sk_if_softc *);
 182 static void sk_stop             (struct sk_if_softc *);
 183 static void sk_watchdog         (struct ifnet *);
 184 static int sk_ifmedia_upd       (struct ifnet *);
 185 static void sk_ifmedia_sts      (struct ifnet *, struct ifmediareq *);
 186 static void sk_reset            (struct sk_softc *);
 187 static int sk_newbuf            (struct sk_if_softc *,
 188                                         struct sk_chain *, struct mbuf *);
 189 static int sk_alloc_jumbo_mem   (struct sk_if_softc *);
 190 static void *sk_jalloc          (struct sk_if_softc *);
 191 static void sk_jfree            (caddr_t, u_int);
 192 static void sk_jref             (caddr_t, u_int);
 193 static int sk_init_rx_ring      (struct sk_if_softc *);
 194 static void sk_init_tx_ring     (struct sk_if_softc *);
 195 static u_int32_t sk_win_read_4  (struct sk_softc *, int);
 196 static u_int16_t sk_win_read_2  (struct sk_softc *, int);
 197 static u_int8_t sk_win_read_1   (struct sk_softc *, int);
 198 static void sk_win_write_4      (struct sk_softc *, int, u_int32_t);
 199 static void sk_win_write_2      (struct sk_softc *, int, u_int32_t);
 200 static void sk_win_write_1      (struct sk_softc *, int, u_int32_t);
 201 static u_int8_t sk_vpd_readbyte (struct sk_softc *, int);
 202 static void sk_vpd_read_res     (struct sk_softc *,
 203                                         struct vpd_res *, int);
 204 static void sk_vpd_read         (struct sk_softc *);
 205
 206 static int sk_miibus_readreg    (device_t, int, int);
 207 static int sk_miibus_writereg   (device_t, int, int, int);
 208 static void sk_miibus_statchg   (device_t);
 209
 210 static int sk_xmac_miibus_readreg     (struct sk_if_softc *, int, int);
 211 static int sk_xmac_miibus_writereg    (struct sk_if_softc *, int, int, int);
 212 static void sk_xmac_miibus_statchg    (struct sk_if_softc *);
 213
 214 static int sk_marv_miibus_readreg     (struct sk_if_softc *, int, int);
 215 static int sk_marv_miibus_writereg    (struct sk_if_softc *, int, int, int);
 216 static void sk_marv_miibus_statchg    (struct sk_if_softc *);
 217
 218 static u_int32_t sk_calchash    (caddr_t);
 219 static void sk_setfilt          (struct sk_if_softc *, caddr_t, int);
 220 static void sk_setmulti         (struct sk_if_softc *);
 221 static void sk_setpromisc       (struct sk_if_softc *);
 222
 223 #ifdef SK_USEIOSPACE
 224 #define SK_RES          SYS_RES_IOPORT
 225 #define SK_RID          SK_PCI_LOIO
 226 #else
 227 #define SK_RES          SYS_RES_MEMORY
 228 #define SK_RID          SK_PCI_LOMEM
 229 #endif
 230
 231 /*
 232  * Note that we have newbus methods for both the GEnesis controller
 233  * itself and the XMAC(s). The XMACs are children of the GEnesis, and
 234  * the miibus code is a child of the XMACs. We need to do it this way
 235  * so that the miibus drivers can access the PHY registers on the
 236  * right PHY. It's not quite what I had in mind, but it's the only
 237  * design that achieves the desired effect.
 238  */
 239 static device_method_t skc_methods[] = {
 240         /* Device interface */
 241         DEVMETHOD(device_probe,         skc_probe),
 242         DEVMETHOD(device_attach,        skc_attach),
 243         DEVMETHOD(device_detach,        skc_detach),
 244         DEVMETHOD(device_shutdown,      skc_shutdown),
 245
 246         /* bus interface */
 247         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 248         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 249
 250         { 0, 0 }
 251 };
 252
 253 static driver_t skc_driver = {
 254         "skc",
 255         skc_methods,
 256         sizeof(struct sk_softc)
 257 };
 258
 259 static devclass_t skc_devclass;
 260
 261 static device_method_t sk_methods[] = {
 262         /* Device interface */
 263         DEVMETHOD(device_probe,         sk_probe),
 264         DEVMETHOD(device_attach,        sk_attach),
 265         DEVMETHOD(device_detach,        sk_detach),
 266         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 267
 268         /* bus interface */
 269         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 270         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 271
 272         /* MII interface */
 273         DEVMETHOD(miibus_readreg,       sk_miibus_readreg),
 274         DEVMETHOD(miibus_writereg,      sk_miibus_writereg),
 275         DEVMETHOD(miibus_statchg,       sk_miibus_statchg),
 276
 277         { 0, 0 }
 278 };
 279
 280 static driver_t sk_driver = {
 281         "sk",
 282         sk_methods,
 283         sizeof(struct sk_if_softc)
 284 };
 285
 286 static devclass_t sk_devclass;
 287
 288 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0);
 289 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0);
 290 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0);
 291
 292 #define SK_SETBIT(sc, reg, x)           \
 293         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
 294
 295 #define SK_CLRBIT(sc, reg, x)           \
 296         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
 297
 298 #define SK_WIN_SETBIT_4(sc, reg, x)     \
 299         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
 300
 301 #define SK_WIN_CLRBIT_4(sc, reg, x)     \
 302         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
 303
 304 #define SK_WIN_SETBIT_2(sc, reg, x)     \
 305         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
 306
 307 #define SK_WIN_CLRBIT_2(sc, reg, x)     \
 308         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
 309
 310 static u_int32_t sk_win_read_4(sc, reg)
 311         struct sk_softc         *sc;
 312         int                     reg;
 313 {
 314 #ifdef SK_USEIOSPACE
 315         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 316         return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
 317 #else
 318         return(CSR_READ_4(sc, reg));
 319 #endif
 320 }
 321
 322 static u_int16_t sk_win_read_2(sc, reg)
 323         struct sk_softc         *sc;
 324         int                     reg;
 325 {
 326 #ifdef SK_USEIOSPACE
 327         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 328         return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
 329 #else
 330         return(CSR_READ_2(sc, reg));
 331 #endif
 332 }
 333
 334 static u_int8_t sk_win_read_1(sc, reg)
 335         struct sk_softc         *sc;
 336         int                     reg;
 337 {
 338 #ifdef SK_USEIOSPACE
 339         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 340         return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
 341 #else
 342         return(CSR_READ_1(sc, reg));
 343 #endif
 344 }
 345
 346 static void sk_win_write_4(sc, reg, val)
 347         struct sk_softc         *sc;
 348         int                     reg;
 349         u_int32_t               val;
 350 {
 351 #ifdef SK_USEIOSPACE
 352         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 353         CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
 354 #else
 355         CSR_WRITE_4(sc, reg, val);
 356 #endif
 357         return;
 358 }
 359
 360 static void sk_win_write_2(sc, reg, val)
 361         struct sk_softc         *sc;
 362         int                     reg;
 363         u_int32_t               val;
 364 {
 365 #ifdef SK_USEIOSPACE
 366         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 367         CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
 368 #else
 369         CSR_WRITE_2(sc, reg, val);
 370 #endif
 371         return;
 372 }
 373
 374 static void sk_win_write_1(sc, reg, val)
 375         struct sk_softc         *sc;
 376         int                     reg;
 377         u_int32_t               val;
 378 {
 379 #ifdef SK_USEIOSPACE
 380         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 381         CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
 382 #else
 383         CSR_WRITE_1(sc, reg, val);
 384 #endif
 385         return;
 386 }
 387
 388 /*
 389  * The VPD EEPROM contains Vital Product Data, as suggested in
 390  * the PCI 2.1 specification. The VPD data is separared into areas
 391  * denoted by resource IDs. The SysKonnect VPD contains an ID string
 392  * resource (the name of the adapter), a read-only area resource
 393  * containing various key/data fields and a read/write area which
 394  * can be used to store asset management information or log messages.
 395  * We read the ID string and read-only into buffers attached to
 396  * the controller softc structure for later use. At the moment,
 397  * we only use the ID string during sk_attach().
 398  */
 399 static u_int8_t sk_vpd_readbyte(sc, addr)
 400         struct sk_softc         *sc;
 401         int                     addr;
 402 {
 403         int                     i;
 404
 405         sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr);
 406         for (i = 0; i < SK_TIMEOUT; i++) {
 407                 DELAY(1);
 408                 if (sk_win_read_2(sc,
 409                     SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG)
 410                         break;
 411         }
 412
 413         if (i == SK_TIMEOUT)
 414                 return(0);
 415
 416         return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)));
 417 }
 418
 419 static void sk_vpd_read_res(sc, res, addr)
 420         struct sk_softc         *sc;
 421         struct vpd_res          *res;
 422         int                     addr;
 423 {
 424         int                     i;
 425         u_int8_t                *ptr;
 426
 427         ptr = (u_int8_t *)res;
 428         for (i = 0; i < sizeof(struct vpd_res); i++)
 429                 ptr[i] = sk_vpd_readbyte(sc, i + addr);
 430
 431         return;
 432 }
 433
 434 static void sk_vpd_read(sc)
 435         struct sk_softc         *sc;
 436 {
 437         int                     pos = 0, i;
 438         struct vpd_res          res;
 439
 440         if (sc->sk_vpd_prodname != NULL)
 441                 free(sc->sk_vpd_prodname, M_DEVBUF);
 442         if (sc->sk_vpd_readonly != NULL)
 443                 free(sc->sk_vpd_readonly, M_DEVBUF);
 444         sc->sk_vpd_prodname = NULL;
 445         sc->sk_vpd_readonly = NULL;
 446
 447         sk_vpd_read_res(sc, &res, pos);
 448
 449         if (res.vr_id != VPD_RES_ID) {
 450                 printf("skc%d: bad VPD resource id: expected %x got %x\n",
 451                     sc->sk_unit, VPD_RES_ID, res.vr_id);
 452                 return;
 453         }
 454
 455         pos += sizeof(res);
 456         sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT);
 457         for (i = 0; i < res.vr_len; i++)
 458                 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos);
 459         sc->sk_vpd_prodname[i] = '\0';
 460         pos += i;
 461
 462         sk_vpd_read_res(sc, &res, pos);
 463
 464         if (res.vr_id != VPD_RES_READ) {
 465                 printf("skc%d: bad VPD resource id: expected %x got %x\n",
 466                     sc->sk_unit, VPD_RES_READ, res.vr_id);
 467                 return;
 468         }
 469
 470         pos += sizeof(res);
 471         sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT);
 472         for (i = 0; i < res.vr_len + 1; i++)
 473                 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos);
 474
 475         return;
 476 }
 477
 478 static int sk_miibus_readreg(dev, phy, reg)
 479         device_t                dev;
 480         int                     phy, reg;
 481 {
 482         struct sk_if_softc      *sc_if;
 483
 484         sc_if = device_get_softc(dev);
 485
 486         switch(sc_if->sk_softc->sk_type) {
 487         case SK_GENESIS:
 488                 return(sk_xmac_miibus_readreg(sc_if, phy, reg));
 489         case SK_YUKON:
 490                 return(sk_marv_miibus_readreg(sc_if, phy, reg));
 491         }
 492
 493         return(0);
 494 }
 495
 496 static int sk_miibus_writereg(dev, phy, reg, val)
 497         device_t                dev;
 498         int                     phy, reg, val;
 499 {
 500         struct sk_if_softc      *sc_if;
 501
 502         sc_if = device_get_softc(dev);
 503
 504         switch(sc_if->sk_softc->sk_type) {
 505         case SK_GENESIS:
 506                 return(sk_xmac_miibus_writereg(sc_if, phy, reg, val));
 507         case SK_YUKON:
 508                 return(sk_marv_miibus_writereg(sc_if, phy, reg, val));
 509         }
 510
 511         return(0);
 512 }
 513
 514 static void sk_miibus_statchg(dev)
 515         device_t                dev;
 516 {
 517         struct sk_if_softc      *sc_if;
 518
 519         sc_if = device_get_softc(dev);
 520
 521         switch(sc_if->sk_softc->sk_type) {
 522         case SK_GENESIS:
 523                 sk_xmac_miibus_statchg(sc_if);
 524                 break;
 525         case SK_YUKON:
 526                 sk_marv_miibus_statchg(sc_if);
 527                 break;
 528         }
 529
 530         return;
 531 }
 532
 533 static int sk_xmac_miibus_readreg(sc_if, phy, reg)
 534         struct sk_if_softc      *sc_if;
 535         int                     phy, reg;
 536 {
 537         int                     i;
 538
 539         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
 540                 return(0);
 541
 542         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 543         SK_XM_READ_2(sc_if, XM_PHY_DATA);
 544         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 545                 for (i = 0; i < SK_TIMEOUT; i++) {
 546                         DELAY(1);
 547                         if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
 548                             XM_MMUCMD_PHYDATARDY)
 549                                 break;
 550                 }
 551
 552                 if (i == SK_TIMEOUT) {
 553                         printf("sk%d: phy failed to come ready\n",
 554                             sc_if->sk_unit);
 555                         return(0);
 556                 }
 557         }
 558         DELAY(1);
 559         return(SK_XM_READ_2(sc_if, XM_PHY_DATA));
 560 }
 561
 562 static int sk_xmac_miibus_writereg(sc_if, phy, reg, val)
 563         struct sk_if_softc      *sc_if;
 564         int                     phy, reg, val;
 565 {
 566         int                     i;
 567
 568         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 569         for (i = 0; i < SK_TIMEOUT; i++) {
 570                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
 571                         break;
 572         }
 573
 574         if (i == SK_TIMEOUT) {
 575                 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit);
 576                 return(ETIMEDOUT);
 577         }
 578
 579         SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
 580         for (i = 0; i < SK_TIMEOUT; i++) {
 581                 DELAY(1);
 582                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
 583                         break;
 584         }
 585
 586         if (i == SK_TIMEOUT)
 587                 printf("sk%d: phy write timed out\n", sc_if->sk_unit);
 588
 589         return(0);
 590 }
 591
 592 static void sk_xmac_miibus_statchg(sc_if)
 593         struct sk_if_softc      *sc_if;
 594 {
 595         struct mii_data         *mii;
 596
 597         mii = device_get_softc(sc_if->sk_miibus);
 598
 599         /*
 600          * If this is a GMII PHY, manually set the XMAC's
 601          * duplex mode accordingly.
 602          */
 603         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 604                 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 605                         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 606                 } else {
 607                         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 608                 }
 609         }
 610
 611         return;
 612 }
 613
 614 static int sk_marv_miibus_readreg(sc_if, phy, reg)
 615         struct sk_if_softc      *sc_if;
 616         int                     phy, reg;
 617 {
 618         u_int16_t               val;
 619         int                     i;
 620
 621         if (phy != 0 ||
 622             (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
 623              sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
 624                 return(0);
 625         }
 626
 627         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 628                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
 629
 630         for (i = 0; i < SK_TIMEOUT; i++) {
 631                 DELAY(1);
 632                 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
 633                 if (val & YU_SMICR_READ_VALID)
 634                         break;
 635         }
 636
 637         if (i == SK_TIMEOUT) {
 638                 printf("sk%d: phy failed to come ready\n",
 639                     sc_if->sk_unit);
 640                 return(0);
 641         }
 642
 643         val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
 644
 645         return(val);
 646 }
 647
 648 static int sk_marv_miibus_writereg(sc_if, phy, reg, val)
 649         struct sk_if_softc      *sc_if;
 650         int                     phy, reg, val;
 651 {
 652         int                     i;
 653
 654         SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
 655         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 656                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
 657
 658         for (i = 0; i < SK_TIMEOUT; i++) {
 659                 DELAY(1);
 660                 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)
 661                         break;
 662         }
 663
 664         return(0);
 665 }
 666
 667 static void sk_marv_miibus_statchg(sc_if)
 668         struct sk_if_softc      *sc_if;
 669 {
 670         return;
 671 }
 672
 673 #define SK_POLY         0xEDB88320
 674 #define SK_BITS         6
 675
 676 static u_int32_t sk_calchash(addr)
 677         caddr_t                 addr;
 678 {
 679         u_int32_t               idx, bit, data, crc;
 680
 681         /* Compute CRC for the address value. */
 682         crc = 0xFFFFFFFF; /* initial value */
 683
 684         for (idx = 0; idx < 6; idx++) {
 685                 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
 686                         crc = (crc >> 1) ^ (((crc ^ data) & 1) ? SK_POLY : 0);
 687         }
 688
 689         return (~crc & ((1 << SK_BITS) - 1));
 690 }
 691
 692 static void sk_setfilt(sc_if, addr, slot)
 693         struct sk_if_softc      *sc_if;
 694         caddr_t                 addr;
 695         int                     slot;
 696 {
 697         int                     base;
 698
 699         base = XM_RXFILT_ENTRY(slot);
 700
 701         SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0]));
 702         SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2]));
 703         SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4]));
 704
 705         return;
 706 }
 707
 708 static void sk_setmulti(sc_if)
 709         struct sk_if_softc      *sc_if;
 710 {
 711         struct sk_softc         *sc = sc_if->sk_softc;
 712         struct ifnet            *ifp = &sc_if->arpcom.ac_if;
 713         u_int32_t               hashes[2] = { 0, 0 };
 714         int                     h, i;
 715         struct ifmultiaddr      *ifma;
 716         u_int8_t                dummy[] = { 0, 0, 0, 0, 0 ,0 };
 717
 718
 719         /* First, zot all the existing filters. */
 720         switch(sc->sk_type) {
 721         case SK_GENESIS:
 722                 for (i = 1; i < XM_RXFILT_MAX; i++)
 723                         sk_setfilt(sc_if, (caddr_t)&dummy, i);
 724
 725                 SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
 726                 SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
 727                 break;
 728         case SK_YUKON:
 729                 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
 730                 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
 731                 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
 732                 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
 733                 break;
 734         }
 735
 736         /* Now program new ones. */
 737         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 738                 hashes[0] = 0xFFFFFFFF;
 739                 hashes[1] = 0xFFFFFFFF;
 740         } else {
 741                 i = 1;
 742                 /* First find the tail of the list. */
 743                 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
 744                                         ifma = ifma->ifma_link.le_next) {
 745                         if (ifma->ifma_link.le_next == NULL)
 746                                 break;
 747                 }
 748                 /* Now traverse the list backwards. */
 749                 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
 750                         ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
 751                         if (ifma->ifma_addr->sa_family != AF_LINK)
 752                                 continue;
 753                         /*
 754                          * Program the first XM_RXFILT_MAX multicast groups
 755                          * into the perfect filter. For all others,
 756                          * use the hash table.
 757                          */
 758                         if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) {
 759                                 sk_setfilt(sc_if,
 760                         LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
 761                                 i++;
 762                                 continue;
 763                         }
 764
 765                         h = sk_calchash(
 766                                 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
 767                         if (h < 32)
 768                                 hashes[0] |= (1 << h);
 769                         else
 770                                 hashes[1] |= (1 << (h - 32));
 771                 }
 772         }
 773
 774         switch(sc->sk_type) {
 775         case SK_GENESIS:
 776                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH|
 777                                XM_MODE_RX_USE_PERFECT);
 778                 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
 779                 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
 780                 break;
 781         case SK_YUKON:
 782                 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
 783                 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
 784                 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
 785                 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
 786                 break;
 787         }
 788
 789         return;
 790 }
 791
 792 static void sk_setpromisc(sc_if)
 793         struct sk_if_softc      *sc_if;
 794 {
 795         struct sk_softc         *sc = sc_if->sk_softc;
 796         struct ifnet            *ifp = &sc_if->arpcom.ac_if;
 797
 798         switch(sc->sk_type) {
 799         case SK_GENESIS:
 800                 if (ifp->if_flags & IFF_PROMISC) {
 801                         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
 802                 } else {
 803                         SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
 804                 }
 805                 break;
 806         case SK_YUKON:
 807                 if (ifp->if_flags & IFF_PROMISC) {
 808                         SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
 809                             YU_RCR_UFLEN | YU_RCR_MUFLEN);
 810                 } else {
 811                         SK_YU_SETBIT_2(sc_if, YUKON_RCR,
 812                             YU_RCR_UFLEN | YU_RCR_MUFLEN);
 813                 }
 814                 break;
 815         }
 816
 817         return;
 818 }
 819
 820 static int sk_init_rx_ring(sc_if)
 821         struct sk_if_softc      *sc_if;
 822 {
 823         struct sk_chain_data    *cd = &sc_if->sk_cdata;
 824         struct sk_ring_data     *rd = sc_if->sk_rdata;
 825         int                     i;
 826
 827         bzero((char *)rd->sk_rx_ring,
 828             sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
 829
 830         for (i = 0; i < SK_RX_RING_CNT; i++) {
 831                 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i];
 832                 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS)
 833                         return(ENOBUFS);
 834                 if (i == (SK_RX_RING_CNT - 1)) {
 835                         cd->sk_rx_chain[i].sk_next =
 836                             &cd->sk_rx_chain[0];
 837                         rd->sk_rx_ring[i].sk_next =
 838                             vtophys(&rd->sk_rx_ring[0]);
 839                 } else {
 840                         cd->sk_rx_chain[i].sk_next =
 841                             &cd->sk_rx_chain[i + 1];
 842                         rd->sk_rx_ring[i].sk_next =
 843                             vtophys(&rd->sk_rx_ring[i + 1]);
 844                 }
 845         }
 846
 847         sc_if->sk_cdata.sk_rx_prod = 0;
 848         sc_if->sk_cdata.sk_rx_cons = 0;
 849
 850         return(0);
 851 }
 852
 853 static void sk_init_tx_ring(sc_if)
 854         struct sk_if_softc      *sc_if;
 855 {
 856         struct sk_chain_data    *cd = &sc_if->sk_cdata;
 857         struct sk_ring_data     *rd = sc_if->sk_rdata;
 858         int                     i;
 859
 860         bzero((char *)sc_if->sk_rdata->sk_tx_ring,
 861             sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
 862
 863         for (i = 0; i < SK_TX_RING_CNT; i++) {
 864                 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i];
 865                 if (i == (SK_TX_RING_CNT - 1)) {
 866                         cd->sk_tx_chain[i].sk_next =
 867                             &cd->sk_tx_chain[0];
 868                         rd->sk_tx_ring[i].sk_next =
 869                             vtophys(&rd->sk_tx_ring[0]);
 870                 } else {
 871                         cd->sk_tx_chain[i].sk_next =
 872                             &cd->sk_tx_chain[i + 1];
 873                         rd->sk_tx_ring[i].sk_next =
 874                             vtophys(&rd->sk_tx_ring[i + 1]);
 875                 }
 876         }
 877
 878         sc_if->sk_cdata.sk_tx_prod = 0;
 879         sc_if->sk_cdata.sk_tx_cons = 0;
 880         sc_if->sk_cdata.sk_tx_cnt = 0;
 881
 882         return;
 883 }
 884
 885 static int sk_newbuf(sc_if, c, m)
 886         struct sk_if_softc      *sc_if;
 887         struct sk_chain         *c;
 888         struct mbuf             *m;
 889 {
 890         struct mbuf             *m_new = NULL;
 891         struct sk_rx_desc       *r;
 892
 893         if (m == NULL) {
 894                 caddr_t                 *buf = NULL;
 895
 896                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 897                 if (m_new == NULL)
 898                         return(ENOBUFS);
 899
 900                 /* Allocate the jumbo buffer */
 901                 buf = sk_jalloc(sc_if);
 902                 if (buf == NULL) {
 903                         m_freem(m_new);
 904 #ifdef SK_VERBOSE
 905                         printf("sk%d: jumbo allocation failed "
 906                             "-- packet dropped!\n", sc_if->sk_unit);
 907 #endif
 908                         return(ENOBUFS);
 909                 }
 910
 911                 /* Attach the buffer to the mbuf */
 912                 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
 913                 m_new->m_flags |= M_EXT;
 914                 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
 915                     m_new->m_len = SK_MCLBYTES;
 916                 m_new->m_ext.ext_free = sk_jfree;
 917                 m_new->m_ext.ext_ref = sk_jref;
 918         } else {
 919                 /*
 920                  * We're re-using a previously allocated mbuf;
 921                  * be sure to re-init pointers and lengths to
 922                  * default values.
 923                  */
 924                 m_new = m;
 925                 m_new->m_len = m_new->m_pkthdr.len = SK_MCLBYTES;
 926                 m_new->m_data = m_new->m_ext.ext_buf;
 927         }
 928
 929         /*
 930          * Adjust alignment so packet payload begins on a
 931          * longword boundary. Mandatory for Alpha, useful on
 932          * x86 too.
 933          */
 934         m_adj(m_new, ETHER_ALIGN);
 935
 936         r = c->sk_desc;
 937         c->sk_mbuf = m_new;
 938         r->sk_data_lo = vtophys(mtod(m_new, caddr_t));
 939         r->sk_ctl = m_new->m_len | SK_RXSTAT;
 940
 941         return(0);
 942 }
 943
 944 /*
 945  * Allocate jumbo buffer storage. The SysKonnect adapters support
 946  * "jumbograms" (9K frames), although SysKonnect doesn't currently
 947  * use them in their drivers. In order for us to use them, we need
 948  * large 9K receive buffers, however standard mbuf clusters are only
 949  * 2048 bytes in size. Consequently, we need to allocate and manage
 950  * our own jumbo buffer pool. Fortunately, this does not require an
 951  * excessive amount of additional code.
 952  */
 953 static int sk_alloc_jumbo_mem(sc_if)
 954         struct sk_if_softc      *sc_if;
 955 {
 956         caddr_t                 ptr;
 957         int             i;
 958         struct sk_jpool_entry   *entry;
 959
 960         /* Grab a big chunk o' storage. */
 961         sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF,
 962             M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
 963
 964         if (sc_if->sk_cdata.sk_jumbo_buf == NULL) {
 965                 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit);
 966                 return(ENOBUFS);
 967         }
 968
 969         SLIST_INIT(&sc_if->sk_jfree_listhead);
 970         SLIST_INIT(&sc_if->sk_jinuse_listhead);
 971
 972         /*
 973          * Now divide it up into 9K pieces and save the addresses
 974          * in an array. Note that we play an evil trick here by using
 975          * the first few bytes in the buffer to hold the the address
 976          * of the softc structure for this interface. This is because
 977          * sk_jfree() needs it, but it is called by the mbuf management
 978          * code which will not pass it to us explicitly.
 979          */
 980         ptr = sc_if->sk_cdata.sk_jumbo_buf;
 981         for (i = 0; i < SK_JSLOTS; i++) {
 982                 u_int64_t               **aptr;
 983                 aptr = (u_int64_t **)ptr;
 984                 aptr[0] = (u_int64_t *)sc_if;
 985                 ptr += sizeof(u_int64_t);
 986                 sc_if->sk_cdata.sk_jslots[i].sk_buf = ptr;
 987                 sc_if->sk_cdata.sk_jslots[i].sk_inuse = 0;
 988                 ptr += SK_MCLBYTES;
 989                 entry = malloc(sizeof(struct sk_jpool_entry),
 990                     M_DEVBUF, M_NOWAIT);
 991                 if (entry == NULL) {
 992                         free(sc_if->sk_cdata.sk_jumbo_buf, M_DEVBUF);
 993                         sc_if->sk_cdata.sk_jumbo_buf = NULL;
 994                         printf("sk%d: no memory for jumbo "
 995                             "buffer queue!\n", sc_if->sk_unit);
 996                         return(ENOBUFS);
 997                 }
 998                 entry->slot = i;
 999                 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
1000                     entry, jpool_entries);
1001         }
1002
1003         return(0);
1004 }
1005
1006 /*
1007  * Allocate a jumbo buffer.
1008  */
1009 static void *sk_jalloc(sc_if)
1010         struct sk_if_softc      *sc_if;
1011 {
1012         struct sk_jpool_entry   *entry;
1013
1014         entry = SLIST_FIRST(&sc_if->sk_jfree_listhead);
1015
1016         if (entry == NULL) {
1017 #ifdef SK_VERBOSE
1018                 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit);
1019 #endif
1020                 return(NULL);
1021         }
1022
1023         SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries);
1024         SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries);
1025         sc_if->sk_cdata.sk_jslots[entry->slot].sk_inuse = 1;
1026         return(sc_if->sk_cdata.sk_jslots[entry->slot].sk_buf);
1027 }
1028
1029 /*
1030  * Adjust usage count on a jumbo buffer. In general this doesn't
1031  * get used much because our jumbo buffers don't get passed around
1032  * a lot, but it's implemented for correctness.
1033  */
1034 static void sk_jref(buf, size)
1035         caddr_t                 buf;
1036         u_int                   size;
1037 {
1038         struct sk_if_softc      *sc_if;
1039         u_int64_t               **aptr;
1040         int             i;
1041
1042         /* Extract the softc struct pointer. */
1043         aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
1044         sc_if = (struct sk_if_softc *)(aptr[0]);
1045
1046         if (sc_if == NULL)
1047                 panic("sk_jref: can't find softc pointer!");
1048
1049         if (size != SK_MCLBYTES)
1050                 panic("sk_jref: adjusting refcount of buf of wrong size!");
1051
1052         /* calculate the slot this buffer belongs to */
1053
1054         i = ((vm_offset_t)aptr
1055              - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN;
1056
1057         if ((i < 0) || (i >= SK_JSLOTS))
1058                 panic("sk_jref: asked to reference buffer "
1059                     "that we don't manage!");
1060         else if (sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0)
1061                 panic("sk_jref: buffer already free!");
1062         else
1063                 sc_if->sk_cdata.sk_jslots[i].sk_inuse++;
1064
1065         return;
1066 }
1067
1068 /*
1069  * Release a jumbo buffer.
1070  */
1071 static void sk_jfree(buf, size)
1072         caddr_t                 buf;
1073         u_int                   size;
1074 {
1075         struct sk_if_softc      *sc_if;
1076         u_int64_t               **aptr;
1077         int                     i;
1078         struct sk_jpool_entry   *entry;
1079
1080         /* Extract the softc struct pointer. */
1081         aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
1082         sc_if = (struct sk_if_softc *)(aptr[0]);
1083
1084         if (sc_if == NULL)
1085                 panic("sk_jfree: can't find softc pointer!");
1086
1087         if (size != SK_MCLBYTES)
1088                 panic("sk_jfree: freeing buffer of wrong size!");
1089
1090         /* calculate the slot this buffer belongs to */
1091
1092         i = ((vm_offset_t)aptr
1093              - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN;
1094
1095         if ((i < 0) || (i >= SK_JSLOTS))
1096                 panic("sk_jfree: asked to free buffer that we don't manage!");
1097         else if (sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0)
1098                 panic("sk_jfree: buffer already free!");
1099         else {
1100                 sc_if->sk_cdata.sk_jslots[i].sk_inuse--;
1101                 if(sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0) {
1102                         entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead);
1103                         if (entry == NULL)
1104                                 panic("sk_jfree: buffer not in use!");
1105                         entry->slot = i;
1106                         SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead,
1107                                           jpool_entries);
1108                         SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
1109                                           entry, jpool_entries);
1110                 }
1111         }
1112
1113         return;
1114 }
1115
1116 /*
1117  * Set media options.
1118  */
1119 static int sk_ifmedia_upd(ifp)
1120         struct ifnet            *ifp;
1121 {
1122         struct sk_if_softc      *sc_if = ifp->if_softc;
1123         struct mii_data         *mii;
1124
1125         mii = device_get_softc(sc_if->sk_miibus);
1126         sk_init(sc_if);
1127         mii_mediachg(mii);
1128
1129         return(0);
1130 }
1131
1132 /*
1133  * Report current media status.
1134  */
1135 static void sk_ifmedia_sts(ifp, ifmr)
1136         struct ifnet            *ifp;
1137         struct ifmediareq       *ifmr;
1138 {
1139         struct sk_if_softc      *sc_if;
1140         struct mii_data         *mii;
1141
1142         sc_if = ifp->if_softc;
1143         mii = device_get_softc(sc_if->sk_miibus);
1144
1145         mii_pollstat(mii);
1146         ifmr->ifm_active = mii->mii_media_active;
1147         ifmr->ifm_status = mii->mii_media_status;
1148
1149         return;
1150 }
1151
1152 static int sk_ioctl(ifp, command, data)
1153         struct ifnet            *ifp;
1154         u_long                  command;
1155         caddr_t                 data;
1156 {
1157         struct sk_if_softc      *sc_if = ifp->if_softc;
1158         struct ifreq            *ifr = (struct ifreq *) data;
1159         int                     s, error = 0;
1160         struct mii_data         *mii;
1161
1162         s = splimp();
1163
1164         switch(command) {
1165         case SIOCSIFADDR:
1166         case SIOCGIFADDR:
1167                 error = ether_ioctl(ifp, command, data);
1168                 break;
1169         case SIOCSIFMTU:
1170                 if (ifr->ifr_mtu > SK_JUMBO_MTU)
1171                         error = EINVAL;
1172                 else {
1173                         ifp->if_mtu = ifr->ifr_mtu;
1174                         sk_init(sc_if);
1175                 }
1176                 break;
1177         case SIOCSIFFLAGS:
1178                 if (ifp->if_flags & IFF_UP) {
1179                         if (ifp->if_flags & IFF_RUNNING) {
1180                                 if ((ifp->if_flags ^ sc_if->sk_if_flags)
1181                                     & IFF_PROMISC) {
1182                                         sk_setpromisc(sc_if);
1183                                         sk_setmulti(sc_if);
1184                                 }
1185                         } else
1186                                 sk_init(sc_if);
1187                 } else {
1188                         if (ifp->if_flags & IFF_RUNNING)
1189                                 sk_stop(sc_if);
1190                 }
1191                 sc_if->sk_if_flags = ifp->if_flags;
1192                 error = 0;
1193                 break;
1194         case SIOCADDMULTI:
1195         case SIOCDELMULTI:
1196                 sk_setmulti(sc_if);
1197                 error = 0;
1198                 break;
1199         case SIOCGIFMEDIA:
1200         case SIOCSIFMEDIA:
1201                 mii = device_get_softc(sc_if->sk_miibus);
1202                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1203                 break;
1204         default:
1205                 error = EINVAL;
1206                 break;
1207         }
1208
1209         (void)splx(s);
1210
1211         return(error);
1212 }
1213
1214 /*
1215  * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1216  * IDs against our list and return a device name if we find a match.
1217  */
1218 static int skc_probe(dev)
1219         device_t                dev;
1220 {
1221         struct sk_softc         *sc;
1222         struct sk_type          *t = sk_devs;
1223
1224         sc = device_get_softc(dev);
1225
1226         while(t->sk_name != NULL) {
1227                 if ((pci_get_vendor(dev) == t->sk_vid) &&
1228                     (pci_get_device(dev) == t->sk_did)) {
1229                         device_set_desc(dev, t->sk_name);
1230                         return(0);
1231                 }
1232                 t++;
1233         }
1234
1235         return(ENXIO);
1236 }
1237
1238 /*
1239  * Force the GEnesis into reset, then bring it out of reset.
1240  */
1241 static void sk_reset(sc)
1242         struct sk_softc         *sc;
1243 {
1244         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1245         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1246         if (sc->sk_type == SK_YUKON)
1247                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1248
1249         DELAY(1000);
1250         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1251         DELAY(2);
1252         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1253         if (sc->sk_type == SK_YUKON)
1254                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1255
1256         if (sc->sk_type == SK_GENESIS) {
1257                 /* Configure packet arbiter */
1258                 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1259                 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1260                 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1261                 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1262                 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1263         }
1264
1265         /* Enable RAM interface */
1266         sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1267
1268         /*
1269          * Configure interrupt moderation. The moderation timer
1270          * defers interrupts specified in the interrupt moderation
1271          * timer mask based on the timeout specified in the interrupt
1272          * moderation timer init register. Each bit in the timer
1273          * register represents 18.825ns, so to specify a timeout in
1274          * microseconds, we have to multiply by 54.
1275          */
1276         sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200));
1277         sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1278             SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1279         sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1280
1281         return;
1282 }
1283
1284 static int sk_probe(dev)
1285         device_t                dev;
1286 {
1287         struct sk_softc         *sc;
1288
1289         sc = device_get_softc(device_get_parent(dev));
1290
1291         /*
1292          * Not much to do here. We always know there will be
1293          * at least one XMAC present, and if there are two,
1294          * skc_attach() will create a second device instance
1295          * for us.
1296          */
1297         switch (sc->sk_type) {
1298         case SK_GENESIS:
1299                 device_set_desc(dev, "XaQti Corp. XMAC II");
1300                 break;
1301         case SK_YUKON:
1302                 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
1303                 break;
1304         }
1305
1306         return(0);
1307 }
1308
1309 /*
1310  * Each XMAC chip is attached as a separate logical IP interface.
1311  * Single port cards will have only one logical interface of course.
1312  */
1313 static int sk_attach(dev)
1314         device_t                dev;
1315 {
1316         struct sk_softc         *sc;
1317         struct sk_if_softc      *sc_if;
1318         struct ifnet            *ifp;
1319         int                     i, port;
1320
1321         if (dev == NULL)
1322                 return(EINVAL);
1323
1324         sc_if = device_get_softc(dev);
1325         sc = device_get_softc(device_get_parent(dev));
1326         port = *(int *)device_get_ivars(dev);
1327         free(device_get_ivars(dev), M_DEVBUF);
1328         device_set_ivars(dev, NULL);
1329         sc_if->sk_dev = dev;
1330
1331         bzero((char *)sc_if, sizeof(struct sk_if_softc));
1332
1333         sc_if->sk_dev = dev;
1334         sc_if->sk_unit = device_get_unit(dev);
1335         sc_if->sk_port = port;
1336         sc_if->sk_softc = sc;
1337         sc->sk_if[port] = sc_if;
1338         if (port == SK_PORT_A)
1339                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1340         if (port == SK_PORT_B)
1341                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1342
1343         /*
1344          * Get station address for this interface. Note that
1345          * dual port cards actually come with three station
1346          * addresses: one for each port, plus an extra. The
1347          * extra one is used by the SysKonnect driver software
1348          * as a 'virtual' station address for when both ports
1349          * are operating in failover mode. Currently we don't
1350          * use this extra address.
1351          */
1352         for (i = 0; i < ETHER_ADDR_LEN; i++)
1353                 sc_if->arpcom.ac_enaddr[i] =
1354                     sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1355
1356         printf("sk%d: Ethernet address: %6D\n",
1357             sc_if->sk_unit, sc_if->arpcom.ac_enaddr, ":");
1358
1359         /*
1360          * Set up RAM buffer addresses. The NIC will have a certain
1361          * amount of SRAM on it, somewhere between 512K and 2MB. We
1362          * need to divide this up a) between the transmitter and
1363          * receiver and b) between the two XMACs, if this is a
1364          * dual port NIC. Our algotithm is to divide up the memory
1365          * evenly so that everyone gets a fair share.
1366          */
1367         if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1368                 u_int32_t               chunk, val;
1369
1370                 chunk = sc->sk_ramsize / 2;
1371                 val = sc->sk_rboff / sizeof(u_int64_t);
1372                 sc_if->sk_rx_ramstart = val;
1373                 val += (chunk / sizeof(u_int64_t));
1374                 sc_if->sk_rx_ramend = val - 1;
1375                 sc_if->sk_tx_ramstart = val;
1376                 val += (chunk / sizeof(u_int64_t));
1377                 sc_if->sk_tx_ramend = val - 1;
1378         } else {
1379                 u_int32_t               chunk, val;
1380
1381                 chunk = sc->sk_ramsize / 4;
1382                 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1383                     sizeof(u_int64_t);
1384                 sc_if->sk_rx_ramstart = val;
1385                 val += (chunk / sizeof(u_int64_t));
1386                 sc_if->sk_rx_ramend = val - 1;
1387                 sc_if->sk_tx_ramstart = val;
1388                 val += (chunk / sizeof(u_int64_t));
1389                 sc_if->sk_tx_ramend = val - 1;
1390         }
1391
1392         /* Read and save PHY type and set PHY address */
1393         sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1394         switch(sc_if->sk_phytype) {
1395         case SK_PHYTYPE_XMAC:
1396                 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1397                 break;
1398         case SK_PHYTYPE_BCOM:
1399                 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1400                 break;
1401         case SK_PHYTYPE_MARV_COPPER:
1402                 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1403                 break;
1404         default:
1405                 printf("skc%d: unsupported PHY type: %d\n",
1406                     sc->sk_unit, sc_if->sk_phytype);
1407                 return(ENODEV);
1408         }
1409
1410         /* Allocate the descriptor queues. */
1411         sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF,
1412             M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1413
1414         if (sc_if->sk_rdata == NULL) {
1415                 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit);
1416                 sc->sk_if[port] = NULL;
1417                 return(ENOMEM);
1418         }
1419
1420         bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data));
1421
1422         /* Try to allocate memory for jumbo buffers. */
1423         if (sk_alloc_jumbo_mem(sc_if)) {
1424                 printf("sk%d: jumbo buffer allocation failed\n",
1425                     sc_if->sk_unit);
1426                 contigfree(sc_if->sk_rdata,
1427                     sizeof(struct sk_ring_data), M_DEVBUF);
1428                 sc->sk_if[port] = NULL;
1429                 return(ENOMEM);
1430         }
1431
1432         ifp = &sc_if->arpcom.ac_if;
1433         ifp->if_softc = sc_if;
1434         ifp->if_unit = sc_if->sk_unit;
1435         ifp->if_name = "sk";
1436         ifp->if_mtu = ETHERMTU;
1437         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1438         ifp->if_ioctl = sk_ioctl;
1439         ifp->if_output = ether_output;
1440         ifp->if_start = sk_start;
1441         ifp->if_watchdog = sk_watchdog;
1442         ifp->if_init = sk_init;
1443         ifp->if_baudrate = 1000000000;
1444         ifp->if_snd.ifq_maxlen = SK_TX_RING_CNT - 1;
1445
1446         /*
1447          * Do miibus setup.
1448          */
1449         switch (sc->sk_type) {
1450         case SK_GENESIS:
1451                 sk_init_xmac(sc_if);
1452                 break;
1453         case SK_YUKON:
1454                 sk_init_yukon(sc_if);
1455                 break;
1456         }
1457
1458         if (mii_phy_probe(dev, &sc_if->sk_miibus,
1459             sk_ifmedia_upd, sk_ifmedia_sts)) {
1460                 printf("skc%d: no PHY found!\n", sc_if->sk_unit);
1461                 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM,
1462                     M_DEVBUF);
1463                 contigfree(sc_if->sk_rdata,
1464                     sizeof(struct sk_ring_data), M_DEVBUF);
1465                 return(ENXIO);
1466         }
1467
1468         /*
1469          * Call MI attach routine.
1470          */
1471         ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1472         callout_handle_init(&sc_if->sk_tick_ch);
1473
1474         return(0);
1475 }
1476
1477 /*
1478  * Attach the interface. Allocate softc structures, do ifmedia
1479  * setup and ethernet/BPF attach.
1480  */
1481 static int skc_attach(dev)
1482         device_t                dev;
1483 {
1484         int                     s;
1485         u_int32_t               command;
1486         struct sk_softc         *sc;
1487         int                     unit, error = 0, rid, *port;
1488
1489         s = splimp();
1490
1491         sc = device_get_softc(dev);
1492         unit = device_get_unit(dev);
1493         bzero(sc, sizeof(struct sk_softc));
1494         switch (pci_get_device(dev)) {
1495         case DEVICEID_SK_V1:
1496                 sc->sk_type = SK_GENESIS;
1497                 break;
1498         case DEVICEID_SK_V2:
1499         case DEVICEID_3COM_3C940:
1500                 sc->sk_type = SK_YUKON;
1501                 break;
1502         }
1503
1504         /*
1505          * Handle power management nonsense.
1506          */
1507         command = pci_read_config(dev, SK_PCI_CAPID, 4) & 0x000000FF;
1508         if (command == 0x01) {
1509                 command = pci_read_config(dev, SK_PCI_PWRMGMTCTRL, 4);
1510                 if (command & SK_PSTATE_MASK) {
1511                         u_int32_t               iobase, membase, irq;
1512
1513                         /* Save important PCI config data. */
1514                         iobase = pci_read_config(dev, SK_PCI_LOIO, 4);
1515                         membase = pci_read_config(dev, SK_PCI_LOMEM, 4);
1516                         irq = pci_read_config(dev, SK_PCI_INTLINE, 4);
1517
1518                         /* Reset the power state. */
1519                         printf("skc%d: chip is in D%d power mode "
1520                         "-- setting to D0\n", unit, command & SK_PSTATE_MASK);
1521                         command &= 0xFFFFFFFC;
1522                         pci_write_config(dev, SK_PCI_PWRMGMTCTRL, command, 4);
1523
1524                         /* Restore PCI config data. */
1525                         pci_write_config(dev, SK_PCI_LOIO, iobase, 4);
1526                         pci_write_config(dev, SK_PCI_LOMEM, membase, 4);
1527                         pci_write_config(dev, SK_PCI_INTLINE, irq, 4);
1528                 }
1529         }
1530
1531         /*
1532          * Map control/status registers.
1533          */
1534         command = pci_read_config(dev, PCIR_COMMAND, 4);
1535         command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1536         pci_write_config(dev, PCIR_COMMAND, command, 4);
1537         command = pci_read_config(dev, PCIR_COMMAND, 4);
1538
1539 #ifdef SK_USEIOSPACE
1540         if (!(command & PCIM_CMD_PORTEN)) {
1541                 printf("skc%d: failed to enable I/O ports!\n", unit);
1542                 error = ENXIO;
1543                 goto fail;
1544         }
1545 #else
1546         if (!(command & PCIM_CMD_MEMEN)) {
1547                 printf("skc%d: failed to enable memory mapping!\n", unit);
1548                 error = ENXIO;
1549                 goto fail;
1550         }
1551 #endif
1552
1553         rid = SK_RID;
1554         sc->sk_res = bus_alloc_resource(dev, SK_RES, &rid,
1555             0, ~0, 1, RF_ACTIVE);
1556
1557         if (sc->sk_res == NULL) {
1558                 printf("sk%d: couldn't map ports/memory\n", unit);
1559                 error = ENXIO;
1560                 goto fail;
1561         }
1562
1563         sc->sk_btag = rman_get_bustag(sc->sk_res);
1564         sc->sk_bhandle = rman_get_bushandle(sc->sk_res);
1565
1566         /* Allocate interrupt */
1567         rid = 0;
1568         sc->sk_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1569             RF_SHAREABLE | RF_ACTIVE);
1570
1571         if (sc->sk_irq == NULL) {
1572                 printf("skc%d: couldn't map interrupt\n", unit);
1573                 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1574                 error = ENXIO;
1575                 goto fail;
1576         }
1577
1578         error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET,
1579             sk_intr, sc, &sc->sk_intrhand);
1580
1581         if (error) {
1582                 printf("skc%d: couldn't set up irq\n", unit);
1583                 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1584                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1585                 goto fail;
1586         }
1587
1588         /* Reset the adapter. */
1589         sk_reset(sc);
1590
1591         sc->sk_unit = unit;
1592
1593         /* Read and save vital product data from EEPROM. */
1594         sk_vpd_read(sc);
1595
1596         if (sc->sk_type == SK_GENESIS) {
1597                 /* Read and save RAM size and RAMbuffer offset */
1598                 switch(sk_win_read_1(sc, SK_EPROM0)) {
1599                 case SK_RAMSIZE_512K_64:
1600                         sc->sk_ramsize = 0x80000;
1601                         sc->sk_rboff = SK_RBOFF_0;
1602                         break;
1603                 case SK_RAMSIZE_1024K_64:
1604                         sc->sk_ramsize = 0x100000;
1605                         sc->sk_rboff = SK_RBOFF_80000;
1606                         break;
1607                 case SK_RAMSIZE_1024K_128:
1608                         sc->sk_ramsize = 0x100000;
1609                         sc->sk_rboff = SK_RBOFF_0;
1610                         break;
1611                 case SK_RAMSIZE_2048K_128:
1612                         sc->sk_ramsize = 0x200000;
1613                         sc->sk_rboff = SK_RBOFF_0;
1614                         break;
1615                 default:
1616                         printf("skc%d: unknown ram size: %d\n",
1617                             sc->sk_unit, sk_win_read_1(sc, SK_EPROM0));
1618                         bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1619                         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1620                         bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1621                         error = ENXIO;
1622                         goto fail;
1623                         break;
1624                 }
1625         } else {
1626                 sc->sk_ramsize = 0x20000;
1627                 sc->sk_rboff = SK_RBOFF_0;
1628         }
1629
1630         /* Read and save physical media type */
1631         switch(sk_win_read_1(sc, SK_PMDTYPE)) {
1632         case SK_PMD_1000BASESX:
1633                 sc->sk_pmd = IFM_1000_SX;
1634                 break;
1635         case SK_PMD_1000BASELX:
1636                 sc->sk_pmd = IFM_1000_LX;
1637                 break;
1638         case SK_PMD_1000BASECX:
1639                 sc->sk_pmd = IFM_1000_CX;
1640                 break;
1641         case SK_PMD_1000BASETX:
1642                 sc->sk_pmd = IFM_1000_TX;
1643                 break;
1644         default:
1645                 printf("skc%d: unknown media type: 0x%x\n",
1646                     sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE));
1647                 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1648                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1649                 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1650                 error = ENXIO;
1651                 goto fail;
1652         }
1653
1654         /* Announce the product name. */
1655         printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname);
1656         sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1657         port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1658         *port = SK_PORT_A;
1659         device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1660
1661         if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1662                 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1663                 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1664                 *port = SK_PORT_B;
1665                 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1666         }
1667
1668         /* Turn on the 'driver is loaded' LED. */
1669         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1670
1671         bus_generic_attach(dev);
1672
1673 fail:
1674         splx(s);
1675         return(error);
1676 }
1677
1678 static int sk_detach(dev)
1679         device_t                dev;
1680 {
1681         struct sk_softc         *sc;
1682         struct sk_if_softc      *sc_if;
1683         struct ifnet            *ifp;
1684         int                     s;
1685
1686         s = splimp();
1687
1688         sc = device_get_softc(device_get_parent(dev));
1689         sc_if = device_get_softc(dev);
1690         ifp = &sc_if->arpcom.ac_if;
1691         sk_stop(sc_if);
1692         ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1693         bus_generic_detach(dev);
1694         if (sc_if->sk_miibus != NULL)
1695                 device_delete_child(dev, sc_if->sk_miibus);
1696         contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF);
1697         contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), M_DEVBUF);
1698
1699         return(0);
1700 }
1701
1702 static int skc_detach(dev)
1703         device_t                dev;
1704 {
1705         struct sk_softc         *sc;
1706         int                     s;
1707
1708         s = splimp();
1709
1710         sc = device_get_softc(dev);
1711
1712         bus_generic_detach(dev);
1713         if (sc->sk_devs[SK_PORT_A] != NULL)
1714                 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1715         if (sc->sk_devs[SK_PORT_B] != NULL)
1716                 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1717
1718         bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1719         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1720         bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1721
1722         splx(s);
1723
1724         return(0);
1725 }
1726
1727 static int sk_encap(sc_if, m_head, txidx)
1728         struct sk_if_softc      *sc_if;
1729         struct mbuf             *m_head;
1730         u_int32_t               *txidx;
1731 {
1732         struct sk_tx_desc       *f = NULL;
1733         struct mbuf             *m;
1734         u_int32_t               frag, cur, cnt = 0;
1735
1736         m = m_head;
1737         cur = frag = *txidx;
1738
1739         /*
1740          * Start packing the mbufs in this chain into
1741          * the fragment pointers. Stop when we run out
1742          * of fragments or hit the end of the mbuf chain.
1743          */
1744         for (m = m_head; m != NULL; m = m->m_next) {
1745                 if (m->m_len != 0) {
1746                         if ((SK_TX_RING_CNT -
1747                             (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2)
1748                                 return(ENOBUFS);
1749                         f = &sc_if->sk_rdata->sk_tx_ring[frag];
1750                         f->sk_data_lo = vtophys(mtod(m, vm_offset_t));
1751                         f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT;
1752                         if (cnt == 0)
1753                                 f->sk_ctl |= SK_TXCTL_FIRSTFRAG;
1754                         else
1755                                 f->sk_ctl |= SK_TXCTL_OWN;
1756                         cur = frag;
1757                         SK_INC(frag, SK_TX_RING_CNT);
1758                         cnt++;
1759                 }
1760         }
1761
1762         if (m != NULL)
1763                 return(ENOBUFS);
1764
1765         sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |=
1766                 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR;
1767         sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head;
1768         sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN;
1769         sc_if->sk_cdata.sk_tx_cnt += cnt;
1770
1771         *txidx = frag;
1772
1773         return(0);
1774 }
1775
1776 static void sk_start(ifp)
1777         struct ifnet            *ifp;
1778 {
1779         struct sk_softc         *sc;
1780         struct sk_if_softc      *sc_if;
1781         struct mbuf             *m_head = NULL;
1782         u_int32_t               idx;
1783
1784         sc_if = ifp->if_softc;
1785         sc = sc_if->sk_softc;
1786
1787         idx = sc_if->sk_cdata.sk_tx_prod;
1788
1789         while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) {
1790                 IF_DEQUEUE(&ifp->if_snd, m_head);
1791                 if (m_head == NULL)
1792                         break;
1793
1794                 /*
1795                  * Pack the data into the transmit ring. If we
1796                  * don't have room, set the OACTIVE flag and wait
1797                  * for the NIC to drain the ring.
1798                  */
1799                 if (sk_encap(sc_if, m_head, &idx)) {
1800                         IF_PREPEND(&ifp->if_snd, m_head);
1801                         ifp->if_flags |= IFF_OACTIVE;
1802                         break;
1803                 }
1804
1805                 /*
1806                  * If there's a BPF listener, bounce a copy of this frame
1807                  * to him.
1808                  */
1809                 if (ifp->if_bpf)
1810                         bpf_mtap(ifp, m_head);
1811         }
1812
1813         /* Transmit */
1814         sc_if->sk_cdata.sk_tx_prod = idx;
1815         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
1816
1817         /* Set a timeout in case the chip goes out to lunch. */
1818         ifp->if_timer = 5;
1819
1820         return;
1821 }
1822
1823
1824 static void sk_watchdog(ifp)
1825         struct ifnet            *ifp;
1826 {
1827         struct sk_if_softc      *sc_if;
1828
1829         sc_if = ifp->if_softc;
1830
1831         printf("sk%d: watchdog timeout\n", sc_if->sk_unit);
1832         sk_init(sc_if);
1833
1834         return;
1835 }
1836
1837 static void skc_shutdown(dev)
1838         device_t                dev;
1839 {
1840         struct sk_softc         *sc;
1841
1842         sc = device_get_softc(dev);
1843
1844         /* Turn off the 'driver is loaded' LED. */
1845         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
1846
1847         /*
1848          * Reset the GEnesis controller. Doing this should also
1849          * assert the resets on the attached XMAC(s).
1850          */
1851         sk_reset(sc);
1852
1853         return;
1854 }
1855
1856 static void sk_rxeof(sc_if)
1857         struct sk_if_softc      *sc_if;
1858 {
1859         struct ether_header     *eh;
1860         struct mbuf             *m;
1861         struct ifnet            *ifp;
1862         struct sk_chain         *cur_rx;
1863         int                     total_len = 0;
1864         int                     i;
1865         u_int32_t               rxstat;
1866
1867         ifp = &sc_if->arpcom.ac_if;
1868         i = sc_if->sk_cdata.sk_rx_prod;
1869         cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
1870
1871         while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) {
1872
1873                 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
1874                 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat;
1875                 m = cur_rx->sk_mbuf;
1876                 cur_rx->sk_mbuf = NULL;
1877                 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl);
1878                 SK_INC(i, SK_RX_RING_CNT);
1879
1880                 if (rxstat & XM_RXSTAT_ERRFRAME) {
1881                         ifp->if_ierrors++;
1882                         sk_newbuf(sc_if, cur_rx, m);
1883                         continue;
1884                 }
1885
1886                 /*
1887                  * Try to allocate a new jumbo buffer. If that
1888                  * fails, copy the packet to mbufs and put the
1889                  * jumbo buffer back in the ring so it can be
1890                  * re-used. If allocating mbufs fails, then we
1891                  * have to drop the packet.
1892                  */
1893                 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) {
1894                         struct mbuf             *m0;
1895                         m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1896                             total_len + ETHER_ALIGN, 0, ifp, NULL);
1897                         sk_newbuf(sc_if, cur_rx, m);
1898                         if (m0 == NULL) {
1899                                 printf("sk%d: no receive buffers "
1900                                     "available -- packet dropped!\n",
1901                                     sc_if->sk_unit);
1902                                 ifp->if_ierrors++;
1903                                 continue;
1904                         }
1905                         m_adj(m0, ETHER_ALIGN);
1906                         m = m0;
1907                 } else {
1908                         m->m_pkthdr.rcvif = ifp;
1909                         m->m_pkthdr.len = m->m_len = total_len;
1910                 }
1911
1912                 ifp->if_ipackets++;
1913                 eh = mtod(m, struct ether_header *);
1914
1915                 /* Remove header from mbuf and pass it on. */
1916                 m_adj(m, sizeof(struct ether_header));
1917                 ether_input(ifp, eh, m);
1918         }
1919
1920         sc_if->sk_cdata.sk_rx_prod = i;
1921
1922         return;
1923 }
1924
1925 static void sk_txeof(sc_if)
1926         struct sk_if_softc      *sc_if;
1927 {
1928         struct sk_tx_desc       *cur_tx = NULL;
1929         struct ifnet            *ifp;
1930         u_int32_t               idx;
1931
1932         ifp = &sc_if->arpcom.ac_if;
1933
1934         /*
1935          * Go through our tx ring and free mbufs for those
1936          * frames that have been sent.
1937          */
1938         idx = sc_if->sk_cdata.sk_tx_cons;
1939         while(idx != sc_if->sk_cdata.sk_tx_prod) {
1940                 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx];
1941                 if (cur_tx->sk_ctl & SK_TXCTL_OWN)
1942                         break;
1943                 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG)
1944                         ifp->if_opackets++;
1945                 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) {
1946                         m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf);
1947                         sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL;
1948                 }
1949                 sc_if->sk_cdata.sk_tx_cnt--;
1950                 SK_INC(idx, SK_TX_RING_CNT);
1951                 ifp->if_timer = 0;
1952         }
1953
1954         sc_if->sk_cdata.sk_tx_cons = idx;
1955
1956         if (cur_tx != NULL)
1957                 ifp->if_flags &= ~IFF_OACTIVE;
1958
1959         return;
1960 }
1961
1962 static void sk_tick(xsc_if)
1963         void                    *xsc_if;
1964 {
1965         struct sk_if_softc      *sc_if;
1966         struct mii_data         *mii;
1967         struct ifnet            *ifp;
1968         int                     i;
1969
1970         sc_if = xsc_if;
1971         ifp = &sc_if->arpcom.ac_if;
1972         mii = device_get_softc(sc_if->sk_miibus);
1973
1974         if (!(ifp->if_flags & IFF_UP))
1975                 return;
1976
1977         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
1978                 sk_intr_bcom(sc_if);
1979                 return;
1980         }
1981
1982         /*
1983          * According to SysKonnect, the correct way to verify that
1984          * the link has come back up is to poll bit 0 of the GPIO
1985          * register three times. This pin has the signal from the
1986          * link_sync pin connected to it; if we read the same link
1987          * state 3 times in a row, we know the link is up.
1988          */
1989         for (i = 0; i < 3; i++) {
1990                 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
1991                         break;
1992         }
1993
1994         if (i != 3) {
1995                 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
1996                 return;
1997         }
1998
1999         /* Turn the GP0 interrupt back on. */
2000         SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2001         SK_XM_READ_2(sc_if, XM_ISR);
2002         mii_tick(mii);
2003         mii_pollstat(mii);
2004         untimeout(sk_tick, sc_if, sc_if->sk_tick_ch);
2005
2006         return;
2007 }
2008
2009 static void sk_intr_bcom(sc_if)
2010         struct sk_if_softc      *sc_if;
2011 {
2012         struct sk_softc         *sc;
2013         struct mii_data         *mii;
2014         struct ifnet            *ifp;
2015         int                     status;
2016
2017         sc = sc_if->sk_softc;
2018         mii = device_get_softc(sc_if->sk_miibus);
2019         ifp = &sc_if->arpcom.ac_if;
2020
2021         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2022
2023         /*
2024          * Read the PHY interrupt register to make sure
2025          * we clear any pending interrupts.
2026          */
2027         status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
2028
2029         if (!(ifp->if_flags & IFF_RUNNING)) {
2030                 sk_init_xmac(sc_if);
2031                 return;
2032         }
2033
2034         if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
2035                 int                     lstat;
2036                 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
2037                     BRGPHY_MII_AUXSTS);
2038
2039                 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
2040                         mii_mediachg(mii);
2041                         /* Turn off the link LED. */
2042                         SK_IF_WRITE_1(sc_if, 0,
2043                             SK_LINKLED1_CTL, SK_LINKLED_OFF);
2044                         sc_if->sk_link = 0;
2045                 } else if (status & BRGPHY_ISR_LNK_CHG) {
2046                         sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2047                             BRGPHY_MII_IMR, 0xFF00);
2048                         mii_tick(mii);
2049                         sc_if->sk_link = 1;
2050                         /* Turn on the link LED. */
2051                         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2052                             SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
2053                             SK_LINKLED_BLINK_OFF);
2054                         mii_pollstat(mii);
2055                 } else {
2056                         mii_tick(mii);
2057                         sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
2058                 }
2059         }
2060
2061         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2062
2063         return;
2064 }
2065
2066 static void sk_intr_xmac(sc_if)
2067         struct sk_if_softc      *sc_if;
2068 {
2069         struct sk_softc         *sc;
2070         u_int16_t               status;
2071         struct mii_data         *mii;
2072
2073         sc = sc_if->sk_softc;
2074         mii = device_get_softc(sc_if->sk_miibus);
2075         status = SK_XM_READ_2(sc_if, XM_ISR);
2076
2077         /*
2078          * Link has gone down. Start MII tick timeout to
2079          * watch for link resync.
2080          */
2081         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
2082                 if (status & XM_ISR_GP0_SET) {
2083                         SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2084                         sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
2085                 }
2086
2087                 if (status & XM_ISR_AUTONEG_DONE) {
2088                         sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
2089                 }
2090         }
2091
2092         if (status & XM_IMR_TX_UNDERRUN)
2093                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
2094
2095         if (status & XM_IMR_RX_OVERRUN)
2096                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
2097
2098         status = SK_XM_READ_2(sc_if, XM_ISR);
2099
2100         return;
2101 }
2102
2103 static void sk_intr_yukon(sc_if)
2104         struct sk_if_softc      *sc_if;
2105 {
2106         int status;
2107
2108         status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2109
2110         return;
2111 }
2112
2113 static void sk_intr(xsc)
2114         void                    *xsc;
2115 {
2116         struct sk_softc         *sc = xsc;
2117         struct sk_if_softc      *sc_if0 = NULL, *sc_if1 = NULL;
2118         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
2119         u_int32_t               status;
2120
2121         sc_if0 = sc->sk_if[SK_PORT_A];
2122         sc_if1 = sc->sk_if[SK_PORT_B];
2123
2124         if (sc_if0 != NULL)
2125                 ifp0 = &sc_if0->arpcom.ac_if;
2126         if (sc_if1 != NULL)
2127                 ifp1 = &sc_if1->arpcom.ac_if;
2128
2129         for (;;) {
2130                 status = CSR_READ_4(sc, SK_ISSR);
2131                 if (!(status & sc->sk_intrmask))
2132                         break;
2133
2134                 /* Handle receive interrupts first. */
2135                 if (status & SK_ISR_RX1_EOF) {
2136                         sk_rxeof(sc_if0);
2137                         CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
2138                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2139                 }
2140                 if (status & SK_ISR_RX2_EOF) {
2141                         sk_rxeof(sc_if1);
2142                         CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
2143                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2144                 }
2145
2146                 /* Then transmit interrupts. */
2147                 if (status & SK_ISR_TX1_S_EOF) {
2148                         sk_txeof(sc_if0);
2149                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR0,
2150                             SK_TXBMU_CLR_IRQ_EOF);
2151                 }
2152                 if (status & SK_ISR_TX2_S_EOF) {
2153                         sk_txeof(sc_if1);
2154                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR1,
2155                             SK_TXBMU_CLR_IRQ_EOF);
2156                 }
2157
2158                 /* Then MAC interrupts. */
2159                 if (status & SK_ISR_MAC1 && ifp0->if_flags & IFF_RUNNING) {
2160                         if (sc->sk_type == SK_GENESIS)
2161                                 sk_intr_xmac(sc_if0);
2162                         else
2163                                 sk_intr_yukon(sc_if0);
2164                 }
2165
2166                 if (status & SK_ISR_MAC2 && ifp1->if_flags & IFF_RUNNING) {
2167                         if (sc->sk_type == SK_GENESIS)
2168                                 sk_intr_xmac(sc_if1);
2169                         else
2170                                 sk_intr_yukon(sc_if0);
2171                 }
2172
2173                 if (status & SK_ISR_EXTERNAL_REG) {
2174                         if (ifp0 != NULL &&
2175                             sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
2176                                 sk_intr_bcom(sc_if0);
2177                         if (ifp1 != NULL &&
2178                             sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
2179                                 sk_intr_bcom(sc_if1);
2180                 }
2181         }
2182
2183         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2184
2185         if (ifp0 != NULL && ifp0->if_snd.ifq_head != NULL)
2186                 sk_start(ifp0);
2187         if (ifp1 != NULL && ifp1->if_snd.ifq_head != NULL)
2188                 sk_start(ifp1);
2189
2190         return;
2191 }
2192
2193 static void sk_init_xmac(sc_if)
2194         struct sk_if_softc      *sc_if;
2195 {
2196         struct sk_softc         *sc;
2197         struct ifnet            *ifp;
2198         struct sk_bcom_hack     bhack[] = {
2199         { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
2200         { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
2201         { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
2202         { 0, 0 } };
2203
2204         sc = sc_if->sk_softc;
2205         ifp = &sc_if->arpcom.ac_if;
2206
2207         /* Unreset the XMAC. */
2208         SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
2209         DELAY(1000);
2210
2211         /* Reset the XMAC's internal state. */
2212         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2213
2214         /* Save the XMAC II revision */
2215         sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
2216
2217         /*
2218          * Perform additional initialization for external PHYs,
2219          * namely for the 1000baseTX cards that use the XMAC's
2220          * GMII mode.
2221          */
2222         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2223                 int                     i = 0;
2224                 u_int32_t               val;
2225
2226                 /* Take PHY out of reset. */
2227                 val = sk_win_read_4(sc, SK_GPIO);
2228                 if (sc_if->sk_port == SK_PORT_A)
2229                         val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
2230                 else
2231                         val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
2232                 sk_win_write_4(sc, SK_GPIO, val);
2233
2234                 /* Enable GMII mode on the XMAC. */
2235                 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
2236
2237                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2238                     BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
2239                 DELAY(10000);
2240                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2241                     BRGPHY_MII_IMR, 0xFFF0);
2242
2243                 /*
2244                  * Early versions of the BCM5400 apparently have
2245                  * a bug that requires them to have their reserved
2246                  * registers initialized to some magic values. I don't
2247                  * know what the numbers do, I'm just the messenger.
2248                  */
2249                 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
2250                     == 0x6041) {
2251                         while(bhack[i].reg) {
2252                                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2253                                     bhack[i].reg, bhack[i].val);
2254                                 i++;
2255                         }
2256                 }
2257         }
2258
2259         /* Set station address */
2260         SK_XM_WRITE_2(sc_if, XM_PAR0,
2261             *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0]));
2262         SK_XM_WRITE_2(sc_if, XM_PAR1,
2263             *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2]));
2264         SK_XM_WRITE_2(sc_if, XM_PAR2,
2265             *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4]));
2266         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
2267
2268         if (ifp->if_flags & IFF_BROADCAST) {
2269                 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2270         } else {
2271                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2272         }
2273
2274         /* We don't need the FCS appended to the packet. */
2275         SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
2276
2277         /* We want short frames padded to 60 bytes. */
2278         SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
2279
2280         /*
2281          * Enable the reception of all error frames. This is is
2282          * a necessary evil due to the design of the XMAC. The
2283          * XMAC's receive FIFO is only 8K in size, however jumbo
2284          * frames can be up to 9000 bytes in length. When bad
2285          * frame filtering is enabled, the XMAC's RX FIFO operates
2286          * in 'store and forward' mode. For this to work, the
2287          * entire frame has to fit into the FIFO, but that means
2288          * that jumbo frames larger than 8192 bytes will be
2289          * truncated. Disabling all bad frame filtering causes
2290          * the RX FIFO to operate in streaming mode, in which
2291          * case the XMAC will start transfering frames out of the
2292          * RX FIFO as soon as the FIFO threshold is reached.
2293          */
2294         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
2295             XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
2296             XM_MODE_RX_INRANGELEN);
2297
2298         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2299                 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2300         else
2301                 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2302
2303         /*
2304          * Bump up the transmit threshold. This helps hold off transmit
2305          * underruns when we're blasting traffic from both ports at once.
2306          */
2307         SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
2308
2309         /* Set promiscuous mode */
2310         sk_setpromisc(sc_if);
2311
2312         /* Set multicast filter */
2313         sk_setmulti(sc_if);
2314
2315         /* Clear and enable interrupts */
2316         SK_XM_READ_2(sc_if, XM_ISR);
2317         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
2318                 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
2319         else
2320                 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2321
2322         /* Configure MAC arbiter */
2323         switch(sc_if->sk_xmac_rev) {
2324         case XM_XMAC_REV_B2:
2325                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
2326                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
2327                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
2328                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
2329                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
2330                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
2331                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
2332                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
2333                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2334                 break;
2335         case XM_XMAC_REV_C1:
2336                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
2337                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
2338                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
2339                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
2340                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
2341                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
2342                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
2343                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
2344                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2345                 break;
2346         default:
2347                 break;
2348         }
2349         sk_win_write_2(sc, SK_MACARB_CTL,
2350             SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
2351
2352         sc_if->sk_link = 1;
2353
2354         return;
2355 }
2356
2357 static void sk_init_yukon(sc_if)
2358         struct sk_if_softc      *sc_if;
2359 {
2360         u_int32_t               phy;
2361         u_int16_t               reg;
2362         int                     i;
2363
2364         /* GMAC and GPHY Reset */
2365         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
2366         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2367         DELAY(1000);
2368         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR);
2369         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2370         DELAY(1000);
2371
2372         phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
2373                 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
2374
2375         switch(sc_if->sk_softc->sk_pmd) {
2376         case IFM_1000_SX:
2377         case IFM_1000_LX:
2378                 phy |= SK_GPHY_FIBER;
2379                 break;
2380
2381         case IFM_1000_CX:
2382         case IFM_1000_TX:
2383                 phy |= SK_GPHY_COPPER;
2384                 break;
2385         }
2386
2387         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
2388         DELAY(1000);
2389         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
2390         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
2391                       SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
2392
2393         /* unused read of the interrupt source register */
2394         SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2395
2396         reg = SK_YU_READ_2(sc_if, YUKON_PAR);
2397
2398         /* MIB Counter Clear Mode set */
2399         reg |= YU_PAR_MIB_CLR;
2400         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2401
2402         /* MIB Counter Clear Mode clear */
2403         reg &= ~YU_PAR_MIB_CLR;
2404         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2405
2406         /* receive control reg */
2407         SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
2408
2409         /* transmit parameter register */
2410         SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
2411                       YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
2412
2413         /* serial mode register */
2414         SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) |
2415                       YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e));
2416
2417         /* Setup Yukon's address */
2418         for (i = 0; i < 3; i++) {
2419                 /* Write Source Address 1 (unicast filter) */
2420                 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
2421                               sc_if->arpcom.ac_enaddr[i * 2] |
2422                               sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8);
2423         }
2424
2425         for (i = 0; i < 3; i++) {
2426                 reg = sk_win_read_2(sc_if->sk_softc,
2427                                     SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
2428                 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
2429         }
2430
2431         /* Set promiscuous mode */
2432         sk_setpromisc(sc_if);
2433
2434         /* Set multicast filter */
2435         sk_setmulti(sc_if);
2436
2437         /* enable interrupt mask for counter overflows */
2438         SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
2439         SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
2440         SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
2441
2442         /* Configure RX MAC FIFO */
2443         SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
2444         SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON);
2445
2446         /* Configure TX MAC FIFO */
2447         SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
2448         SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
2449 }
2450
2451 /*
2452  * Note that to properly initialize any part of the GEnesis chip,
2453  * you first have to take it out of reset mode.
2454  */
2455 static void sk_init(xsc)
2456         void                    *xsc;
2457 {
2458         struct sk_if_softc      *sc_if = xsc;
2459         struct sk_softc         *sc;
2460         struct ifnet            *ifp;
2461         struct mii_data         *mii;
2462         int                     s;
2463         u_int16_t               reg;
2464
2465         s = splimp();
2466
2467         ifp = &sc_if->arpcom.ac_if;
2468         sc = sc_if->sk_softc;
2469         mii = device_get_softc(sc_if->sk_miibus);
2470
2471         /* Cancel pending I/O and free all RX/TX buffers. */
2472         sk_stop(sc_if);
2473
2474         if (sc->sk_type == SK_GENESIS) {
2475                 /* Configure LINK_SYNC LED */
2476                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
2477                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2478                         SK_LINKLED_LINKSYNC_ON);
2479
2480                 /* Configure RX LED */
2481                 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
2482                         SK_RXLEDCTL_COUNTER_START);
2483
2484                 /* Configure TX LED */
2485                 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
2486                         SK_TXLEDCTL_COUNTER_START);
2487         }
2488
2489         /* Configure I2C registers */
2490
2491         /* Configure XMAC(s) */
2492         switch (sc->sk_type) {
2493         case SK_GENESIS:
2494                 sk_init_xmac(sc_if);
2495                 break;
2496         case SK_YUKON:
2497                 sk_init_yukon(sc_if);
2498                 break;
2499         }
2500         mii_mediachg(mii);
2501
2502         if (sc->sk_type == SK_GENESIS) {
2503                 /* Configure MAC FIFOs */
2504                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
2505                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
2506                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
2507
2508                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
2509                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
2510                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
2511         }
2512
2513         /* Configure transmit arbiter(s) */
2514         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
2515             SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
2516
2517         /* Configure RAMbuffers */
2518         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2519         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2520         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2521         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2522         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2523         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2524
2525         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
2526         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
2527         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
2528         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
2529         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
2530         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
2531         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
2532
2533         /* Configure BMUs */
2534         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
2535         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
2536             vtophys(&sc_if->sk_rdata->sk_rx_ring[0]));
2537         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0);
2538
2539         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
2540         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
2541             vtophys(&sc_if->sk_rdata->sk_tx_ring[0]));
2542         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0);
2543
2544         /* Init descriptors */
2545         if (sk_init_rx_ring(sc_if) == ENOBUFS) {
2546                 printf("sk%d: initialization failed: no "
2547                     "memory for rx buffers\n", sc_if->sk_unit);
2548                 sk_stop(sc_if);
2549                 (void)splx(s);
2550                 return;
2551         }
2552         sk_init_tx_ring(sc_if);
2553
2554         /* Configure interrupt handling */
2555         CSR_READ_4(sc, SK_ISSR);
2556         if (sc_if->sk_port == SK_PORT_A)
2557                 sc->sk_intrmask |= SK_INTRS1;
2558         else
2559                 sc->sk_intrmask |= SK_INTRS2;
2560
2561         sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
2562
2563         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2564
2565         /* Start BMUs. */
2566         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
2567
2568         switch(sc->sk_type) {
2569         case SK_GENESIS:
2570                 /* Enable XMACs TX and RX state machines */
2571                 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
2572                 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2573                 break;
2574         case SK_YUKON:
2575                 reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
2576                 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
2577                 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN);
2578                 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
2579         }
2580
2581         ifp->if_flags |= IFF_RUNNING;
2582         ifp->if_flags &= ~IFF_OACTIVE;
2583
2584         splx(s);
2585
2586         return;
2587 }
2588
2589 static void sk_stop(sc_if)
2590         struct sk_if_softc      *sc_if;
2591 {
2592         int                     i;
2593         struct sk_softc         *sc;
2594         struct ifnet            *ifp;
2595
2596         sc = sc_if->sk_softc;
2597         ifp = &sc_if->arpcom.ac_if;
2598
2599         untimeout(sk_tick, sc_if, sc_if->sk_tick_ch);
2600
2601         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2602                 u_int32_t               val;
2603
2604                 /* Put PHY back into reset. */
2605                 val = sk_win_read_4(sc, SK_GPIO);
2606                 if (sc_if->sk_port == SK_PORT_A) {
2607                         val |= SK_GPIO_DIR0;
2608                         val &= ~SK_GPIO_DAT0;
2609                 } else {
2610                         val |= SK_GPIO_DIR2;
2611                         val &= ~SK_GPIO_DAT2;
2612                 }
2613                 sk_win_write_4(sc, SK_GPIO, val);
2614         }
2615
2616         /* Turn off various components of this interface. */
2617         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2618         switch (sc->sk_type) {
2619         case SK_GENESIS:
2620                 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
2621                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
2622                 break;
2623         case SK_YUKON:
2624                 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
2625                 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
2626                 break;
2627         }
2628         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
2629         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2630         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
2631         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2632         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2633         SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2634         SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2635         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2636         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2637
2638         /* Disable interrupts */
2639         if (sc_if->sk_port == SK_PORT_A)
2640                 sc->sk_intrmask &= ~SK_INTRS1;
2641         else
2642                 sc->sk_intrmask &= ~SK_INTRS2;
2643         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2644
2645         SK_XM_READ_2(sc_if, XM_ISR);
2646         SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2647
2648         /* Free RX and TX mbufs still in the queues. */
2649         for (i = 0; i < SK_RX_RING_CNT; i++) {
2650                 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) {
2651                         m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf);
2652                         sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL;
2653                 }
2654         }
2655
2656         for (i = 0; i < SK_TX_RING_CNT; i++) {
2657                 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) {
2658                         m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf);
2659                         sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL;
2660                 }
2661         }
2662
2663         ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
2664
2665         return;
2666 }