2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $
33 * $DragonFly: src/sys/dev/netif/dc/if_dc.c,v 1.26 2005/05/24 20:59:01 dillon Exp $
37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
38 * series chips and several workalikes including the following:
40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
42 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
43 * ASIX Electronics AX88140A (www.asix.com.tw)
44 * ASIX Electronics AX88141 (www.asix.com.tw)
45 * ADMtek AL981 (www.admtek.com.tw)
46 * ADMtek AN985 (www.admtek.com.tw)
47 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
48 * Accton EN1217 (www.accton.com)
49 * Conexant LANfinity (www.conexant.com)
51 * Datasheets for the 21143 are available at developer.intel.com.
52 * Datasheets for the clone parts can be found at their respective sites.
53 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
54 * The PNIC II is essentially a Macronix 98715A chip; the only difference
55 * worth noting is that its multicast hash table is only 128 bits wide
58 * Written by Bill Paul <wpaul@ee.columbia.edu>
59 * Electrical Engineering Department
60 * Columbia University, New York City
64 * The Intel 21143 is the successor to the DEC 21140. It is basically
65 * the same as the 21140 but with a few new features. The 21143 supports
66 * three kinds of media attachments:
68 * o MII port, for 10Mbps and 100Mbps support and NWAY
69 * autonegotiation provided by an external PHY.
70 * o SYM port, for symbol mode 100Mbps support.
74 * The 100Mbps SYM port and 10baseT port can be used together in
75 * combination with the internal NWAY support to create a 10/100
76 * autosensing configuration.
78 * Note that not all tulip workalikes are handled in this driver: we only
79 * deal with those which are relatively well behaved. The Winbond is
80 * handled separately due to its different register offsets and the
81 * special handling needed for its various bugs. The PNIC is handled
82 * here, but I'm not thrilled about it.
84 * All of the workalike chips use some form of MII transceiver support
85 * with the exception of the Macronix chips, which also have a SYM port.
86 * The ASIX AX88140A is also documented to have a SYM port, but all
87 * the cards I've seen use an MII transceiver, probably because the
88 * AX88140A doesn't support internal NWAY.
91 #include <sys/param.h>
92 #include <sys/systm.h>
93 #include <sys/sockio.h>
95 #include <sys/malloc.h>
96 #include <sys/kernel.h>
97 #include <sys/socket.h>
98 #include <sys/sysctl.h>
101 #include <net/ifq_var.h>
102 #include <net/if_arp.h>
103 #include <net/ethernet.h>
104 #include <net/if_dl.h>
105 #include <net/if_media.h>
106 #include <net/if_types.h>
107 #include <net/vlan/if_vlan_var.h>
111 #include <vm/vm.h> /* for vtophys */
112 #include <vm/pmap.h> /* for vtophys */
113 #include <machine/clock.h> /* for DELAY */
114 #include <machine/bus_pio.h>
115 #include <machine/bus_memio.h>
116 #include <machine/bus.h>
117 #include <machine/resource.h>
119 #include <sys/rman.h>
121 #include "../mii_layer/mii.h"
122 #include "../mii_layer/miivar.h"
124 #include <bus/pci/pcireg.h>
125 #include <bus/pci/pcivar.h>
127 #define DC_USEIOSPACE
129 #include "if_dcreg.h"
131 /* "controller miibus0" required. See GENERIC if you get errors here. */
132 #include "miibus_if.h"
135 * Various supported device vendors/types and their names.
137 static struct dc_type dc_devs[] = {
138 { DC_VENDORID_DEC, DC_DEVICEID_21143,
139 "Intel 21143 10/100BaseTX" },
140 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009,
141 "Davicom DM9009 10/100BaseTX" },
142 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100,
143 "Davicom DM9100 10/100BaseTX" },
144 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
145 "Davicom DM9102 10/100BaseTX" },
146 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
147 "Davicom DM9102A 10/100BaseTX" },
148 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981,
149 "ADMtek AL981 10/100BaseTX" },
150 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985,
151 "ADMtek AN985 10/100BaseTX" },
152 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
153 "ASIX AX88140A 10/100BaseTX" },
154 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
155 "ASIX AX88141 10/100BaseTX" },
156 { DC_VENDORID_MX, DC_DEVICEID_98713,
157 "Macronix 98713 10/100BaseTX" },
158 { DC_VENDORID_MX, DC_DEVICEID_98713,
159 "Macronix 98713A 10/100BaseTX" },
160 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
161 "Compex RL100-TX 10/100BaseTX" },
162 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
163 "Compex RL100-TX 10/100BaseTX" },
164 { DC_VENDORID_MX, DC_DEVICEID_987x5,
165 "Macronix 98715/98715A 10/100BaseTX" },
166 { DC_VENDORID_MX, DC_DEVICEID_987x5,
167 "Macronix 98715AEC-C 10/100BaseTX" },
168 { DC_VENDORID_MX, DC_DEVICEID_987x5,
169 "Macronix 98725 10/100BaseTX" },
170 { DC_VENDORID_MX, DC_DEVICEID_98727,
171 "Macronix 98727/98732 10/100BaseTX" },
172 { DC_VENDORID_LO, DC_DEVICEID_82C115,
173 "LC82C115 PNIC II 10/100BaseTX" },
174 { DC_VENDORID_LO, DC_DEVICEID_82C168,
175 "82c168 PNIC 10/100BaseTX" },
176 { DC_VENDORID_LO, DC_DEVICEID_82C168,
177 "82c169 PNIC 10/100BaseTX" },
178 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217,
179 "Accton EN1217 10/100BaseTX" },
180 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242,
181 "Accton EN2242 MiniPCI 10/100BaseTX" },
182 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112,
183 "Conexant LANfinity MiniPCI 10/100BaseTX" },
184 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB,
185 "3Com OfficeConnect 10/100B" },
189 static int dc_probe (device_t);
190 static int dc_attach (device_t);
191 static int dc_detach (device_t);
192 static int dc_suspend (device_t);
193 static int dc_resume (device_t);
194 static void dc_acpi (device_t);
195 static struct dc_type *dc_devtype (device_t);
196 static int dc_newbuf (struct dc_softc *, int, struct mbuf *);
197 static int dc_encap (struct dc_softc *, struct mbuf *,
199 static void dc_pnic_rx_bug_war (struct dc_softc *, int);
200 static int dc_rx_resync (struct dc_softc *);
201 static void dc_rxeof (struct dc_softc *);
202 static void dc_txeof (struct dc_softc *);
203 static void dc_tick (void *);
204 static void dc_tx_underrun (struct dc_softc *);
205 static void dc_intr (void *);
206 static void dc_start (struct ifnet *);
207 static int dc_ioctl (struct ifnet *, u_long, caddr_t,
209 static void dc_init (void *);
210 static void dc_stop (struct dc_softc *);
211 static void dc_watchdog (struct ifnet *);
212 static void dc_shutdown (device_t);
213 static int dc_ifmedia_upd (struct ifnet *);
214 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *);
216 static void dc_delay (struct dc_softc *);
217 static void dc_eeprom_idle (struct dc_softc *);
218 static void dc_eeprom_putbyte (struct dc_softc *, int);
219 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *);
220 static void dc_eeprom_getword_pnic
221 (struct dc_softc *, int, u_int16_t *);
222 static void dc_eeprom_width (struct dc_softc *);
223 static void dc_read_eeprom (struct dc_softc *, caddr_t, int,
226 static void dc_mii_writebit (struct dc_softc *, int);
227 static int dc_mii_readbit (struct dc_softc *);
228 static void dc_mii_sync (struct dc_softc *);
229 static void dc_mii_send (struct dc_softc *, u_int32_t, int);
230 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *);
231 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *);
232 static int dc_miibus_readreg (device_t, int, int);
233 static int dc_miibus_writereg (device_t, int, int, int);
234 static void dc_miibus_statchg (device_t);
235 static void dc_miibus_mediainit (device_t);
237 static void dc_setcfg (struct dc_softc *, int);
238 static u_int32_t dc_crc_le (struct dc_softc *, c_caddr_t);
239 static u_int32_t dc_crc_be (caddr_t);
240 static void dc_setfilt_21143 (struct dc_softc *);
241 static void dc_setfilt_asix (struct dc_softc *);
242 static void dc_setfilt_admtek (struct dc_softc *);
244 static void dc_setfilt (struct dc_softc *);
246 static void dc_reset (struct dc_softc *);
247 static int dc_list_rx_init (struct dc_softc *);
248 static int dc_list_tx_init (struct dc_softc *);
250 static void dc_read_srom (struct dc_softc *, int);
251 static void dc_parse_21143_srom (struct dc_softc *);
252 static void dc_decode_leaf_sia (struct dc_softc *,
253 struct dc_eblock_sia *);
254 static void dc_decode_leaf_mii (struct dc_softc *,
255 struct dc_eblock_mii *);
256 static void dc_decode_leaf_sym (struct dc_softc *,
257 struct dc_eblock_sym *);
258 static void dc_apply_fixup (struct dc_softc *, int);
261 #define DC_RES SYS_RES_IOPORT
262 #define DC_RID DC_PCI_CFBIO
264 #define DC_RES SYS_RES_MEMORY
265 #define DC_RID DC_PCI_CFBMA
268 static device_method_t dc_methods[] = {
269 /* Device interface */
270 DEVMETHOD(device_probe, dc_probe),
271 DEVMETHOD(device_attach, dc_attach),
272 DEVMETHOD(device_detach, dc_detach),
273 DEVMETHOD(device_suspend, dc_suspend),
274 DEVMETHOD(device_resume, dc_resume),
275 DEVMETHOD(device_shutdown, dc_shutdown),
278 DEVMETHOD(bus_print_child, bus_generic_print_child),
279 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
282 DEVMETHOD(miibus_readreg, dc_miibus_readreg),
283 DEVMETHOD(miibus_writereg, dc_miibus_writereg),
284 DEVMETHOD(miibus_statchg, dc_miibus_statchg),
285 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
290 static driver_t dc_driver = {
293 sizeof(struct dc_softc)
296 static devclass_t dc_devclass;
299 static int dc_quick=1;
300 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW,
301 &dc_quick,0,"do not mdevget in dc driver");
304 DECLARE_DUMMY_MODULE(if_dc);
305 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0);
306 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
308 #define DC_SETBIT(sc, reg, x) \
309 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
311 #define DC_CLRBIT(sc, reg, x) \
312 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
314 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
315 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
317 static void dc_delay(sc)
322 for (idx = (300 / 33) + 1; idx > 0; idx--)
323 CSR_READ_4(sc, DC_BUSCTL);
326 static void dc_eeprom_width(sc)
331 /* Force EEPROM to idle state. */
334 /* Enter EEPROM access mode. */
335 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
337 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
339 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
341 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
346 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
348 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
350 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
352 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
356 for (i = 1; i <= 12; i++) {
357 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
359 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
360 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
364 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
368 /* Turn off EEPROM access mode. */
376 /* Enter EEPROM access mode. */
377 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
379 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
381 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
383 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
386 /* Turn off EEPROM access mode. */
390 static void dc_eeprom_idle(sc)
395 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
397 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
399 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
401 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
404 for (i = 0; i < 25; i++) {
405 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
407 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
411 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
413 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
415 CSR_WRITE_4(sc, DC_SIO, 0x00000000);
421 * Send a read command and address to the EEPROM, check for ACK.
423 static void dc_eeprom_putbyte(sc, addr)
429 d = DC_EECMD_READ >> 6;
432 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
434 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
436 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
438 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
443 * Feed in each bit and strobe the clock.
445 for (i = sc->dc_romwidth; i--;) {
446 if (addr & (1 << i)) {
447 SIO_SET(DC_SIO_EE_DATAIN);
449 SIO_CLR(DC_SIO_EE_DATAIN);
452 SIO_SET(DC_SIO_EE_CLK);
454 SIO_CLR(DC_SIO_EE_CLK);
462 * Read a word of data stored in the EEPROM at address 'addr.'
463 * The PNIC 82c168/82c169 has its own non-standard way to read
466 static void dc_eeprom_getword_pnic(sc, addr, dest)
474 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr);
476 for (i = 0; i < DC_TIMEOUT; i++) {
478 r = CSR_READ_4(sc, DC_SIO);
479 if (!(r & DC_PN_SIOCTL_BUSY)) {
480 *dest = (u_int16_t)(r & 0xFFFF);
489 * Read a word of data stored in the EEPROM at address 'addr.'
491 static void dc_eeprom_getword(sc, addr, dest)
499 /* Force EEPROM to idle state. */
502 /* Enter EEPROM access mode. */
503 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
505 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
507 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
509 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
513 * Send address of word we want to read.
515 dc_eeprom_putbyte(sc, addr);
518 * Start reading bits from EEPROM.
520 for (i = 0x8000; i; i >>= 1) {
521 SIO_SET(DC_SIO_EE_CLK);
523 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
526 SIO_CLR(DC_SIO_EE_CLK);
530 /* Turn off EEPROM access mode. */
539 * Read a sequence of words from the EEPROM.
541 static void dc_read_eeprom(sc, dest, off, cnt, swap)
549 u_int16_t word = 0, *ptr;
551 for (i = 0; i < cnt; i++) {
553 dc_eeprom_getword_pnic(sc, off + i, &word);
555 dc_eeprom_getword(sc, off + i, &word);
556 ptr = (u_int16_t *)(dest + (i * 2));
567 * The following two routines are taken from the Macronix 98713
568 * Application Notes pp.19-21.
571 * Write a bit to the MII bus.
573 static void dc_mii_writebit(sc, bit)
578 CSR_WRITE_4(sc, DC_SIO,
579 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT);
581 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
583 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
584 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
590 * Read a bit from the MII bus.
592 static int dc_mii_readbit(sc)
595 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR);
596 CSR_READ_4(sc, DC_SIO);
597 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
598 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
599 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
606 * Sync the PHYs by setting data bit and strobing the clock 32 times.
608 static void dc_mii_sync(sc)
613 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
615 for (i = 0; i < 32; i++)
616 dc_mii_writebit(sc, 1);
622 * Clock a series of bits through the MII.
624 static void dc_mii_send(sc, bits, cnt)
631 for (i = (0x1 << (cnt - 1)); i; i >>= 1)
632 dc_mii_writebit(sc, bits & i);
636 * Read an PHY register through the MII.
638 static int dc_mii_readreg(sc, frame)
640 struct dc_mii_frame *frame;
648 * Set up frame for RX.
650 frame->mii_stdelim = DC_MII_STARTDELIM;
651 frame->mii_opcode = DC_MII_READOP;
652 frame->mii_turnaround = 0;
661 * Send command/address info.
663 dc_mii_send(sc, frame->mii_stdelim, 2);
664 dc_mii_send(sc, frame->mii_opcode, 2);
665 dc_mii_send(sc, frame->mii_phyaddr, 5);
666 dc_mii_send(sc, frame->mii_regaddr, 5);
670 dc_mii_writebit(sc, 1);
671 dc_mii_writebit(sc, 0);
675 ack = dc_mii_readbit(sc);
678 * Now try reading data bits. If the ack failed, we still
679 * need to clock through 16 cycles to keep the PHY(s) in sync.
682 for(i = 0; i < 16; i++) {
688 for (i = 0x8000; i; i >>= 1) {
690 if (dc_mii_readbit(sc))
691 frame->mii_data |= i;
697 dc_mii_writebit(sc, 0);
698 dc_mii_writebit(sc, 0);
708 * Write to a PHY register through the MII.
710 static int dc_mii_writereg(sc, frame)
712 struct dc_mii_frame *frame;
719 * Set up frame for TX.
722 frame->mii_stdelim = DC_MII_STARTDELIM;
723 frame->mii_opcode = DC_MII_WRITEOP;
724 frame->mii_turnaround = DC_MII_TURNAROUND;
731 dc_mii_send(sc, frame->mii_stdelim, 2);
732 dc_mii_send(sc, frame->mii_opcode, 2);
733 dc_mii_send(sc, frame->mii_phyaddr, 5);
734 dc_mii_send(sc, frame->mii_regaddr, 5);
735 dc_mii_send(sc, frame->mii_turnaround, 2);
736 dc_mii_send(sc, frame->mii_data, 16);
739 dc_mii_writebit(sc, 0);
740 dc_mii_writebit(sc, 0);
747 static int dc_miibus_readreg(dev, phy, reg)
751 struct dc_mii_frame frame;
753 int i, rval, phy_reg = 0;
755 sc = device_get_softc(dev);
756 bzero((char *)&frame, sizeof(frame));
759 * Note: both the AL981 and AN985 have internal PHYs,
760 * however the AL981 provides direct access to the PHY
761 * registers while the AN985 uses a serial MII interface.
762 * The AN985's MII interface is also buggy in that you
763 * can read from any MII address (0 to 31), but only address 1
764 * behaves normally. To deal with both cases, we pretend
765 * that the PHY is at MII address 1.
767 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
771 * Note: the ukphy probes of the RS7112 report a PHY at
772 * MII address 0 (possibly HomePNA?) and 1 (ethernet)
773 * so we only respond to correct one.
775 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
778 if (sc->dc_pmode != DC_PMODE_MII) {
779 if (phy == (MII_NPHY - 1)) {
783 * Fake something to make the probe
784 * code think there's a PHY here.
786 return(BMSR_MEDIAMASK);
790 return(DC_VENDORID_LO);
791 return(DC_VENDORID_DEC);
795 return(DC_DEVICEID_82C168);
796 return(DC_DEVICEID_21143);
806 if (DC_IS_PNIC(sc)) {
807 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
808 (phy << 23) | (reg << 18));
809 for (i = 0; i < DC_TIMEOUT; i++) {
811 rval = CSR_READ_4(sc, DC_PN_MII);
812 if (!(rval & DC_PN_MII_BUSY)) {
814 return(rval == 0xFFFF ? 0 : rval);
820 if (DC_IS_COMET(sc)) {
823 phy_reg = DC_AL_BMCR;
826 phy_reg = DC_AL_BMSR;
829 phy_reg = DC_AL_VENID;
832 phy_reg = DC_AL_DEVID;
835 phy_reg = DC_AL_ANAR;
838 phy_reg = DC_AL_LPAR;
841 phy_reg = DC_AL_ANER;
844 printf("dc%d: phy_read: bad phy register %x\n",
850 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
857 frame.mii_phyaddr = phy;
858 frame.mii_regaddr = reg;
859 if (sc->dc_type == DC_TYPE_98713) {
860 phy_reg = CSR_READ_4(sc, DC_NETCFG);
861 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
863 dc_mii_readreg(sc, &frame);
864 if (sc->dc_type == DC_TYPE_98713)
865 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
867 return(frame.mii_data);
870 static int dc_miibus_writereg(dev, phy, reg, data)
875 struct dc_mii_frame frame;
878 sc = device_get_softc(dev);
879 bzero((char *)&frame, sizeof(frame));
881 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
884 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
887 if (DC_IS_PNIC(sc)) {
888 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
889 (phy << 23) | (reg << 10) | data);
890 for (i = 0; i < DC_TIMEOUT; i++) {
891 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
897 if (DC_IS_COMET(sc)) {
900 phy_reg = DC_AL_BMCR;
903 phy_reg = DC_AL_BMSR;
906 phy_reg = DC_AL_VENID;
909 phy_reg = DC_AL_DEVID;
912 phy_reg = DC_AL_ANAR;
915 phy_reg = DC_AL_LPAR;
918 phy_reg = DC_AL_ANER;
921 printf("dc%d: phy_write: bad phy register %x\n",
927 CSR_WRITE_4(sc, phy_reg, data);
931 frame.mii_phyaddr = phy;
932 frame.mii_regaddr = reg;
933 frame.mii_data = data;
935 if (sc->dc_type == DC_TYPE_98713) {
936 phy_reg = CSR_READ_4(sc, DC_NETCFG);
937 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
939 dc_mii_writereg(sc, &frame);
940 if (sc->dc_type == DC_TYPE_98713)
941 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
946 static void dc_miibus_statchg(dev)
950 struct mii_data *mii;
953 sc = device_get_softc(dev);
954 if (DC_IS_ADMTEK(sc))
957 mii = device_get_softc(sc->dc_miibus);
958 ifm = &mii->mii_media;
959 if (DC_IS_DAVICOM(sc) &&
960 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
961 dc_setcfg(sc, ifm->ifm_media);
962 sc->dc_if_media = ifm->ifm_media;
964 dc_setcfg(sc, mii->mii_media_active);
965 sc->dc_if_media = mii->mii_media_active;
972 * Special support for DM9102A cards with HomePNA PHYs. Note:
973 * with the Davicom DM9102A/DM9801 eval board that I have, it seems
974 * to be impossible to talk to the management interface of the DM9801
975 * PHY (its MDIO pin is not connected to anything). Consequently,
976 * the driver has to just 'know' about the additional mode and deal
977 * with it itself. *sigh*
979 static void dc_miibus_mediainit(dev)
983 struct mii_data *mii;
987 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF;
989 sc = device_get_softc(dev);
990 mii = device_get_softc(sc->dc_miibus);
991 ifm = &mii->mii_media;
993 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
994 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
999 #define DC_POLY 0xEDB88320
1000 #define DC_BITS_512 9
1001 #define DC_BITS_128 7
1002 #define DC_BITS_64 6
1004 static u_int32_t dc_crc_le(sc, addr)
1005 struct dc_softc *sc;
1008 u_int32_t idx, bit, data, crc;
1010 /* Compute CRC for the address value. */
1011 crc = 0xFFFFFFFF; /* initial value */
1013 for (idx = 0; idx < 6; idx++) {
1014 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
1015 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0);
1019 * The hash table on the PNIC II and the MX98715AEC-C/D/E
1020 * chips is only 128 bits wide.
1022 if (sc->dc_flags & DC_128BIT_HASH)
1023 return (crc & ((1 << DC_BITS_128) - 1));
1025 /* The hash table on the MX98715BEC is only 64 bits wide. */
1026 if (sc->dc_flags & DC_64BIT_HASH)
1027 return (crc & ((1 << DC_BITS_64) - 1));
1029 return (crc & ((1 << DC_BITS_512) - 1));
1033 * Calculate CRC of a multicast group address, return the lower 6 bits.
1035 static u_int32_t dc_crc_be(addr)
1038 u_int32_t crc, carry;
1042 /* Compute CRC for the address value. */
1043 crc = 0xFFFFFFFF; /* initial value */
1045 for (i = 0; i < 6; i++) {
1047 for (j = 0; j < 8; j++) {
1048 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
1052 crc = (crc ^ 0x04c11db6) | carry;
1056 /* return the filter bit position */
1057 return((crc >> 26) & 0x0000003F);
1061 * 21143-style RX filter setup routine. Filter programming is done by
1062 * downloading a special setup frame into the TX engine. 21143, Macronix,
1063 * PNIC, PNIC II and Davicom chips are programmed this way.
1065 * We always program the chip using 'hash perfect' mode, i.e. one perfect
1066 * address (our node address) and a 512-bit hash filter for multicast
1067 * frames. We also sneak the broadcast address into the hash filter since
1070 void dc_setfilt_21143(sc)
1071 struct dc_softc *sc;
1073 struct dc_desc *sframe;
1075 struct ifmultiaddr *ifma;
1079 ifp = &sc->arpcom.ac_if;
1081 i = sc->dc_cdata.dc_tx_prod;
1082 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1083 sc->dc_cdata.dc_tx_cnt++;
1084 sframe = &sc->dc_ldata->dc_tx_list[i];
1085 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf;
1086 bzero((char *)sp, DC_SFRAME_LEN);
1088 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf);
1089 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK |
1090 DC_FILTER_HASHPERF | DC_TXCTL_FINT;
1092 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf;
1094 /* If we want promiscuous mode, set the allframes bit. */
1095 if (ifp->if_flags & IFF_PROMISC)
1096 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1098 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1100 if (ifp->if_flags & IFF_ALLMULTI)
1101 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1103 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1105 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1106 ifma = ifma->ifma_link.le_next) {
1107 if (ifma->ifma_addr->sa_family != AF_LINK)
1110 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1111 sp[h >> 4] |= 1 << (h & 0xF);
1114 if (ifp->if_flags & IFF_BROADCAST) {
1115 h = dc_crc_le(sc, ifp->if_broadcastaddr);
1116 sp[h >> 4] |= 1 << (h & 0xF);
1119 /* Set our MAC address */
1120 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0];
1121 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1];
1122 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2];
1124 sframe->dc_status = DC_TXSTAT_OWN;
1125 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1128 * The PNIC takes an exceedingly long time to process its
1129 * setup frame; wait 10ms after posting the setup frame
1130 * before proceeding, just so it has time to swallow its
1140 void dc_setfilt_admtek(sc)
1141 struct dc_softc *sc;
1145 u_int32_t hashes[2] = { 0, 0 };
1146 struct ifmultiaddr *ifma;
1148 ifp = &sc->arpcom.ac_if;
1150 /* Init our MAC address */
1151 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1152 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1154 /* If we want promiscuous mode, set the allframes bit. */
1155 if (ifp->if_flags & IFF_PROMISC)
1156 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1158 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1160 if (ifp->if_flags & IFF_ALLMULTI)
1161 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1163 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1165 /* first, zot all the existing hash bits */
1166 CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1167 CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1170 * If we're already in promisc or allmulti mode, we
1171 * don't have to bother programming the multicast filter.
1173 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1176 /* now program new ones */
1177 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1178 ifma = ifma->ifma_link.le_next) {
1179 if (ifma->ifma_addr->sa_family != AF_LINK)
1181 if (DC_IS_CENTAUR(sc))
1182 h = dc_crc_le(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1184 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1186 hashes[0] |= (1 << h);
1188 hashes[1] |= (1 << (h - 32));
1191 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1192 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1197 void dc_setfilt_asix(sc)
1198 struct dc_softc *sc;
1202 u_int32_t hashes[2] = { 0, 0 };
1203 struct ifmultiaddr *ifma;
1205 ifp = &sc->arpcom.ac_if;
1207 /* Init our MAC address */
1208 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1209 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1210 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1211 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1212 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1213 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1215 /* If we want promiscuous mode, set the allframes bit. */
1216 if (ifp->if_flags & IFF_PROMISC)
1217 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1219 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1221 if (ifp->if_flags & IFF_ALLMULTI)
1222 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1224 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1227 * The ASIX chip has a special bit to enable reception
1228 * of broadcast frames.
1230 if (ifp->if_flags & IFF_BROADCAST)
1231 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1233 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1235 /* first, zot all the existing hash bits */
1236 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1237 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1238 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1239 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1242 * If we're already in promisc or allmulti mode, we
1243 * don't have to bother programming the multicast filter.
1245 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1248 /* now program new ones */
1249 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1250 ifma = ifma->ifma_link.le_next) {
1251 if (ifma->ifma_addr->sa_family != AF_LINK)
1253 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1255 hashes[0] |= (1 << h);
1257 hashes[1] |= (1 << (h - 32));
1260 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1261 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1262 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1263 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1268 static void dc_setfilt(sc)
1269 struct dc_softc *sc;
1271 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
1272 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
1273 dc_setfilt_21143(sc);
1276 dc_setfilt_asix(sc);
1278 if (DC_IS_ADMTEK(sc))
1279 dc_setfilt_admtek(sc);
1285 * In order to fiddle with the
1286 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
1287 * first have to put the transmit and/or receive logic in the idle state.
1289 static void dc_setcfg(sc, media)
1290 struct dc_softc *sc;
1296 if (IFM_SUBTYPE(media) == IFM_NONE)
1299 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) {
1301 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON));
1303 for (i = 0; i < DC_TIMEOUT; i++) {
1304 isr = CSR_READ_4(sc, DC_ISR);
1305 if (isr & DC_ISR_TX_IDLE ||
1306 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED)
1311 if (i == DC_TIMEOUT)
1312 printf("dc%d: failed to force tx and "
1313 "rx to idle state\n", sc->dc_unit);
1316 if (IFM_SUBTYPE(media) == IFM_100_TX) {
1317 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1318 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1319 if (sc->dc_pmode == DC_PMODE_MII) {
1322 if (DC_IS_INTEL(sc)) {
1323 /* there's a write enable bit here that reads as 1 */
1324 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1325 watchdogreg &= ~DC_WDOG_CTLWREN;
1326 watchdogreg |= DC_WDOG_JABBERDIS;
1327 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1329 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1331 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1332 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1333 if (sc->dc_type == DC_TYPE_98713)
1334 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1335 DC_NETCFG_SCRAMBLER));
1336 if (!DC_IS_DAVICOM(sc))
1337 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1338 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1339 if (DC_IS_INTEL(sc))
1340 dc_apply_fixup(sc, IFM_AUTO);
1342 if (DC_IS_PNIC(sc)) {
1343 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1344 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1345 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1347 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1348 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1349 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1350 if (DC_IS_INTEL(sc))
1352 (media & IFM_GMASK) == IFM_FDX ?
1353 IFM_100_TX|IFM_FDX : IFM_100_TX);
1357 if (IFM_SUBTYPE(media) == IFM_10_T) {
1358 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1359 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1360 if (sc->dc_pmode == DC_PMODE_MII) {
1363 /* there's a write enable bit here that reads as 1 */
1364 if (DC_IS_INTEL(sc)) {
1365 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1366 watchdogreg &= ~DC_WDOG_CTLWREN;
1367 watchdogreg |= DC_WDOG_JABBERDIS;
1368 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1370 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1372 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1373 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1374 if (sc->dc_type == DC_TYPE_98713)
1375 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1376 if (!DC_IS_DAVICOM(sc))
1377 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1378 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1379 if (DC_IS_INTEL(sc))
1380 dc_apply_fixup(sc, IFM_AUTO);
1382 if (DC_IS_PNIC(sc)) {
1383 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1384 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1385 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1387 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1388 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1389 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1390 if (DC_IS_INTEL(sc)) {
1391 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1392 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1393 if ((media & IFM_GMASK) == IFM_FDX)
1394 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1396 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1397 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1398 DC_CLRBIT(sc, DC_10BTCTRL,
1399 DC_TCTL_AUTONEGENBL);
1401 (media & IFM_GMASK) == IFM_FDX ?
1402 IFM_10_T|IFM_FDX : IFM_10_T);
1409 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1410 * PHY and we want HomePNA mode, set the portsel bit to turn
1411 * on the external MII port.
1413 if (DC_IS_DAVICOM(sc)) {
1414 if (IFM_SUBTYPE(media) == IFM_HPNA_1) {
1415 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1418 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1422 if ((media & IFM_GMASK) == IFM_FDX) {
1423 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1424 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1425 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1427 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1428 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1429 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1433 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON);
1438 static void dc_reset(sc)
1439 struct dc_softc *sc;
1443 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1445 for (i = 0; i < DC_TIMEOUT; i++) {
1447 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1451 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc)) {
1453 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1457 if (i == DC_TIMEOUT)
1458 printf("dc%d: reset never completed!\n", sc->dc_unit);
1460 /* Wait a little while for the chip to get its brains in order. */
1463 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1464 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1465 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1468 * Bring the SIA out of reset. In some cases, it looks
1469 * like failing to unreset the SIA soon enough gets it
1470 * into a state where it will never come out of reset
1471 * until we reset the whole chip again.
1473 if (DC_IS_INTEL(sc)) {
1474 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1475 CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1476 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1482 static struct dc_type *dc_devtype(dev)
1490 while(t->dc_name != NULL) {
1491 if ((pci_get_vendor(dev) == t->dc_vid) &&
1492 (pci_get_device(dev) == t->dc_did)) {
1493 /* Check the PCI revision */
1494 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF;
1495 if (t->dc_did == DC_DEVICEID_98713 &&
1496 rev >= DC_REVISION_98713A)
1498 if (t->dc_did == DC_DEVICEID_98713_CP &&
1499 rev >= DC_REVISION_98713A)
1501 if (t->dc_did == DC_DEVICEID_987x5 &&
1502 rev >= DC_REVISION_98715AEC_C)
1504 if (t->dc_did == DC_DEVICEID_987x5 &&
1505 rev >= DC_REVISION_98725)
1507 if (t->dc_did == DC_DEVICEID_AX88140A &&
1508 rev >= DC_REVISION_88141)
1510 if (t->dc_did == DC_DEVICEID_82C168 &&
1511 rev >= DC_REVISION_82C169)
1513 if (t->dc_did == DC_DEVICEID_DM9102 &&
1514 rev >= DC_REVISION_DM9102A)
1525 * Probe for a 21143 or clone chip. Check the PCI vendor and device
1526 * IDs against our list and return a device name if we find a match.
1527 * We do a little bit of extra work to identify the exact type of
1528 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1529 * but different revision IDs. The same is true for 98715/98715A
1530 * chips and the 98725, as well as the ASIX and ADMtek chips. In some
1531 * cases, the exact chip revision affects driver behavior.
1533 static int dc_probe(dev)
1538 t = dc_devtype(dev);
1541 device_set_desc(dev, t->dc_name);
1548 static void dc_acpi(dev)
1554 unit = device_get_unit(dev);
1556 /* Find the location of the capabilities block */
1557 cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF;
1559 r = pci_read_config(dev, cptr, 4) & 0xFF;
1562 r = pci_read_config(dev, cptr + 4, 4);
1563 if (r & DC_PSTATE_D3) {
1564 u_int32_t iobase, membase, irq;
1566 /* Save important PCI config data. */
1567 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4);
1568 membase = pci_read_config(dev, DC_PCI_CFBMA, 4);
1569 irq = pci_read_config(dev, DC_PCI_CFIT, 4);
1571 /* Reset the power state. */
1572 printf("dc%d: chip is in D%d power mode "
1573 "-- setting to D0\n", unit, r & DC_PSTATE_D3);
1575 pci_write_config(dev, cptr + 4, r, 4);
1577 /* Restore PCI config data. */
1578 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4);
1579 pci_write_config(dev, DC_PCI_CFBMA, membase, 4);
1580 pci_write_config(dev, DC_PCI_CFIT, irq, 4);
1586 static void dc_apply_fixup(sc, media)
1587 struct dc_softc *sc;
1590 struct dc_mediainfo *m;
1598 if (m->dc_media == media)
1606 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1607 reg = (p[0] | (p[1] << 8)) << 16;
1608 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1611 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1612 reg = (p[0] | (p[1] << 8)) << 16;
1613 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1619 static void dc_decode_leaf_sia(sc, l)
1620 struct dc_softc *sc;
1621 struct dc_eblock_sia *l;
1623 struct dc_mediainfo *m;
1625 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1626 if (l->dc_sia_code == DC_SIA_CODE_10BT)
1627 m->dc_media = IFM_10_T;
1629 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX)
1630 m->dc_media = IFM_10_T|IFM_FDX;
1632 if (l->dc_sia_code == DC_SIA_CODE_10B2)
1633 m->dc_media = IFM_10_2;
1635 if (l->dc_sia_code == DC_SIA_CODE_10B5)
1636 m->dc_media = IFM_10_5;
1639 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl;
1641 m->dc_next = sc->dc_mi;
1644 sc->dc_pmode = DC_PMODE_SIA;
1649 static void dc_decode_leaf_sym(sc, l)
1650 struct dc_softc *sc;
1651 struct dc_eblock_sym *l;
1653 struct dc_mediainfo *m;
1655 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1656 if (l->dc_sym_code == DC_SYM_CODE_100BT)
1657 m->dc_media = IFM_100_TX;
1659 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1660 m->dc_media = IFM_100_TX|IFM_FDX;
1663 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
1665 m->dc_next = sc->dc_mi;
1668 sc->dc_pmode = DC_PMODE_SYM;
1673 static void dc_decode_leaf_mii(sc, l)
1674 struct dc_softc *sc;
1675 struct dc_eblock_mii *l;
1678 struct dc_mediainfo *m;
1680 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1681 /* We abuse IFM_AUTO to represent MII. */
1682 m->dc_media = IFM_AUTO;
1683 m->dc_gp_len = l->dc_gpr_len;
1686 p += sizeof(struct dc_eblock_mii);
1688 p += 2 * l->dc_gpr_len;
1689 m->dc_reset_len = *p;
1691 m->dc_reset_ptr = p;
1693 m->dc_next = sc->dc_mi;
1699 static void dc_read_srom(sc, bits)
1700 struct dc_softc *sc;
1706 sc->dc_srom = malloc(size, M_DEVBUF, M_INTWAIT);
1707 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1710 static void dc_parse_21143_srom(sc)
1711 struct dc_softc *sc;
1713 struct dc_leaf_hdr *lhdr;
1714 struct dc_eblock_hdr *hdr;
1720 loff = sc->dc_srom[27];
1721 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1724 ptr += sizeof(struct dc_leaf_hdr) - 1;
1726 * Look if we got a MII media block.
1728 for (i = 0; i < lhdr->dc_mcnt; i++) {
1729 hdr = (struct dc_eblock_hdr *)ptr;
1730 if (hdr->dc_type == DC_EBLOCK_MII)
1733 ptr += (hdr->dc_len & 0x7F);
1738 * Do the same thing again. Only use SIA and SYM media
1739 * blocks if no MII media block is available.
1742 ptr += sizeof(struct dc_leaf_hdr) - 1;
1743 for (i = 0; i < lhdr->dc_mcnt; i++) {
1744 hdr = (struct dc_eblock_hdr *)ptr;
1745 switch(hdr->dc_type) {
1747 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1751 dc_decode_leaf_sia(sc,
1752 (struct dc_eblock_sia *)hdr);
1756 dc_decode_leaf_sym(sc,
1757 (struct dc_eblock_sym *)hdr);
1760 /* Don't care. Yet. */
1763 ptr += (hdr->dc_len & 0x7F);
1771 * Attach the interface. Allocate softc structures, do ifmedia
1772 * setup and ethernet/BPF attach.
1774 static int dc_attach(dev)
1778 u_char eaddr[ETHER_ADDR_LEN];
1780 struct dc_softc *sc;
1783 int unit, error = 0, rid, mac_offset;
1787 sc = device_get_softc(dev);
1788 unit = device_get_unit(dev);
1789 bzero(sc, sizeof(struct dc_softc));
1790 callout_init(&sc->dc_stat_timer);
1793 * Handle power management nonsense.
1798 * Map control/status registers.
1800 command = pci_read_config(dev, PCIR_COMMAND, 4);
1801 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1802 pci_write_config(dev, PCIR_COMMAND, command, 4);
1803 command = pci_read_config(dev, PCIR_COMMAND, 4);
1805 #ifdef DC_USEIOSPACE
1806 if (!(command & PCIM_CMD_PORTEN)) {
1807 printf("dc%d: failed to enable I/O ports!\n", unit);
1812 if (!(command & PCIM_CMD_MEMEN)) {
1813 printf("dc%d: failed to enable memory mapping!\n", unit);
1820 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE);
1822 if (sc->dc_res == NULL) {
1823 printf("dc%d: couldn't map ports/memory\n", unit);
1828 sc->dc_btag = rman_get_bustag(sc->dc_res);
1829 sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
1831 /* Allocate interrupt */
1833 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1834 RF_SHAREABLE | RF_ACTIVE);
1836 if (sc->dc_irq == NULL) {
1837 printf("dc%d: couldn't map interrupt\n", unit);
1838 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
1843 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET,
1844 dc_intr, sc, &sc->dc_intrhand, NULL);
1847 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
1848 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
1849 printf("dc%d: couldn't set up irq\n", unit);
1853 /* Need this info to decide on a chip type. */
1854 sc->dc_info = dc_devtype(dev);
1855 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF;
1857 /* Get the eeprom width, but PNIC has diff eeprom */
1858 if (sc->dc_info->dc_did != DC_DEVICEID_82C168)
1859 dc_eeprom_width(sc);
1861 switch(sc->dc_info->dc_did) {
1862 case DC_DEVICEID_21143:
1863 sc->dc_type = DC_TYPE_21143;
1864 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1865 sc->dc_flags |= DC_REDUCED_MII_POLL;
1866 /* Save EEPROM contents so we can parse them later. */
1867 dc_read_srom(sc, sc->dc_romwidth);
1869 case DC_DEVICEID_DM9009:
1870 case DC_DEVICEID_DM9100:
1871 case DC_DEVICEID_DM9102:
1872 sc->dc_type = DC_TYPE_DM9102;
1873 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS;
1874 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD;
1875 sc->dc_pmode = DC_PMODE_MII;
1876 /* Increase the latency timer value. */
1877 command = pci_read_config(dev, DC_PCI_CFLT, 4);
1878 command &= 0xFFFF00FF;
1879 command |= 0x00008000;
1880 pci_write_config(dev, DC_PCI_CFLT, command, 4);
1882 case DC_DEVICEID_AL981:
1883 sc->dc_type = DC_TYPE_AL981;
1884 sc->dc_flags |= DC_TX_USE_TX_INTR;
1885 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1886 sc->dc_pmode = DC_PMODE_MII;
1887 dc_read_srom(sc, sc->dc_romwidth);
1889 case DC_DEVICEID_AN985:
1890 case DC_DEVICEID_EN2242:
1891 case DC_DEVICEID_3CSOHOB:
1892 sc->dc_type = DC_TYPE_AN985;
1893 sc->dc_flags |= DC_64BIT_HASH;
1894 sc->dc_flags |= DC_TX_USE_TX_INTR;
1895 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1896 sc->dc_pmode = DC_PMODE_MII;
1897 dc_read_srom(sc, sc->dc_romwidth);
1899 case DC_DEVICEID_98713:
1900 case DC_DEVICEID_98713_CP:
1901 if (revision < DC_REVISION_98713A) {
1902 sc->dc_type = DC_TYPE_98713;
1904 if (revision >= DC_REVISION_98713A) {
1905 sc->dc_type = DC_TYPE_98713A;
1906 sc->dc_flags |= DC_21143_NWAY;
1908 sc->dc_flags |= DC_REDUCED_MII_POLL;
1909 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1911 case DC_DEVICEID_987x5:
1912 case DC_DEVICEID_EN1217:
1914 * Macronix MX98715AEC-C/D/E parts have only a
1915 * 128-bit hash table. We need to deal with these
1916 * in the same manner as the PNIC II so that we
1917 * get the right number of bits out of the
1920 if (revision >= DC_REVISION_98715AEC_C &&
1921 revision < DC_REVISION_98725)
1922 sc->dc_flags |= DC_128BIT_HASH;
1923 sc->dc_type = DC_TYPE_987x5;
1924 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1925 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1927 case DC_DEVICEID_98727:
1928 sc->dc_type = DC_TYPE_987x5;
1929 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1930 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1932 case DC_DEVICEID_82C115:
1933 sc->dc_type = DC_TYPE_PNICII;
1934 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH;
1935 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1937 case DC_DEVICEID_82C168:
1938 sc->dc_type = DC_TYPE_PNIC;
1939 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS;
1940 sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
1941 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_WAITOK);
1942 if (revision < DC_REVISION_82C169)
1943 sc->dc_pmode = DC_PMODE_SYM;
1945 case DC_DEVICEID_AX88140A:
1946 sc->dc_type = DC_TYPE_ASIX;
1947 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG;
1948 sc->dc_flags |= DC_REDUCED_MII_POLL;
1949 sc->dc_pmode = DC_PMODE_MII;
1951 case DC_DEVICEID_RS7112:
1952 sc->dc_type = DC_TYPE_CONEXANT;
1953 sc->dc_flags |= DC_TX_INTR_ALWAYS;
1954 sc->dc_flags |= DC_REDUCED_MII_POLL;
1955 sc->dc_pmode = DC_PMODE_MII;
1956 dc_read_srom(sc, sc->dc_romwidth);
1959 printf("dc%d: unknown device: %x\n", sc->dc_unit,
1960 sc->dc_info->dc_did);
1964 /* Save the cache line size. */
1965 if (DC_IS_DAVICOM(sc))
1966 sc->dc_cachesize = 0;
1968 sc->dc_cachesize = pci_read_config(dev,
1969 DC_PCI_CFLT, 4) & 0xFF;
1971 /* Reset the adapter. */
1974 /* Take 21143 out of snooze mode */
1975 if (DC_IS_INTEL(sc)) {
1976 command = pci_read_config(dev, DC_PCI_CFDD, 4);
1977 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE);
1978 pci_write_config(dev, DC_PCI_CFDD, command, 4);
1982 * Try to learn something about the supported media.
1983 * We know that ASIX and ADMtek and Davicom devices
1984 * will *always* be using MII media, so that's a no-brainer.
1985 * The tricky ones are the Macronix/PNIC II and the
1988 if (DC_IS_INTEL(sc))
1989 dc_parse_21143_srom(sc);
1990 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
1991 if (sc->dc_type == DC_TYPE_98713)
1992 sc->dc_pmode = DC_PMODE_MII;
1994 sc->dc_pmode = DC_PMODE_SYM;
1995 } else if (!sc->dc_pmode)
1996 sc->dc_pmode = DC_PMODE_MII;
1999 * Get station address from the EEPROM.
2001 switch(sc->dc_type) {
2003 case DC_TYPE_98713A:
2005 case DC_TYPE_PNICII:
2006 dc_read_eeprom(sc, (caddr_t)&mac_offset,
2007 (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2008 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2011 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2013 case DC_TYPE_DM9102:
2016 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2020 bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr,
2022 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0);
2024 case DC_TYPE_CONEXANT:
2025 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6);
2028 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2034 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF,
2035 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
2037 if (sc->dc_ldata == NULL) {
2038 printf("dc%d: no memory for list buffers!\n", unit);
2039 if (sc->dc_pnic_rx_buf != NULL)
2040 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2041 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2042 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2043 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2048 bzero(sc->dc_ldata, sizeof(struct dc_list_data));
2050 ifp = &sc->arpcom.ac_if;
2052 if_initname(ifp, "dc", unit);
2053 ifp->if_mtu = ETHERMTU;
2054 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2055 ifp->if_ioctl = dc_ioctl;
2056 ifp->if_start = dc_start;
2057 ifp->if_watchdog = dc_watchdog;
2058 ifp->if_init = dc_init;
2059 ifp->if_baudrate = 10000000;
2060 ifq_set_maxlen(&ifp->if_snd, DC_TX_LIST_CNT - 1);
2061 ifq_set_ready(&ifp->if_snd);
2064 * Do MII setup. If this is a 21143, check for a PHY on the
2065 * MII bus after applying any necessary fixups to twiddle the
2066 * GPIO bits. If we don't end up finding a PHY, restore the
2067 * old selection (SIA only or SIA/SYM) and attach the dcphy
2070 if (DC_IS_INTEL(sc)) {
2071 dc_apply_fixup(sc, IFM_AUTO);
2073 sc->dc_pmode = DC_PMODE_MII;
2076 error = mii_phy_probe(dev, &sc->dc_miibus,
2077 dc_ifmedia_upd, dc_ifmedia_sts);
2079 if (error && DC_IS_INTEL(sc)) {
2081 if (sc->dc_pmode != DC_PMODE_SIA)
2082 sc->dc_pmode = DC_PMODE_SYM;
2083 sc->dc_flags |= DC_21143_NWAY;
2084 mii_phy_probe(dev, &sc->dc_miibus,
2085 dc_ifmedia_upd, dc_ifmedia_sts);
2087 * For non-MII cards, we need to have the 21143
2088 * drive the LEDs. Except there are some systems
2089 * like the NEC VersaPro NoteBook PC which have no
2090 * LEDs, and twiddling these bits has adverse effects
2091 * on them. (I.e. you suddenly can't get a link.)
2093 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033)
2094 sc->dc_flags |= DC_TULIP_LEDS;
2099 printf("dc%d: MII without any PHY!\n", sc->dc_unit);
2100 contigfree(sc->dc_ldata, sizeof(struct dc_list_data),
2102 if (sc->dc_pnic_rx_buf != NULL)
2103 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2104 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2105 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2106 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2112 * Call MI attach routine.
2114 ether_ifattach(ifp, eaddr);
2116 if (DC_IS_ADMTEK(sc)) {
2118 * Set automatic TX underrun recovery for the ADMtek chips
2120 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2124 * Tell the upper layer(s) we support long frames.
2126 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2134 static int dc_detach(dev)
2137 struct dc_softc *sc;
2140 struct dc_mediainfo *m;
2144 sc = device_get_softc(dev);
2145 ifp = &sc->arpcom.ac_if;
2148 ether_ifdetach(ifp);
2150 bus_generic_detach(dev);
2151 device_delete_child(dev, sc->dc_miibus);
2153 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2154 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2155 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2157 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF);
2158 if (sc->dc_pnic_rx_buf != NULL)
2159 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2161 while(sc->dc_mi != NULL) {
2162 m = sc->dc_mi->dc_next;
2163 free(sc->dc_mi, M_DEVBUF);
2166 free(sc->dc_srom, M_DEVBUF);
2174 * Initialize the transmit descriptors.
2176 static int dc_list_tx_init(sc)
2177 struct dc_softc *sc;
2179 struct dc_chain_data *cd;
2180 struct dc_list_data *ld;
2185 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2186 if (i == (DC_TX_LIST_CNT - 1)) {
2187 ld->dc_tx_list[i].dc_next =
2188 vtophys(&ld->dc_tx_list[0]);
2190 ld->dc_tx_list[i].dc_next =
2191 vtophys(&ld->dc_tx_list[i + 1]);
2193 cd->dc_tx_chain[i] = NULL;
2194 ld->dc_tx_list[i].dc_data = 0;
2195 ld->dc_tx_list[i].dc_ctl = 0;
2198 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2205 * Initialize the RX descriptors and allocate mbufs for them. Note that
2206 * we arrange the descriptors in a closed ring, so that the last descriptor
2207 * points back to the first.
2209 static int dc_list_rx_init(sc)
2210 struct dc_softc *sc;
2212 struct dc_chain_data *cd;
2213 struct dc_list_data *ld;
2219 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2220 if (dc_newbuf(sc, i, NULL) == ENOBUFS)
2222 if (i == (DC_RX_LIST_CNT - 1)) {
2223 ld->dc_rx_list[i].dc_next =
2224 vtophys(&ld->dc_rx_list[0]);
2226 ld->dc_rx_list[i].dc_next =
2227 vtophys(&ld->dc_rx_list[i + 1]);
2237 * Initialize an RX descriptor and attach an MBUF cluster.
2239 static int dc_newbuf(sc, i, m)
2240 struct dc_softc *sc;
2244 struct mbuf *m_new = NULL;
2247 c = &sc->dc_ldata->dc_rx_list[i];
2250 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
2254 MCLGET(m_new, MB_DONTWAIT);
2255 if (!(m_new->m_flags & M_EXT)) {
2259 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2262 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2263 m_new->m_data = m_new->m_ext.ext_buf;
2266 m_adj(m_new, sizeof(u_int64_t));
2269 * If this is a PNIC chip, zero the buffer. This is part
2270 * of the workaround for the receive bug in the 82c168 and
2273 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2274 bzero((char *)mtod(m_new, char *), m_new->m_len);
2276 sc->dc_cdata.dc_rx_chain[i] = m_new;
2277 c->dc_data = vtophys(mtod(m_new, caddr_t));
2278 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN;
2279 c->dc_status = DC_RXSTAT_OWN;
2286 * The PNIC chip has a terrible bug in it that manifests itself during
2287 * periods of heavy activity. The exact mode of failure if difficult to
2288 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2289 * will happen on slow machines. The bug is that sometimes instead of
2290 * uploading one complete frame during reception, it uploads what looks
2291 * like the entire contents of its FIFO memory. The frame we want is at
2292 * the end of the whole mess, but we never know exactly how much data has
2293 * been uploaded, so salvaging the frame is hard.
2295 * There is only one way to do it reliably, and it's disgusting.
2296 * Here's what we know:
2298 * - We know there will always be somewhere between one and three extra
2299 * descriptors uploaded.
2301 * - We know the desired received frame will always be at the end of the
2302 * total data upload.
2304 * - We know the size of the desired received frame because it will be
2305 * provided in the length field of the status word in the last descriptor.
2307 * Here's what we do:
2309 * - When we allocate buffers for the receive ring, we bzero() them.
2310 * This means that we know that the buffer contents should be all
2311 * zeros, except for data uploaded by the chip.
2313 * - We also force the PNIC chip to upload frames that include the
2314 * ethernet CRC at the end.
2316 * - We gather all of the bogus frame data into a single buffer.
2318 * - We then position a pointer at the end of this buffer and scan
2319 * backwards until we encounter the first non-zero byte of data.
2320 * This is the end of the received frame. We know we will encounter
2321 * some data at the end of the frame because the CRC will always be
2322 * there, so even if the sender transmits a packet of all zeros,
2323 * we won't be fooled.
2325 * - We know the size of the actual received frame, so we subtract
2326 * that value from the current pointer location. This brings us
2327 * to the start of the actual received packet.
2329 * - We copy this into an mbuf and pass it on, along with the actual
2332 * The performance hit is tremendous, but it beats dropping frames all
2336 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG)
2337 static void dc_pnic_rx_bug_war(sc, idx)
2338 struct dc_softc *sc;
2341 struct dc_desc *cur_rx;
2342 struct dc_desc *c = NULL;
2343 struct mbuf *m = NULL;
2346 u_int32_t rxstat = 0;
2348 i = sc->dc_pnic_rx_bug_save;
2349 cur_rx = &sc->dc_ldata->dc_rx_list[idx];
2350 ptr = sc->dc_pnic_rx_buf;
2351 bzero(ptr, DC_RXLEN * 5);
2353 /* Copy all the bytes from the bogus buffers. */
2355 c = &sc->dc_ldata->dc_rx_list[i];
2356 rxstat = c->dc_status;
2357 m = sc->dc_cdata.dc_rx_chain[i];
2358 bcopy(mtod(m, char *), ptr, DC_RXLEN);
2360 /* If this is the last buffer, break out. */
2361 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
2363 dc_newbuf(sc, i, m);
2364 DC_INC(i, DC_RX_LIST_CNT);
2367 /* Find the length of the actual receive frame. */
2368 total_len = DC_RXBYTES(rxstat);
2370 /* Scan backwards until we hit a non-zero byte. */
2375 if ((uintptr_t)(ptr) & 0x3)
2378 /* Now find the start of the frame. */
2380 if (ptr < sc->dc_pnic_rx_buf)
2381 ptr = sc->dc_pnic_rx_buf;
2384 * Now copy the salvaged frame to the last mbuf and fake up
2385 * the status word to make it look like a successful
2388 dc_newbuf(sc, i, m);
2389 bcopy(ptr, mtod(m, char *), total_len);
2390 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG;
2396 * This routine searches the RX ring for dirty descriptors in the
2397 * event that the rxeof routine falls out of sync with the chip's
2398 * current descriptor pointer. This may happen sometimes as a result
2399 * of a "no RX buffer available" condition that happens when the chip
2400 * consumes all of the RX buffers before the driver has a chance to
2401 * process the RX ring. This routine may need to be called more than
2402 * once to bring the driver back in sync with the chip, however we
2403 * should still be getting RX DONE interrupts to drive the search
2404 * for new packets in the RX ring, so we should catch up eventually.
2406 static int dc_rx_resync(sc)
2407 struct dc_softc *sc;
2410 struct dc_desc *cur_rx;
2412 pos = sc->dc_cdata.dc_rx_prod;
2414 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2415 cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2416 if (!(cur_rx->dc_status & DC_RXSTAT_OWN))
2418 DC_INC(pos, DC_RX_LIST_CNT);
2421 /* If the ring really is empty, then just return. */
2422 if (i == DC_RX_LIST_CNT)
2425 /* We've fallen behing the chip: catch it. */
2426 sc->dc_cdata.dc_rx_prod = pos;
2432 * A frame has been uploaded: pass the resulting mbuf chain up to
2433 * the higher level protocols.
2435 static void dc_rxeof(sc)
2436 struct dc_softc *sc;
2440 struct dc_desc *cur_rx;
2441 int i, total_len = 0;
2444 ifp = &sc->arpcom.ac_if;
2445 i = sc->dc_cdata.dc_rx_prod;
2447 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) {
2449 #ifdef DEVICE_POLLING
2450 if (ifp->if_flags & IFF_POLLING) {
2451 if (sc->rxcycles <= 0)
2455 #endif /* DEVICE_POLLING */
2456 cur_rx = &sc->dc_ldata->dc_rx_list[i];
2457 rxstat = cur_rx->dc_status;
2458 m = sc->dc_cdata.dc_rx_chain[i];
2459 total_len = DC_RXBYTES(rxstat);
2461 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2462 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2463 if (rxstat & DC_RXSTAT_FIRSTFRAG)
2464 sc->dc_pnic_rx_bug_save = i;
2465 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
2466 DC_INC(i, DC_RX_LIST_CNT);
2469 dc_pnic_rx_bug_war(sc, i);
2470 rxstat = cur_rx->dc_status;
2471 total_len = DC_RXBYTES(rxstat);
2475 sc->dc_cdata.dc_rx_chain[i] = NULL;
2478 * If an error occurs, update stats, clear the
2479 * status word and leave the mbuf cluster in place:
2480 * it should simply get re-used next time this descriptor
2481 * comes up in the ring. However, don't report long
2482 * frames as errors since they could be vlans
2484 if ((rxstat & DC_RXSTAT_RXERR)){
2485 if (!(rxstat & DC_RXSTAT_GIANT) ||
2486 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
2487 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
2488 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) {
2490 if (rxstat & DC_RXSTAT_COLLSEEN)
2491 ifp->if_collisions++;
2492 dc_newbuf(sc, i, m);
2493 if (rxstat & DC_RXSTAT_CRCERR) {
2494 DC_INC(i, DC_RX_LIST_CNT);
2503 /* No errors; receive the packet. */
2504 total_len -= ETHER_CRC_LEN;
2508 * On the x86 we do not have alignment problems, so try to
2509 * allocate a new buffer for the receive ring, and pass up
2510 * the one where the packet is already, saving the expensive
2511 * copy done in m_devget().
2512 * If we are on an architecture with alignment problems, or
2513 * if the allocation fails, then use m_devget and leave the
2514 * existing buffer in the receive ring.
2516 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) {
2517 m->m_pkthdr.rcvif = ifp;
2518 m->m_pkthdr.len = m->m_len = total_len;
2519 DC_INC(i, DC_RX_LIST_CNT);
2525 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
2526 total_len + ETHER_ALIGN, 0, ifp, NULL);
2527 dc_newbuf(sc, i, m);
2528 DC_INC(i, DC_RX_LIST_CNT);
2533 m_adj(m0, ETHER_ALIGN);
2538 (*ifp->if_input)(ifp, m);
2541 sc->dc_cdata.dc_rx_prod = i;
2545 * A frame was downloaded to the chip. It's safe for us to clean up
2551 struct dc_softc *sc;
2553 struct dc_desc *cur_tx = NULL;
2557 ifp = &sc->arpcom.ac_if;
2560 * Go through our tx list and free mbufs for those
2561 * frames that have been transmitted.
2563 idx = sc->dc_cdata.dc_tx_cons;
2564 while(idx != sc->dc_cdata.dc_tx_prod) {
2567 cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2568 txstat = cur_tx->dc_status;
2570 if (txstat & DC_TXSTAT_OWN)
2573 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) ||
2574 cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2575 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2577 * Yes, the PNIC is so brain damaged
2578 * that it will sometimes generate a TX
2579 * underrun error while DMAing the RX
2580 * filter setup frame. If we detect this,
2581 * we have to send the setup frame again,
2582 * or else the filter won't be programmed
2585 if (DC_IS_PNIC(sc)) {
2586 if (txstat & DC_TXSTAT_ERRSUM)
2589 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2591 sc->dc_cdata.dc_tx_cnt--;
2592 DC_INC(idx, DC_TX_LIST_CNT);
2596 if (DC_IS_CONEXANT(sc)) {
2598 * For some reason Conexant chips like
2599 * setting the CARRLOST flag even when
2600 * the carrier is there. In CURRENT we
2601 * have the same problem for Xircom
2604 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2605 sc->dc_pmode == DC_PMODE_MII &&
2606 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2607 DC_TXSTAT_NOCARRIER)))
2608 txstat &= ~DC_TXSTAT_ERRSUM;
2610 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2611 sc->dc_pmode == DC_PMODE_MII &&
2612 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2613 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST)))
2614 txstat &= ~DC_TXSTAT_ERRSUM;
2617 if (txstat & DC_TXSTAT_ERRSUM) {
2619 if (txstat & DC_TXSTAT_EXCESSCOLL)
2620 ifp->if_collisions++;
2621 if (txstat & DC_TXSTAT_LATECOLL)
2622 ifp->if_collisions++;
2623 if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2629 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2632 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
2633 m_freem(sc->dc_cdata.dc_tx_chain[idx]);
2634 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2637 sc->dc_cdata.dc_tx_cnt--;
2638 DC_INC(idx, DC_TX_LIST_CNT);
2641 if (idx != sc->dc_cdata.dc_tx_cons) {
2642 /* some buffers have been freed */
2643 sc->dc_cdata.dc_tx_cons = idx;
2644 ifp->if_flags &= ~IFF_OACTIVE;
2646 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5;
2651 static void dc_tick(xsc)
2654 struct dc_softc *sc;
2655 struct mii_data *mii;
2663 ifp = &sc->arpcom.ac_if;
2664 mii = device_get_softc(sc->dc_miibus);
2666 if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2667 if (sc->dc_flags & DC_21143_NWAY) {
2668 r = CSR_READ_4(sc, DC_10BTSTAT);
2669 if (IFM_SUBTYPE(mii->mii_media_active) ==
2670 IFM_100_TX && (r & DC_TSTAT_LS100)) {
2674 if (IFM_SUBTYPE(mii->mii_media_active) ==
2675 IFM_10_T && (r & DC_TSTAT_LS10)) {
2679 if (sc->dc_link == 0)
2682 r = CSR_READ_4(sc, DC_ISR);
2683 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT &&
2684 sc->dc_cdata.dc_tx_cnt == 0)
2686 if (!(mii->mii_media_status & IFM_ACTIVE))
2693 * When the init routine completes, we expect to be able to send
2694 * packets right away, and in fact the network code will send a
2695 * gratuitous ARP the moment the init routine marks the interface
2696 * as running. However, even though the MAC may have been initialized,
2697 * there may be a delay of a few seconds before the PHY completes
2698 * autonegotiation and the link is brought up. Any transmissions
2699 * made during that delay will be lost. Dealing with this is tricky:
2700 * we can't just pause in the init routine while waiting for the
2701 * PHY to come ready since that would bring the whole system to
2702 * a screeching halt for several seconds.
2704 * What we do here is prevent the TX start routine from sending
2705 * any packets until a link has been established. After the
2706 * interface has been initialized, the tick routine will poll
2707 * the state of the PHY until the IFM_ACTIVE flag is set. Until
2708 * that time, packets will stay in the send queue, and once the
2709 * link comes up, they will be flushed out to the wire.
2713 if (mii->mii_media_status & IFM_ACTIVE &&
2714 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2716 if (!ifq_is_empty(&ifp->if_snd))
2721 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2722 callout_reset(&sc->dc_stat_timer, hz / 10, dc_tick, sc);
2724 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc);
2732 * A transmit underrun has occurred. Back off the transmit threshold,
2733 * or switch to store and forward mode if we have to.
2735 static void dc_tx_underrun(sc)
2736 struct dc_softc *sc;
2741 if (DC_IS_DAVICOM(sc))
2744 if (DC_IS_INTEL(sc)) {
2746 * The real 21143 requires that the transmitter be idle
2747 * in order to change the transmit threshold or store
2748 * and forward state.
2750 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2752 for (i = 0; i < DC_TIMEOUT; i++) {
2753 isr = CSR_READ_4(sc, DC_ISR);
2754 if (isr & DC_ISR_TX_IDLE)
2758 if (i == DC_TIMEOUT) {
2759 printf("dc%d: failed to force tx to idle state\n",
2765 printf("dc%d: TX underrun -- ", sc->dc_unit);
2766 sc->dc_txthresh += DC_TXTHRESH_INC;
2767 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
2768 printf("using store and forward mode\n");
2769 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
2771 printf("increasing TX threshold\n");
2772 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
2773 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
2776 if (DC_IS_INTEL(sc))
2777 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2782 #ifdef DEVICE_POLLING
2783 static poll_handler_t dc_poll;
2786 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2788 struct dc_softc *sc = ifp->if_softc;
2790 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
2791 /* Re-enable interrupts. */
2792 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2795 sc->rxcycles = count;
2798 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd))
2801 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2804 status = CSR_READ_4(sc, DC_ISR);
2805 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF|
2806 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN|
2810 /* ack what we have */
2811 CSR_WRITE_4(sc, DC_ISR, status);
2813 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) {
2814 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
2815 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
2817 if (dc_rx_resync(sc))
2820 /* restart transmit unit if necessary */
2821 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
2822 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2824 if (status & DC_ISR_TX_UNDERRUN)
2827 if (status & DC_ISR_BUS_ERR) {
2828 printf("dc_poll: dc%d bus error\n", sc->dc_unit);
2834 #endif /* DEVICE_POLLING */
2836 static void dc_intr(arg)
2839 struct dc_softc *sc;
2845 if (sc->suspended) {
2849 ifp = &sc->arpcom.ac_if;
2851 #ifdef DEVICE_POLLING
2852 if (ifp->if_flags & IFF_POLLING)
2854 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */
2855 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
2858 #endif /* DEVICE_POLLING */
2860 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
2863 /* Suppress unwanted interrupts */
2864 if (!(ifp->if_flags & IFF_UP)) {
2865 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
2870 /* Disable interrupts. */
2871 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
2873 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) {
2875 CSR_WRITE_4(sc, DC_ISR, status);
2877 if (status & DC_ISR_RX_OK) {
2879 curpkts = ifp->if_ipackets;
2881 if (curpkts == ifp->if_ipackets) {
2882 while(dc_rx_resync(sc))
2887 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF))
2890 if (status & DC_ISR_TX_IDLE) {
2892 if (sc->dc_cdata.dc_tx_cnt) {
2893 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2894 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2898 if (status & DC_ISR_TX_UNDERRUN)
2901 if ((status & DC_ISR_RX_WATDOGTIMEO)
2902 || (status & DC_ISR_RX_NOBUF)) {
2904 curpkts = ifp->if_ipackets;
2906 if (curpkts == ifp->if_ipackets) {
2907 while(dc_rx_resync(sc))
2912 if (status & DC_ISR_BUS_ERR) {
2918 /* Re-enable interrupts. */
2919 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2921 if (!ifq_is_empty(&ifp->if_snd))
2928 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2929 * pointers to the fragment pointers.
2931 static int dc_encap(sc, m_head, txidx)
2932 struct dc_softc *sc;
2933 struct mbuf *m_head;
2936 struct dc_desc *f = NULL;
2938 int frag, cur, cnt = 0;
2941 * Start packing the mbufs in this chain into
2942 * the fragment pointers. Stop when we run out
2943 * of fragments or hit the end of the mbuf chain.
2946 cur = frag = *txidx;
2948 for (m = m_head; m != NULL; m = m->m_next) {
2949 if (m->m_len != 0) {
2950 if (sc->dc_flags & DC_TX_ADMTEK_WAR) {
2951 if (*txidx != sc->dc_cdata.dc_tx_prod &&
2952 frag == (DC_TX_LIST_CNT - 1))
2955 if ((DC_TX_LIST_CNT -
2956 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5)
2959 f = &sc->dc_ldata->dc_tx_list[frag];
2960 f->dc_ctl = DC_TXCTL_TLINK | m->m_len;
2963 f->dc_ctl |= DC_TXCTL_FIRSTFRAG;
2965 f->dc_status = DC_TXSTAT_OWN;
2966 f->dc_data = vtophys(mtod(m, vm_offset_t));
2968 DC_INC(frag, DC_TX_LIST_CNT);
2976 sc->dc_cdata.dc_tx_cnt += cnt;
2977 sc->dc_cdata.dc_tx_chain[cur] = m_head;
2978 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG;
2979 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
2980 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT;
2981 if (sc->dc_flags & DC_TX_INTR_ALWAYS)
2982 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT;
2983 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
2984 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT;
2985 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN;
2992 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2993 * to the mbuf data regions directly in the transmit lists. We also save a
2994 * copy of the pointers since the transmit list fragment pointers are
2995 * physical addresses.
2998 static void dc_start(ifp)
3001 struct dc_softc *sc;
3002 struct mbuf *m_head = NULL, *m_new;
3003 int did_defrag, idx;
3010 if (ifp->if_flags & IFF_OACTIVE)
3013 idx = sc->dc_cdata.dc_tx_prod;
3015 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) {
3017 m_head = ifq_poll(&ifp->if_snd);
3021 if (sc->dc_flags & DC_TX_COALESCE &&
3022 m_head->m_next != NULL) {
3024 * Check first if coalescing allows us to queue
3025 * the packet. We don't want to loose it if
3026 * the TX queue is full.
3028 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) &&
3029 idx != sc->dc_cdata.dc_tx_prod &&
3030 idx == (DC_TX_LIST_CNT - 1)) {
3031 ifp->if_flags |= IFF_OACTIVE;
3034 if ((DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt) < 5) {
3035 ifp->if_flags |= IFF_OACTIVE;
3039 /* only coalesce if have >1 mbufs */
3040 m_new = m_defrag_nofree(m_head, MB_DONTWAIT);
3041 if (m_new == NULL) {
3042 ifp->if_flags |= IFF_OACTIVE;
3050 if (dc_encap(sc, m_head, &idx)) {
3053 m_new = ifq_dequeue(&ifp->if_snd);
3056 ifp->if_flags |= IFF_OACTIVE;
3060 m_new = ifq_dequeue(&ifp->if_snd);
3065 * If there's a BPF listener, bounce a copy of this frame
3068 BPF_MTAP(ifp, m_head);
3070 if (sc->dc_flags & DC_TX_ONE) {
3071 ifp->if_flags |= IFF_OACTIVE;
3077 sc->dc_cdata.dc_tx_prod = idx;
3078 if (!(sc->dc_flags & DC_TX_POLL))
3079 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3082 * Set a timeout in case the chip goes out to lunch.
3089 static void dc_init(xsc)
3092 struct dc_softc *sc = xsc;
3093 struct ifnet *ifp = &sc->arpcom.ac_if;
3094 struct mii_data *mii;
3099 mii = device_get_softc(sc->dc_miibus);
3102 * Cancel pending I/O and free all RX/TX buffers.
3108 * Set cache alignment and burst length.
3110 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
3111 CSR_WRITE_4(sc, DC_BUSCTL, 0);
3113 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE);
3115 * Evenly share the bus between receive and transmit process.
3117 if (DC_IS_INTEL(sc))
3118 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3119 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
3120 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3122 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3124 if (sc->dc_flags & DC_TX_POLL)
3125 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3126 switch(sc->dc_cachesize) {
3128 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3131 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3134 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3138 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3142 if (sc->dc_flags & DC_TX_STORENFWD)
3143 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3145 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3146 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3148 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3149 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3153 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3154 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3156 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
3158 * The app notes for the 98713 and 98715A say that
3159 * in order to have the chips operate properly, a magic
3160 * number must be written to CSR16. Macronix does not
3161 * document the meaning of these bits so there's no way
3162 * to know exactly what they do. The 98713 has a magic
3163 * number all its own; the rest all use a different one.
3165 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3166 if (sc->dc_type == DC_TYPE_98713)
3167 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3169 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3172 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3173 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3175 /* Init circular RX list. */
3176 if (dc_list_rx_init(sc) == ENOBUFS) {
3177 printf("dc%d: initialization failed: no "
3178 "memory for rx buffers\n", sc->dc_unit);
3185 * Init tx descriptors.
3187 dc_list_tx_init(sc);
3190 * Load the address of the RX list.
3192 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0]));
3193 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0]));
3196 * Enable interrupts.
3198 #ifdef DEVICE_POLLING
3200 * ... but only if we are not polling, and make sure they are off in
3201 * the case of polling. Some cards (e.g. fxp) turn interrupts on
3204 if (ifp->if_flags & IFF_POLLING)
3205 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3208 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3209 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3211 /* Enable transmitter. */
3212 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3215 * If this is an Intel 21143 and we're not using the
3216 * MII port, program the LED control pins so we get
3217 * link and activity indications.
3219 if (sc->dc_flags & DC_TULIP_LEDS) {
3220 CSR_WRITE_4(sc, DC_WATCHDOG,
3221 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY);
3222 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3226 * Load the RX/multicast filter. We do this sort of late
3227 * because the filter programming scheme on the 21143 and
3228 * some clones requires DMAing a setup frame via the TX
3229 * engine, and we need the transmitter enabled for that.
3233 /* Enable receiver. */
3234 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3235 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3238 dc_setcfg(sc, sc->dc_if_media);
3240 ifp->if_flags |= IFF_RUNNING;
3241 ifp->if_flags &= ~IFF_OACTIVE;
3245 /* Don't start the ticker if this is a homePNA link. */
3246 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1)
3249 if (sc->dc_flags & DC_21143_NWAY)
3250 callout_reset(&sc->dc_stat_timer, hz/10, dc_tick, sc);
3252 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc);
3259 * Set media options.
3261 static int dc_ifmedia_upd(ifp)
3264 struct dc_softc *sc;
3265 struct mii_data *mii;
3266 struct ifmedia *ifm;
3269 mii = device_get_softc(sc->dc_miibus);
3271 ifm = &mii->mii_media;
3273 if (DC_IS_DAVICOM(sc) &&
3274 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
3275 dc_setcfg(sc, ifm->ifm_media);
3283 * Report current media status.
3285 static void dc_ifmedia_sts(ifp, ifmr)
3287 struct ifmediareq *ifmr;
3289 struct dc_softc *sc;
3290 struct mii_data *mii;
3291 struct ifmedia *ifm;
3294 mii = device_get_softc(sc->dc_miibus);
3296 ifm = &mii->mii_media;
3297 if (DC_IS_DAVICOM(sc)) {
3298 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
3299 ifmr->ifm_active = ifm->ifm_media;
3300 ifmr->ifm_status = 0;
3304 ifmr->ifm_active = mii->mii_media_active;
3305 ifmr->ifm_status = mii->mii_media_status;
3310 static int dc_ioctl(ifp, command, data, cr)
3316 struct dc_softc *sc = ifp->if_softc;
3317 struct ifreq *ifr = (struct ifreq *) data;
3318 struct mii_data *mii;
3327 error = ether_ioctl(ifp, command, data);
3330 if (ifp->if_flags & IFF_UP) {
3331 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3332 (IFF_PROMISC | IFF_ALLMULTI);
3333 if (ifp->if_flags & IFF_RUNNING) {
3337 sc->dc_txthresh = 0;
3341 if (ifp->if_flags & IFF_RUNNING)
3344 sc->dc_if_flags = ifp->if_flags;
3354 mii = device_get_softc(sc->dc_miibus);
3355 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3367 static void dc_watchdog(ifp)
3370 struct dc_softc *sc;
3375 printf("dc%d: watchdog timeout\n", sc->dc_unit);
3381 if (!ifq_is_empty(&ifp->if_snd))
3388 * Stop the adapter and free any mbufs allocated to the
3391 static void dc_stop(sc)
3392 struct dc_softc *sc;
3397 ifp = &sc->arpcom.ac_if;
3400 callout_stop(&sc->dc_stat_timer);
3402 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3403 #ifdef DEVICE_POLLING
3404 ether_poll_deregister(ifp);
3407 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON));
3408 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3409 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3410 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3414 * Free data in the RX lists.
3416 for (i = 0; i < DC_RX_LIST_CNT; i++) {
3417 if (sc->dc_cdata.dc_rx_chain[i] != NULL) {
3418 m_freem(sc->dc_cdata.dc_rx_chain[i]);
3419 sc->dc_cdata.dc_rx_chain[i] = NULL;
3422 bzero((char *)&sc->dc_ldata->dc_rx_list,
3423 sizeof(sc->dc_ldata->dc_rx_list));
3426 * Free the TX list buffers.
3428 for (i = 0; i < DC_TX_LIST_CNT; i++) {
3429 if (sc->dc_cdata.dc_tx_chain[i] != NULL) {
3430 if ((sc->dc_ldata->dc_tx_list[i].dc_ctl &
3432 !(sc->dc_ldata->dc_tx_list[i].dc_ctl &
3433 DC_TXCTL_LASTFRAG)) {
3434 sc->dc_cdata.dc_tx_chain[i] = NULL;
3437 m_freem(sc->dc_cdata.dc_tx_chain[i]);
3438 sc->dc_cdata.dc_tx_chain[i] = NULL;
3442 bzero((char *)&sc->dc_ldata->dc_tx_list,
3443 sizeof(sc->dc_ldata->dc_tx_list));
3449 * Stop all chip I/O so that the kernel's probe routines don't
3450 * get confused by errant DMAs when rebooting.
3452 static void dc_shutdown(dev)
3455 struct dc_softc *sc;
3457 sc = device_get_softc(dev);
3465 * Device suspend routine. Stop the interface and save some PCI
3466 * settings in case the BIOS doesn't restore them properly on
3469 static int dc_suspend(dev)
3474 struct dc_softc *sc;
3478 sc = device_get_softc(dev);
3482 for (i = 0; i < 5; i++)
3483 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
3484 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
3485 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
3486 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3487 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3496 * Device resume routine. Restore some PCI settings in case the BIOS
3497 * doesn't, re-enable busmastering, and restart the interface if
3500 static int dc_resume(dev)
3505 struct dc_softc *sc;
3510 sc = device_get_softc(dev);
3511 ifp = &sc->arpcom.ac_if;
3515 /* better way to do this? */
3516 for (i = 0; i < 5; i++)
3517 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
3518 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
3519 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
3520 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
3521 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
3523 /* reenable busmastering */
3524 pci_enable_busmaster(dev);
3525 pci_enable_io(dev, DC_RES);
3527 /* reinitialize interface if necessary */
3528 if (ifp->if_flags & IFF_UP)