2 * Copyright (c) 1990 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
37 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
38 * $DragonFly: src/sys/i386/isa/Attic/clock.c,v 1.19 2004/09/27 04:04:09 dillon Exp $
42 * Routines to handle clock hardware.
46 * inittodr, settodr and support routines written
47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
54 #include "opt_clock.h"
56 #include <sys/param.h>
57 #include <sys/systm.h>
59 #include <sys/kernel.h>
64 #include <sys/sysctl.h>
66 #include <sys/systimer.h>
67 #include <sys/globaldata.h>
68 #include <sys/thread2.h>
69 #include <sys/systimer.h>
71 #include <machine/clock.h>
72 #ifdef CLK_CALIBRATION_LOOP
74 #include <machine/cputypes.h>
75 #include <machine/frame.h>
76 #include <machine/ipl.h>
77 #include <machine/limits.h>
78 #include <machine/md_var.h>
79 #include <machine/psl.h>
81 #include <machine/segments.h>
83 #if defined(SMP) || defined(APIC_IO)
84 #include <machine/smp.h>
85 #endif /* SMP || APIC_IO */
86 #include <machine/specialreg.h>
88 #include <i386/isa/icu.h>
89 #include <bus/isa/i386/isa.h>
90 #include <bus/isa/rtc.h>
91 #include <i386/isa/timerreg.h>
93 #include <i386/isa/intr_machdep.h>
96 #include <bus/mca/i386/mca_machdep.h>
100 #include <i386/isa/intr_machdep.h>
101 /* The interrupt triggered by the 8254 (timer) chip */
103 static u_long read_intr_count (int vec);
104 static void setup_8254_mixed_mode (void);
106 static void i8254_restore(void);
109 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
110 * can use a simple formula for leap years.
112 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
113 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
116 #define TIMER_FREQ 1193182
120 #define TIMER_SELX TIMER_SEL1
121 #define TIMER_CNTRX TIMER_CNTR1
123 #define TIMER_SELX TIMER_SEL2
124 #define TIMER_CNTRX TIMER_CNTR2
127 int adjkerntz; /* local offset from GMT in seconds */
128 int disable_rtc_set; /* disable resettodr() if != 0 */
129 volatile u_int idelayed;
130 int statclock_disable = 1; /* we don't use the statclock right now */
131 u_int stat_imask = SWI_CLOCK_MASK;
132 u_int cputimer_freq = TIMER_FREQ;
134 int64_t cputimer_freq64_usec = ((int64_t)TIMER_FREQ << 32) / 1000000;
135 int64_t cputimer_freq64_nsec = ((int64_t)TIMER_FREQ << 32) / 1000000000LL;
137 int64_t cputimer_freq64_usec = (1000000LL << 32) / TIMER_FREQ;
138 int64_t cputimer_freq64_nsec = (1000000000LL << 32) / TIMER_FREQ;
141 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
143 enum tstate { RELEASED, ACQUIRED };
144 enum tstate timer0_state;
145 enum tstate timer1_state;
146 enum tstate timer2_state;
148 static int beeping = 0;
149 static u_int clk_imask = HWI_MASK | SWI_MASK;
150 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
151 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
152 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
153 static u_int tsc_present;
155 static struct callout sysbeepstop_ch;
158 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped
159 * counting as of this interrupt. We use timer1 in free-running mode (not
160 * generating any interrupts) as our main counter. Each cpu has timeouts
164 clkintr(struct intrframe frame)
166 static sysclock_t timer1_count;
167 struct globaldata *gd = mycpu;
168 struct globaldata *gscan;
172 * SWSTROBE mode is a one-shot, the timer is no longer running
177 * XXX this could be done more efficiently by using a bitmask?
179 timer1_count = cputimer_count();
180 for (n = 0; n < ncpus; ++n) {
181 gscan = globaldata_find(n);
182 if (gscan->gd_nextclock == 0)
185 lwkt_send_ipiq(gscan, (ipifunc_t)systimer_intr, &timer1_count);
187 systimer_intr(&timer1_count, &frame);
191 /* Reset clock interrupt by asserting bit 7 of port 0x61 */
193 outb(0x61, inb(0x61) | 0x80);
202 acquire_timer2(int mode)
205 if (timer2_state != RELEASED)
207 timer2_state = ACQUIRED;
210 * This access to the timer registers is as atomic as possible
211 * because it is a single instruction. We could do better if we
214 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
217 /* Timer2 is being used for time count operation */
225 if (timer2_state != ACQUIRED)
227 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
228 timer2_state = RELEASED;
233 * This routine receives statistical clock interrupts from the RTC.
234 * As explained above, these occur at 128 interrupts per second.
235 * When profiling, we receive interrupts at a rate of 1024 Hz.
237 * This does not actually add as much overhead as it sounds, because
238 * when the statistical clock is active, the hardclock driver no longer
239 * needs to keep (inaccurate) statistics on its own. This decouples
240 * statistics gathering from scheduling interrupts.
242 * The RTC chip requires that we read status register C (RTC_INTR)
243 * to acknowledge an interrupt, before it will generate the next one.
244 * Under high interrupt load, rtcintr() can be indefinitely delayed and
245 * the clock can tick immediately after the read from RTC_INTR. In this
246 * case, the mc146818A interrupt signal will not drop for long enough
247 * to register with the 8259 PIC. If an interrupt is missed, the stat
248 * clock will halt, considerably degrading system performance. This is
249 * why we use 'while' rather than a more straightforward 'if' below.
250 * Stat clock ticks can still be lost, causing minor loss of accuracy
251 * in the statistics, but the stat clock will no longer stop.
254 rtcintr(struct intrframe frame)
256 while (rtcin(RTC_INTR) & RTCIR_PERIOD)
258 /* statclock(&frame); no longer used */
265 DB_SHOW_COMMAND(rtc, rtc)
267 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
268 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
269 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
270 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
275 * Convert a frequency to a cpu timer count.
278 cputimer_fromhz(int freq)
280 return(cputimer_freq / freq + 1);
284 cputimer_fromus(int us)
286 return((int64_t)cputimer_freq * us / 1000000);
290 * Return the current cpu timer count as a 32 bit integer.
295 static sysclock_t cputimer_base;
296 static __uint16_t cputimer_last;
301 outb(TIMER_MODE, TIMER_SELX | TIMER_LATCH);
302 count = (__uint8_t)inb(TIMER_CNTRX); /* get countdown */
303 count |= ((__uint8_t)inb(TIMER_CNTRX) << 8);
304 count = -count; /* -> countup */
305 if (count < cputimer_last) /* rollover */
306 cputimer_base += 0x00010000;
307 ret = cputimer_base | count;
308 cputimer_last = count;
314 * Reload for the next timeout. It is possible for the reload value
315 * to be 0 or negative, indicating that an immediate timer interrupt
316 * is desired. For now make the minimum 2 ticks.
319 cputimer_intr_reload(sysclock_t reload)
327 if (timer0_running) {
328 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */
329 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */
330 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */
331 if (reload < count) {
332 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
333 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
334 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
339 reload = 0; /* full count */
340 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
341 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
342 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
348 * Wait "n" microseconds.
349 * Relies on timer 1 counting down from (cputimer_freq / hz)
350 * Note: timer had better have been programmed before this is first used!
355 int delta, prev_tick, tick, ticks_left;
360 static int state = 0;
364 for (n1 = 1; n1 <= 10000000; n1 *= 10)
369 printf("DELAY(%d)...", n);
372 * Guard against the timer being uninitialized if we are called
373 * early for console i/o.
375 if (timer0_state == RELEASED)
379 * Read the counter first, so that the rest of the setup overhead is
380 * counted. Guess the initial overhead is 20 usec (on most systems it
381 * takes about 1.5 usec for each of the i/o's in getit(). The loop
382 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The
383 * multiplications and divisions to scale the count take a while).
385 prev_tick = cputimer_count();
386 n -= 0; /* XXX actually guess no initial overhead */
388 * Calculate (n * (cputimer_freq / 1e6)) without using floating point
389 * and without any avoidable overflows.
393 } else if (n < 256) {
395 * Use fixed point to avoid a slow division by 1000000.
396 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest.
397 * 2^15 is the first power of 2 that gives exact results
398 * for n between 0 and 256.
400 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15;
403 * Don't bother using fixed point, although gcc-2.7.2
404 * generates particularly poor code for the long long
405 * division, since even the slow way will complete long
406 * before the delay is up (unless we're interrupted).
408 ticks_left = ((u_int)n * (long long)cputimer_freq + 999999)
412 while (ticks_left > 0) {
413 tick = cputimer_count();
417 delta = tick - prev_tick;
425 printf(" %d calls to getit() at %d usec each\n",
426 getit_calls, (n + 5) / getit_calls);
431 sysbeepstop(void *chan)
433 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
439 sysbeep(int pitch, int period)
441 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
444 * Nobody else is using timer2, we do not need the clock lock
446 outb(TIMER_CNTR2, pitch);
447 outb(TIMER_CNTR2, (pitch>>8));
449 /* enable counter2 output to speaker */
450 outb(IO_PPI, inb(IO_PPI) | 3);
452 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL);
458 * RTC support routines
471 val = inb(IO_RTC + 1);
478 writertc(u_char reg, u_char val)
486 outb(IO_RTC + 1, val);
487 inb(0x84); /* XXX work around wrong order in rtcin() */
494 return(bcd2bin(rtcin(port)));
498 calibrate_clocks(void)
501 u_int count, prev_count, tot_count;
502 int sec, start_sec, timeout;
505 printf("Calibrating clock(s) ... ");
506 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
510 /* Read the mc146818A seconds counter. */
512 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
513 sec = rtcin(RTC_SEC);
520 /* Wait for the mC146818A seconds counter to change. */
523 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
524 sec = rtcin(RTC_SEC);
525 if (sec != start_sec)
532 /* Start keeping track of the i8254 counter. */
533 prev_count = cputimer_count();
539 old_tsc = 0; /* shut up gcc */
542 * Wait for the mc146818A seconds counter to change. Read the i8254
543 * counter for each iteration since this is convenient and only
544 * costs a few usec of inaccuracy. The timing of the final reads
545 * of the counters almost matches the timing of the initial reads,
546 * so the main cause of inaccuracy is the varying latency from
547 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
548 * rtcin(RTC_SEC) that returns a changed seconds count. The
549 * maximum inaccuracy from this cause is < 10 usec on 486's.
553 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
554 sec = rtcin(RTC_SEC);
555 count = cputimer_count();
556 tot_count += (int)(count - prev_count);
558 if (sec != start_sec)
565 * Read the cpu cycle counter. The timing considerations are
566 * similar to those for the i8254 clock.
569 tsc_freq = rdtsc() - old_tsc;
572 printf("TSC clock: %u Hz, ", tsc_freq);
573 printf("i8254 clock: %u Hz\n", tot_count);
577 printf("failed, using default i8254 clock of %u Hz\n", cputimer_freq);
578 return (cputimer_freq);
584 timer0_state = ACQUIRED;
586 timer1_state = ACQUIRED;
588 timer2_state = ACQUIRED;
591 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
592 outb(TIMER_CNTR0, 2); /* lsb */
593 outb(TIMER_CNTR0, 0); /* msb */
594 outb(TIMER_MODE, TIMER_SELX | TIMER_RATEGEN | TIMER_16BIT);
595 outb(TIMER_CNTRX, 0); /* lsb */
596 outb(TIMER_CNTRX, 0); /* msb */
597 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */
604 /* Restore all of the RTC's "status" (actually, control) registers. */
605 writertc(RTC_STATUSB, RTCSB_24HR);
606 writertc(RTC_STATUSA, rtc_statusa);
607 writertc(RTC_STATUSB, rtc_statusb);
611 * Restore all the timers.
613 * This function is called from apm_default_resume() / pmtimer to restore
614 * all the timers. We also have to restore our timebases, especially on
615 * MP systems, because cputimer_count() counter's delta may have grown
616 * too large for nanouptime() and friends to handle.
622 i8254_restore(); /* restore timer_freq and hz */
623 rtc_restore(); /* reenable RTC interrupts */
629 * Initialize 8254 timer 0 early so that it can be used in DELAY().
637 * Can we use the TSC?
639 if (cpu_feature & CPUID_TSC)
645 * Initial RTC state, don't do anything unexpected
647 writertc(RTC_STATUSA, rtc_statusa);
648 writertc(RTC_STATUSB, RTCSB_24HR);
651 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
652 * generate an interrupt, which we will ignore for now.
654 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
655 * (so it counts a full 2^16 and repeats). We will use this timer
659 freq = calibrate_clocks();
660 #ifdef CLK_CALIBRATION_LOOP
663 "Press a key on the console to abort clock calibration\n");
664 while (cncheckc() == -1)
670 * Use the calibrated i8254 frequency if it seems reasonable.
671 * Otherwise use the default, and don't use the calibrated i586
674 delta = freq > cputimer_freq ?
675 freq - cputimer_freq : cputimer_freq - freq;
676 if (delta < cputimer_freq / 100) {
677 #ifndef CLK_USE_I8254_CALIBRATION
680 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
681 freq = cputimer_freq;
683 cputimer_freq = freq;
684 cputimer_freq64_usec = (1000000LL << 32) / freq;
685 cputimer_freq64_nsec = (1000000000LL << 32) / freq;
689 "%d Hz differs from default of %d Hz by more than 1%%\n",
690 freq, cputimer_freq);
694 #ifndef CLK_USE_TSC_CALIBRATION
698 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
702 if (tsc_present && tsc_freq == 0) {
704 * Calibration of the i586 clock relative to the mc146818A
705 * clock failed. Do a less accurate calibration relative
706 * to the i8254 clock.
708 u_int64_t old_tsc = rdtsc();
711 tsc_freq = rdtsc() - old_tsc;
712 #ifdef CLK_USE_TSC_CALIBRATION
714 printf("TSC clock: %u Hz (Method B)\n", tsc_freq);
720 * We can not use the TSC in SMP mode, until we figure out a
721 * cheap (impossible), reliable and precise (yeah right!) way
722 * to synchronize the TSCs of all the CPUs.
723 * Curse Intel for leaving the counter out of the I/O APIC.
728 * We can not use the TSC if we support APM. Precise timekeeping
729 * on an APM'ed machine is at best a fools pursuit, since
730 * any and all of the time spent in various SMM code can't
731 * be reliably accounted for. Reading the RTC is your only
732 * source of reliable time info. The i8254 looses too of course
733 * but we need to have some kind of time...
734 * We don't know at this point whether APM is going to be used
735 * or not, nor when it might be activated. Play it safe.
738 #endif /* NAPM > 0 */
740 #endif /* !defined(SMP) */
744 * Initialize the time of day register, based on the time base which is, e.g.
748 inittodr(time_t base)
750 unsigned long sec, days;
762 /* Look if we have a RTC present and the time is valid */
763 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
766 /* wait for time update to complete */
767 /* If RTCSA_TUP is zero, we have at least 244us before next update */
769 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
775 #ifdef USE_RTC_CENTURY
776 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
778 year = readrtc(RTC_YEAR) + 1900;
786 month = readrtc(RTC_MONTH);
787 for (m = 1; m < month; m++)
788 days += daysinmonth[m-1];
789 if ((month > 2) && LEAPYEAR(year))
791 days += readrtc(RTC_DAY) - 1;
793 for (y = 1970; y < year; y++)
794 days += DAYSPERYEAR + LEAPYEAR(y);
795 sec = ((( days * 24 +
796 readrtc(RTC_HRS)) * 60 +
797 readrtc(RTC_MIN)) * 60 +
799 /* sec now contains the number of seconds, since Jan 1 1970,
800 in the local time zone */
802 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
804 y = time_second - sec;
805 if (y <= -2 || y >= 2) {
806 /* badly off, adjust it */
815 printf("Invalid time in real time clock.\n");
816 printf("Check and reset the date immediately!\n");
820 * Write system time back to RTC
837 /* Disable RTC updates and interrupts. */
838 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
840 /* Calculate local time to put in RTC */
842 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
844 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
845 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
846 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
848 /* We have now the days since 01-01-1970 in tm */
849 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
850 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
852 y++, m = DAYSPERYEAR + LEAPYEAR(y))
855 /* Now we have the years in y and the day-of-the-year in tm */
856 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
857 #ifdef USE_RTC_CENTURY
858 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
864 if (m == 1 && LEAPYEAR(y))
871 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
872 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
874 /* Reenable RTC updates and interrupts. */
875 writertc(RTC_STATUSB, rtc_statusb);
881 * Start both clocks running. DragonFly note: the stat clock is no longer
882 * used. Instead, 8254 based systimers are used for all major clock
883 * interrupts. statclock_disable is set by default.
891 struct intrec *clkdesc;
894 if (statclock_disable) {
896 * The stat interrupt mask is different without the
897 * statistics clock. Also, don't set the interrupt
898 * flag which would normally cause the RTC to generate
901 stat_imask = HWI_MASK | SWI_MASK;
902 rtc_statusb = RTCSB_24HR;
904 /* Setting stathz to nonzero early helps avoid races. */
905 stathz = RTC_NOPROFRATE;
906 profhz = RTC_PROFRATE;
909 /* Finish initializing 8253 timer 0. */
912 apic_8254_intr = isa_apic_irq(0);
914 if (apic_8254_intr >= 0 ) {
915 if (apic_int_type(0, 0) == 3)
918 /* look for ExtInt on pin 0 */
919 if (apic_int_type(0, 0) == 3) {
920 apic_8254_intr = apic_irq(0, 0);
921 setup_8254_mixed_mode();
923 panic("APIC_IO: Cannot route 8254 interrupt to CPU");
926 clkdesc = inthand_add("clk", apic_8254_intr, (inthand2_t *)clkintr,
927 NULL, &clk_imask, INTR_EXCL | INTR_FAST);
928 INTREN(1 << apic_8254_intr);
932 inthand_add("clk", 0, (inthand2_t *)clkintr, NULL, &clk_imask,
933 INTR_EXCL | INTR_FAST);
938 /* Initialize RTC. */
939 writertc(RTC_STATUSA, rtc_statusa);
940 writertc(RTC_STATUSB, RTCSB_24HR);
942 if (statclock_disable == 0) {
943 diag = rtcin(RTC_DIAG);
945 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
948 if (isa_apic_irq(8) != 8)
949 panic("APIC RTC != 8");
952 inthand_add("rtc", 8, (inthand2_t *)rtcintr, NULL, &stat_imask,
953 INTR_EXCL | INTR_FAST);
961 writertc(RTC_STATUSB, rtc_statusb);
965 if (apic_8254_trial) {
967 int lastcnt = read_intr_count(apic_8254_intr);
970 * XXX this assumes the 8254 is the cpu timer. Force an
971 * 8254 Timer0 interrupt and wait 1/100s for it to happen,
972 * then see if we got it.
974 printf("APIC_IO: Testing 8254 interrupt delivery\n");
975 cputimer_intr_reload(2); /* XXX assumes 8254 */
976 base = cputimer_count();
977 while (cputimer_count() - base < cputimer_freq / 100)
979 if (read_intr_count(apic_8254_intr) - lastcnt == 0) {
981 * The MP table is broken.
982 * The 8254 was not connected to the specified pin
984 * Workaround: Limited variant of mixed mode.
986 INTRDIS(1 << apic_8254_intr);
987 inthand_remove(clkdesc);
988 printf("APIC_IO: Broken MP table detected: "
989 "8254 is not connected to "
990 "IOAPIC #%d intpin %d\n",
991 int_to_apicintpin[apic_8254_intr].ioapic,
992 int_to_apicintpin[apic_8254_intr].int_pin);
994 * Revoke current ISA IRQ 0 assignment and
995 * configure a fallback interrupt routing from
996 * the 8254 Timer via the 8259 PIC to the
997 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
998 * We reuse the low level interrupt handler number.
1000 if (apic_irq(0, 0) < 0) {
1001 revoke_apic_irq(apic_8254_intr);
1002 assign_apic_irq(0, 0, apic_8254_intr);
1004 apic_8254_intr = apic_irq(0, 0);
1005 setup_8254_mixed_mode();
1006 inthand_add("clk", apic_8254_intr,
1007 (inthand2_t *)clkintr,
1008 NULL, &clk_imask, INTR_EXCL | INTR_FAST);
1009 INTREN(1 << apic_8254_intr);
1013 if (apic_int_type(0, 0) != 3 ||
1014 int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
1015 int_to_apicintpin[apic_8254_intr].int_pin != 0) {
1016 printf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1017 int_to_apicintpin[apic_8254_intr].ioapic,
1018 int_to_apicintpin[apic_8254_intr].int_pin);
1021 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
1024 callout_init(&sysbeepstop_ch);
1029 read_intr_count(int vec)
1032 up = intr_countp[vec];
1039 setup_8254_mixed_mode()
1042 * Allow 8254 timer to INTerrupt 8259:
1043 * re-initialize master 8259:
1044 * reset; prog 4 bytes, single ICU, edge triggered
1046 outb(IO_ICU1, 0x13);
1047 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */
1048 outb(IO_ICU1 + 1, 0x00); /* ignore slave */
1049 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
1050 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
1052 /* program IO APIC for type 3 INT on INT0 */
1053 if (ext_int_setup(0, 0) < 0)
1054 panic("8254 redirect via APIC pin0 impossible!");
1059 setstatclockrate(int newhz)
1061 if (newhz == RTC_PROFRATE)
1062 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1064 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1065 writertc(RTC_STATUSA, rtc_statusa);
1070 tsc_get_timecount(struct timecounter *tc)
1076 #ifdef KERN_TIMESTAMP
1077 #define KERN_TIMESTAMP_SIZE 16384
1078 static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1079 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1080 sizeof(tsc), "LU", "Kernel timestamps");
1086 tsc[i] = (u_int32_t)rdtsc();
1089 if (i >= KERN_TIMESTAMP_SIZE)
1091 tsc[i] = 0; /* mark last entry */
1093 #endif /* KERN_TIMESTAMP */
1100 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS)
1107 count = cputimer_count();
1113 snprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval);
1114 return(SYSCTL_OUT(req, buf, strlen(buf) + 1));
1117 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254");
1118 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &cputimer_freq, 0, "");
1119 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD,
1120 0, 0, hw_i8254_timestamp, "A", "");