2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.29 2003/12/01 21:06:59 ambrisko Exp $
34 * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.43 2005/08/19 14:41:07 joerg Exp $
39 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
41 * Written by Bill Paul <wpaul@windriver.com>
42 * Senior Engineer, Wind River Systems
46 * The Broadcom BCM5700 is based on technology originally developed by
47 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
48 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
49 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
50 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
51 * frames, highly configurable RX filtering, and 16 RX and TX queues
52 * (which, along with RX filter rules, can be used for QOS applications).
53 * Other features, such as TCP segmentation, may be available as part
54 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
55 * firmware images can be stored in hardware and need not be compiled
58 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
59 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
61 * The BCM5701 is a single-chip solution incorporating both the BCM5700
62 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
63 * does not support external SSRAM.
65 * Broadcom also produces a variation of the BCM5700 under the "Altima"
66 * brand name, which is functionally similar but lacks PCI-X support.
68 * Without external SSRAM, you can only have at most 4 TX rings,
69 * and the use of the mini RX ring is disabled. This seems to imply
70 * that these features are simply not available on the BCM5701. As a
71 * result, this driver does not implement any support for the mini RX
75 #include <sys/param.h>
76 #include <sys/systm.h>
77 #include <sys/sockio.h>
79 #include <sys/malloc.h>
80 #include <sys/kernel.h>
81 #include <sys/socket.h>
82 #include <sys/queue.h>
83 #include <sys/thread2.h>
86 #include <net/ifq_var.h>
87 #include <net/if_arp.h>
88 #include <net/ethernet.h>
89 #include <net/if_dl.h>
90 #include <net/if_media.h>
94 #include <net/if_types.h>
95 #include <net/vlan/if_vlan_var.h>
97 #include <netinet/in_systm.h>
98 #include <netinet/in.h>
99 #include <netinet/ip.h>
101 #include <vm/vm.h> /* for vtophys */
102 #include <vm/pmap.h> /* for vtophys */
103 #include <machine/resource.h>
105 #include <sys/rman.h>
107 #include <dev/netif/mii_layer/mii.h>
108 #include <dev/netif/mii_layer/miivar.h>
109 #include <dev/netif/mii_layer/miidevs.h>
110 #include <dev/netif/mii_layer/brgphyreg.h>
112 #include <bus/pci/pcidevs.h>
113 #include <bus/pci/pcireg.h>
114 #include <bus/pci/pcivar.h>
116 #include "if_bgereg.h"
118 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
120 /* "controller miibus0" required. See GENERIC if you get errors here. */
121 #include "miibus_if.h"
124 * Various supported device vendors/types and their names. Note: the
125 * spec seems to indicate that the hardware still has Alteon's vendor
126 * ID burned into it, though it will always be overriden by the vendor
127 * ID in the EEPROM. Just to be safe, we cover all possibilities.
129 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */
131 static struct bge_type bge_devs[] = {
132 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
133 "Alteon BCM5700 Gigabit Ethernet" },
134 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
135 "Alteon BCM5701 Gigabit Ethernet" },
136 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
137 "Broadcom BCM5700 Gigabit Ethernet" },
138 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
139 "Broadcom BCM5701 Gigabit Ethernet" },
140 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
141 "Broadcom BCM5702X Gigabit Ethernet" },
142 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
143 "Broadcom BCM5702 Gigabit Ethernet" },
144 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
145 "Broadcom BCM5703X Gigabit Ethernet" },
146 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
147 "Broadcom BCM5703 Gigabit Ethernet" },
148 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
149 "Broadcom BCM5704C Dual Gigabit Ethernet" },
150 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
151 "Broadcom BCM5704S Dual Gigabit Ethernet" },
152 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
153 "Broadcom BCM5705 Gigabit Ethernet" },
154 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
155 "Broadcom BCM5705K Gigabit Ethernet" },
156 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
157 "Broadcom BCM5705M Gigabit Ethernet" },
158 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
159 "Broadcom BCM5705M Gigabit Ethernet" },
160 { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5714C,
161 "Broadcom BCM5714C Gigabit Ethernet" },
162 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
163 "Broadcom BCM5721 Gigabit Ethernet" },
164 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
165 "Broadcom BCM5750 Gigabit Ethernet" },
166 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
167 "Broadcom BCM5750M Gigabit Ethernet" },
168 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
169 "Broadcom BCM5751 Gigabit Ethernet" },
170 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
171 "Broadcom BCM5751M Gigabit Ethernet" },
172 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
173 "Broadcom BCM5782 Gigabit Ethernet" },
174 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
175 "Broadcom BCM5788 Gigabit Ethernet" },
176 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
177 "Broadcom BCM5789 Gigabit Ethernet" },
178 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
179 "Broadcom BCM5901 Fast Ethernet" },
180 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
181 "Broadcom BCM5901A2 Fast Ethernet" },
182 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
183 "SysKonnect Gigabit Ethernet" },
184 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
185 "Altima AC1000 Gigabit Ethernet" },
186 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
187 "Altima AC1002 Gigabit Ethernet" },
188 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
189 "Altima AC9100 Gigabit Ethernet" },
193 static int bge_probe(device_t);
194 static int bge_attach(device_t);
195 static int bge_detach(device_t);
196 static void bge_release_resources(struct bge_softc *);
197 static void bge_txeof(struct bge_softc *);
198 static void bge_rxeof(struct bge_softc *);
200 static void bge_tick(void *);
201 static void bge_stats_update(struct bge_softc *);
202 static void bge_stats_update_regs(struct bge_softc *);
203 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *);
205 static void bge_intr(void *);
206 static void bge_start(struct ifnet *);
207 static int bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
208 static void bge_init(void *);
209 static void bge_stop(struct bge_softc *);
210 static void bge_watchdog(struct ifnet *);
211 static void bge_shutdown(device_t);
212 static int bge_ifmedia_upd(struct ifnet *);
213 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
215 static uint8_t bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
216 static int bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
218 static void bge_setmulti(struct bge_softc *);
220 static void bge_handle_events(struct bge_softc *);
221 static int bge_alloc_jumbo_mem(struct bge_softc *);
222 static void bge_free_jumbo_mem(struct bge_softc *);
223 static struct bge_jslot
224 *bge_jalloc(struct bge_softc *);
225 static void bge_jfree(void *);
226 static void bge_jref(void *);
227 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
228 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
229 static int bge_init_rx_ring_std(struct bge_softc *);
230 static void bge_free_rx_ring_std(struct bge_softc *);
231 static int bge_init_rx_ring_jumbo(struct bge_softc *);
232 static void bge_free_rx_ring_jumbo(struct bge_softc *);
233 static void bge_free_tx_ring(struct bge_softc *);
234 static int bge_init_tx_ring(struct bge_softc *);
236 static int bge_chipinit(struct bge_softc *);
237 static int bge_blockinit(struct bge_softc *);
240 static uint8_t bge_vpd_readbyte(struct bge_softc *, uint32_t);
241 static void bge_vpd_read_res(struct bge_softc *, struct vpd_res *, uint32_t);
242 static void bge_vpd_read(struct bge_softc *);
245 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
246 static void bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
248 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
250 static void bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
252 static int bge_miibus_readreg(device_t, int, int);
253 static int bge_miibus_writereg(device_t, int, int, int);
254 static void bge_miibus_statchg(device_t);
256 static void bge_reset(struct bge_softc *);
258 static device_method_t bge_methods[] = {
259 /* Device interface */
260 DEVMETHOD(device_probe, bge_probe),
261 DEVMETHOD(device_attach, bge_attach),
262 DEVMETHOD(device_detach, bge_detach),
263 DEVMETHOD(device_shutdown, bge_shutdown),
266 DEVMETHOD(bus_print_child, bus_generic_print_child),
267 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
270 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
271 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
272 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
277 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
278 static devclass_t bge_devclass;
280 DECLARE_DUMMY_MODULE(if_bge);
281 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
282 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
285 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
287 device_t dev = sc->bge_dev;
289 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
290 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4));
294 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
296 device_t dev = sc->bge_dev;
298 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
299 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
304 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
306 device_t dev = sc->bge_dev;
308 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
309 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
314 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
316 device_t dev = sc->bge_dev;
318 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
319 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
324 bge_vpd_readbyte(struct bge_softc *sc, uint32_t addr)
326 device_t dev = sc->bge_dev;
330 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2);
331 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
333 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG)
337 if (i == BGE_TIMEOUT) {
338 device_printf(sc->bge_dev, "VPD read timed out\n");
342 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4);
344 return((val >> ((addr % 4) * 8)) & 0xFF);
348 bge_vpd_read_res(struct bge_softc *sc, struct vpd_res *res, uint32_t addr)
353 ptr = (uint8_t *)res;
354 for (i = 0; i < sizeof(struct vpd_res); i++)
355 ptr[i] = bge_vpd_readbyte(sc, i + addr);
361 bge_vpd_read(struct bge_softc *sc)
366 if (sc->bge_vpd_prodname != NULL)
367 free(sc->bge_vpd_prodname, M_DEVBUF);
368 if (sc->bge_vpd_readonly != NULL)
369 free(sc->bge_vpd_readonly, M_DEVBUF);
370 sc->bge_vpd_prodname = NULL;
371 sc->bge_vpd_readonly = NULL;
373 bge_vpd_read_res(sc, &res, pos);
375 if (res.vr_id != VPD_RES_ID) {
376 device_printf(sc->bge_dev,
377 "bad VPD resource id: expected %x got %x\n",
378 VPD_RES_ID, res.vr_id);
383 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT);
384 for (i = 0; i < res.vr_len; i++)
385 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos);
386 sc->bge_vpd_prodname[i] = '\0';
389 bge_vpd_read_res(sc, &res, pos);
391 if (res.vr_id != VPD_RES_READ) {
392 device_printf(sc->bge_dev,
393 "bad VPD resource id: expected %x got %x\n",
394 VPD_RES_READ, res.vr_id);
399 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_INTWAIT);
400 for (i = 0; i < res.vr_len + 1; i++)
401 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos);
406 * Read a byte of data stored in the EEPROM at address 'addr.' The
407 * BCM570x supports both the traditional bitbang interface and an
408 * auto access interface for reading the EEPROM. We use the auto
412 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
418 * Enable use of auto EEPROM access so we can avoid
419 * having to use the bitbang method.
421 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
423 /* Reset the EEPROM, load the clock period. */
424 CSR_WRITE_4(sc, BGE_EE_ADDR,
425 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
428 /* Issue the read EEPROM command. */
429 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
431 /* Wait for completion */
432 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
434 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
438 if (i == BGE_TIMEOUT) {
439 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
444 byte = CSR_READ_4(sc, BGE_EE_DATA);
446 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
452 * Read a sequence of bytes from the EEPROM.
455 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
461 for (byte = 0, err = 0, i = 0; i < len; i++) {
462 err = bge_eeprom_getbyte(sc, off + i, &byte);
472 bge_miibus_readreg(device_t dev, int phy, int reg)
474 struct bge_softc *sc;
476 uint32_t val, autopoll;
479 sc = device_get_softc(dev);
480 ifp = &sc->arpcom.ac_if;
483 * Broadcom's own driver always assumes the internal
484 * PHY is at GMII address 1. On some chips, the PHY responds
485 * to accesses at all addresses, which could cause us to
486 * bogusly attach the PHY 32 times at probe type. Always
487 * restricting the lookup to address 1 is simpler than
488 * trying to figure out which chips revisions should be
494 /* Reading with autopolling on may trigger PCI errors */
495 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
496 if (autopoll & BGE_MIMODE_AUTOPOLL) {
497 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
501 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
502 BGE_MIPHY(phy)|BGE_MIREG(reg));
504 for (i = 0; i < BGE_TIMEOUT; i++) {
505 val = CSR_READ_4(sc, BGE_MI_COMM);
506 if (!(val & BGE_MICOMM_BUSY))
510 if (i == BGE_TIMEOUT) {
511 if_printf(ifp, "PHY read timed out\n");
516 val = CSR_READ_4(sc, BGE_MI_COMM);
519 if (autopoll & BGE_MIMODE_AUTOPOLL) {
520 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
524 if (val & BGE_MICOMM_READFAIL)
527 return(val & 0xFFFF);
531 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
533 struct bge_softc *sc;
537 sc = device_get_softc(dev);
539 /* Reading with autopolling on may trigger PCI errors */
540 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
541 if (autopoll & BGE_MIMODE_AUTOPOLL) {
542 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
546 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
547 BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
549 for (i = 0; i < BGE_TIMEOUT; i++) {
550 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
554 if (autopoll & BGE_MIMODE_AUTOPOLL) {
555 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
559 if (i == BGE_TIMEOUT) {
560 if_printf(&sc->arpcom.ac_if, "PHY read timed out\n");
568 bge_miibus_statchg(device_t dev)
570 struct bge_softc *sc;
571 struct mii_data *mii;
573 sc = device_get_softc(dev);
574 mii = device_get_softc(sc->bge_miibus);
576 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
577 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
578 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
580 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
583 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
584 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
586 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
591 * Handle events that have triggered interrupts.
594 bge_handle_events(struct bge_softc *sc)
599 * Memory management for jumbo frames.
602 bge_alloc_jumbo_mem(struct bge_softc *sc)
604 struct bge_jslot *entry;
608 /* Grab a big chunk o' storage. */
609 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF,
610 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
612 if (sc->bge_cdata.bge_jumbo_buf == NULL) {
613 if_printf(&sc->arpcom.ac_if, "no memory for jumbo buffers!\n");
617 SLIST_INIT(&sc->bge_jfree_listhead);
620 * Now divide it up into 9K pieces and save the addresses
621 * in an array. Note that we play an evil trick here by using
622 * the first few bytes in the buffer to hold the the address
623 * of the softc structure for this interface. This is because
624 * bge_jfree() needs it, but it is called by the mbuf management
625 * code which will not pass it to us explicitly.
627 ptr = sc->bge_cdata.bge_jumbo_buf;
628 for (i = 0; i < BGE_JSLOTS; i++) {
629 entry = &sc->bge_cdata.bge_jslots[i];
631 entry->bge_buf = ptr;
632 entry->bge_inuse = 0;
634 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
642 bge_free_jumbo_mem(struct bge_softc *sc)
644 if (sc->bge_cdata.bge_jumbo_buf)
645 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF);
649 * Allocate a jumbo buffer.
651 static struct bge_jslot *
652 bge_jalloc(struct bge_softc *sc)
654 struct bge_jslot *entry;
656 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
659 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
663 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
664 entry->bge_inuse = 1;
669 * Adjust usage count on a jumbo buffer.
674 struct bge_jslot *entry = (struct bge_jslot *)arg;
675 struct bge_softc *sc = entry->bge_sc;
678 panic("bge_jref: can't find softc pointer!");
680 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry)
681 panic("bge_jref: asked to reference buffer "
682 "that we don't manage!");
683 else if (entry->bge_inuse == 0)
684 panic("bge_jref: buffer already free!");
690 * Release a jumbo buffer.
695 struct bge_jslot *entry = (struct bge_jslot *)arg;
696 struct bge_softc *sc = entry->bge_sc;
699 panic("bge_jfree: can't find softc pointer!");
701 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry)
702 panic("bge_jfree: asked to free buffer that we don't manage!");
703 else if (entry->bge_inuse == 0)
704 panic("bge_jfree: buffer already free!");
705 else if (--entry->bge_inuse == 0)
706 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
711 * Intialize a standard receive ring descriptor.
714 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
716 struct mbuf *m_new = NULL;
720 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
723 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
726 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
727 m_new->m_data = m_new->m_ext.ext_buf;
730 if (!sc->bge_rx_alignment_bug)
731 m_adj(m_new, ETHER_ALIGN);
732 sc->bge_cdata.bge_rx_std_chain[i] = m_new;
733 r = &sc->bge_rdata->bge_rx_std_ring[i];
734 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t)));
735 r->bge_flags = BGE_RXBDFLAG_END;
736 r->bge_len = m_new->m_len;
743 * Initialize a jumbo receive ring descriptor. This allocates
744 * a jumbo buffer from the pool managed internally by the driver.
747 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
749 struct mbuf *m_new = NULL;
753 struct bge_jslot *buf;
755 /* Allocate the mbuf. */
756 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
760 /* Allocate the jumbo buffer */
761 buf = bge_jalloc(sc);
764 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
765 "-- packet dropped!\n");
769 /* Attach the buffer to the mbuf. */
770 m_new->m_ext.ext_arg = buf;
771 m_new->m_ext.ext_buf = buf->bge_buf;
772 m_new->m_ext.ext_free = bge_jfree;
773 m_new->m_ext.ext_ref = bge_jref;
774 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
776 m_new->m_data = m_new->m_ext.ext_buf;
777 m_new->m_flags |= M_EXT;
778 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
781 m_new->m_data = m_new->m_ext.ext_buf;
782 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
785 if (!sc->bge_rx_alignment_bug)
786 m_adj(m_new, ETHER_ALIGN);
787 /* Set up the descriptor. */
788 r = &sc->bge_rdata->bge_rx_jumbo_ring[i];
789 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
790 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t)));
791 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
792 r->bge_len = m_new->m_len;
799 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
800 * that's 1MB or memory, which is a lot. For now, we fill only the first
801 * 256 ring entries and hope that our CPU is fast enough to keep up with
805 bge_init_rx_ring_std(struct bge_softc *sc)
809 for (i = 0; i < BGE_SSLOTS; i++) {
810 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
815 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
821 bge_free_rx_ring_std(struct bge_softc *sc)
825 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
826 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
827 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
828 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
830 bzero(&sc->bge_rdata->bge_rx_std_ring[i],
831 sizeof(struct bge_rx_bd));
836 bge_init_rx_ring_jumbo(struct bge_softc *sc)
841 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
842 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
846 sc->bge_jumbo = i - 1;
848 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
849 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
850 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
852 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
858 bge_free_rx_ring_jumbo(struct bge_softc *sc)
862 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
863 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
864 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
865 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
867 bzero(&sc->bge_rdata->bge_rx_jumbo_ring[i],
868 sizeof(struct bge_rx_bd));
873 bge_free_tx_ring(struct bge_softc *sc)
877 if (sc->bge_rdata->bge_tx_ring == NULL)
880 for (i = 0; i < BGE_TX_RING_CNT; i++) {
881 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
882 m_freem(sc->bge_cdata.bge_tx_chain[i]);
883 sc->bge_cdata.bge_tx_chain[i] = NULL;
885 bzero(&sc->bge_rdata->bge_tx_ring[i],
886 sizeof(struct bge_tx_bd));
891 bge_init_tx_ring(struct bge_softc *sc)
894 sc->bge_tx_saved_considx = 0;
896 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
898 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
899 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
901 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
903 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
904 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
910 bge_setmulti(struct bge_softc *sc)
913 struct ifmultiaddr *ifma;
914 uint32_t hashes[4] = { 0, 0, 0, 0 };
917 ifp = &sc->arpcom.ac_if;
919 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
920 for (i = 0; i < 4; i++)
921 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
925 /* First, zot all the existing filters. */
926 for (i = 0; i < 4; i++)
927 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
929 /* Now program new ones. */
930 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
931 if (ifma->ifma_addr->sa_family != AF_LINK)
934 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
935 ETHER_ADDR_LEN) & 0x7f;
936 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
939 for (i = 0; i < 4; i++)
940 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
944 * Do endian, PCI and DMA initialization. Also check the on-board ROM
948 bge_chipinit(struct bge_softc *sc)
953 /* Set endianness before we access any non-PCI registers. */
954 #if BYTE_ORDER == BIG_ENDIAN
955 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
956 BGE_BIGENDIAN_INIT, 4);
958 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
959 BGE_LITTLEENDIAN_INIT, 4);
963 * Check the 'ROM failed' bit on the RX CPU to see if
966 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
967 if_printf(&sc->arpcom.ac_if,
968 "RX CPU self-diagnostics failed!\n");
972 /* Clear the MAC control register */
973 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
976 * Clear the MAC statistics block in the NIC's
979 for (i = BGE_STATS_BLOCK;
980 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
981 BGE_MEMWIN_WRITE(sc, i, 0);
983 for (i = BGE_STATUS_BLOCK;
984 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
985 BGE_MEMWIN_WRITE(sc, i, 0);
987 /* Set up the PCI DMA control register. */
990 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
991 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
992 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
993 } else if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
994 BGE_PCISTATE_PCI_BUSMODE) {
995 /* Conventional PCI bus */
996 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
997 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
998 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1003 * The 5704 uses a different encoding of read/write
1006 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1007 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1008 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1009 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1011 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1012 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1013 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1017 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1018 * for hardware bugs.
1020 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1021 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1024 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1025 if (tmp == 0x6 || tmp == 0x7)
1026 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1030 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1031 sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1032 sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1033 sc->bge_asicrev == BGE_ASICREV_BCM5750)
1034 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1035 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1038 * Set up general mode register.
1040 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME|
1041 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1042 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1043 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM);
1046 * Disable memory write invalidate. Apparently it is not supported
1047 * properly by these devices.
1049 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1051 /* Set the timer prescaler (always 66Mhz) */
1052 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1058 bge_blockinit(struct bge_softc *sc)
1060 struct bge_rcb *rcb;
1061 volatile struct bge_rcb *vrcb;
1065 * Initialize the memory window pointer register so that
1066 * we can access the first 32K of internal NIC RAM. This will
1067 * allow us to set up the TX send ring RCBs and the RX return
1068 * ring RCBs, plus other things which live in NIC memory.
1070 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1072 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1074 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1075 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1076 /* Configure mbuf memory pool */
1077 if (sc->bge_extram) {
1078 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1080 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1081 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1083 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1085 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1087 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1088 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1090 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1093 /* Configure DMA resource pool */
1094 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1095 BGE_DMA_DESCRIPTORS);
1096 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1099 /* Configure mbuf pool watermarks */
1100 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1101 sc->bge_asicrev == BGE_ASICREV_BCM5750) {
1102 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1103 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1105 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1106 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1108 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1110 /* Configure DMA resource watermarks */
1111 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1112 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1114 /* Enable buffer manager */
1115 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1116 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1117 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1118 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1120 /* Poll for buffer manager start indication */
1121 for (i = 0; i < BGE_TIMEOUT; i++) {
1122 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1127 if (i == BGE_TIMEOUT) {
1128 if_printf(&sc->arpcom.ac_if,
1129 "buffer manager failed to start\n");
1134 /* Enable flow-through queues */
1135 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1136 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1138 /* Wait until queue initialization is complete */
1139 for (i = 0; i < BGE_TIMEOUT; i++) {
1140 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1145 if (i == BGE_TIMEOUT) {
1146 if_printf(&sc->arpcom.ac_if,
1147 "flow-through queue init failed\n");
1151 /* Initialize the standard RX ring control block */
1152 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
1153 BGE_HOSTADDR(rcb->bge_hostaddr,
1154 vtophys(&sc->bge_rdata->bge_rx_std_ring));
1155 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1156 sc->bge_asicrev == BGE_ASICREV_BCM5750)
1157 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1159 rcb->bge_maxlen_flags =
1160 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1162 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
1164 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1165 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1166 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1167 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1168 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1171 * Initialize the jumbo RX ring control block
1172 * We set the 'ring disabled' bit in the flags
1173 * field until we're actually ready to start
1174 * using this ring (i.e. once we set the MTU
1175 * high enough to require it).
1177 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1178 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1179 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
1180 BGE_HOSTADDR(rcb->bge_hostaddr,
1181 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring));
1182 rcb->bge_maxlen_flags =
1183 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1184 BGE_RCB_FLAG_RING_DISABLED);
1186 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS;
1188 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1189 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1190 rcb->bge_hostaddr.bge_addr_hi);
1191 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1192 rcb->bge_hostaddr.bge_addr_lo);
1193 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1194 rcb->bge_maxlen_flags);
1195 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1197 /* Set up dummy disabled mini ring RCB */
1198 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
1199 rcb->bge_maxlen_flags =
1200 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1201 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1202 rcb->bge_maxlen_flags);
1206 * Set the BD ring replentish thresholds. The recommended
1207 * values are 1/8th the number of descriptors allocated to
1210 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
1211 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1214 * Disable all unused send rings by setting the 'ring disabled'
1215 * bit in the flags field of all the TX send ring control blocks.
1216 * These are located in NIC memory.
1218 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1220 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1221 vrcb->bge_maxlen_flags =
1222 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1223 vrcb->bge_nicaddr = 0;
1227 /* Configure TX RCB 0 (we use only the first ring) */
1228 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1230 vrcb->bge_hostaddr.bge_addr_hi = 0;
1231 BGE_HOSTADDR(vrcb->bge_hostaddr, vtophys(&sc->bge_rdata->bge_tx_ring));
1232 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT);
1233 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1234 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1235 vrcb->bge_maxlen_flags =
1236 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0);
1238 /* Disable all unused RX return rings */
1239 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1240 BGE_RX_RETURN_RING_RCB);
1241 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1242 vrcb->bge_hostaddr.bge_addr_hi = 0;
1243 vrcb->bge_hostaddr.bge_addr_lo = 0;
1244 vrcb->bge_maxlen_flags =
1245 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1246 BGE_RCB_FLAG_RING_DISABLED);
1247 vrcb->bge_nicaddr = 0;
1248 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1249 (i * (sizeof(uint64_t))), 0);
1253 /* Initialize RX ring indexes */
1254 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1255 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1256 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1259 * Set up RX return ring 0
1260 * Note that the NIC address for RX return rings is 0x00000000.
1261 * The return rings live entirely within the host, so the
1262 * nicaddr field in the RCB isn't used.
1264 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1265 BGE_RX_RETURN_RING_RCB);
1266 vrcb->bge_hostaddr.bge_addr_hi = 0;
1267 BGE_HOSTADDR(vrcb->bge_hostaddr,
1268 vtophys(&sc->bge_rdata->bge_rx_return_ring));
1269 vrcb->bge_nicaddr = 0x00000000;
1270 vrcb->bge_maxlen_flags =
1271 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0);
1273 /* Set random backoff seed for TX */
1274 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1275 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1276 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1277 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1278 BGE_TX_BACKOFF_SEED_MASK);
1280 /* Set inter-packet gap */
1281 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1284 * Specify which ring to use for packets that don't match
1287 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1290 * Configure number of RX lists. One interrupt distribution
1291 * list, sixteen active lists, one bad frames class.
1293 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1295 /* Inialize RX list placement stats mask. */
1296 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1297 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1299 /* Disable host coalescing until we get it set up */
1300 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1302 /* Poll to make sure it's shut down. */
1303 for (i = 0; i < BGE_TIMEOUT; i++) {
1304 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1309 if (i == BGE_TIMEOUT) {
1310 if_printf(&sc->arpcom.ac_if,
1311 "host coalescing engine failed to idle\n");
1315 /* Set up host coalescing defaults */
1316 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1317 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1318 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1319 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1320 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1321 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1322 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1323 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1325 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
1326 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
1328 /* Set up address of statistics block */
1329 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1330 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1331 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0);
1332 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1333 vtophys(&sc->bge_rdata->bge_info.bge_stats));
1335 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1336 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1337 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1340 /* Set up address of status block */
1341 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0);
1342 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1343 vtophys(&sc->bge_rdata->bge_status_block));
1345 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
1346 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;
1348 /* Turn on host coalescing state machine */
1349 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1351 /* Turn on RX BD completion state machine and enable attentions */
1352 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1353 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1355 /* Turn on RX list placement state machine */
1356 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1358 /* Turn on RX list selector state machine. */
1359 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1360 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1361 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1363 /* Turn on DMA, clear stats */
1364 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1365 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1366 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1367 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1368 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1370 /* Set misc. local control, enable interrupts on attentions */
1371 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1374 /* Assert GPIO pins for PHY reset */
1375 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1376 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1377 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1378 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1381 /* Turn on DMA completion state machine */
1382 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1383 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1384 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1386 /* Turn on write DMA state machine */
1387 CSR_WRITE_4(sc, BGE_WDMA_MODE,
1388 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
1390 /* Turn on read DMA state machine */
1391 CSR_WRITE_4(sc, BGE_RDMA_MODE,
1392 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1394 /* Turn on RX data completion state machine */
1395 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1397 /* Turn on RX BD initiator state machine */
1398 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1400 /* Turn on RX data and RX BD initiator state machine */
1401 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1403 /* Turn on Mbuf cluster free state machine */
1404 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1405 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1406 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1408 /* Turn on send BD completion state machine */
1409 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1411 /* Turn on send data completion state machine */
1412 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1414 /* Turn on send data initiator state machine */
1415 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1417 /* Turn on send BD initiator state machine */
1418 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1420 /* Turn on send BD selector state machine */
1421 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1423 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1424 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1425 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1427 /* ack/clear link change events */
1428 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1429 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1430 BGE_MACSTAT_LINK_CHANGED);
1432 /* Enable PHY auto polling (for MII/GMII only) */
1434 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1436 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1437 if (sc->bge_asicrev == BGE_ASICREV_BCM5700)
1438 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1439 BGE_EVTENB_MI_INTERRUPT);
1442 /* Enable link state change attentions. */
1443 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1449 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1450 * against our list and return its name if we find a match. Note
1451 * that since the Broadcom controller contains VPD support, we
1452 * can get the device name string from the controller itself instead
1453 * of the compiled-in string. This is a little slow, but it guarantees
1454 * we'll always announce the right product name.
1457 bge_probe(device_t dev)
1459 struct bge_softc *sc;
1462 uint16_t product, vendor;
1464 product = pci_get_device(dev);
1465 vendor = pci_get_vendor(dev);
1467 for (t = bge_devs; t->bge_name != NULL; t++) {
1468 if (vendor == t->bge_vid && product == t->bge_did)
1472 if (t->bge_name == NULL)
1475 sc = device_get_softc(dev);
1480 device_set_desc(dev, sc->bge_vpd_prodname);
1482 descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_WAITOK);
1483 snprintf(descbuf, BGE_DEVDESC_MAX, "%s, ASIC rev. %#04x", t->bge_name,
1484 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16);
1485 device_set_desc_copy(dev, descbuf);
1486 if (pci_get_subvendor(dev) == PCI_VENDOR_DELL)
1487 sc->bge_no_3_led = 1;
1488 free(descbuf, M_TEMP);
1493 bge_attach(device_t dev)
1496 struct bge_softc *sc;
1498 uint32_t mac_addr = 0;
1500 uint8_t ether_addr[ETHER_ADDR_LEN];
1502 sc = device_get_softc(dev);
1504 callout_init(&sc->bge_stat_timer);
1507 * Map control/status registers.
1509 pci_enable_busmaster(dev);
1512 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1515 if (sc->bge_res == NULL) {
1516 device_printf(dev, "couldn't map memory\n");
1521 sc->bge_btag = rman_get_bustag(sc->bge_res);
1522 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1523 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res);
1525 /* Allocate interrupt */
1528 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1529 RF_SHAREABLE | RF_ACTIVE);
1531 if (sc->bge_irq == NULL) {
1532 device_printf(dev, "couldn't map interrupt\n");
1537 /* Save ASIC rev. */
1539 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1540 BGE_PCIMISCCTL_ASICREV;
1541 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1542 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1545 * Treat the 5714 like the 5750 until we have more info
1548 if (sc->bge_asicrev == BGE_ASICREV_BCM5714)
1549 sc->bge_asicrev = BGE_ASICREV_BCM5750;
1552 * XXX: Broadcom Linux driver. Not in specs or eratta.
1555 if (sc->bge_asicrev == BGE_ASICREV_BCM5750) {
1558 v = pci_read_config(dev, BGE_PCI_MSI_CAPID, 4);
1559 if (((v >> 8) & 0xff) == BGE_PCIE_MSI_CAPID) {
1560 v = pci_read_config(dev, BGE_PCIE_MSI_CAPID, 4);
1561 if ((v & 0xff) == BGE_PCIE_MSI_CAPID_VAL)
1566 ifp = &sc->arpcom.ac_if;
1567 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1569 /* Try to reset the chip. */
1572 if (bge_chipinit(sc)) {
1573 device_printf(dev, "chip initialization failed\n");
1579 * Get station address from the EEPROM.
1581 mac_addr = bge_readmem_ind(sc, 0x0c14);
1582 if ((mac_addr >> 16) == 0x484b) {
1583 ether_addr[0] = (uint8_t)(mac_addr >> 8);
1584 ether_addr[1] = (uint8_t)mac_addr;
1585 mac_addr = bge_readmem_ind(sc, 0x0c18);
1586 ether_addr[2] = (uint8_t)(mac_addr >> 24);
1587 ether_addr[3] = (uint8_t)(mac_addr >> 16);
1588 ether_addr[4] = (uint8_t)(mac_addr >> 8);
1589 ether_addr[5] = (uint8_t)mac_addr;
1590 } else if (bge_read_eeprom(sc, ether_addr,
1591 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1592 device_printf(dev, "failed to read station address\n");
1597 /* Allocate the general information block and ring buffers. */
1598 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF,
1599 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
1601 if (sc->bge_rdata == NULL) {
1603 device_printf(dev, "no memory for list buffers!\n");
1607 bzero(sc->bge_rdata, sizeof(struct bge_ring_data));
1610 * Try to allocate memory for jumbo buffers.
1611 * The 5705/5750 does not appear to support jumbo frames.
1613 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1614 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1615 if (bge_alloc_jumbo_mem(sc)) {
1616 device_printf(dev, "jumbo buffer allocation failed\n");
1622 /* Set default tuneable values. */
1623 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1624 sc->bge_rx_coal_ticks = 150;
1625 sc->bge_tx_coal_ticks = 150;
1626 sc->bge_rx_max_coal_bds = 64;
1627 sc->bge_tx_max_coal_bds = 128;
1629 /* 5705/5750 limits RX return ring to 512 entries. */
1630 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1631 sc->bge_asicrev == BGE_ASICREV_BCM5750)
1632 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1634 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1636 /* Set up ifnet structure */
1638 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1639 ifp->if_ioctl = bge_ioctl;
1640 ifp->if_start = bge_start;
1641 ifp->if_watchdog = bge_watchdog;
1642 ifp->if_init = bge_init;
1643 ifp->if_mtu = ETHERMTU;
1644 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1645 ifq_set_ready(&ifp->if_snd);
1646 ifp->if_hwassist = BGE_CSUM_FEATURES;
1647 ifp->if_capabilities = IFCAP_HWCSUM;
1648 ifp->if_capenable = ifp->if_capabilities;
1651 * Figure out what sort of media we have by checking the
1652 * hardware config word in the first 32k of NIC internal memory,
1653 * or fall back to examining the EEPROM if necessary.
1654 * Note: on some BCM5700 cards, this value appears to be unset.
1655 * If that's the case, we have to rely on identifying the NIC
1656 * by its PCI subsystem ID, as we do below for the SysKonnect
1659 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1660 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1662 bge_read_eeprom(sc, (caddr_t)&hwcfg,
1663 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg));
1664 hwcfg = ntohl(hwcfg);
1667 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1670 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1671 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
1675 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1676 bge_ifmedia_upd, bge_ifmedia_sts);
1677 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1678 ifmedia_add(&sc->bge_ifmedia,
1679 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1680 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1681 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1684 * Do transceiver setup.
1686 if (mii_phy_probe(dev, &sc->bge_miibus,
1687 bge_ifmedia_upd, bge_ifmedia_sts)) {
1688 device_printf(dev, "MII without any PHY!\n");
1695 * When using the BCM5701 in PCI-X mode, data corruption has
1696 * been observed in the first few bytes of some received packets.
1697 * Aligning the packet buffer in memory eliminates the corruption.
1698 * Unfortunately, this misaligns the packet payloads. On platforms
1699 * which do not support unaligned accesses, we will realign the
1700 * payloads by copying the received packets.
1702 switch (sc->bge_chipid) {
1703 case BGE_CHIPID_BCM5701_A0:
1704 case BGE_CHIPID_BCM5701_B0:
1705 case BGE_CHIPID_BCM5701_B2:
1706 case BGE_CHIPID_BCM5701_B5:
1707 /* If in PCI-X mode, work around the alignment bug. */
1708 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
1709 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) ==
1710 BGE_PCISTATE_PCI_BUSSPEED)
1711 sc->bge_rx_alignment_bug = 1;
1716 * Call MI attach routine.
1718 ether_ifattach(ifp, ether_addr);
1720 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET,
1721 bge_intr, sc, &sc->bge_intrhand, NULL);
1723 ether_ifdetach(ifp);
1724 device_printf(dev, "couldn't set up irq\n");
1737 bge_detach(device_t dev)
1739 struct bge_softc *sc = device_get_softc(dev);
1740 struct ifnet *ifp = &sc->arpcom.ac_if;
1744 if (device_is_attached(dev)) {
1745 ether_ifdetach(ifp);
1751 ifmedia_removeall(&sc->bge_ifmedia);
1752 if (sc->bge_miibus);
1753 device_delete_child(dev, sc->bge_miibus);
1754 bus_generic_detach(dev);
1756 bge_release_resources(sc);
1760 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1761 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1762 bge_free_jumbo_mem(sc);
1768 bge_release_resources(struct bge_softc *sc)
1774 if (sc->bge_vpd_prodname != NULL)
1775 free(sc->bge_vpd_prodname, M_DEVBUF);
1777 if (sc->bge_vpd_readonly != NULL)
1778 free(sc->bge_vpd_readonly, M_DEVBUF);
1780 if (sc->bge_intrhand != NULL)
1781 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
1783 if (sc->bge_irq != NULL)
1784 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
1786 if (sc->bge_res != NULL)
1787 bus_release_resource(dev, SYS_RES_MEMORY,
1788 BGE_PCI_BAR0, sc->bge_res);
1790 if (sc->bge_rdata != NULL)
1791 contigfree(sc->bge_rdata, sizeof(struct bge_ring_data),
1798 bge_reset(struct bge_softc *sc)
1801 uint32_t cachesize, command, pcistate, reset;
1806 /* Save some important PCI state. */
1807 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
1808 command = pci_read_config(dev, BGE_PCI_CMD, 4);
1809 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
1811 pci_write_config(dev, BGE_PCI_MISC_CTL,
1812 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1813 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1815 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
1817 /* XXX: Broadcom Linux driver. */
1819 if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */
1820 CSR_WRITE_4(sc, 0x7e2c, 0x20);
1821 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
1822 /* Prevent PCIE link training during global reset */
1823 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
1828 /* Issue global reset */
1829 bge_writereg_ind(sc, BGE_MISC_CFG, reset);
1833 /* XXX: Broadcom Linux driver. */
1835 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
1838 DELAY(500000); /* wait for link training to complete */
1839 v = pci_read_config(dev, 0xc4, 4);
1840 pci_write_config(dev, 0xc4, v | (1<<15), 4);
1842 /* Set PCIE max payload size and clear error status. */
1843 pci_write_config(dev, 0xd8, 0xf5000, 4);
1846 /* Reset some of the PCI state that got zapped by reset */
1847 pci_write_config(dev, BGE_PCI_MISC_CTL,
1848 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1849 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1850 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
1851 pci_write_config(dev, BGE_PCI_CMD, command, 4);
1852 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
1855 * Prevent PXE restart: write a magic number to the
1856 * general communications memory at 0xB50.
1858 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1860 * Poll the value location we just wrote until
1861 * we see the 1's complement of the magic number.
1862 * This indicates that the firmware initialization
1865 for (i = 0; i < BGE_TIMEOUT; i++) {
1866 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
1867 if (val == ~BGE_MAGIC_NUMBER)
1872 if (i == BGE_TIMEOUT) {
1873 if_printf(&sc->arpcom.ac_if, "firmware handshake timed out\n");
1878 * XXX Wait for the value of the PCISTATE register to
1879 * return to its original pre-reset state. This is a
1880 * fairly good indicator of reset completion. If we don't
1881 * wait for the reset to fully complete, trying to read
1882 * from the device's non-PCI registers may yield garbage
1885 for (i = 0; i < BGE_TIMEOUT; i++) {
1886 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
1891 /* Enable memory arbiter. */
1892 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1893 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1894 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
1896 /* Fix up byte swapping */
1897 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME|
1898 BGE_MODECTL_BYTESWAP_DATA);
1900 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1902 /* XXX: Broadcom Linux driver. */
1903 if (sc->bge_pcie && sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
1906 v = CSR_READ_4(sc, 0x7c00);
1907 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
1914 * Frame reception handling. This is called if there's a frame
1915 * on the receive return list.
1917 * Note: we have to be able to handle two possibilities here:
1918 * 1) the frame is from the jumbo recieve ring
1919 * 2) the frame is from the standard receive ring
1923 bge_rxeof(struct bge_softc *sc)
1926 int stdcnt = 0, jumbocnt = 0;
1928 ifp = &sc->arpcom.ac_if;
1930 while(sc->bge_rx_saved_considx !=
1931 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) {
1932 struct bge_rx_bd *cur_rx;
1934 struct mbuf *m = NULL;
1935 uint16_t vlan_tag = 0;
1939 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx];
1941 rxidx = cur_rx->bge_idx;
1942 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
1944 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
1946 vlan_tag = cur_rx->bge_vlan_tag;
1949 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
1950 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1951 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
1952 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
1954 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
1956 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
1959 if (bge_newbuf_jumbo(sc,
1960 sc->bge_jumbo, NULL) == ENOBUFS) {
1962 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
1966 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1967 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
1968 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
1970 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
1972 bge_newbuf_std(sc, sc->bge_std, m);
1975 if (bge_newbuf_std(sc, sc->bge_std,
1978 bge_newbuf_std(sc, sc->bge_std, m);
1986 * The i386 allows unaligned accesses, but for other
1987 * platforms we must make sure the payload is aligned.
1989 if (sc->bge_rx_alignment_bug) {
1990 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
1992 m->m_data += ETHER_ALIGN;
1995 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
1996 m->m_pkthdr.rcvif = ifp;
1998 #if 0 /* currently broken for some packets, possibly related to TCP options */
1999 if (ifp->if_hwassist) {
2000 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2001 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2002 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2003 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2004 m->m_pkthdr.csum_data =
2005 cur_rx->bge_tcp_udp_csum;
2006 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
2012 * If we received a packet with a vlan tag, pass it
2013 * to vlan_input() instead of ether_input().
2016 VLAN_INPUT_TAG(m, vlan_tag);
2017 have_tag = vlan_tag = 0;
2021 (*ifp->if_input)(ifp, m);
2024 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2026 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2028 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2032 bge_txeof(struct bge_softc *sc)
2034 struct bge_tx_bd *cur_tx = NULL;
2037 ifp = &sc->arpcom.ac_if;
2040 * Go through our tx ring and free mbufs for those
2041 * frames that have been sent.
2043 while (sc->bge_tx_saved_considx !=
2044 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) {
2047 idx = sc->bge_tx_saved_considx;
2048 cur_tx = &sc->bge_rdata->bge_tx_ring[idx];
2049 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2051 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2052 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2053 sc->bge_cdata.bge_tx_chain[idx] = NULL;
2056 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2061 ifp->if_flags &= ~IFF_OACTIVE;
2067 struct bge_softc *sc = xsc;
2068 struct ifnet *ifp = &sc->arpcom.ac_if;
2069 uint32_t status, statusword;
2072 statusword = loadandclear(&sc->bge_rdata->bge_status_block.bge_status);
2075 /* Avoid this for now -- checking this register is expensive. */
2076 /* Make sure this is really our interrupt. */
2077 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE))
2080 /* Ack interrupt and stop others from occuring. */
2081 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2084 * Process link state changes.
2085 * Grrr. The link status word in the status block does
2086 * not work correctly on the BCM5700 rev AX and BX chips,
2087 * according to all available information. Hence, we have
2088 * to enable MII interrupts in order to properly obtain
2089 * async link changes. Unfortunately, this also means that
2090 * we have to read the MAC status register to detect link
2091 * changes, thereby adding an additional register access to
2092 * the interrupt handler.
2095 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) {
2096 status = CSR_READ_4(sc, BGE_MAC_STS);
2097 if (status & BGE_MACSTAT_MI_INTERRUPT) {
2099 callout_stop(&sc->bge_stat_timer);
2101 /* Clear the interrupt */
2102 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2103 BGE_EVTENB_MI_INTERRUPT);
2104 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
2105 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
2109 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) {
2111 * Sometimes PCS encoding errors are detected in
2112 * TBI mode (on fiber NICs), and for some reason
2113 * the chip will signal them as link changes.
2114 * If we get a link change event, but the 'PCS
2115 * encoding error' bit in the MAC status register
2116 * is set, don't bother doing a link check.
2117 * This avoids spurious "gigabit link up" messages
2118 * that sometimes appear on fiber NICs during
2119 * periods of heavy traffic. (There should be no
2120 * effect on copper NICs.)
2122 status = CSR_READ_4(sc, BGE_MAC_STS);
2123 if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR|
2124 BGE_MACSTAT_MI_COMPLETE))) {
2126 callout_stop(&sc->bge_stat_timer);
2130 callout_stop(&sc->bge_stat_timer);
2132 /* Clear the interrupt */
2133 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
2134 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
2135 BGE_MACSTAT_LINK_CHANGED);
2137 /* Force flush the status block cached by PCI bridge */
2138 CSR_READ_4(sc, BGE_MBX_IRQ0_LO);
2142 if (ifp->if_flags & IFF_RUNNING) {
2143 /* Check RX return ring producer/consumer */
2146 /* Check TX ring producer/consumer */
2150 bge_handle_events(sc);
2152 /* Re-enable interrupts. */
2153 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2155 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
2156 (*ifp->if_start)(ifp);
2162 struct bge_softc *sc = xsc;
2163 struct ifnet *ifp = &sc->arpcom.ac_if;
2164 struct mii_data *mii = NULL;
2165 struct ifmedia *ifm = NULL;
2169 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
2170 sc->bge_asicrev == BGE_ASICREV_BCM5750)
2171 bge_stats_update_regs(sc);
2173 bge_stats_update(sc);
2175 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2183 ifm = &sc->bge_ifmedia;
2184 if (CSR_READ_4(sc, BGE_MAC_STS) &
2185 BGE_MACSTAT_TBI_PCS_SYNCHED) {
2187 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
2188 if_printf(ifp, "gigabit link up\n");
2189 if (!ifq_is_empty(&ifp->if_snd))
2190 (*ifp->if_start)(ifp);
2196 mii = device_get_softc(sc->bge_miibus);
2199 if (!sc->bge_link) {
2201 if (mii->mii_media_status & IFM_ACTIVE &&
2202 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2204 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
2205 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
2206 if_printf(ifp, "gigabit link up\n");
2207 if (!ifq_is_empty(&ifp->if_snd))
2208 (*ifp->if_start)(ifp);
2216 bge_stats_update_regs(struct bge_softc *sc)
2218 struct ifnet *ifp = &sc->arpcom.ac_if;
2219 struct bge_mac_stats_regs stats;
2223 s = (uint32_t *)&stats;
2224 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2225 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2229 ifp->if_collisions +=
2230 (stats.dot3StatsSingleCollisionFrames +
2231 stats.dot3StatsMultipleCollisionFrames +
2232 stats.dot3StatsExcessiveCollisions +
2233 stats.dot3StatsLateCollisions) -
2238 bge_stats_update(struct bge_softc *sc)
2240 struct ifnet *ifp = &sc->arpcom.ac_if;
2241 struct bge_stats *stats;
2243 stats = (struct bge_stats *)(sc->bge_vhandle +
2244 BGE_MEMWIN_START + BGE_STATS_BLOCK);
2246 ifp->if_collisions +=
2247 (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo +
2248 stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo +
2249 stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo +
2250 stats->txstats.dot3StatsLateCollisions.bge_addr_lo) -
2254 ifp->if_collisions +=
2255 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2256 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2257 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2258 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2264 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2265 * pointers to descriptors.
2268 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
2270 struct bge_tx_bd *f = NULL;
2272 uint32_t frag, cur, cnt = 0;
2273 uint16_t csum_flags = 0;
2274 struct ifvlan *ifv = NULL;
2276 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2277 m_head->m_pkthdr.rcvif != NULL &&
2278 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2279 ifv = m_head->m_pkthdr.rcvif->if_softc;
2282 cur = frag = *txidx;
2284 if (m_head->m_pkthdr.csum_flags) {
2285 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2286 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2287 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2288 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2289 if (m_head->m_flags & M_LASTFRAG)
2290 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2291 else if (m_head->m_flags & M_FRAG)
2292 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2295 * Start packing the mbufs in this chain into
2296 * the fragment pointers. Stop when we run out
2297 * of fragments or hit the end of the mbuf chain.
2299 for (m = m_head; m != NULL; m = m->m_next) {
2300 if (m->m_len != 0) {
2301 f = &sc->bge_rdata->bge_tx_ring[frag];
2302 if (sc->bge_cdata.bge_tx_chain[frag] != NULL)
2304 BGE_HOSTADDR(f->bge_addr,
2305 vtophys(mtod(m, vm_offset_t)));
2306 f->bge_len = m->m_len;
2307 f->bge_flags = csum_flags;
2309 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2310 f->bge_vlan_tag = ifv->ifv_tag;
2312 f->bge_vlan_tag = 0;
2315 * Sanity check: avoid coming within 16 descriptors
2316 * of the end of the ring.
2318 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16)
2321 BGE_INC(frag, BGE_TX_RING_CNT);
2329 if (frag == sc->bge_tx_saved_considx)
2332 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END;
2333 sc->bge_cdata.bge_tx_chain[cur] = m_head;
2334 sc->bge_txcnt += cnt;
2342 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2343 * to the mbuf data regions directly in the transmit descriptors.
2346 bge_start(struct ifnet *ifp)
2348 struct bge_softc *sc;
2349 struct mbuf *m_head = NULL;
2350 uint32_t prodidx = 0;
2357 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO);
2359 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2360 m_head = ifq_poll(&ifp->if_snd);
2366 * safety overkill. If this is a fragmented packet chain
2367 * with delayed TCP/UDP checksums, then only encapsulate
2368 * it if we have enough descriptors to handle the entire
2370 * (paranoia -- may not actually be needed)
2372 if (m_head->m_flags & M_FIRSTFRAG &&
2373 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2374 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2375 m_head->m_pkthdr.csum_data + 16) {
2376 ifp->if_flags |= IFF_OACTIVE;
2382 * Pack the data into the transmit ring. If we
2383 * don't have room, set the OACTIVE flag and wait
2384 * for the NIC to drain the ring.
2386 if (bge_encap(sc, m_head, &prodidx)) {
2387 ifp->if_flags |= IFF_OACTIVE;
2390 m_head = ifq_dequeue(&ifp->if_snd);
2392 BPF_MTAP(ifp, m_head);
2396 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2397 /* 5700 b2 errata */
2398 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2399 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2402 * Set a timeout in case the chip goes out to lunch.
2410 struct bge_softc *sc = xsc;
2411 struct ifnet *ifp = &sc->arpcom.ac_if;
2416 if (ifp->if_flags & IFF_RUNNING) {
2421 /* Cancel pending I/O and flush buffers. */
2427 * Init the various state machines, ring
2428 * control blocks and firmware.
2430 if (bge_blockinit(sc)) {
2431 if_printf(ifp, "initialization failure\n");
2437 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2438 ETHER_HDR_LEN + ETHER_CRC_LEN);
2440 /* Load our MAC address. */
2441 m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2442 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2443 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2445 /* Enable or disable promiscuous mode as needed. */
2446 if (ifp->if_flags & IFF_PROMISC) {
2447 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2449 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2452 /* Program multicast filter. */
2456 bge_init_rx_ring_std(sc);
2459 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2460 * memory to insure that the chip has in fact read the first
2461 * entry of the ring.
2463 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
2465 for (i = 0; i < 10; i++) {
2467 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
2468 if (v == (MCLBYTES - ETHER_ALIGN))
2472 if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
2475 /* Init jumbo RX ring. */
2476 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2477 bge_init_rx_ring_jumbo(sc);
2479 /* Init our RX return ring index */
2480 sc->bge_rx_saved_considx = 0;
2483 bge_init_tx_ring(sc);
2485 /* Turn on transmitter */
2486 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2488 /* Turn on receiver */
2489 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2491 /* Tell firmware we're alive. */
2492 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2494 /* Enable host interrupts. */
2495 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2496 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2497 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2499 bge_ifmedia_upd(ifp);
2501 ifp->if_flags |= IFF_RUNNING;
2502 ifp->if_flags &= ~IFF_OACTIVE;
2504 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2510 * Set media options.
2513 bge_ifmedia_upd(struct ifnet *ifp)
2515 struct bge_softc *sc = ifp->if_softc;
2516 struct ifmedia *ifm = &sc->bge_ifmedia;
2517 struct mii_data *mii;
2519 /* If this is a 1000baseX NIC, enable the TBI port. */
2521 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2523 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2527 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2528 BGE_CLRBIT(sc, BGE_MAC_MODE,
2529 BGE_MACMODE_HALF_DUPLEX);
2531 BGE_SETBIT(sc, BGE_MAC_MODE,
2532 BGE_MACMODE_HALF_DUPLEX);
2541 mii = device_get_softc(sc->bge_miibus);
2543 if (mii->mii_instance) {
2544 struct mii_softc *miisc;
2545 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
2546 miisc = LIST_NEXT(miisc, mii_list))
2547 mii_phy_reset(miisc);
2555 * Report current media status.
2558 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2560 struct bge_softc *sc = ifp->if_softc;
2561 struct mii_data *mii;
2564 ifmr->ifm_status = IFM_AVALID;
2565 ifmr->ifm_active = IFM_ETHER;
2566 if (CSR_READ_4(sc, BGE_MAC_STS) &
2567 BGE_MACSTAT_TBI_PCS_SYNCHED)
2568 ifmr->ifm_status |= IFM_ACTIVE;
2569 ifmr->ifm_active |= IFM_1000_SX;
2570 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
2571 ifmr->ifm_active |= IFM_HDX;
2573 ifmr->ifm_active |= IFM_FDX;
2577 mii = device_get_softc(sc->bge_miibus);
2579 ifmr->ifm_active = mii->mii_media_active;
2580 ifmr->ifm_status = mii->mii_media_status;
2584 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2586 struct bge_softc *sc = ifp->if_softc;
2587 struct ifreq *ifr = (struct ifreq *) data;
2588 int mask, error = 0;
2589 struct mii_data *mii;
2595 /* Disallow jumbo frames on 5705/5750. */
2596 if (((sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
2597 sc->bge_asicrev == BGE_ASICREV_BCM5750) &&
2598 ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU)
2601 ifp->if_mtu = ifr->ifr_mtu;
2602 ifp->if_flags &= ~IFF_RUNNING;
2607 if (ifp->if_flags & IFF_UP) {
2609 * If only the state of the PROMISC flag changed,
2610 * then just use the 'set promisc mode' command
2611 * instead of reinitializing the entire NIC. Doing
2612 * a full re-init means reloading the firmware and
2613 * waiting for it to start up, which may take a
2616 if (ifp->if_flags & IFF_RUNNING &&
2617 ifp->if_flags & IFF_PROMISC &&
2618 !(sc->bge_if_flags & IFF_PROMISC)) {
2619 BGE_SETBIT(sc, BGE_RX_MODE,
2620 BGE_RXMODE_RX_PROMISC);
2621 } else if (ifp->if_flags & IFF_RUNNING &&
2622 !(ifp->if_flags & IFF_PROMISC) &&
2623 sc->bge_if_flags & IFF_PROMISC) {
2624 BGE_CLRBIT(sc, BGE_RX_MODE,
2625 BGE_RXMODE_RX_PROMISC);
2629 if (ifp->if_flags & IFF_RUNNING) {
2633 sc->bge_if_flags = ifp->if_flags;
2638 if (ifp->if_flags & IFF_RUNNING) {
2646 error = ifmedia_ioctl(ifp, ifr,
2647 &sc->bge_ifmedia, command);
2649 mii = device_get_softc(sc->bge_miibus);
2650 error = ifmedia_ioctl(ifp, ifr,
2651 &mii->mii_media, command);
2655 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2656 if (mask & IFCAP_HWCSUM) {
2657 if (IFCAP_HWCSUM & ifp->if_capenable)
2658 ifp->if_capenable &= ~IFCAP_HWCSUM;
2660 ifp->if_capenable |= IFCAP_HWCSUM;
2665 error = ether_ioctl(ifp, command, data);
2675 bge_watchdog(struct ifnet *ifp)
2677 struct bge_softc *sc = ifp->if_softc;
2679 if_printf(ifp, "watchdog timeout -- resetting\n");
2681 ifp->if_flags &= ~IFF_RUNNING;
2688 * Stop the adapter and free any mbufs allocated to the
2692 bge_stop(struct bge_softc *sc)
2694 struct ifnet *ifp = &sc->arpcom.ac_if;
2695 struct ifmedia_entry *ifm;
2696 struct mii_data *mii = NULL;
2700 mii = device_get_softc(sc->bge_miibus);
2702 callout_stop(&sc->bge_stat_timer);
2705 * Disable all of the receiver blocks
2707 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2708 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2709 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2710 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2711 sc->bge_asicrev != BGE_ASICREV_BCM5750)
2712 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2713 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
2714 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2715 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
2718 * Disable all of the transmit blocks
2720 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2721 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2722 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2723 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
2724 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
2725 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2726 sc->bge_asicrev != BGE_ASICREV_BCM5750)
2727 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2728 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2731 * Shut down all of the memory managers and related
2734 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
2735 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
2736 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2737 sc->bge_asicrev != BGE_ASICREV_BCM5750)
2738 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2739 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2740 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2741 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2742 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
2743 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
2744 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2747 /* Disable host interrupts. */
2748 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2749 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2752 * Tell firmware we're shutting down.
2754 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2756 /* Free the RX lists. */
2757 bge_free_rx_ring_std(sc);
2759 /* Free jumbo RX list. */
2760 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2761 sc->bge_asicrev != BGE_ASICREV_BCM5750)
2762 bge_free_rx_ring_jumbo(sc);
2764 /* Free TX buffers. */
2765 bge_free_tx_ring(sc);
2768 * Isolate/power down the PHY, but leave the media selection
2769 * unchanged so that things will be put back to normal when
2770 * we bring the interface back up.
2773 itmp = ifp->if_flags;
2774 ifp->if_flags |= IFF_UP;
2775 ifm = mii->mii_media.ifm_cur;
2776 mtmp = ifm->ifm_media;
2777 ifm->ifm_media = IFM_ETHER|IFM_NONE;
2779 ifm->ifm_media = mtmp;
2780 ifp->if_flags = itmp;
2785 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
2787 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2791 * Stop all chip I/O so that the kernel's probe routines don't
2792 * get confused by errant DMAs when rebooting.
2795 bge_shutdown(device_t dev)
2797 struct bge_softc *sc = device_get_softc(dev);