sys/dev/netif/bge/if_bge.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  */
  35
  36 /*
  37  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  38  *
  39  * Written by Bill Paul <wpaul@windriver.com>
  40  * Senior Engineer, Wind River Systems
  41  */
  42
  43 /*
  44  * The Broadcom BCM5700 is based on technology originally developed by
  45  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  46  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  47  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  48  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  49  * frames, highly configurable RX filtering, and 16 RX and TX queues
  50  * (which, along with RX filter rules, can be used for QOS applications).
  51  * Other features, such as TCP segmentation, may be available as part
  52  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  53  * firmware images can be stored in hardware and need not be compiled
  54  * into the driver.
  55  *
  56  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  57  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  58  *
  59  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  60  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  61  * does not support external SSRAM.
  62  *
  63  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  64  * brand name, which is functionally similar but lacks PCI-X support.
  65  *
  66  * Without external SSRAM, you can only have at most 4 TX rings,
  67  * and the use of the mini RX ring is disabled. This seems to imply
  68  * that these features are simply not available on the BCM5701. As a
  69  * result, this driver does not implement any support for the mini RX
  70  * ring.
  71  */
  72
  73 #include "opt_polling.h"
  74
  75 #include <sys/param.h>
  76 #include <sys/bus.h>
  77 #include <sys/endian.h>
  78 #include <sys/kernel.h>
  79 #include <sys/ktr.h>
  80 #include <sys/interrupt.h>
  81 #include <sys/mbuf.h>
  82 #include <sys/malloc.h>
  83 #include <sys/queue.h>
  84 #include <sys/rman.h>
  85 #include <sys/serialize.h>
  86 #include <sys/socket.h>
  87 #include <sys/sockio.h>
  88 #include <sys/sysctl.h>
  89
  90 #include <net/bpf.h>
  91 #include <net/ethernet.h>
  92 #include <net/if.h>
  93 #include <net/if_arp.h>
  94 #include <net/if_dl.h>
  95 #include <net/if_media.h>
  96 #include <net/if_types.h>
  97 #include <net/ifq_var.h>
  98 #include <net/vlan/if_vlan_var.h>
  99 #include <net/vlan/if_vlan_ether.h>
 100
 101 #include <dev/netif/mii_layer/mii.h>
 102 #include <dev/netif/mii_layer/miivar.h>
 103 #include <dev/netif/mii_layer/brgphyreg.h>
 104
 105 #include <bus/pci/pcidevs.h>
 106 #include <bus/pci/pcireg.h>
 107 #include <bus/pci/pcivar.h>
 108
 109 #include <dev/netif/bge/if_bgereg.h>
 110
 111 /* "device miibus" required.  See GENERIC if you get errors here. */
 112 #include "miibus_if.h"
 113
 114 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 115 #define BGE_MIN_FRAME           60
 116
 117 static const struct bge_type bge_devs[] = {
 118         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
 119                 "3COM 3C996 Gigabit Ethernet" },
 120
 121         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 122                 "Alteon BCM5700 Gigabit Ethernet" },
 123         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
 124                 "Alteon BCM5701 Gigabit Ethernet" },
 125
 126         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
 127                 "Altima AC1000 Gigabit Ethernet" },
 128         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
 129                 "Altima AC1002 Gigabit Ethernet" },
 130         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
 131                 "Altima AC9100 Gigabit Ethernet" },
 132
 133         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
 134                 "Apple BCM5701 Gigabit Ethernet" },
 135
 136         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
 137                 "Broadcom BCM5700 Gigabit Ethernet" },
 138         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
 139                 "Broadcom BCM5701 Gigabit Ethernet" },
 140         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
 141                 "Broadcom BCM5702 Gigabit Ethernet" },
 142         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
 143                 "Broadcom BCM5702X Gigabit Ethernet" },
 144         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
 145                 "Broadcom BCM5702 Gigabit Ethernet" },
 146         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
 147                 "Broadcom BCM5703 Gigabit Ethernet" },
 148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
 149                 "Broadcom BCM5703X Gigabit Ethernet" },
 150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
 151                 "Broadcom BCM5703 Gigabit Ethernet" },
 152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
 153                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
 154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
 155                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
 157                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
 159                 "Broadcom BCM5705 Gigabit Ethernet" },
 160         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
 161                 "Broadcom BCM5705F Gigabit Ethernet" },
 162         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
 163                 "Broadcom BCM5705K Gigabit Ethernet" },
 164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
 165                 "Broadcom BCM5705M Gigabit Ethernet" },
 166         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
 167                 "Broadcom BCM5705M Gigabit Ethernet" },
 168         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
 169                 "Broadcom BCM5714C Gigabit Ethernet" },
 170         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
 171                 "Broadcom BCM5714S Gigabit Ethernet" },
 172         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
 173                 "Broadcom BCM5715 Gigabit Ethernet" },
 174         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
 175                 "Broadcom BCM5715S Gigabit Ethernet" },
 176         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
 177                 "Broadcom BCM5720 Gigabit Ethernet" },
 178         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
 179                 "Broadcom BCM5721 Gigabit Ethernet" },
 180         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
 181                 "Broadcom BCM5722 Gigabit Ethernet" },
 182         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723,
 183                 "Broadcom BCM5723 Gigabit Ethernet" },
 184         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
 185                 "Broadcom BCM5750 Gigabit Ethernet" },
 186         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
 187                 "Broadcom BCM5750M Gigabit Ethernet" },
 188         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
 189                 "Broadcom BCM5751 Gigabit Ethernet" },
 190         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
 191                 "Broadcom BCM5751F Gigabit Ethernet" },
 192         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
 193                 "Broadcom BCM5751M Gigabit Ethernet" },
 194         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
 195                 "Broadcom BCM5752 Gigabit Ethernet" },
 196         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
 197                 "Broadcom BCM5752M Gigabit Ethernet" },
 198         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
 199                 "Broadcom BCM5753 Gigabit Ethernet" },
 200         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
 201                 "Broadcom BCM5753F Gigabit Ethernet" },
 202         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
 203                 "Broadcom BCM5753M Gigabit Ethernet" },
 204         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
 205                 "Broadcom BCM5754 Gigabit Ethernet" },
 206         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
 207                 "Broadcom BCM5754M Gigabit Ethernet" },
 208         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
 209                 "Broadcom BCM5755 Gigabit Ethernet" },
 210         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
 211                 "Broadcom BCM5755M Gigabit Ethernet" },
 212         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
 213                 "Broadcom BCM5756 Gigabit Ethernet" },
 214         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761,
 215                 "Broadcom BCM5761 Gigabit Ethernet" },
 216         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E,
 217                 "Broadcom BCM5761E Gigabit Ethernet" },
 218         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S,
 219                 "Broadcom BCM5761S Gigabit Ethernet" },
 220         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE,
 221                 "Broadcom BCM5761SE Gigabit Ethernet" },
 222         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764,
 223                 "Broadcom BCM5764 Gigabit Ethernet" },
 224         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
 225                 "Broadcom BCM5780 Gigabit Ethernet" },
 226         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
 227                 "Broadcom BCM5780S Gigabit Ethernet" },
 228         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
 229                 "Broadcom BCM5781 Gigabit Ethernet" },
 230         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
 231                 "Broadcom BCM5782 Gigabit Ethernet" },
 232         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784,
 233                 "Broadcom BCM5784 Gigabit Ethernet" },
 234         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F,
 235                 "Broadcom BCM5785F Gigabit Ethernet" },
 236         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G,
 237                 "Broadcom BCM5785G Gigabit Ethernet" },
 238         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
 239                 "Broadcom BCM5786 Gigabit Ethernet" },
 240         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
 241                 "Broadcom BCM5787 Gigabit Ethernet" },
 242         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
 243                 "Broadcom BCM5787F Gigabit Ethernet" },
 244         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
 245                 "Broadcom BCM5787M Gigabit Ethernet" },
 246         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
 247                 "Broadcom BCM5788 Gigabit Ethernet" },
 248         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
 249                 "Broadcom BCM5789 Gigabit Ethernet" },
 250         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
 251                 "Broadcom BCM5901 Fast Ethernet" },
 252         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
 253                 "Broadcom BCM5901A2 Fast Ethernet" },
 254         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
 255                 "Broadcom BCM5903M Fast Ethernet" },
 256         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
 257                 "Broadcom BCM5906 Fast Ethernet"},
 258         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
 259                 "Broadcom BCM5906M Fast Ethernet"},
 260         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760,
 261                 "Broadcom BCM57760 Gigabit Ethernet"},
 262         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780,
 263                 "Broadcom BCM57780 Gigabit Ethernet"},
 264         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788,
 265                 "Broadcom BCM57788 Gigabit Ethernet"},
 266         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790,
 267                 "Broadcom BCM57790 Gigabit Ethernet"},
 268         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
 269                 "SysKonnect Gigabit Ethernet" },
 270
 271         { 0, 0, NULL }
 272 };
 273
 274 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 275 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 276 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 277 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 278 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 279 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
 280
 281 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 282
 283 static int      bge_probe(device_t);
 284 static int      bge_attach(device_t);
 285 static int      bge_detach(device_t);
 286 static void     bge_txeof(struct bge_softc *);
 287 static void     bge_rxeof(struct bge_softc *);
 288
 289 static void     bge_tick(void *);
 290 static void     bge_stats_update(struct bge_softc *);
 291 static void     bge_stats_update_regs(struct bge_softc *);
 292 static int      bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 293
 294 #ifdef DEVICE_POLLING
 295 static void     bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 296 #endif
 297 static void     bge_intr(void *);
 298 static void     bge_enable_intr(struct bge_softc *);
 299 static void     bge_disable_intr(struct bge_softc *);
 300 static void     bge_start(struct ifnet *);
 301 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 302 static void     bge_init(void *);
 303 static void     bge_stop(struct bge_softc *);
 304 static void     bge_watchdog(struct ifnet *);
 305 static void     bge_shutdown(device_t);
 306 static int      bge_suspend(device_t);
 307 static int      bge_resume(device_t);
 308 static int      bge_ifmedia_upd(struct ifnet *);
 309 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 310
 311 static uint8_t  bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 312 static int      bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 313
 314 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
 315 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
 316
 317 static void     bge_setmulti(struct bge_softc *);
 318 static void     bge_setpromisc(struct bge_softc *);
 319
 320 static int      bge_alloc_jumbo_mem(struct bge_softc *);
 321 static void     bge_free_jumbo_mem(struct bge_softc *);
 322 static struct bge_jslot
 323                 *bge_jalloc(struct bge_softc *);
 324 static void     bge_jfree(void *);
 325 static void     bge_jref(void *);
 326 static int      bge_newbuf_std(struct bge_softc *, int, int);
 327 static int      bge_newbuf_jumbo(struct bge_softc *, int, int);
 328 static void     bge_setup_rxdesc_std(struct bge_softc *, int);
 329 static void     bge_setup_rxdesc_jumbo(struct bge_softc *, int);
 330 static int      bge_init_rx_ring_std(struct bge_softc *);
 331 static void     bge_free_rx_ring_std(struct bge_softc *);
 332 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
 333 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
 334 static void     bge_free_tx_ring(struct bge_softc *);
 335 static int      bge_init_tx_ring(struct bge_softc *);
 336
 337 static int      bge_chipinit(struct bge_softc *);
 338 static int      bge_blockinit(struct bge_softc *);
 339
 340 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
 341 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
 342 #ifdef notdef
 343 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
 344 #endif
 345 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
 346 static void     bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
 347 static void     bge_writembx(struct bge_softc *, int, int);
 348
 349 static int      bge_miibus_readreg(device_t, int, int);
 350 static int      bge_miibus_writereg(device_t, int, int, int);
 351 static void     bge_miibus_statchg(device_t);
 352 static void     bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
 353 static void     bge_tbi_link_upd(struct bge_softc *, uint32_t);
 354 static void     bge_copper_link_upd(struct bge_softc *, uint32_t);
 355
 356 static void     bge_reset(struct bge_softc *);
 357
 358 static int      bge_dma_alloc(struct bge_softc *);
 359 static void     bge_dma_free(struct bge_softc *);
 360 static int      bge_dma_block_alloc(struct bge_softc *, bus_size_t,
 361                                     bus_dma_tag_t *, bus_dmamap_t *,
 362                                     void **, bus_addr_t *);
 363 static void     bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 364
 365 static int      bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 366 static int      bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 367 static int      bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 368 static int      bge_get_eaddr(struct bge_softc *, uint8_t[]);
 369
 370 static void     bge_coal_change(struct bge_softc *);
 371 static int      bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 372 static int      bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 373 static int      bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 374 static int      bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 375 static int      bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
 376
 377 /*
 378  * Set following tunable to 1 for some IBM blade servers with the DNLK
 379  * switch module. Auto negotiation is broken for those configurations.
 380  */
 381 static int      bge_fake_autoneg = 0;
 382 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
 383
 384 /* Interrupt moderation control variables. */
 385 static int      bge_rx_coal_ticks = 100;        /* usec */
 386 static int      bge_tx_coal_ticks = 1023;       /* usec */
 387 static int      bge_rx_max_coal_bds = 80;
 388 static int      bge_tx_max_coal_bds = 128;
 389
 390 TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
 391 TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
 392 TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
 393 TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
 394
 395 #if !defined(KTR_IF_BGE)
 396 #define KTR_IF_BGE      KTR_ALL
 397 #endif
 398 KTR_INFO_MASTER(if_bge);
 399 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr");
 400 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt");
 401 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt");
 402 #define logif(name)     KTR_LOG(if_bge_ ## name)
 403
 404 static device_method_t bge_methods[] = {
 405         /* Device interface */
 406         DEVMETHOD(device_probe,         bge_probe),
 407         DEVMETHOD(device_attach,        bge_attach),
 408         DEVMETHOD(device_detach,        bge_detach),
 409         DEVMETHOD(device_shutdown,      bge_shutdown),
 410         DEVMETHOD(device_suspend,       bge_suspend),
 411         DEVMETHOD(device_resume,        bge_resume),
 412
 413         /* bus interface */
 414         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 415         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 416
 417         /* MII interface */
 418         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 419         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 420         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 421
 422         { 0, 0 }
 423 };
 424
 425 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
 426 static devclass_t bge_devclass;
 427
 428 DECLARE_DUMMY_MODULE(if_bge);
 429 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL);
 430 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL);
 431
 432 static uint32_t
 433 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
 434 {
 435         device_t dev = sc->bge_dev;
 436         uint32_t val;
 437
 438         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 439         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 440         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 441         return (val);
 442 }
 443
 444 static void
 445 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 446 {
 447         device_t dev = sc->bge_dev;
 448
 449         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 450         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 451         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 452 }
 453
 454 #ifdef notdef
 455 static uint32_t
 456 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
 457 {
 458         device_t dev = sc->bge_dev;
 459
 460         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 461         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 462 }
 463 #endif
 464
 465 static void
 466 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 467 {
 468         device_t dev = sc->bge_dev;
 469
 470         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 471         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 472 }
 473
 474 static void
 475 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
 476 {
 477         CSR_WRITE_4(sc, off, val);
 478 }
 479
 480 static void
 481 bge_writembx(struct bge_softc *sc, int off, int val)
 482 {
 483         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 484                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 485
 486         CSR_WRITE_4(sc, off, val);
 487 }
 488
 489 static uint8_t
 490 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 491 {
 492         uint32_t access, byte = 0;
 493         int i;
 494
 495         /* Lock. */
 496         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 497         for (i = 0; i < 8000; i++) {
 498                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 499                         break;
 500                 DELAY(20);
 501         }
 502         if (i == 8000)
 503                 return (1);
 504
 505         /* Enable access. */
 506         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 507         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 508
 509         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 510         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 511         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 512                 DELAY(10);
 513                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 514                         DELAY(10);
 515                         break;
 516                 }
 517         }
 518
 519         if (i == BGE_TIMEOUT * 10) {
 520                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
 521                 return (1);
 522         }
 523
 524         /* Get result. */
 525         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 526
 527         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 528
 529         /* Disable access. */
 530         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 531
 532         /* Unlock. */
 533         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 534         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 535
 536         return (0);
 537 }
 538
 539 /*
 540  * Read a sequence of bytes from NVRAM.
 541  */
 542 static int
 543 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 544 {
 545         int err = 0, i;
 546         uint8_t byte = 0;
 547
 548         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 549                 return (1);
 550
 551         for (i = 0; i < cnt; i++) {
 552                 err = bge_nvram_getbyte(sc, off + i, &byte);
 553                 if (err)
 554                         break;
 555                 *(dest + i) = byte;
 556         }
 557
 558         return (err ? 1 : 0);
 559 }
 560
 561 /*
 562  * Read a byte of data stored in the EEPROM at address 'addr.' The
 563  * BCM570x supports both the traditional bitbang interface and an
 564  * auto access interface for reading the EEPROM. We use the auto
 565  * access method.
 566  */
 567 static uint8_t
 568 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
 569 {
 570         int i;
 571         uint32_t byte = 0;
 572
 573         /*
 574          * Enable use of auto EEPROM access so we can avoid
 575          * having to use the bitbang method.
 576          */
 577         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 578
 579         /* Reset the EEPROM, load the clock period. */
 580         CSR_WRITE_4(sc, BGE_EE_ADDR,
 581             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 582         DELAY(20);
 583
 584         /* Issue the read EEPROM command. */
 585         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 586
 587         /* Wait for completion */
 588         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 589                 DELAY(10);
 590                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 591                         break;
 592         }
 593
 594         if (i == BGE_TIMEOUT) {
 595                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 596                 return(1);
 597         }
 598
 599         /* Get result. */
 600         byte = CSR_READ_4(sc, BGE_EE_DATA);
 601
 602         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 603
 604         return(0);
 605 }
 606
 607 /*
 608  * Read a sequence of bytes from the EEPROM.
 609  */
 610 static int
 611 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
 612 {
 613         size_t i;
 614         int err;
 615         uint8_t byte;
 616
 617         for (byte = 0, err = 0, i = 0; i < len; i++) {
 618                 err = bge_eeprom_getbyte(sc, off + i, &byte);
 619                 if (err)
 620                         break;
 621                 *(dest + i) = byte;
 622         }
 623
 624         return(err ? 1 : 0);
 625 }
 626
 627 static int
 628 bge_miibus_readreg(device_t dev, int phy, int reg)
 629 {
 630         struct bge_softc *sc = device_get_softc(dev);
 631         struct ifnet *ifp = &sc->arpcom.ac_if;
 632         uint32_t val, autopoll;
 633         int i;
 634
 635         /*
 636          * Broadcom's own driver always assumes the internal
 637          * PHY is at GMII address 1. On some chips, the PHY responds
 638          * to accesses at all addresses, which could cause us to
 639          * bogusly attach the PHY 32 times at probe type. Always
 640          * restricting the lookup to address 1 is simpler than
 641          * trying to figure out which chips revisions should be
 642          * special-cased.
 643          */
 644         if (phy != 1)
 645                 return(0);
 646
 647         /* Reading with autopolling on may trigger PCI errors */
 648         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 649         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 650                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 651                 DELAY(40);
 652         }
 653
 654         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
 655             BGE_MIPHY(phy)|BGE_MIREG(reg));
 656
 657         for (i = 0; i < BGE_TIMEOUT; i++) {
 658                 DELAY(10);
 659                 val = CSR_READ_4(sc, BGE_MI_COMM);
 660                 if (!(val & BGE_MICOMM_BUSY))
 661                         break;
 662         }
 663
 664         if (i == BGE_TIMEOUT) {
 665                 if_printf(ifp, "PHY read timed out "
 666                           "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
 667                 val = 0;
 668                 goto done;
 669         }
 670
 671         DELAY(5);
 672         val = CSR_READ_4(sc, BGE_MI_COMM);
 673
 674 done:
 675         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 676                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 677                 DELAY(40);
 678         }
 679
 680         if (val & BGE_MICOMM_READFAIL)
 681                 return(0);
 682
 683         return(val & 0xFFFF);
 684 }
 685
 686 static int
 687 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 688 {
 689         struct bge_softc *sc = device_get_softc(dev);
 690         uint32_t autopoll;
 691         int i;
 692
 693         /*
 694          * See the related comment in bge_miibus_readreg()
 695          */
 696         if (phy != 1)
 697                 return(0);
 698
 699         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 700             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 701                return(0);
 702
 703         /* Reading with autopolling on may trigger PCI errors */
 704         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 705         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 706                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 707                 DELAY(40);
 708         }
 709
 710         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
 711             BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
 712
 713         for (i = 0; i < BGE_TIMEOUT; i++) {
 714                 DELAY(10);
 715                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 716                         DELAY(5);
 717                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 718                         break;
 719                 }
 720         }
 721
 722         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 723                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 724                 DELAY(40);
 725         }
 726
 727         if (i == BGE_TIMEOUT) {
 728                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
 729                           "(phy %d, reg %d, val %d)\n", phy, reg, val);
 730                 return(0);
 731         }
 732
 733         return(0);
 734 }
 735
 736 static void
 737 bge_miibus_statchg(device_t dev)
 738 {
 739         struct bge_softc *sc;
 740         struct mii_data *mii;
 741
 742         sc = device_get_softc(dev);
 743         mii = device_get_softc(sc->bge_miibus);
 744
 745         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 746         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
 747                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 748         } else {
 749                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 750         }
 751
 752         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 753                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 754         } else {
 755                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 756         }
 757 }
 758
 759 /*
 760  * Memory management for jumbo frames.
 761  */
 762 static int
 763 bge_alloc_jumbo_mem(struct bge_softc *sc)
 764 {
 765         struct ifnet *ifp = &sc->arpcom.ac_if;
 766         struct bge_jslot *entry;
 767         uint8_t *ptr;
 768         bus_addr_t paddr;
 769         int i, error;
 770
 771         /*
 772          * Create tag for jumbo mbufs.
 773          * This is really a bit of a kludge. We allocate a special
 774          * jumbo buffer pool which (thanks to the way our DMA
 775          * memory allocation works) will consist of contiguous
 776          * pages. This means that even though a jumbo buffer might
 777          * be larger than a page size, we don't really need to
 778          * map it into more than one DMA segment. However, the
 779          * default mbuf tag will result in multi-segment mappings,
 780          * so we have to create a special jumbo mbuf tag that
 781          * lets us get away with mapping the jumbo buffers as
 782          * a single segment. I think eventually the driver should
 783          * be changed so that it uses ordinary mbufs and cluster
 784          * buffers, i.e. jumbo frames can span multiple DMA
 785          * descriptors. But that's a project for another day.
 786          */
 787
 788         /*
 789          * Create DMA stuffs for jumbo RX ring.
 790          */
 791         error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 792                                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
 793                                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
 794                                     (void *)&sc->bge_ldata.bge_rx_jumbo_ring,
 795                                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
 796         if (error) {
 797                 if_printf(ifp, "could not create jumbo RX ring\n");
 798                 return error;
 799         }
 800
 801         /*
 802          * Create DMA stuffs for jumbo buffer block.
 803          */
 804         error = bge_dma_block_alloc(sc, BGE_JMEM,
 805                                     &sc->bge_cdata.bge_jumbo_tag,
 806                                     &sc->bge_cdata.bge_jumbo_map,
 807                                     (void **)&sc->bge_ldata.bge_jumbo_buf,
 808                                     &paddr);
 809         if (error) {
 810                 if_printf(ifp, "could not create jumbo buffer\n");
 811                 return error;
 812         }
 813
 814         SLIST_INIT(&sc->bge_jfree_listhead);
 815
 816         /*
 817          * Now divide it up into 9K pieces and save the addresses
 818          * in an array. Note that we play an evil trick here by using
 819          * the first few bytes in the buffer to hold the the address
 820          * of the softc structure for this interface. This is because
 821          * bge_jfree() needs it, but it is called by the mbuf management
 822          * code which will not pass it to us explicitly.
 823          */
 824         for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
 825                 entry = &sc->bge_cdata.bge_jslots[i];
 826                 entry->bge_sc = sc;
 827                 entry->bge_buf = ptr;
 828                 entry->bge_paddr = paddr;
 829                 entry->bge_inuse = 0;
 830                 entry->bge_slot = i;
 831                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 832
 833                 ptr += BGE_JLEN;
 834                 paddr += BGE_JLEN;
 835         }
 836         return 0;
 837 }
 838
 839 static void
 840 bge_free_jumbo_mem(struct bge_softc *sc)
 841 {
 842         /* Destroy jumbo RX ring. */
 843         bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 844                            sc->bge_cdata.bge_rx_jumbo_ring_map,
 845                            sc->bge_ldata.bge_rx_jumbo_ring);
 846
 847         /* Destroy jumbo buffer block. */
 848         bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
 849                            sc->bge_cdata.bge_jumbo_map,
 850                            sc->bge_ldata.bge_jumbo_buf);
 851 }
 852
 853 /*
 854  * Allocate a jumbo buffer.
 855  */
 856 static struct bge_jslot *
 857 bge_jalloc(struct bge_softc *sc)
 858 {
 859         struct bge_jslot *entry;
 860
 861         lwkt_serialize_enter(&sc->bge_jslot_serializer);
 862         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
 863         if (entry) {
 864                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
 865                 entry->bge_inuse = 1;
 866         } else {
 867                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 868         }
 869         lwkt_serialize_exit(&sc->bge_jslot_serializer);
 870         return(entry);
 871 }
 872
 873 /*
 874  * Adjust usage count on a jumbo buffer.
 875  */
 876 static void
 877 bge_jref(void *arg)
 878 {
 879         struct bge_jslot *entry = (struct bge_jslot *)arg;
 880         struct bge_softc *sc = entry->bge_sc;
 881
 882         if (sc == NULL)
 883                 panic("bge_jref: can't find softc pointer!");
 884
 885         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 886                 panic("bge_jref: asked to reference buffer "
 887                     "that we don't manage!");
 888         } else if (entry->bge_inuse == 0) {
 889                 panic("bge_jref: buffer already free!");
 890         } else {
 891                 atomic_add_int(&entry->bge_inuse, 1);
 892         }
 893 }
 894
 895 /*
 896  * Release a jumbo buffer.
 897  */
 898 static void
 899 bge_jfree(void *arg)
 900 {
 901         struct bge_jslot *entry = (struct bge_jslot *)arg;
 902         struct bge_softc *sc = entry->bge_sc;
 903
 904         if (sc == NULL)
 905                 panic("bge_jfree: can't find softc pointer!");
 906
 907         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 908                 panic("bge_jfree: asked to free buffer that we don't manage!");
 909         } else if (entry->bge_inuse == 0) {
 910                 panic("bge_jfree: buffer already free!");
 911         } else {
 912                 /*
 913                  * Possible MP race to 0, use the serializer.  The atomic insn
 914                  * is still needed for races against bge_jref().
 915                  */
 916                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
 917                 atomic_subtract_int(&entry->bge_inuse, 1);
 918                 if (entry->bge_inuse == 0) {
 919                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
 920                                           entry, jslot_link);
 921                 }
 922                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
 923         }
 924 }
 925
 926
 927 /*
 928  * Intialize a standard receive ring descriptor.
 929  */
 930 static int
 931 bge_newbuf_std(struct bge_softc *sc, int i, int init)
 932 {
 933         struct mbuf *m_new = NULL;
 934         bus_dma_segment_t seg;
 935         bus_dmamap_t map;
 936         int error, nsegs;
 937
 938         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 939         if (m_new == NULL)
 940                 return ENOBUFS;
 941         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 942
 943         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 944                 m_adj(m_new, ETHER_ALIGN);
 945
 946         error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag,
 947                         sc->bge_cdata.bge_rx_tmpmap, m_new,
 948                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
 949         if (error) {
 950                 m_freem(m_new);
 951                 return error;
 952         }
 953
 954         if (!init) {
 955                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 956                                 sc->bge_cdata.bge_rx_std_dmamap[i],
 957                                 BUS_DMASYNC_POSTREAD);
 958                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
 959                         sc->bge_cdata.bge_rx_std_dmamap[i]);
 960         }
 961
 962         map = sc->bge_cdata.bge_rx_tmpmap;
 963         sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i];
 964         sc->bge_cdata.bge_rx_std_dmamap[i] = map;
 965
 966         sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new;
 967         sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr;
 968
 969         bge_setup_rxdesc_std(sc, i);
 970         return 0;
 971 }
 972
 973 static void
 974 bge_setup_rxdesc_std(struct bge_softc *sc, int i)
 975 {
 976         struct bge_rxchain *rc;
 977         struct bge_rx_bd *r;
 978
 979         rc = &sc->bge_cdata.bge_rx_std_chain[i];
 980         r = &sc->bge_ldata.bge_rx_std_ring[i];
 981
 982         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
 983         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
 984         r->bge_len = rc->bge_mbuf->m_len;
 985         r->bge_idx = i;
 986         r->bge_flags = BGE_RXBDFLAG_END;
 987 }
 988
 989 /*
 990  * Initialize a jumbo receive ring descriptor. This allocates
 991  * a jumbo buffer from the pool managed internally by the driver.
 992  */
 993 static int
 994 bge_newbuf_jumbo(struct bge_softc *sc, int i, int init)
 995 {
 996         struct mbuf *m_new = NULL;
 997         struct bge_jslot *buf;
 998         bus_addr_t paddr;
 999
1000         /* Allocate the mbuf. */
1001         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1002         if (m_new == NULL)
1003                 return ENOBUFS;
1004
1005         /* Allocate the jumbo buffer */
1006         buf = bge_jalloc(sc);
1007         if (buf == NULL) {
1008                 m_freem(m_new);
1009                 return ENOBUFS;
1010         }
1011
1012         /* Attach the buffer to the mbuf. */
1013         m_new->m_ext.ext_arg = buf;
1014         m_new->m_ext.ext_buf = buf->bge_buf;
1015         m_new->m_ext.ext_free = bge_jfree;
1016         m_new->m_ext.ext_ref = bge_jref;
1017         m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
1018
1019         m_new->m_flags |= M_EXT;
1020
1021         m_new->m_data = m_new->m_ext.ext_buf;
1022         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1023
1024         paddr = buf->bge_paddr;
1025         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
1026                 m_adj(m_new, ETHER_ALIGN);
1027                 paddr += ETHER_ALIGN;
1028         }
1029
1030         /* Save necessary information */
1031         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new;
1032         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr;
1033
1034         /* Set up the descriptor. */
1035         bge_setup_rxdesc_jumbo(sc, i);
1036         return 0;
1037 }
1038
1039 static void
1040 bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i)
1041 {
1042         struct bge_rx_bd *r;
1043         struct bge_rxchain *rc;
1044
1045         r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1046         rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1047
1048         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1049         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1050         r->bge_len = rc->bge_mbuf->m_len;
1051         r->bge_idx = i;
1052         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
1053 }
1054
1055 static int
1056 bge_init_rx_ring_std(struct bge_softc *sc)
1057 {
1058         int i, error;
1059
1060         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1061                 error = bge_newbuf_std(sc, i, 1);
1062                 if (error)
1063                         return error;
1064         };
1065
1066         sc->bge_std = BGE_STD_RX_RING_CNT - 1;
1067         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1068
1069         return(0);
1070 }
1071
1072 static void
1073 bge_free_rx_ring_std(struct bge_softc *sc)
1074 {
1075         int i;
1076
1077         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1078                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i];
1079
1080                 if (rc->bge_mbuf != NULL) {
1081                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1082                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
1083                         m_freem(rc->bge_mbuf);
1084                         rc->bge_mbuf = NULL;
1085                 }
1086                 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
1087                     sizeof(struct bge_rx_bd));
1088         }
1089 }
1090
1091 static int
1092 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1093 {
1094         struct bge_rcb *rcb;
1095         int i, error;
1096
1097         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1098                 error = bge_newbuf_jumbo(sc, i, 1);
1099                 if (error)
1100                         return error;
1101         };
1102
1103         sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
1104
1105         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1106         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1107         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1108
1109         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1110
1111         return(0);
1112 }
1113
1114 static void
1115 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1116 {
1117         int i;
1118
1119         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1120                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1121
1122                 if (rc->bge_mbuf != NULL) {
1123                         m_freem(rc->bge_mbuf);
1124                         rc->bge_mbuf = NULL;
1125                 }
1126                 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1127                     sizeof(struct bge_rx_bd));
1128         }
1129 }
1130
1131 static void
1132 bge_free_tx_ring(struct bge_softc *sc)
1133 {
1134         int i;
1135
1136         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1137                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1138                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1139                                           sc->bge_cdata.bge_tx_dmamap[i]);
1140                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1141                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1142                 }
1143                 bzero(&sc->bge_ldata.bge_tx_ring[i],
1144                     sizeof(struct bge_tx_bd));
1145         }
1146 }
1147
1148 static int
1149 bge_init_tx_ring(struct bge_softc *sc)
1150 {
1151         sc->bge_txcnt = 0;
1152         sc->bge_tx_saved_considx = 0;
1153         sc->bge_tx_prodidx = 0;
1154
1155         /* Initialize transmit producer index for host-memory send ring. */
1156         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1157
1158         /* 5700 b2 errata */
1159         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1160                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1161
1162         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1163         /* 5700 b2 errata */
1164         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1165                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1166
1167         return(0);
1168 }
1169
1170 static void
1171 bge_setmulti(struct bge_softc *sc)
1172 {
1173         struct ifnet *ifp;
1174         struct ifmultiaddr *ifma;
1175         uint32_t hashes[4] = { 0, 0, 0, 0 };
1176         int h, i;
1177
1178         ifp = &sc->arpcom.ac_if;
1179
1180         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1181                 for (i = 0; i < 4; i++)
1182                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1183                 return;
1184         }
1185
1186         /* First, zot all the existing filters. */
1187         for (i = 0; i < 4; i++)
1188                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1189
1190         /* Now program new ones. */
1191         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1192                 if (ifma->ifma_addr->sa_family != AF_LINK)
1193                         continue;
1194                 h = ether_crc32_le(
1195                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1196                     ETHER_ADDR_LEN) & 0x7f;
1197                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1198         }
1199
1200         for (i = 0; i < 4; i++)
1201                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1202 }
1203
1204 /*
1205  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1206  * self-test results.
1207  */
1208 static int
1209 bge_chipinit(struct bge_softc *sc)
1210 {
1211         int i;
1212         uint32_t dma_rw_ctl;
1213         uint16_t val;
1214
1215         /* Set endian type before we access any non-PCI registers. */
1216         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1217
1218         /* Clear the MAC control register */
1219         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1220
1221         /*
1222          * Clear the MAC statistics block in the NIC's
1223          * internal memory.
1224          */
1225         for (i = BGE_STATS_BLOCK;
1226             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1227                 BGE_MEMWIN_WRITE(sc, i, 0);
1228
1229         for (i = BGE_STATUS_BLOCK;
1230             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1231                 BGE_MEMWIN_WRITE(sc, i, 0);
1232
1233         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1234                 /*
1235                  * Fix data corruption caused by non-qword write with WB.
1236                  * Fix master abort in PCI mode.
1237                  * Fix PCI latency timer.
1238                  */
1239                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1240                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1241                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1242         }
1243
1244         /* Set up the PCI DMA control register. */
1245         if (sc->bge_flags & BGE_FLAG_PCIE) {
1246                 /* PCI Express */
1247                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1248                     (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1249                     (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1250         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1251                 /* PCI-X bus */
1252                 if (BGE_IS_5714_FAMILY(sc)) {
1253                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1254                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1255                         /* XXX magic values, Broadcom-supplied Linux driver */
1256                         if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1257                                 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1258                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1259                         } else {
1260                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1261                         }
1262                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1263                         /*
1264                          * In the BCM5703, the DMA read watermark should
1265                          * be set to less than or equal to the maximum
1266                          * memory read byte count of the PCI-X command
1267                          * register.
1268                          */
1269                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1270                             (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1271                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1272                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1273                         /*
1274                          * The 5704 uses a different encoding of read/write
1275                          * watermarks.
1276                          */
1277                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1278                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1279                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1280                 } else {
1281                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1282                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1283                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1284                             (0x0F);
1285                 }
1286
1287                 /*
1288                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1289                  * for hardware bugs.
1290                  */
1291                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1292                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1293                         uint32_t tmp;
1294
1295                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1296                         if (tmp == 0x6 || tmp == 0x7)
1297                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1298                 }
1299         } else {
1300                 /* Conventional PCI bus */
1301                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1302                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1303                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1304                     (0x0F);
1305         }
1306
1307         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1308             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1309             sc->bge_asicrev == BGE_ASICREV_BCM5705)
1310                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1311         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1312
1313         /*
1314          * Set up general mode register.
1315          */
1316         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1317             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1318             BGE_MODECTL_TX_NO_PHDR_CSUM);
1319
1320         /*
1321          * BCM5701 B5 have a bug causing data corruption when using
1322          * 64-bit DMA reads, which can be terminated early and then
1323          * completed later as 32-bit accesses, in combination with
1324          * certain bridges.
1325          */
1326         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1327             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1328                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1329
1330         /*
1331          * Disable memory write invalidate.  Apparently it is not supported
1332          * properly by these devices.
1333          */
1334         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1335
1336         /* Set the timer prescaler (always 66Mhz) */
1337         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1338
1339         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1340                 DELAY(40);      /* XXX */
1341
1342                 /* Put PHY into ready state */
1343                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1344                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1345                 DELAY(40);
1346         }
1347
1348         return(0);
1349 }
1350
1351 static int
1352 bge_blockinit(struct bge_softc *sc)
1353 {
1354         struct bge_rcb *rcb;
1355         bus_size_t vrcb;
1356         bge_hostaddr taddr;
1357         uint32_t val;
1358         int i;
1359
1360         /*
1361          * Initialize the memory window pointer register so that
1362          * we can access the first 32K of internal NIC RAM. This will
1363          * allow us to set up the TX send ring RCBs and the RX return
1364          * ring RCBs, plus other things which live in NIC memory.
1365          */
1366         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1367
1368         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1369
1370         if (!BGE_IS_5705_PLUS(sc)) {
1371                 /* Configure mbuf memory pool */
1372                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1373                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1374                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1375                 else
1376                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1377
1378                 /* Configure DMA resource pool */
1379                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1380                     BGE_DMA_DESCRIPTORS);
1381                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1382         }
1383
1384         /* Configure mbuf pool watermarks */
1385         if (!BGE_IS_5705_PLUS(sc)) {
1386                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1387                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1388                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1389         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1390                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1391                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1392                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1393         } else {
1394                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1395                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1396                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1397         }
1398
1399         /* Configure DMA resource watermarks */
1400         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1401         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1402
1403         /* Enable buffer manager */
1404         if (!BGE_IS_5705_PLUS(sc)) {
1405                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1406                     BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1407
1408                 /* Poll for buffer manager start indication */
1409                 for (i = 0; i < BGE_TIMEOUT; i++) {
1410                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1411                                 break;
1412                         DELAY(10);
1413                 }
1414
1415                 if (i == BGE_TIMEOUT) {
1416                         if_printf(&sc->arpcom.ac_if,
1417                                   "buffer manager failed to start\n");
1418                         return(ENXIO);
1419                 }
1420         }
1421
1422         /* Enable flow-through queues */
1423         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1424         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1425
1426         /* Wait until queue initialization is complete */
1427         for (i = 0; i < BGE_TIMEOUT; i++) {
1428                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1429                         break;
1430                 DELAY(10);
1431         }
1432
1433         if (i == BGE_TIMEOUT) {
1434                 if_printf(&sc->arpcom.ac_if,
1435                           "flow-through queue init failed\n");
1436                 return(ENXIO);
1437         }
1438
1439         /* Initialize the standard RX ring control block */
1440         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1441         rcb->bge_hostaddr.bge_addr_lo =
1442             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1443         rcb->bge_hostaddr.bge_addr_hi =
1444             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1445         if (BGE_IS_5705_PLUS(sc))
1446                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1447         else
1448                 rcb->bge_maxlen_flags =
1449                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1450         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1451         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1452         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1453         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1454         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1455
1456         /*
1457          * Initialize the jumbo RX ring control block
1458          * We set the 'ring disabled' bit in the flags
1459          * field until we're actually ready to start
1460          * using this ring (i.e. once we set the MTU
1461          * high enough to require it).
1462          */
1463         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1464                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1465
1466                 rcb->bge_hostaddr.bge_addr_lo =
1467                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1468                 rcb->bge_hostaddr.bge_addr_hi =
1469                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1470                 rcb->bge_maxlen_flags =
1471                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1472                     BGE_RCB_FLAG_RING_DISABLED);
1473                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1474                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1475                     rcb->bge_hostaddr.bge_addr_hi);
1476                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1477                     rcb->bge_hostaddr.bge_addr_lo);
1478                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1479                     rcb->bge_maxlen_flags);
1480                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1481
1482                 /* Set up dummy disabled mini ring RCB */
1483                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1484                 rcb->bge_maxlen_flags =
1485                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1486                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1487                     rcb->bge_maxlen_flags);
1488         }
1489
1490         /*
1491          * Set the BD ring replentish thresholds. The recommended
1492          * values are 1/8th the number of descriptors allocated to
1493          * each ring.
1494          */
1495         if (BGE_IS_5705_PLUS(sc))
1496                 val = 8;
1497         else
1498                 val = BGE_STD_RX_RING_CNT / 8;
1499         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1500         CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1501
1502         /*
1503          * Disable all unused send rings by setting the 'ring disabled'
1504          * bit in the flags field of all the TX send ring control blocks.
1505          * These are located in NIC memory.
1506          */
1507         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1508         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1509                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1510                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1511                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1512                 vrcb += sizeof(struct bge_rcb);
1513         }
1514
1515         /* Configure TX RCB 0 (we use only the first ring) */
1516         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1517         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1518         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1519         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1520         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1521             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1522         if (!BGE_IS_5705_PLUS(sc)) {
1523                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1524                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1525         }
1526
1527         /* Disable all unused RX return rings */
1528         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1529         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1530                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1531                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1532                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1533                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1534                     BGE_RCB_FLAG_RING_DISABLED));
1535                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1536                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1537                     (i * (sizeof(uint64_t))), 0);
1538                 vrcb += sizeof(struct bge_rcb);
1539         }
1540
1541         /* Initialize RX ring indexes */
1542         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1543         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1544         bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1545
1546         /*
1547          * Set up RX return ring 0
1548          * Note that the NIC address for RX return rings is 0x00000000.
1549          * The return rings live entirely within the host, so the
1550          * nicaddr field in the RCB isn't used.
1551          */
1552         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1553         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1554         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1555         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1556         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1557         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1558             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1559
1560         /* Set random backoff seed for TX */
1561         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1562             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1563             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1564             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1565             BGE_TX_BACKOFF_SEED_MASK);
1566
1567         /* Set inter-packet gap */
1568         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1569
1570         /*
1571          * Specify which ring to use for packets that don't match
1572          * any RX rules.
1573          */
1574         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1575
1576         /*
1577          * Configure number of RX lists. One interrupt distribution
1578          * list, sixteen active lists, one bad frames class.
1579          */
1580         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1581
1582         /* Inialize RX list placement stats mask. */
1583         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1584         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1585
1586         /* Disable host coalescing until we get it set up */
1587         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1588
1589         /* Poll to make sure it's shut down. */
1590         for (i = 0; i < BGE_TIMEOUT; i++) {
1591                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1592                         break;
1593                 DELAY(10);
1594         }
1595
1596         if (i == BGE_TIMEOUT) {
1597                 if_printf(&sc->arpcom.ac_if,
1598                           "host coalescing engine failed to idle\n");
1599                 return(ENXIO);
1600         }
1601
1602         /* Set up host coalescing defaults */
1603         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1604         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1605         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1606         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1607         if (!BGE_IS_5705_PLUS(sc)) {
1608                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1609                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1610         }
1611         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1612         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1613
1614         /* Set up address of statistics block */
1615         if (!BGE_IS_5705_PLUS(sc)) {
1616                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1617                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1618                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1619                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1620
1621                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1622                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1623                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1624         }
1625
1626         /* Set up address of status block */
1627         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1628             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1629         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1630             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1631         sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1632         sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1633
1634         /* Turn on host coalescing state machine */
1635         CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1636
1637         /* Turn on RX BD completion state machine and enable attentions */
1638         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1639             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1640
1641         /* Turn on RX list placement state machine */
1642         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1643
1644         /* Turn on RX list selector state machine. */
1645         if (!BGE_IS_5705_PLUS(sc))
1646                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1647
1648         /* Turn on DMA, clear stats */
1649         CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1650             BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1651             BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1652             BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1653             ((sc->bge_flags & BGE_FLAG_TBI) ?
1654              BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1655
1656         /* Set misc. local control, enable interrupts on attentions */
1657         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1658
1659 #ifdef notdef
1660         /* Assert GPIO pins for PHY reset */
1661         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1662             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1663         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1664             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1665 #endif
1666
1667         /* Turn on DMA completion state machine */
1668         if (!BGE_IS_5705_PLUS(sc))
1669                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1670
1671         /* Turn on write DMA state machine */
1672         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1673         if (BGE_IS_5755_PLUS(sc)) {
1674                 /* Enable host coalescing bug fix. */
1675                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1676         }
1677         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1678         DELAY(40);
1679
1680         /* Turn on read DMA state machine */
1681         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1682         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1683             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1684             sc->bge_asicrev == BGE_ASICREV_BCM57780)
1685                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1686                   BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1687                   BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1688         if (sc->bge_flags & BGE_FLAG_PCIE)
1689                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1690         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1691         DELAY(40);
1692
1693         /* Turn on RX data completion state machine */
1694         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1695
1696         /* Turn on RX BD initiator state machine */
1697         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1698
1699         /* Turn on RX data and RX BD initiator state machine */
1700         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1701
1702         /* Turn on Mbuf cluster free state machine */
1703         if (!BGE_IS_5705_PLUS(sc))
1704                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1705
1706         /* Turn on send BD completion state machine */
1707         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1708
1709         /* Turn on send data completion state machine */
1710         val = BGE_SDCMODE_ENABLE;
1711         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1712                 val |= BGE_SDCMODE_CDELAY;
1713         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1714
1715         /* Turn on send data initiator state machine */
1716         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1717
1718         /* Turn on send BD initiator state machine */
1719         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1720
1721         /* Turn on send BD selector state machine */
1722         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1723
1724         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1725         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1726             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1727
1728         /* ack/clear link change events */
1729         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1730             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1731             BGE_MACSTAT_LINK_CHANGED);
1732         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1733
1734         /* Enable PHY auto polling (for MII/GMII only) */
1735         if (sc->bge_flags & BGE_FLAG_TBI) {
1736                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1737         } else {
1738                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1739                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1740                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1741                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1742                             BGE_EVTENB_MI_INTERRUPT);
1743                 }
1744         }
1745
1746         /*
1747          * Clear any pending link state attention.
1748          * Otherwise some link state change events may be lost until attention
1749          * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1750          * It's not necessary on newer BCM chips - perhaps enabling link
1751          * state change attentions implies clearing pending attention.
1752          */
1753         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1754             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1755             BGE_MACSTAT_LINK_CHANGED);
1756
1757         /* Enable link state change attentions. */
1758         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1759
1760         return(0);
1761 }
1762
1763 /*
1764  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1765  * against our list and return its name if we find a match. Note
1766  * that since the Broadcom controller contains VPD support, we
1767  * can get the device name string from the controller itself instead
1768  * of the compiled-in string. This is a little slow, but it guarantees
1769  * we'll always announce the right product name.
1770  */
1771 static int
1772 bge_probe(device_t dev)
1773 {
1774         const struct bge_type *t;
1775         uint16_t product, vendor;
1776
1777         product = pci_get_device(dev);
1778         vendor = pci_get_vendor(dev);
1779
1780         for (t = bge_devs; t->bge_name != NULL; t++) {
1781                 if (vendor == t->bge_vid && product == t->bge_did)
1782                         break;
1783         }
1784         if (t->bge_name == NULL)
1785                 return(ENXIO);
1786
1787         device_set_desc(dev, t->bge_name);
1788         if (pci_get_subvendor(dev) == PCI_VENDOR_DELL) {
1789                 struct bge_softc *sc = device_get_softc(dev);
1790                 sc->bge_flags |= BGE_FLAG_NO_3LED;
1791         }
1792         return(0);
1793 }
1794
1795 static int
1796 bge_attach(device_t dev)
1797 {
1798         struct ifnet *ifp;
1799         struct bge_softc *sc;
1800         uint32_t hwcfg = 0;
1801         int error = 0, rid;
1802         uint8_t ether_addr[ETHER_ADDR_LEN];
1803
1804         sc = device_get_softc(dev);
1805         sc->bge_dev = dev;
1806         callout_init(&sc->bge_stat_timer);
1807         lwkt_serialize_init(&sc->bge_jslot_serializer);
1808
1809 #ifndef BURN_BRIDGES
1810         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1811                 uint32_t irq, mem;
1812
1813                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1814                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1815
1816                 device_printf(dev, "chip is in D%d power mode "
1817                     "-- setting to D0\n", pci_get_powerstate(dev));
1818
1819                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1820
1821                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1822                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1823         }
1824 #endif  /* !BURN_BRIDGE */
1825
1826         /*
1827          * Map control/status registers.
1828          */
1829         pci_enable_busmaster(dev);
1830
1831         rid = BGE_PCI_BAR0;
1832         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1833             RF_ACTIVE);
1834
1835         if (sc->bge_res == NULL) {
1836                 device_printf(dev, "couldn't map memory\n");
1837                 return ENXIO;
1838         }
1839
1840         sc->bge_btag = rman_get_bustag(sc->bge_res);
1841         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1842
1843         /* Save various chip information */
1844         sc->bge_chipid =
1845             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1846             BGE_PCIMISCCTL_ASICREV_SHIFT;
1847         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
1848                 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
1849         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1850         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1851
1852         /* Save chipset family. */
1853         switch (sc->bge_asicrev) {
1854         case BGE_ASICREV_BCM5755:
1855         case BGE_ASICREV_BCM5761:
1856         case BGE_ASICREV_BCM5784:
1857         case BGE_ASICREV_BCM5785:
1858         case BGE_ASICREV_BCM5787:
1859         case BGE_ASICREV_BCM57780:
1860             sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
1861                 BGE_FLAG_5705_PLUS;
1862             break;
1863
1864         case BGE_ASICREV_BCM5700:
1865         case BGE_ASICREV_BCM5701:
1866         case BGE_ASICREV_BCM5703:
1867         case BGE_ASICREV_BCM5704:
1868                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
1869                 break;
1870
1871         case BGE_ASICREV_BCM5714_A0:
1872         case BGE_ASICREV_BCM5780:
1873         case BGE_ASICREV_BCM5714:
1874                 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
1875                 /* Fall through */
1876
1877         case BGE_ASICREV_BCM5750:
1878         case BGE_ASICREV_BCM5752:
1879         case BGE_ASICREV_BCM5906:
1880                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
1881                 /* Fall through */
1882
1883         case BGE_ASICREV_BCM5705:
1884                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
1885                 break;
1886         }
1887
1888         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
1889                 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
1890
1891         /*
1892          * Set various quirk flags.
1893          */
1894
1895         sc->bge_flags |= BGE_FLAG_ETH_WIRESPEED;
1896         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1897             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
1898              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
1899               sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
1900             sc->bge_asicrev == BGE_ASICREV_BCM5906)
1901                 sc->bge_flags &= ~BGE_FLAG_ETH_WIRESPEED;
1902
1903         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
1904             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
1905                 sc->bge_flags |= BGE_FLAG_CRC_BUG;
1906
1907         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
1908             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
1909                 sc->bge_flags |= BGE_FLAG_ADC_BUG;
1910
1911         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
1912                 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
1913
1914         if (BGE_IS_5705_PLUS(sc)) {
1915                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1916                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
1917                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1918                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
1919                         uint32_t product = pci_get_device(dev);
1920
1921                         if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
1922                             product != PCI_PRODUCT_BROADCOM_BCM5756)
1923                                 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
1924                         if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
1925                                 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1926                 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) {
1927                         sc->bge_flags |= BGE_FLAG_BER_BUG;
1928                 }
1929         }
1930
1931         /* Allocate interrupt */
1932         rid = 0;
1933
1934         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1935             RF_SHAREABLE | RF_ACTIVE);
1936
1937         if (sc->bge_irq == NULL) {
1938                 device_printf(dev, "couldn't map interrupt\n");
1939                 error = ENXIO;
1940                 goto fail;
1941         }
1942
1943         /*
1944          * Check if this is a PCI-X or PCI Express device.
1945          */
1946         if (BGE_IS_5705_PLUS(sc)) {
1947                 if (pci_is_pcie(dev)) {
1948                         sc->bge_flags |= BGE_FLAG_PCIE;
1949                         pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1950                 }
1951         } else {
1952                 /*
1953                  * Check if the device is in PCI-X Mode.
1954                  * (This bit is not valid on PCI Express controllers.)
1955                  */
1956                 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1957                     BGE_PCISTATE_PCI_BUSMODE) == 0) {
1958                         sc->bge_flags |= BGE_FLAG_PCIX;
1959                         sc->bge_pcixcap = pci_get_pcixcap_ptr(sc->bge_dev);
1960                 }
1961         }
1962
1963         device_printf(dev, "CHIP ID 0x%08x; "
1964                       "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
1965                       sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
1966                       (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
1967                       : ((sc->bge_flags & BGE_FLAG_PCIE) ?
1968                         "PCI-E" : "PCI"));
1969
1970         /*
1971          * All controllers that are not 5755 or higher have 4GB
1972          * boundary DMA bug.
1973          * Whenever an address crosses a multiple of the 4GB boundary
1974          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
1975          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
1976          * state machine will lockup and cause the device to hang.
1977          */
1978         if (BGE_IS_5755_PLUS(sc) == 0)
1979                 sc->bge_flags |= BGE_FLAG_BOUNDARY_4G;
1980
1981         /*
1982          * The 40bit DMA bug applies to the 5714/5715 controllers and is
1983          * not actually a MAC controller bug but an issue with the embedded
1984          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
1985          */
1986         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
1987                 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT;
1988
1989         ifp = &sc->arpcom.ac_if;
1990         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1991
1992         /* Try to reset the chip. */
1993         bge_reset(sc);
1994
1995         if (bge_chipinit(sc)) {
1996                 device_printf(dev, "chip initialization failed\n");
1997                 error = ENXIO;
1998                 goto fail;
1999         }
2000
2001         /*
2002          * Get station address
2003          */
2004         error = bge_get_eaddr(sc, ether_addr);
2005         if (error) {
2006                 device_printf(dev, "failed to read station address\n");
2007                 goto fail;
2008         }
2009
2010         /* 5705/5750 limits RX return ring to 512 entries. */
2011         if (BGE_IS_5705_PLUS(sc))
2012                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2013         else
2014                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2015
2016         error = bge_dma_alloc(sc);
2017         if (error)
2018                 goto fail;
2019
2020         /* Set default tuneable values. */
2021         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2022         sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
2023         sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
2024         sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
2025         sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
2026
2027         /* Set up ifnet structure */
2028         ifp->if_softc = sc;
2029         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2030         ifp->if_ioctl = bge_ioctl;
2031         ifp->if_start = bge_start;
2032 #ifdef DEVICE_POLLING
2033         ifp->if_poll = bge_poll;
2034 #endif
2035         ifp->if_watchdog = bge_watchdog;
2036         ifp->if_init = bge_init;
2037         ifp->if_mtu = ETHERMTU;
2038         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2039         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2040         ifq_set_ready(&ifp->if_snd);
2041
2042         /*
2043          * 5700 B0 chips do not support checksumming correctly due
2044          * to hardware bugs.
2045          */
2046         if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
2047                 ifp->if_capabilities |= IFCAP_HWCSUM;
2048                 ifp->if_hwassist = BGE_CSUM_FEATURES;
2049         }
2050         ifp->if_capenable = ifp->if_capabilities;
2051
2052         /*
2053          * Figure out what sort of media we have by checking the
2054          * hardware config word in the first 32k of NIC internal memory,
2055          * or fall back to examining the EEPROM if necessary.
2056          * Note: on some BCM5700 cards, this value appears to be unset.
2057          * If that's the case, we have to rely on identifying the NIC
2058          * by its PCI subsystem ID, as we do below for the SysKonnect
2059          * SK-9D41.
2060          */
2061         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2062                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2063         else {
2064                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2065                                     sizeof(hwcfg))) {
2066                         device_printf(dev, "failed to read EEPROM\n");
2067                         error = ENXIO;
2068                         goto fail;
2069                 }
2070                 hwcfg = ntohl(hwcfg);
2071         }
2072
2073         if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2074                 sc->bge_flags |= BGE_FLAG_TBI;
2075
2076         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2077         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
2078                 sc->bge_flags |= BGE_FLAG_TBI;
2079
2080         if (sc->bge_flags & BGE_FLAG_TBI) {
2081                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
2082                     bge_ifmedia_upd, bge_ifmedia_sts);
2083                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2084                 ifmedia_add(&sc->bge_ifmedia,
2085                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2086                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2087                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
2088                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2089         } else {
2090                 /*
2091                  * Do transceiver setup.
2092                  */
2093                 if (mii_phy_probe(dev, &sc->bge_miibus,
2094                     bge_ifmedia_upd, bge_ifmedia_sts)) {
2095                         device_printf(dev, "MII without any PHY!\n");
2096                         error = ENXIO;
2097                         goto fail;
2098                 }
2099         }
2100
2101         /*
2102          * When using the BCM5701 in PCI-X mode, data corruption has
2103          * been observed in the first few bytes of some received packets.
2104          * Aligning the packet buffer in memory eliminates the corruption.
2105          * Unfortunately, this misaligns the packet payloads.  On platforms
2106          * which do not support unaligned accesses, we will realign the
2107          * payloads by copying the received packets.
2108          */
2109         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2110             (sc->bge_flags & BGE_FLAG_PCIX))
2111                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2112
2113         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2114             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2115                 sc->bge_link_upd = bge_bcm5700_link_upd;
2116                 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
2117         } else if (sc->bge_flags & BGE_FLAG_TBI) {
2118                 sc->bge_link_upd = bge_tbi_link_upd;
2119                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2120         } else {
2121                 sc->bge_link_upd = bge_copper_link_upd;
2122                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2123         }
2124
2125         /*
2126          * Create sysctl nodes.
2127          */
2128         sysctl_ctx_init(&sc->bge_sysctl_ctx);
2129         sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
2130                                               SYSCTL_STATIC_CHILDREN(_hw),
2131                                               OID_AUTO,
2132                                               device_get_nameunit(dev),
2133                                               CTLFLAG_RD, 0, "");
2134         if (sc->bge_sysctl_tree == NULL) {
2135                 device_printf(dev, "can't add sysctl node\n");
2136                 error = ENXIO;
2137                 goto fail;
2138         }
2139
2140         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2141                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2142                         OID_AUTO, "rx_coal_ticks",
2143                         CTLTYPE_INT | CTLFLAG_RW,
2144                         sc, 0, bge_sysctl_rx_coal_ticks, "I",
2145                         "Receive coalescing ticks (usec).");
2146         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2147                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2148                         OID_AUTO, "tx_coal_ticks",
2149                         CTLTYPE_INT | CTLFLAG_RW,
2150                         sc, 0, bge_sysctl_tx_coal_ticks, "I",
2151                         "Transmit coalescing ticks (usec).");
2152         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2153                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2154                         OID_AUTO, "rx_max_coal_bds",
2155                         CTLTYPE_INT | CTLFLAG_RW,
2156                         sc, 0, bge_sysctl_rx_max_coal_bds, "I",
2157                         "Receive max coalesced BD count.");
2158         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2159                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2160                         OID_AUTO, "tx_max_coal_bds",
2161                         CTLTYPE_INT | CTLFLAG_RW,
2162                         sc, 0, bge_sysctl_tx_max_coal_bds, "I",
2163                         "Transmit max coalesced BD count.");
2164
2165         /*
2166          * Call MI attach routine.
2167          */
2168         ether_ifattach(ifp, ether_addr, NULL);
2169
2170         error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE,
2171                                bge_intr, sc, &sc->bge_intrhand,
2172                                ifp->if_serializer);
2173         if (error) {
2174                 ether_ifdetach(ifp);
2175                 device_printf(dev, "couldn't set up irq\n");
2176                 goto fail;
2177         }
2178
2179         ifp->if_cpuid = rman_get_cpuid(sc->bge_irq);
2180         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2181
2182         return(0);
2183 fail:
2184         bge_detach(dev);
2185         return(error);
2186 }
2187
2188 static int
2189 bge_detach(device_t dev)
2190 {
2191         struct bge_softc *sc = device_get_softc(dev);
2192
2193         if (device_is_attached(dev)) {
2194                 struct ifnet *ifp = &sc->arpcom.ac_if;
2195
2196                 lwkt_serialize_enter(ifp->if_serializer);
2197                 bge_stop(sc);
2198                 bge_reset(sc);
2199                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2200                 lwkt_serialize_exit(ifp->if_serializer);
2201
2202                 ether_ifdetach(ifp);
2203         }
2204
2205         if (sc->bge_flags & BGE_FLAG_TBI)
2206                 ifmedia_removeall(&sc->bge_ifmedia);
2207         if (sc->bge_miibus)
2208                 device_delete_child(dev, sc->bge_miibus);
2209         bus_generic_detach(dev);
2210
2211         if (sc->bge_irq != NULL)
2212                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
2213
2214         if (sc->bge_res != NULL)
2215                 bus_release_resource(dev, SYS_RES_MEMORY,
2216                     BGE_PCI_BAR0, sc->bge_res);
2217
2218         if (sc->bge_sysctl_tree != NULL)
2219                 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2220
2221         bge_dma_free(sc);
2222
2223         return 0;
2224 }
2225
2226 static void
2227 bge_reset(struct bge_softc *sc)
2228 {
2229         device_t dev;
2230         uint32_t cachesize, command, pcistate, reset;
2231         void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2232         int i, val = 0;
2233
2234         dev = sc->bge_dev;
2235
2236         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2237             sc->bge_asicrev != BGE_ASICREV_BCM5906) {
2238                 if (sc->bge_flags & BGE_FLAG_PCIE)
2239                         write_op = bge_writemem_direct;
2240                 else
2241                         write_op = bge_writemem_ind;
2242         } else {
2243                 write_op = bge_writereg_ind;
2244         }
2245
2246         /* Save some important PCI state. */
2247         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2248         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2249         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2250
2251         pci_write_config(dev, BGE_PCI_MISC_CTL,
2252             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2253             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2254
2255         /* Disable fastboot on controllers that support it. */
2256         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2257             BGE_IS_5755_PLUS(sc)) {
2258                 if (bootverbose)
2259                         if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2260                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2261         }
2262
2263         /*
2264          * Write the magic number to SRAM at offset 0xB50.
2265          * When firmware finishes its initialization it will
2266          * write ~BGE_MAGIC_NUMBER to the same location.
2267          */
2268         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2269
2270         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2271
2272         /* XXX: Broadcom Linux driver. */
2273         if (sc->bge_flags & BGE_FLAG_PCIE) {
2274                 if (CSR_READ_4(sc, 0x7e2c) == 0x60)     /* PCIE 1.0 */
2275                         CSR_WRITE_4(sc, 0x7e2c, 0x20);
2276                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2277                         /* Prevent PCIE link training during global reset */
2278                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2279                         reset |= (1<<29);
2280                 }
2281         }
2282
2283         /*
2284          * Set GPHY Power Down Override to leave GPHY
2285          * powered up in D0 uninitialized.
2286          */
2287         if (BGE_IS_5705_PLUS(sc))
2288                 reset |= 0x04000000;
2289
2290         /* Issue global reset */
2291         write_op(sc, BGE_MISC_CFG, reset);
2292
2293         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2294                 uint32_t status, ctrl;
2295
2296                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2297                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2298                     status | BGE_VCPU_STATUS_DRV_RESET);
2299                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2300                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2301                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2302         }
2303
2304         DELAY(1000);
2305
2306         /* XXX: Broadcom Linux driver. */
2307         if (sc->bge_flags & BGE_FLAG_PCIE) {
2308                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2309                         uint32_t v;
2310
2311                         DELAY(500000); /* wait for link training to complete */
2312                         v = pci_read_config(dev, 0xc4, 4);
2313                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
2314                 }
2315                 /*
2316                  * Set PCIE max payload size to 128 bytes and
2317                  * clear error status.
2318                  */
2319                 pci_write_config(dev, 0xd8, 0xf5000, 4);
2320         }
2321
2322         /* Reset some of the PCI state that got zapped by reset */
2323         pci_write_config(dev, BGE_PCI_MISC_CTL,
2324             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2325             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2326         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2327         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2328         write_op(sc, BGE_MISC_CFG, (65 << 1));
2329
2330         /*
2331          * Disable PCI-X relaxed ordering to ensure status block update
2332          * comes first then packet buffer DMA. Otherwise driver may
2333          * read stale status block.
2334          */
2335         if (sc->bge_flags & BGE_FLAG_PCIX) {
2336                 uint16_t devctl;
2337
2338                 devctl = pci_read_config(dev,
2339                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
2340                 devctl &= ~PCIXM_COMMAND_ERO;
2341                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
2342                         devctl &= ~PCIXM_COMMAND_MAX_READ;
2343                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2344                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2345                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
2346                             PCIXM_COMMAND_MAX_READ);
2347                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2348                 }
2349                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
2350                     devctl, 2);
2351         }
2352
2353         /* Enable memory arbiter. */
2354         if (BGE_IS_5714_FAMILY(sc)) {
2355                 uint32_t val;
2356
2357                 val = CSR_READ_4(sc, BGE_MARB_MODE);
2358                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2359         } else {
2360                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2361         }
2362
2363         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2364                 for (i = 0; i < BGE_TIMEOUT; i++) {
2365                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2366                         if (val & BGE_VCPU_STATUS_INIT_DONE)
2367                                 break;
2368                         DELAY(100);
2369                 }
2370                 if (i == BGE_TIMEOUT) {
2371                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2372                         return;
2373                 }
2374         } else {
2375                 /*
2376                  * Poll until we see the 1's complement of the magic number.
2377                  * This indicates that the firmware initialization
2378                  * is complete.
2379                  */
2380                 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
2381                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2382                         if (val == ~BGE_MAGIC_NUMBER)
2383                                 break;
2384                         DELAY(10);
2385                 }
2386                 if (i == BGE_FIRMWARE_TIMEOUT) {
2387                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
2388                                   "timed out, found 0x%08x\n", val);
2389                         return;
2390                 }
2391         }
2392
2393         /*
2394          * XXX Wait for the value of the PCISTATE register to
2395          * return to its original pre-reset state. This is a
2396          * fairly good indicator of reset completion. If we don't
2397          * wait for the reset to fully complete, trying to read
2398          * from the device's non-PCI registers may yield garbage
2399          * results.
2400          */
2401         for (i = 0; i < BGE_TIMEOUT; i++) {
2402                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2403                         break;
2404                 DELAY(10);
2405         }
2406
2407         if (sc->bge_flags & BGE_FLAG_PCIE) {
2408                 reset = bge_readmem_ind(sc, 0x7c00);
2409                 bge_writemem_ind(sc, 0x7c00, reset | (1 << 25));
2410         }
2411
2412         /* Fix up byte swapping */
2413         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2414             BGE_MODECTL_BYTESWAP_DATA);
2415
2416         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2417
2418         /*
2419          * The 5704 in TBI mode apparently needs some special
2420          * adjustment to insure the SERDES drive level is set
2421          * to 1.2V.
2422          */
2423         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2424             (sc->bge_flags & BGE_FLAG_TBI)) {
2425                 uint32_t serdescfg;
2426
2427                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2428                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2429                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2430         }
2431
2432         /* XXX: Broadcom Linux driver. */
2433         if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2434             sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2435                 uint32_t v;
2436
2437                 v = CSR_READ_4(sc, 0x7c00);
2438                 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2439         }
2440
2441         DELAY(10000);
2442 }
2443
2444 /*
2445  * Frame reception handling. This is called if there's a frame
2446  * on the receive return list.
2447  *
2448  * Note: we have to be able to handle two possibilities here:
2449  * 1) the frame is from the jumbo recieve ring
2450  * 2) the frame is from the standard receive ring
2451  */
2452
2453 static void
2454 bge_rxeof(struct bge_softc *sc)
2455 {
2456         struct ifnet *ifp;
2457         int stdcnt = 0, jumbocnt = 0;
2458
2459         if (sc->bge_rx_saved_considx ==
2460             sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2461                 return;
2462
2463         ifp = &sc->arpcom.ac_if;
2464
2465         while (sc->bge_rx_saved_considx !=
2466                sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2467                 struct bge_rx_bd        *cur_rx;
2468                 uint32_t                rxidx;
2469                 struct mbuf             *m = NULL;
2470                 uint16_t                vlan_tag = 0;
2471                 int                     have_tag = 0;
2472
2473                 cur_rx =
2474             &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2475
2476                 rxidx = cur_rx->bge_idx;
2477                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2478                 logif(rx_pkt);
2479
2480                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2481                         have_tag = 1;
2482                         vlan_tag = cur_rx->bge_vlan_tag;
2483                 }
2484
2485                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2486                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2487                         jumbocnt++;
2488
2489                         if (rxidx != sc->bge_jumbo) {
2490                                 ifp->if_ierrors++;
2491                                 if_printf(ifp, "sw jumbo index(%d) "
2492                                     "and hw jumbo index(%d) mismatch, drop!\n",
2493                                     sc->bge_jumbo, rxidx);
2494                                 bge_setup_rxdesc_jumbo(sc, rxidx);
2495                                 continue;
2496                         }
2497
2498                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf;
2499                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2500                                 ifp->if_ierrors++;
2501                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2502                                 continue;
2503                         }
2504                         if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) {
2505                                 ifp->if_ierrors++;
2506                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2507                                 continue;
2508                         }
2509                 } else {
2510                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2511                         stdcnt++;
2512
2513                         if (rxidx != sc->bge_std) {
2514                                 ifp->if_ierrors++;
2515                                 if_printf(ifp, "sw std index(%d) "
2516                                     "and hw std index(%d) mismatch, drop!\n",
2517                                     sc->bge_std, rxidx);
2518                                 bge_setup_rxdesc_std(sc, rxidx);
2519                                 continue;
2520                         }
2521
2522                         m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf;
2523                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2524                                 ifp->if_ierrors++;
2525                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2526                                 continue;
2527                         }
2528                         if (bge_newbuf_std(sc, sc->bge_std, 0)) {
2529                                 ifp->if_ierrors++;
2530                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2531                                 continue;
2532                         }
2533                 }
2534
2535                 ifp->if_ipackets++;
2536 #if !defined(__i386__) && !defined(__x86_64__)
2537                 /*
2538                  * The x86 allows unaligned accesses, but for other
2539                  * platforms we must make sure the payload is aligned.
2540                  */
2541                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2542                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2543                             cur_rx->bge_len);
2544                         m->m_data += ETHER_ALIGN;
2545                 }
2546 #endif
2547                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2548                 m->m_pkthdr.rcvif = ifp;
2549
2550                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2551                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2552                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2553                                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2554                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2555                         }
2556                         if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
2557                             m->m_pkthdr.len >= BGE_MIN_FRAME) {
2558                                 m->m_pkthdr.csum_data =
2559                                         cur_rx->bge_tcp_udp_csum;
2560                                 m->m_pkthdr.csum_flags |=
2561                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2562                         }
2563                 }
2564
2565                 /*
2566                  * If we received a packet with a vlan tag, pass it
2567                  * to vlan_input() instead of ether_input().
2568                  */
2569                 if (have_tag) {
2570                         m->m_flags |= M_VLANTAG;
2571                         m->m_pkthdr.ether_vlantag = vlan_tag;
2572                         have_tag = vlan_tag = 0;
2573                 }
2574                 ifp->if_input(ifp, m);
2575         }
2576
2577         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2578         if (stdcnt)
2579                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2580         if (jumbocnt)
2581                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2582 }
2583
2584 static void
2585 bge_txeof(struct bge_softc *sc)
2586 {
2587         struct bge_tx_bd *cur_tx = NULL;
2588         struct ifnet *ifp;
2589
2590         if (sc->bge_tx_saved_considx ==
2591             sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2592                 return;
2593
2594         ifp = &sc->arpcom.ac_if;
2595
2596         /*
2597          * Go through our tx ring and free mbufs for those
2598          * frames that have been sent.
2599          */
2600         while (sc->bge_tx_saved_considx !=
2601                sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2602                 uint32_t idx = 0;
2603
2604                 idx = sc->bge_tx_saved_considx;
2605                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2606                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2607                         ifp->if_opackets++;
2608                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2609                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
2610                             sc->bge_cdata.bge_tx_dmamap[idx]);
2611                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2612                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2613                 }
2614                 sc->bge_txcnt--;
2615                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2616                 logif(tx_pkt);
2617         }
2618
2619         if (cur_tx != NULL &&
2620             (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2621             (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2622                 ifp->if_flags &= ~IFF_OACTIVE;
2623
2624         if (sc->bge_txcnt == 0)
2625                 ifp->if_timer = 0;
2626
2627         if (!ifq_is_empty(&ifp->if_snd))
2628                 if_devstart(ifp);
2629 }
2630
2631 #ifdef DEVICE_POLLING
2632
2633 static void
2634 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2635 {
2636         struct bge_softc *sc = ifp->if_softc;
2637         uint32_t status;
2638
2639         switch(cmd) {
2640         case POLL_REGISTER:
2641                 bge_disable_intr(sc);
2642                 break;
2643         case POLL_DEREGISTER:
2644                 bge_enable_intr(sc);
2645                 break;
2646         case POLL_AND_CHECK_STATUS:
2647                 /*
2648                  * Process link state changes.
2649                  */
2650                 status = CSR_READ_4(sc, BGE_MAC_STS);
2651                 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2652                         sc->bge_link_evt = 0;
2653                         sc->bge_link_upd(sc, status);
2654                 }
2655                 /* fall through */
2656         case POLL_ONLY:
2657                 if (ifp->if_flags & IFF_RUNNING) {
2658                         bge_rxeof(sc);
2659                         bge_txeof(sc);
2660                 }
2661                 break;
2662         }
2663 }
2664
2665 #endif
2666
2667 static void
2668 bge_intr(void *xsc)
2669 {
2670         struct bge_softc *sc = xsc;
2671         struct ifnet *ifp = &sc->arpcom.ac_if;
2672         uint32_t status;
2673
2674         logif(intr);
2675
2676         /*
2677          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
2678          * disable interrupts by writing nonzero like we used to, since with
2679          * our current organization this just gives complications and
2680          * pessimizations for re-enabling interrupts.  We used to have races
2681          * instead of the necessary complications.  Disabling interrupts
2682          * would just reduce the chance of a status update while we are
2683          * running (by switching to the interrupt-mode coalescence
2684          * parameters), but this chance is already very low so it is more
2685          * efficient to get another interrupt than prevent it.
2686          *
2687          * We do the ack first to ensure another interrupt if there is a
2688          * status update after the ack.  We don't check for the status
2689          * changing later because it is more efficient to get another
2690          * interrupt than prevent it, not quite as above (not checking is
2691          * a smaller optimization than not toggling the interrupt enable,
2692          * since checking doesn't involve PCI accesses and toggling require
2693          * the status check).  So toggling would probably be a pessimization
2694          * even with MSI.  It would only be needed for using a task queue.
2695          */
2696         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
2697
2698         /*
2699          * Process link state changes.
2700          */
2701         status = CSR_READ_4(sc, BGE_MAC_STS);
2702         if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2703                 sc->bge_link_evt = 0;
2704                 sc->bge_link_upd(sc, status);
2705         }
2706
2707         if (ifp->if_flags & IFF_RUNNING) {
2708                 /* Check RX return ring producer/consumer */
2709                 bge_rxeof(sc);
2710
2711                 /* Check TX ring producer/consumer */
2712                 bge_txeof(sc);
2713         }
2714
2715         if (sc->bge_coal_chg)
2716                 bge_coal_change(sc);
2717 }
2718
2719 static void
2720 bge_tick(void *xsc)
2721 {
2722         struct bge_softc *sc = xsc;
2723         struct ifnet *ifp = &sc->arpcom.ac_if;
2724
2725         lwkt_serialize_enter(ifp->if_serializer);
2726
2727         if (BGE_IS_5705_PLUS(sc))
2728                 bge_stats_update_regs(sc);
2729         else
2730                 bge_stats_update(sc);
2731
2732         if (sc->bge_flags & BGE_FLAG_TBI) {
2733                 /*
2734                  * Since in TBI mode auto-polling can't be used we should poll
2735                  * link status manually. Here we register pending link event
2736                  * and trigger interrupt.
2737                  */
2738                 sc->bge_link_evt++;
2739                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
2740         } else if (!sc->bge_link) {
2741                 mii_tick(device_get_softc(sc->bge_miibus));
2742         }
2743
2744         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2745
2746         lwkt_serialize_exit(ifp->if_serializer);
2747 }
2748
2749 static void
2750 bge_stats_update_regs(struct bge_softc *sc)
2751 {
2752         struct ifnet *ifp = &sc->arpcom.ac_if;
2753         struct bge_mac_stats_regs stats;
2754         uint32_t *s;
2755         int i;
2756
2757         s = (uint32_t *)&stats;
2758         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2759                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2760                 s++;
2761         }
2762
2763         ifp->if_collisions +=
2764            (stats.dot3StatsSingleCollisionFrames +
2765            stats.dot3StatsMultipleCollisionFrames +
2766            stats.dot3StatsExcessiveCollisions +
2767            stats.dot3StatsLateCollisions) -
2768            ifp->if_collisions;
2769 }
2770
2771 static void
2772 bge_stats_update(struct bge_softc *sc)
2773 {
2774         struct ifnet *ifp = &sc->arpcom.ac_if;
2775         bus_size_t stats;
2776
2777         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
2778
2779 #define READ_STAT(sc, stats, stat)      \
2780         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
2781
2782         ifp->if_collisions +=
2783            (READ_STAT(sc, stats,
2784                 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
2785             READ_STAT(sc, stats,
2786                 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2787             READ_STAT(sc, stats,
2788                 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
2789             READ_STAT(sc, stats,
2790                 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
2791            ifp->if_collisions;
2792
2793 #undef READ_STAT
2794
2795 #ifdef notdef
2796         ifp->if_collisions +=
2797            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2798            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2799            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2800            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2801            ifp->if_collisions;
2802 #endif
2803 }
2804
2805 /*
2806  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2807  * pointers to descriptors.
2808  */
2809 static int
2810 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
2811 {
2812         struct bge_tx_bd *d = NULL;
2813         uint16_t csum_flags = 0;
2814         bus_dma_segment_t segs[BGE_NSEG_NEW];
2815         bus_dmamap_t map;
2816         int error, maxsegs, nsegs, idx, i;
2817         struct mbuf *m_head = *m_head0;
2818
2819         if (m_head->m_pkthdr.csum_flags) {
2820                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2821                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2822                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2823                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2824                 if (m_head->m_flags & M_LASTFRAG)
2825                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2826                 else if (m_head->m_flags & M_FRAG)
2827                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2828         }
2829
2830         idx = *txidx;
2831         map = sc->bge_cdata.bge_tx_dmamap[idx];
2832
2833         maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
2834         KASSERT(maxsegs >= BGE_NSEG_SPARE,
2835                 ("not enough segments %d", maxsegs));
2836
2837         if (maxsegs > BGE_NSEG_NEW)
2838                 maxsegs = BGE_NSEG_NEW;
2839
2840         /*
2841          * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
2842          * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
2843          * but when such padded frames employ the bge IP/TCP checksum
2844          * offload, the hardware checksum assist gives incorrect results
2845          * (possibly from incorporating its own padding into the UDP/TCP
2846          * checksum; who knows).  If we pad such runts with zeros, the
2847          * onboard checksum comes out correct.
2848          */
2849         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2850             m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2851                 error = m_devpad(m_head, BGE_MIN_FRAME);
2852                 if (error)
2853                         goto back;
2854         }
2855
2856         error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map,
2857                         m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2858         if (error)
2859                 goto back;
2860
2861         m_head = *m_head0;
2862         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2863
2864         for (i = 0; ; i++) {
2865                 d = &sc->bge_ldata.bge_tx_ring[idx];
2866
2867                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
2868                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
2869                 d->bge_len = segs[i].ds_len;
2870                 d->bge_flags = csum_flags;
2871
2872                 if (i == nsegs - 1)
2873                         break;
2874                 BGE_INC(idx, BGE_TX_RING_CNT);
2875         }
2876         /* Mark the last segment as end of packet... */
2877         d->bge_flags |= BGE_TXBDFLAG_END;
2878
2879         /* Set vlan tag to the first segment of the packet. */
2880         d = &sc->bge_ldata.bge_tx_ring[*txidx];
2881         if (m_head->m_flags & M_VLANTAG) {
2882                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2883                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
2884         } else {
2885                 d->bge_vlan_tag = 0;
2886         }
2887
2888         /*
2889          * Insure that the map for this transmission is placed at
2890          * the array index of the last descriptor in this chain.
2891          */
2892         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
2893         sc->bge_cdata.bge_tx_dmamap[idx] = map;
2894         sc->bge_cdata.bge_tx_chain[idx] = m_head;
2895         sc->bge_txcnt += nsegs;
2896
2897         BGE_INC(idx, BGE_TX_RING_CNT);
2898         *txidx = idx;
2899 back:
2900         if (error) {
2901                 m_freem(*m_head0);
2902                 *m_head0 = NULL;
2903         }
2904         return error;
2905 }
2906
2907 /*
2908  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2909  * to the mbuf data regions directly in the transmit descriptors.
2910  */
2911 static void
2912 bge_start(struct ifnet *ifp)
2913 {
2914         struct bge_softc *sc = ifp->if_softc;
2915         struct mbuf *m_head = NULL;
2916         uint32_t prodidx;
2917         int need_trans;
2918
2919         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2920                 return;
2921
2922         prodidx = sc->bge_tx_prodidx;
2923
2924         need_trans = 0;
2925         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2926                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2927                 if (m_head == NULL)
2928                         break;
2929
2930                 /*
2931                  * XXX
2932                  * The code inside the if() block is never reached since we
2933                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2934                  * requests to checksum TCP/UDP in a fragmented packet.
2935                  *
2936                  * XXX
2937                  * safety overkill.  If this is a fragmented packet chain
2938                  * with delayed TCP/UDP checksums, then only encapsulate
2939                  * it if we have enough descriptors to handle the entire
2940                  * chain at once.
2941                  * (paranoia -- may not actually be needed)
2942                  */
2943                 if ((m_head->m_flags & M_FIRSTFRAG) &&
2944                     (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
2945                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2946                             m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
2947                                 ifp->if_flags |= IFF_OACTIVE;
2948                                 ifq_prepend(&ifp->if_snd, m_head);
2949                                 break;
2950                         }
2951                 }
2952
2953                 /*
2954                  * Sanity check: avoid coming within BGE_NSEG_RSVD
2955                  * descriptors of the end of the ring.  Also make
2956                  * sure there are BGE_NSEG_SPARE descriptors for
2957                  * jumbo buffers' defragmentation.
2958                  */
2959                 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2960                     (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
2961                         ifp->if_flags |= IFF_OACTIVE;
2962                         ifq_prepend(&ifp->if_snd, m_head);
2963                         break;
2964                 }
2965
2966                 /*
2967                  * Pack the data into the transmit ring. If we
2968                  * don't have room, set the OACTIVE flag and wait
2969                  * for the NIC to drain the ring.
2970                  */
2971                 if (bge_encap(sc, &m_head, &prodidx)) {
2972                         ifp->if_flags |= IFF_OACTIVE;
2973                         ifp->if_oerrors++;
2974                         break;
2975                 }
2976                 need_trans = 1;
2977
2978                 ETHER_BPF_MTAP(ifp, m_head);
2979         }
2980
2981         if (!need_trans)
2982                 return;
2983
2984         /* Transmit */
2985         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2986         /* 5700 b2 errata */
2987         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2988                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2989
2990         sc->bge_tx_prodidx = prodidx;
2991
2992         /*
2993          * Set a timeout in case the chip goes out to lunch.
2994          */
2995         ifp->if_timer = 5;
2996 }
2997
2998 static void
2999 bge_init(void *xsc)
3000 {
3001         struct bge_softc *sc = xsc;
3002         struct ifnet *ifp = &sc->arpcom.ac_if;
3003         uint16_t *m;
3004
3005         ASSERT_SERIALIZED(ifp->if_serializer);
3006
3007         if (ifp->if_flags & IFF_RUNNING)
3008                 return;
3009
3010         /* Cancel pending I/O and flush buffers. */
3011         bge_stop(sc);
3012         bge_reset(sc);
3013         bge_chipinit(sc);
3014
3015         /*
3016          * Init the various state machines, ring
3017          * control blocks and firmware.
3018          */
3019         if (bge_blockinit(sc)) {
3020                 if_printf(ifp, "initialization failure\n");
3021                 bge_stop(sc);
3022                 return;
3023         }
3024
3025         /* Specify MTU. */
3026         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3027             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3028
3029         /* Load our MAC address. */
3030         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3031         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3032         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3033
3034         /* Enable or disable promiscuous mode as needed. */
3035         bge_setpromisc(sc);
3036
3037         /* Program multicast filter. */
3038         bge_setmulti(sc);
3039
3040         /* Init RX ring. */
3041         if (bge_init_rx_ring_std(sc)) {
3042                 if_printf(ifp, "RX ring initialization failed\n");
3043                 bge_stop(sc);
3044                 return;
3045         }
3046
3047         /*
3048          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3049          * memory to insure that the chip has in fact read the first
3050          * entry of the ring.
3051          */
3052         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3053                 uint32_t                v, i;
3054                 for (i = 0; i < 10; i++) {
3055                         DELAY(20);
3056                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3057                         if (v == (MCLBYTES - ETHER_ALIGN))
3058                                 break;
3059                 }
3060                 if (i == 10)
3061                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
3062         }
3063
3064         /* Init jumbo RX ring. */
3065         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3066                 if (bge_init_rx_ring_jumbo(sc)) {
3067                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
3068                         bge_stop(sc);
3069                         return;
3070                 }
3071         }
3072
3073         /* Init our RX return ring index */
3074         sc->bge_rx_saved_considx = 0;
3075
3076         /* Init TX ring. */
3077         bge_init_tx_ring(sc);
3078
3079         /* Turn on transmitter */
3080         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
3081
3082         /* Turn on receiver */
3083         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3084
3085         /* Tell firmware we're alive. */
3086         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3087
3088         /* Enable host interrupts if polling(4) is not enabled. */
3089         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
3090 #ifdef DEVICE_POLLING
3091         if (ifp->if_flags & IFF_POLLING)
3092                 bge_disable_intr(sc);
3093         else
3094 #endif
3095         bge_enable_intr(sc);
3096
3097         bge_ifmedia_upd(ifp);
3098
3099         ifp->if_flags |= IFF_RUNNING;
3100         ifp->if_flags &= ~IFF_OACTIVE;
3101
3102         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3103 }
3104
3105 /*
3106  * Set media options.
3107  */
3108 static int
3109 bge_ifmedia_upd(struct ifnet *ifp)
3110 {
3111         struct bge_softc *sc = ifp->if_softc;
3112
3113         /* If this is a 1000baseX NIC, enable the TBI port. */
3114         if (sc->bge_flags & BGE_FLAG_TBI) {
3115                 struct ifmedia *ifm = &sc->bge_ifmedia;
3116
3117                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3118                         return(EINVAL);
3119
3120                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3121                 case IFM_AUTO:
3122                         /*
3123                          * The BCM5704 ASIC appears to have a special
3124                          * mechanism for programming the autoneg
3125                          * advertisement registers in TBI mode.
3126                          */
3127                         if (!bge_fake_autoneg &&
3128                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3129                                 uint32_t sgdig;
3130
3131                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3132                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3133                                 sgdig |= BGE_SGDIGCFG_AUTO |
3134                                          BGE_SGDIGCFG_PAUSE_CAP |
3135                                          BGE_SGDIGCFG_ASYM_PAUSE;
3136                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3137                                             sgdig | BGE_SGDIGCFG_SEND);
3138                                 DELAY(5);
3139                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3140                         }
3141                         break;
3142                 case IFM_1000_SX:
3143                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3144                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3145                                     BGE_MACMODE_HALF_DUPLEX);
3146                         } else {
3147                                 BGE_SETBIT(sc, BGE_MAC_MODE,
3148                                     BGE_MACMODE_HALF_DUPLEX);
3149                         }
3150                         break;
3151                 default:
3152                         return(EINVAL);
3153                 }
3154         } else {
3155                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3156
3157                 sc->bge_link_evt++;
3158                 sc->bge_link = 0;
3159                 if (mii->mii_instance) {
3160                         struct mii_softc *miisc;
3161
3162                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3163                                 mii_phy_reset(miisc);
3164                 }
3165                 mii_mediachg(mii);
3166         }
3167         return(0);
3168 }
3169
3170 /*
3171  * Report current media status.
3172  */
3173 static void
3174 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3175 {
3176         struct bge_softc *sc = ifp->if_softc;
3177
3178         if (sc->bge_flags & BGE_FLAG_TBI) {
3179                 ifmr->ifm_status = IFM_AVALID;
3180                 ifmr->ifm_active = IFM_ETHER;
3181                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3182                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3183                         ifmr->ifm_status |= IFM_ACTIVE;
3184                 } else {
3185                         ifmr->ifm_active |= IFM_NONE;
3186                         return;
3187                 }
3188
3189                 ifmr->ifm_active |= IFM_1000_SX;
3190                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3191                         ifmr->ifm_active |= IFM_HDX;
3192                 else
3193                         ifmr->ifm_active |= IFM_FDX;
3194         } else {
3195                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3196
3197                 mii_pollstat(mii);
3198                 ifmr->ifm_active = mii->mii_media_active;
3199                 ifmr->ifm_status = mii->mii_media_status;
3200         }
3201 }
3202
3203 static int
3204 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3205 {
3206         struct bge_softc *sc = ifp->if_softc;
3207         struct ifreq *ifr = (struct ifreq *)data;
3208         int mask, error = 0;
3209
3210         ASSERT_SERIALIZED(ifp->if_serializer);
3211
3212         switch (command) {
3213         case SIOCSIFMTU:
3214                 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3215                     (BGE_IS_JUMBO_CAPABLE(sc) &&
3216                      ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3217                         error = EINVAL;
3218                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3219                         ifp->if_mtu = ifr->ifr_mtu;
3220                         ifp->if_flags &= ~IFF_RUNNING;
3221                         bge_init(sc);
3222                 }
3223                 break;
3224         case SIOCSIFFLAGS:
3225                 if (ifp->if_flags & IFF_UP) {
3226                         if (ifp->if_flags & IFF_RUNNING) {
3227                                 mask = ifp->if_flags ^ sc->bge_if_flags;
3228
3229                                 /*
3230                                  * If only the state of the PROMISC flag
3231                                  * changed, then just use the 'set promisc
3232                                  * mode' command instead of reinitializing
3233                                  * the entire NIC. Doing a full re-init
3234                                  * means reloading the firmware and waiting
3235                                  * for it to start up, which may take a
3236                                  * second or two.  Similarly for ALLMULTI.
3237                                  */
3238                                 if (mask & IFF_PROMISC)
3239                                         bge_setpromisc(sc);
3240                                 if (mask & IFF_ALLMULTI)
3241                                         bge_setmulti(sc);
3242                         } else {
3243                                 bge_init(sc);
3244                         }
3245                 } else {
3246                         if (ifp->if_flags & IFF_RUNNING)
3247                                 bge_stop(sc);
3248                 }
3249                 sc->bge_if_flags = ifp->if_flags;
3250                 break;
3251         case SIOCADDMULTI:
3252         case SIOCDELMULTI:
3253                 if (ifp->if_flags & IFF_RUNNING)
3254                         bge_setmulti(sc);
3255                 break;
3256         case SIOCSIFMEDIA:
3257         case SIOCGIFMEDIA:
3258                 if (sc->bge_flags & BGE_FLAG_TBI) {
3259                         error = ifmedia_ioctl(ifp, ifr,
3260                             &sc->bge_ifmedia, command);
3261                 } else {
3262                         struct mii_data *mii;
3263
3264                         mii = device_get_softc(sc->bge_miibus);
3265                         error = ifmedia_ioctl(ifp, ifr,
3266                                               &mii->mii_media, command);
3267                 }
3268                 break;
3269         case SIOCSIFCAP:
3270                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3271                 if (mask & IFCAP_HWCSUM) {
3272                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3273                         if (IFCAP_HWCSUM & ifp->if_capenable)
3274                                 ifp->if_hwassist = BGE_CSUM_FEATURES;
3275                         else
3276                                 ifp->if_hwassist = 0;
3277                 }
3278                 break;
3279         default:
3280                 error = ether_ioctl(ifp, command, data);
3281                 break;
3282         }
3283         return error;
3284 }
3285
3286 static void
3287 bge_watchdog(struct ifnet *ifp)
3288 {
3289         struct bge_softc *sc = ifp->if_softc;
3290
3291         if_printf(ifp, "watchdog timeout -- resetting\n");
3292
3293         ifp->if_flags &= ~IFF_RUNNING;
3294         bge_init(sc);
3295
3296         ifp->if_oerrors++;
3297
3298         if (!ifq_is_empty(&ifp->if_snd))
3299                 if_devstart(ifp);
3300 }
3301
3302 /*
3303  * Stop the adapter and free any mbufs allocated to the
3304  * RX and TX lists.
3305  */
3306 static void
3307 bge_stop(struct bge_softc *sc)
3308 {
3309         struct ifnet *ifp = &sc->arpcom.ac_if;
3310
3311         ASSERT_SERIALIZED(ifp->if_serializer);
3312
3313         callout_stop(&sc->bge_stat_timer);
3314
3315         /*
3316          * Disable all of the receiver blocks
3317          */
3318         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3319         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3320         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3321         if (!BGE_IS_5705_PLUS(sc))
3322                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3323         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3324         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3325         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3326
3327         /*
3328          * Disable all of the transmit blocks
3329          */
3330         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3331         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3332         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3333         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3334         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3335         if (!BGE_IS_5705_PLUS(sc))
3336                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3337         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3338
3339         /*
3340          * Shut down all of the memory managers and related
3341          * state machines.
3342          */
3343         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3344         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3345         if (!BGE_IS_5705_PLUS(sc))
3346                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3347         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3348         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3349         if (!BGE_IS_5705_PLUS(sc)) {
3350                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3351                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3352         }
3353
3354         /* Disable host interrupts. */
3355         bge_disable_intr(sc);
3356
3357         /*
3358          * Tell firmware we're shutting down.
3359          */
3360         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3361
3362         /* Free the RX lists. */
3363         bge_free_rx_ring_std(sc);
3364
3365         /* Free jumbo RX list. */
3366         if (BGE_IS_JUMBO_CAPABLE(sc))
3367                 bge_free_rx_ring_jumbo(sc);
3368
3369         /* Free TX buffers. */
3370         bge_free_tx_ring(sc);
3371
3372         sc->bge_link = 0;
3373         sc->bge_coal_chg = 0;
3374
3375         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3376
3377         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3378         ifp->if_timer = 0;
3379 }
3380
3381 /*
3382  * Stop all chip I/O so that the kernel's probe routines don't
3383  * get confused by errant DMAs when rebooting.
3384  */
3385 static void
3386 bge_shutdown(device_t dev)
3387 {
3388         struct bge_softc *sc = device_get_softc(dev);
3389         struct ifnet *ifp = &sc->arpcom.ac_if;
3390
3391         lwkt_serialize_enter(ifp->if_serializer);
3392         bge_stop(sc);
3393         bge_reset(sc);
3394         lwkt_serialize_exit(ifp->if_serializer);
3395 }
3396
3397 static int
3398 bge_suspend(device_t dev)
3399 {
3400         struct bge_softc *sc = device_get_softc(dev);
3401         struct ifnet *ifp = &sc->arpcom.ac_if;
3402
3403         lwkt_serialize_enter(ifp->if_serializer);
3404         bge_stop(sc);
3405         lwkt_serialize_exit(ifp->if_serializer);
3406
3407         return 0;
3408 }
3409
3410 static int
3411 bge_resume(device_t dev)
3412 {
3413         struct bge_softc *sc = device_get_softc(dev);
3414         struct ifnet *ifp = &sc->arpcom.ac_if;
3415
3416         lwkt_serialize_enter(ifp->if_serializer);
3417
3418         if (ifp->if_flags & IFF_UP) {
3419                 bge_init(sc);
3420
3421                 if (!ifq_is_empty(&ifp->if_snd))
3422                         if_devstart(ifp);
3423         }
3424
3425         lwkt_serialize_exit(ifp->if_serializer);
3426
3427         return 0;
3428 }
3429
3430 static void
3431 bge_setpromisc(struct bge_softc *sc)
3432 {
3433         struct ifnet *ifp = &sc->arpcom.ac_if;
3434
3435         if (ifp->if_flags & IFF_PROMISC)
3436                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3437         else
3438                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3439 }
3440
3441 static void
3442 bge_dma_free(struct bge_softc *sc)
3443 {
3444         int i;
3445
3446         /* Destroy RX mbuf DMA stuffs. */
3447         if (sc->bge_cdata.bge_rx_mtag != NULL) {
3448                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3449                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3450                             sc->bge_cdata.bge_rx_std_dmamap[i]);
3451                 }
3452                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3453                                    sc->bge_cdata.bge_rx_tmpmap);
3454                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3455         }
3456
3457         /* Destroy TX mbuf DMA stuffs. */
3458         if (sc->bge_cdata.bge_tx_mtag != NULL) {
3459                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3460                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3461                             sc->bge_cdata.bge_tx_dmamap[i]);
3462                 }
3463                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3464         }
3465
3466         /* Destroy standard RX ring */
3467         bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3468                            sc->bge_cdata.bge_rx_std_ring_map,
3469                            sc->bge_ldata.bge_rx_std_ring);
3470
3471         if (BGE_IS_JUMBO_CAPABLE(sc))
3472                 bge_free_jumbo_mem(sc);
3473
3474         /* Destroy RX return ring */
3475         bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3476                            sc->bge_cdata.bge_rx_return_ring_map,
3477                            sc->bge_ldata.bge_rx_return_ring);
3478
3479         /* Destroy TX ring */
3480         bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3481                            sc->bge_cdata.bge_tx_ring_map,
3482                            sc->bge_ldata.bge_tx_ring);
3483
3484         /* Destroy status block */
3485         bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3486                            sc->bge_cdata.bge_status_map,
3487                            sc->bge_ldata.bge_status_block);
3488
3489         /* Destroy statistics block */
3490         bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3491                            sc->bge_cdata.bge_stats_map,
3492                            sc->bge_ldata.bge_stats);
3493
3494         /* Destroy the parent tag */
3495         if (sc->bge_cdata.bge_parent_tag != NULL)
3496                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3497 }
3498
3499 static int
3500 bge_dma_alloc(struct bge_softc *sc)
3501 {
3502         struct ifnet *ifp = &sc->arpcom.ac_if;
3503         int i, error;
3504         bus_addr_t lowaddr;
3505         bus_size_t boundary;
3506
3507         boundary = 0;
3508         if (sc->bge_flags & BGE_FLAG_BOUNDARY_4G)
3509                 boundary = BGE_DMA_BOUNDARY_4G;
3510
3511         lowaddr = BUS_SPACE_MAXADDR;
3512         if (sc->bge_flags & BGE_FLAG_MAXADDR_40BIT)
3513                 lowaddr = BGE_DMA_MAXADDR_40BIT;
3514
3515         /*
3516          * Allocate the parent bus DMA tag appropriate for PCI.
3517          */
3518         error = bus_dma_tag_create(NULL, 1, boundary,
3519                                    lowaddr, BUS_SPACE_MAXADDR,
3520                                    NULL, NULL,
3521                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3522                                    BUS_SPACE_MAXSIZE_32BIT,
3523                                    0, &sc->bge_cdata.bge_parent_tag);
3524         if (error) {
3525                 if_printf(ifp, "could not allocate parent dma tag\n");
3526                 return error;
3527         }
3528
3529         /*
3530          * Create DMA tag and maps for RX mbufs.
3531          */
3532         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3533                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3534                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
3535                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3536                                    &sc->bge_cdata.bge_rx_mtag);
3537         if (error) {
3538                 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
3539                 return error;
3540         }
3541
3542         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3543                                   BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_tmpmap);
3544         if (error) {
3545                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3546                 sc->bge_cdata.bge_rx_mtag = NULL;
3547                 return error;
3548         }
3549
3550         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3551                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3552                                           BUS_DMA_WAITOK,
3553                                           &sc->bge_cdata.bge_rx_std_dmamap[i]);
3554                 if (error) {
3555                         int j;
3556
3557                         for (j = 0; j < i; ++j) {
3558                                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3559                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3560                         }
3561                         bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3562                         sc->bge_cdata.bge_rx_mtag = NULL;
3563
3564                         if_printf(ifp, "could not create DMA map for RX\n");
3565                         return error;
3566                 }
3567         }
3568
3569         /*
3570          * Create DMA tag and maps for TX mbufs.
3571          */
3572         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3573                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3574                                    NULL, NULL,
3575                                    BGE_JUMBO_FRAMELEN, BGE_NSEG_NEW, MCLBYTES,
3576                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
3577                                    BUS_DMA_ONEBPAGE,
3578                                    &sc->bge_cdata.bge_tx_mtag);
3579         if (error) {
3580                 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
3581                 return error;
3582         }
3583
3584         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3585                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag,
3586                                           BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
3587                                           &sc->bge_cdata.bge_tx_dmamap[i]);
3588                 if (error) {
3589                         int j;
3590
3591                         for (j = 0; j < i; ++j) {
3592                                 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3593                                         sc->bge_cdata.bge_tx_dmamap[j]);
3594                         }
3595                         bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3596                         sc->bge_cdata.bge_tx_mtag = NULL;
3597
3598                         if_printf(ifp, "could not create DMA map for TX\n");
3599                         return error;
3600                 }
3601         }
3602
3603         /*
3604          * Create DMA stuffs for standard RX ring.
3605          */
3606         error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3607                                     &sc->bge_cdata.bge_rx_std_ring_tag,
3608                                     &sc->bge_cdata.bge_rx_std_ring_map,
3609                                     (void *)&sc->bge_ldata.bge_rx_std_ring,
3610                                     &sc->bge_ldata.bge_rx_std_ring_paddr);
3611         if (error) {
3612                 if_printf(ifp, "could not create std RX ring\n");
3613                 return error;
3614         }
3615
3616         /*
3617          * Create jumbo buffer pool.
3618          */
3619         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3620                 error = bge_alloc_jumbo_mem(sc);
3621                 if (error) {
3622                         if_printf(ifp, "could not create jumbo buffer pool\n");
3623                         return error;
3624                 }
3625         }
3626
3627         /*
3628          * Create DMA stuffs for RX return ring.
3629          */
3630         error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3631                                     &sc->bge_cdata.bge_rx_return_ring_tag,
3632                                     &sc->bge_cdata.bge_rx_return_ring_map,
3633                                     (void *)&sc->bge_ldata.bge_rx_return_ring,
3634                                     &sc->bge_ldata.bge_rx_return_ring_paddr);
3635         if (error) {
3636                 if_printf(ifp, "could not create RX ret ring\n");
3637                 return error;
3638         }
3639
3640         /*
3641          * Create DMA stuffs for TX ring.
3642          */
3643         error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
3644                                     &sc->bge_cdata.bge_tx_ring_tag,
3645                                     &sc->bge_cdata.bge_tx_ring_map,
3646                                     (void *)&sc->bge_ldata.bge_tx_ring,
3647                                     &sc->bge_ldata.bge_tx_ring_paddr);
3648         if (error) {
3649                 if_printf(ifp, "could not create TX ring\n");
3650                 return error;
3651         }
3652
3653         /*
3654          * Create DMA stuffs for status block.
3655          */
3656         error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3657                                     &sc->bge_cdata.bge_status_tag,
3658                                     &sc->bge_cdata.bge_status_map,
3659                                     (void *)&sc->bge_ldata.bge_status_block,
3660                                     &sc->bge_ldata.bge_status_block_paddr);
3661         if (error) {
3662                 if_printf(ifp, "could not create status block\n");
3663                 return error;
3664         }
3665
3666         /*
3667          * Create DMA stuffs for statistics block.
3668          */
3669         error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
3670                                     &sc->bge_cdata.bge_stats_tag,
3671                                     &sc->bge_cdata.bge_stats_map,
3672                                     (void *)&sc->bge_ldata.bge_stats,
3673                                     &sc->bge_ldata.bge_stats_paddr);
3674         if (error) {
3675                 if_printf(ifp, "could not create stats block\n");
3676                 return error;
3677         }
3678         return 0;
3679 }
3680
3681 static int
3682 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3683                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3684 {
3685         bus_dmamem_t dmem;
3686         int error;
3687
3688         error = bus_dmamem_coherent(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
3689                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3690                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3691         if (error)
3692                 return error;
3693
3694         *tag = dmem.dmem_tag;
3695         *map = dmem.dmem_map;
3696         *addr = dmem.dmem_addr;
3697         *paddr = dmem.dmem_busaddr;
3698
3699         return 0;
3700 }
3701
3702 static void
3703 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3704 {
3705         if (tag != NULL) {
3706                 bus_dmamap_unload(tag, map);
3707                 bus_dmamem_free(tag, addr, map);
3708                 bus_dma_tag_destroy(tag);
3709         }
3710 }
3711
3712 /*
3713  * Grrr. The link status word in the status block does
3714  * not work correctly on the BCM5700 rev AX and BX chips,
3715  * according to all available information. Hence, we have
3716  * to enable MII interrupts in order to properly obtain
3717  * async link changes. Unfortunately, this also means that
3718  * we have to read the MAC status register to detect link
3719  * changes, thereby adding an additional register access to
3720  * the interrupt handler.
3721  *
3722  * XXX: perhaps link state detection procedure used for
3723  * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
3724  */
3725 static void
3726 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
3727 {
3728         struct ifnet *ifp = &sc->arpcom.ac_if;
3729         struct mii_data *mii = device_get_softc(sc->bge_miibus);
3730
3731         mii_pollstat(mii);
3732
3733         if (!sc->bge_link &&
3734             (mii->mii_media_status & IFM_ACTIVE) &&
3735             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3736                 sc->bge_link++;
3737                 if (bootverbose)
3738                         if_printf(ifp, "link UP\n");
3739         } else if (sc->bge_link &&
3740             (!(mii->mii_media_status & IFM_ACTIVE) ||
3741             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3742                 sc->bge_link = 0;
3743                 if (bootverbose)
3744                         if_printf(ifp, "link DOWN\n");
3745         }
3746
3747         /* Clear the interrupt. */
3748         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
3749         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
3750         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
3751 }
3752
3753 static void
3754 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
3755 {
3756         struct ifnet *ifp = &sc->arpcom.ac_if;
3757
3758 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3759
3760         /*
3761          * Sometimes PCS encoding errors are detected in
3762          * TBI mode (on fiber NICs), and for some reason
3763          * the chip will signal them as link changes.
3764          * If we get a link change event, but the 'PCS
3765          * encoding error' bit in the MAC status register
3766          * is set, don't bother doing a link check.
3767          * This avoids spurious "gigabit link up" messages
3768          * that sometimes appear on fiber NICs during
3769          * periods of heavy traffic.
3770          */
3771         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3772                 if (!sc->bge_link) {
3773                         sc->bge_link++;
3774                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3775                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3776                                     BGE_MACMODE_TBI_SEND_CFGS);
3777                         }
3778                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3779
3780                         if (bootverbose)
3781                                 if_printf(ifp, "link UP\n");
3782
3783                         ifp->if_link_state = LINK_STATE_UP;
3784                         if_link_state_change(ifp);
3785                 }
3786         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3787                 if (sc->bge_link) {
3788                         sc->bge_link = 0;
3789
3790                         if (bootverbose)
3791                                 if_printf(ifp, "link DOWN\n");
3792
3793                         ifp->if_link_state = LINK_STATE_DOWN;
3794                         if_link_state_change(ifp);
3795                 }
3796         }
3797
3798 #undef PCS_ENCODE_ERR
3799
3800         /* Clear the attention. */
3801         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3802             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3803             BGE_MACSTAT_LINK_CHANGED);
3804 }
3805
3806 static void
3807 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
3808 {
3809         /*
3810          * Check that the AUTOPOLL bit is set before
3811          * processing the event as a real link change.
3812          * Turning AUTOPOLL on and off in the MII read/write
3813          * functions will often trigger a link status
3814          * interrupt for no reason.
3815          */
3816         if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
3817                 struct ifnet *ifp = &sc->arpcom.ac_if;
3818                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3819
3820                 mii_pollstat(mii);
3821
3822                 if (!sc->bge_link &&
3823                     (mii->mii_media_status & IFM_ACTIVE) &&
3824                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3825                         sc->bge_link++;
3826                         if (bootverbose)
3827                                 if_printf(ifp, "link UP\n");
3828                 } else if (sc->bge_link &&
3829                     (!(mii->mii_media_status & IFM_ACTIVE) ||
3830                     IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3831                         sc->bge_link = 0;
3832                         if (bootverbose)
3833                                 if_printf(ifp, "link DOWN\n");
3834                 }
3835         }
3836
3837         /* Clear the attention. */
3838         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3839             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3840             BGE_MACSTAT_LINK_CHANGED);
3841 }
3842
3843 static int
3844 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3845 {
3846         struct bge_softc *sc = arg1;
3847
3848         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3849                                    &sc->bge_rx_coal_ticks,
3850                                    BGE_RX_COAL_TICKS_CHG);
3851 }
3852
3853 static int
3854 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3855 {
3856         struct bge_softc *sc = arg1;
3857
3858         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3859                                    &sc->bge_tx_coal_ticks,
3860                                    BGE_TX_COAL_TICKS_CHG);
3861 }
3862
3863 static int
3864 bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3865 {
3866         struct bge_softc *sc = arg1;
3867
3868         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3869                                    &sc->bge_rx_max_coal_bds,
3870                                    BGE_RX_MAX_COAL_BDS_CHG);
3871 }
3872
3873 static int
3874 bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3875 {
3876         struct bge_softc *sc = arg1;
3877
3878         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3879                                    &sc->bge_tx_max_coal_bds,
3880                                    BGE_TX_MAX_COAL_BDS_CHG);
3881 }
3882
3883 static int
3884 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3885                     uint32_t coal_chg_mask)
3886 {
3887         struct bge_softc *sc = arg1;
3888         struct ifnet *ifp = &sc->arpcom.ac_if;
3889         int error = 0, v;
3890
3891         lwkt_serialize_enter(ifp->if_serializer);
3892
3893         v = *coal;
3894         error = sysctl_handle_int(oidp, &v, 0, req);
3895         if (!error && req->newptr != NULL) {
3896                 if (v < 0) {
3897                         error = EINVAL;
3898                 } else {
3899                         *coal = v;
3900                         sc->bge_coal_chg |= coal_chg_mask;
3901                 }
3902         }
3903
3904         lwkt_serialize_exit(ifp->if_serializer);
3905         return error;
3906 }
3907
3908 static void
3909 bge_coal_change(struct bge_softc *sc)
3910 {
3911         struct ifnet *ifp = &sc->arpcom.ac_if;
3912         uint32_t val;
3913
3914         ASSERT_SERIALIZED(ifp->if_serializer);
3915
3916         if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
3917                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3918                             sc->bge_rx_coal_ticks);
3919                 DELAY(10);
3920                 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3921
3922                 if (bootverbose) {
3923                         if_printf(ifp, "rx_coal_ticks -> %u\n",
3924                                   sc->bge_rx_coal_ticks);
3925                 }
3926         }
3927
3928         if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
3929                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3930                             sc->bge_tx_coal_ticks);
3931                 DELAY(10);
3932                 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3933
3934                 if (bootverbose) {
3935                         if_printf(ifp, "tx_coal_ticks -> %u\n",
3936                                   sc->bge_tx_coal_ticks);
3937                 }
3938         }
3939
3940         if (sc->bge_coal_chg & BGE_RX_MAX_COAL_BDS_CHG) {
3941                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3942                             sc->bge_rx_max_coal_bds);
3943                 DELAY(10);
3944                 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3945
3946                 if (bootverbose) {
3947                         if_printf(ifp, "rx_max_coal_bds -> %u\n",
3948                                   sc->bge_rx_max_coal_bds);
3949                 }
3950         }
3951
3952         if (sc->bge_coal_chg & BGE_TX_MAX_COAL_BDS_CHG) {
3953                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3954                             sc->bge_tx_max_coal_bds);
3955                 DELAY(10);
3956                 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3957
3958                 if (bootverbose) {
3959                         if_printf(ifp, "tx_max_coal_bds -> %u\n",
3960                                   sc->bge_tx_max_coal_bds);
3961                 }
3962         }
3963
3964         sc->bge_coal_chg = 0;
3965 }
3966
3967 static void
3968 bge_enable_intr(struct bge_softc *sc)
3969 {
3970         struct ifnet *ifp = &sc->arpcom.ac_if;
3971
3972         lwkt_serialize_handler_enable(ifp->if_serializer);
3973
3974         /*
3975          * Enable interrupt.
3976          */
3977         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3978
3979         /*
3980          * Unmask the interrupt when we stop polling.
3981          */
3982         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3983
3984         /*
3985          * Trigger another interrupt, since above writing
3986          * to interrupt mailbox0 may acknowledge pending
3987          * interrupt.
3988          */
3989         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3990 }
3991
3992 static void
3993 bge_disable_intr(struct bge_softc *sc)
3994 {
3995         struct ifnet *ifp = &sc->arpcom.ac_if;
3996
3997         /*
3998          * Mask the interrupt when we start polling.
3999          */
4000         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4001
4002         /*
4003          * Acknowledge possible asserted interrupt.
4004          */
4005         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4006
4007         lwkt_serialize_handler_disable(ifp->if_serializer);
4008 }
4009
4010 static int
4011 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
4012 {
4013         uint32_t mac_addr;
4014         int ret = 1;
4015
4016         mac_addr = bge_readmem_ind(sc, 0x0c14);
4017         if ((mac_addr >> 16) == 0x484b) {
4018                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4019                 ether_addr[1] = (uint8_t)mac_addr;
4020                 mac_addr = bge_readmem_ind(sc, 0x0c18);
4021                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4022                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4023                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4024                 ether_addr[5] = (uint8_t)mac_addr;
4025                 ret = 0;
4026         }
4027         return ret;
4028 }
4029
4030 static int
4031 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
4032 {
4033         int mac_offset = BGE_EE_MAC_OFFSET;
4034
4035         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
4036                 mac_offset = BGE_EE_MAC_OFFSET_5906;
4037
4038         return bge_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4039 }
4040
4041 static int
4042 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
4043 {
4044         if (sc->bge_flags & BGE_FLAG_NO_EEPROM)
4045                 return 1;
4046
4047         return bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4048                                ETHER_ADDR_LEN);
4049 }
4050
4051 static int
4052 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
4053 {
4054         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
4055                 /* NOTE: Order is critical */
4056                 bge_get_eaddr_mem,
4057                 bge_get_eaddr_nvram,
4058                 bge_get_eaddr_eeprom,
4059                 NULL
4060         };
4061         const bge_eaddr_fcn_t *func;
4062
4063         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
4064                 if ((*func)(sc, eaddr) == 0)
4065                         break;
4066         }
4067         return (*func == NULL ? ENXIO : 0);
4068 }