2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 * $FreeBSD: head/sys/dev/drm2/radeon/rs400.c 254885 2013-08-25 19:37:15Z dumbbell $
33 #include "radeon_asic.h"
36 /* This files gather functions specifics to : rs400,rs480 */
37 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
39 void rs400_gart_adjust_size(struct radeon_device *rdev)
42 switch (rdev->mc.gtt_size/(1024*1024)) {
52 DRM_ERROR("Unable to use IGP GART size %uM\n",
53 (unsigned)(rdev->mc.gtt_size >> 20));
54 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
55 DRM_ERROR("Forcing to 32M GART size\n");
56 rdev->mc.gtt_size = 32 * 1024 * 1024;
61 void rs400_gart_tlb_flush(struct radeon_device *rdev)
64 unsigned int timeout = rdev->usec_timeout;
66 WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
68 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
69 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
73 } while (timeout > 0);
74 WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
77 int rs400_gart_init(struct radeon_device *rdev)
82 DRM_ERROR("RS400 GART already initialized\n");
86 switch(rdev->mc.gtt_size / (1024 * 1024)) {
98 /* Initialize common gart structure */
99 r = radeon_gart_init(rdev);
102 if (rs400_debugfs_pcie_gart_info_init(rdev))
103 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
104 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
105 return radeon_gart_table_ram_alloc(rdev);
108 int rs400_gart_enable(struct radeon_device *rdev)
113 radeon_gart_restore(rdev);
114 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
115 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
116 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
117 /* Check gart size */
118 switch(rdev->mc.gtt_size / (1024 * 1024)) {
120 size_reg = RS480_VA_SIZE_32MB;
123 size_reg = RS480_VA_SIZE_64MB;
126 size_reg = RS480_VA_SIZE_128MB;
129 size_reg = RS480_VA_SIZE_256MB;
132 size_reg = RS480_VA_SIZE_512MB;
135 size_reg = RS480_VA_SIZE_1GB;
138 size_reg = RS480_VA_SIZE_2GB;
143 /* It should be fine to program it to max value */
144 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
145 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
146 WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
148 WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
149 WREG32(RS480_AGP_BASE_2, 0);
151 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
152 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
153 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
154 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
155 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
156 WREG32(RADEON_BUS_CNTL, tmp);
158 WREG32(RADEON_MC_AGP_LOCATION, tmp);
159 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
160 WREG32(RADEON_BUS_CNTL, tmp);
162 /* Table should be in 32bits address space so ignore bits above. */
163 tmp = (u32)rdev->gart.table_addr & 0xfffff000;
164 tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
166 WREG32_MC(RS480_GART_BASE, tmp);
167 /* TODO: more tweaking here */
168 WREG32_MC(RS480_GART_FEATURE_ID,
170 RS480_GTW_LAC_EN | RS480_1LEVEL_GART));
171 /* Disable snooping */
172 WREG32_MC(RS480_AGP_MODE_CNTL,
173 (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS);
174 /* Disable AGP mode */
175 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
176 tmp = RREG32_MC(RS690_MC_NB_CNTL);
177 tmp &= ~(RS690_HIDE_MMCFG_BAR |
179 RS690_AGP30ENHANCED);
180 WREG32_MC(RS690_MC_NB_CNTL, tmp);
181 WREG32_MC(RS480_MC_MISC_CNTL,
182 (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN));
184 WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
187 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
188 rs400_gart_tlb_flush(rdev);
189 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
190 (unsigned)(rdev->mc.gtt_size >> 20),
191 (unsigned long long)rdev->gart.table_addr);
192 rdev->gart.ready = true;
196 void rs400_gart_disable(struct radeon_device *rdev)
200 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
201 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
202 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
203 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
206 void rs400_gart_fini(struct radeon_device *rdev)
208 radeon_gart_fini(rdev);
209 rs400_gart_disable(rdev);
210 radeon_gart_table_ram_free(rdev);
213 #define RS400_PTE_WRITEABLE (1 << 2)
214 #define RS400_PTE_READABLE (1 << 3)
216 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
219 u32 *gtt = rdev->gart.ptr;
221 if (i < 0 || i > rdev->gart.num_gpu_pages) {
225 entry = (lower_32_bits(addr) & 0xfffff000) |
226 ((upper_32_bits(addr) & 0xff) << 4) |
227 RS400_PTE_WRITEABLE | RS400_PTE_READABLE;
228 entry = cpu_to_le32(entry);
233 int rs400_mc_wait_for_idle(struct radeon_device *rdev)
238 for (i = 0; i < rdev->usec_timeout; i++) {
240 tmp = RREG32(RADEON_MC_STATUS);
241 if (tmp & RADEON_MC_IDLE) {
249 static void rs400_gpu_init(struct radeon_device *rdev)
251 /* FIXME: is this correct ? */
252 r420_pipes_init(rdev);
253 if (rs400_mc_wait_for_idle(rdev)) {
254 DRM_ERROR("rs400: Failed to wait MC idle while "
255 "programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS));
259 static void rs400_mc_init(struct radeon_device *rdev)
263 rs400_gart_adjust_size(rdev);
264 rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
265 /* DDR for all card after R300 & IGP */
266 rdev->mc.vram_is_ddr = true;
267 rdev->mc.vram_width = 128;
268 r100_vram_init_sizes(rdev);
269 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
270 radeon_vram_location(rdev, &rdev->mc, base);
271 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
272 radeon_gtt_location(rdev, &rdev->mc);
273 radeon_update_bandwidth_info(rdev);
276 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
280 WREG32(RS480_NB_MC_INDEX, reg & 0xff);
281 r = RREG32(RS480_NB_MC_DATA);
282 WREG32(RS480_NB_MC_INDEX, 0xff);
286 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
288 WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
289 WREG32(RS480_NB_MC_DATA, (v));
290 WREG32(RS480_NB_MC_INDEX, 0xff);
293 #if defined(CONFIG_DEBUG_FS)
294 static int rs400_debugfs_gart_info(struct seq_file *m, void *data)
296 struct drm_info_node *node = (struct drm_info_node *) m->private;
297 struct drm_device *dev = node->minor->dev;
298 struct radeon_device *rdev = dev->dev_private;
301 tmp = RREG32(RADEON_HOST_PATH_CNTL);
302 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
303 tmp = RREG32(RADEON_BUS_CNTL);
304 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
305 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
306 seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
307 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
308 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
309 seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
310 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
311 seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
312 tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
313 seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
314 tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION);
315 seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
316 tmp = RREG32(RS690_HDP_FB_LOCATION);
317 seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
319 tmp = RREG32(RADEON_AGP_BASE);
320 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
321 tmp = RREG32(RS480_AGP_BASE_2);
322 seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
323 tmp = RREG32(RADEON_MC_AGP_LOCATION);
324 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
326 tmp = RREG32_MC(RS480_GART_BASE);
327 seq_printf(m, "GART_BASE 0x%08x\n", tmp);
328 tmp = RREG32_MC(RS480_GART_FEATURE_ID);
329 seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
330 tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
331 seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
332 tmp = RREG32_MC(RS480_MC_MISC_CNTL);
333 seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
334 tmp = RREG32_MC(0x5F);
335 seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
336 tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
337 seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
338 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
339 seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
340 tmp = RREG32_MC(0x3B);
341 seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
342 tmp = RREG32_MC(0x3C);
343 seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
344 tmp = RREG32_MC(0x30);
345 seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
346 tmp = RREG32_MC(0x31);
347 seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
348 tmp = RREG32_MC(0x32);
349 seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
350 tmp = RREG32_MC(0x33);
351 seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
352 tmp = RREG32_MC(0x34);
353 seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
354 tmp = RREG32_MC(0x35);
355 seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
356 tmp = RREG32_MC(0x36);
357 seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
358 tmp = RREG32_MC(0x37);
359 seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
363 static struct drm_info_list rs400_gart_info_list[] = {
364 {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL},
368 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
370 #if defined(CONFIG_DEBUG_FS)
371 return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
377 static void rs400_mc_program(struct radeon_device *rdev)
379 struct r100_mc_save save;
381 /* Stops all mc clients */
382 r100_mc_stop(rdev, &save);
384 /* Wait for mc idle */
385 if (rs400_mc_wait_for_idle(rdev))
386 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
387 WREG32(R_000148_MC_FB_LOCATION,
388 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
389 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
391 r100_mc_resume(rdev, &save);
394 static int rs400_startup(struct radeon_device *rdev)
398 r100_set_common_regs(rdev);
400 rs400_mc_program(rdev);
402 r300_clock_startup(rdev);
403 /* Initialize GPU configuration (# pipes, ...) */
404 rs400_gpu_init(rdev);
405 r100_enable_bm(rdev);
406 /* Initialize GART (initialize after TTM so we can allocate
407 * memory through TTM but finalize after TTM) */
408 r = rs400_gart_enable(rdev);
412 /* allocate wb buffer */
413 r = radeon_wb_init(rdev);
417 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
419 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
425 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
427 r = r100_cp_init(rdev, 1024 * 1024);
429 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
433 r = radeon_ib_pool_init(rdev);
435 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
442 int rs400_resume(struct radeon_device *rdev)
446 /* Make sur GART are not working */
447 rs400_gart_disable(rdev);
448 /* Resume clock before doing reset */
449 r300_clock_startup(rdev);
450 /* setup MC before calling post tables */
451 rs400_mc_program(rdev);
452 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
453 if (radeon_asic_reset(rdev)) {
454 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
455 RREG32(R_000E40_RBBM_STATUS),
456 RREG32(R_0007C0_CP_STAT));
459 radeon_combios_asic_init(rdev->ddev);
460 /* Resume clock after posting */
461 r300_clock_startup(rdev);
462 /* Initialize surface registers */
463 radeon_surface_init(rdev);
465 rdev->accel_working = true;
466 r = rs400_startup(rdev);
468 rdev->accel_working = false;
473 int rs400_suspend(struct radeon_device *rdev)
475 r100_cp_disable(rdev);
476 radeon_wb_disable(rdev);
477 r100_irq_disable(rdev);
478 rs400_gart_disable(rdev);
482 void rs400_fini(struct radeon_device *rdev)
485 radeon_wb_fini(rdev);
486 radeon_ib_pool_fini(rdev);
487 radeon_gem_fini(rdev);
488 rs400_gart_fini(rdev);
489 radeon_irq_kms_fini(rdev);
490 radeon_fence_driver_fini(rdev);
491 radeon_bo_fini(rdev);
492 radeon_atombios_fini(rdev);
493 drm_free(rdev->bios, DRM_MEM_DRIVER);
497 int rs400_init(struct radeon_device *rdev)
502 r100_vga_render_disable(rdev);
503 /* Initialize scratch registers */
504 radeon_scratch_init(rdev);
505 /* Initialize surface registers */
506 radeon_surface_init(rdev);
507 /* TODO: disable VGA need to use VGA request */
508 /* restore some register to sane defaults */
509 r100_restore_sanity(rdev);
511 if (!radeon_get_bios(rdev)) {
512 if (ASIC_IS_AVIVO(rdev))
515 if (rdev->is_atom_bios) {
516 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
519 r = radeon_combios_init(rdev);
523 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
524 if (radeon_asic_reset(rdev)) {
526 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
527 RREG32(R_000E40_RBBM_STATUS),
528 RREG32(R_0007C0_CP_STAT));
530 /* check if cards are posted or not */
531 if (radeon_boot_test_post_card(rdev) == false)
534 /* Initialize clocks */
535 radeon_get_clock_info(rdev->ddev);
536 /* initialize memory controller */
539 r = radeon_fence_driver_init(rdev);
542 r = radeon_irq_kms_init(rdev);
546 r = radeon_bo_init(rdev);
549 r = rs400_gart_init(rdev);
552 r300_set_reg_safe(rdev);
554 rdev->accel_working = true;
555 r = rs400_startup(rdev);
557 /* Somethings want wront with the accel init stop accel */
558 dev_err(rdev->dev, "Disabling GPU acceleration\n");
560 radeon_wb_fini(rdev);
561 radeon_ib_pool_fini(rdev);
562 rs400_gart_fini(rdev);
563 radeon_irq_kms_fini(rdev);
564 rdev->accel_working = false;