2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 #include "opt_ifpoll.h"
70 #include <sys/param.h>
72 #include <sys/endian.h>
73 #include <sys/interrupt.h>
74 #include <sys/kernel.h>
76 #include <sys/malloc.h>
80 #include <sys/serialize.h>
81 #include <sys/serialize2.h>
82 #include <sys/socket.h>
83 #include <sys/sockio.h>
84 #include <sys/sysctl.h>
85 #include <sys/systm.h>
88 #include <net/ethernet.h>
90 #include <net/if_arp.h>
91 #include <net/if_dl.h>
92 #include <net/if_media.h>
93 #include <net/ifq_var.h>
94 #include <net/toeplitz.h>
95 #include <net/toeplitz2.h>
96 #include <net/vlan/if_vlan_var.h>
97 #include <net/vlan/if_vlan_ether.h>
98 #include <net/if_poll.h>
100 #include <netinet/in_systm.h>
101 #include <netinet/in.h>
102 #include <netinet/ip.h>
103 #include <netinet/tcp.h>
104 #include <netinet/udp.h>
106 #include <bus/pci/pcivar.h>
107 #include <bus/pci/pcireg.h>
109 #include <dev/netif/ig_hal/e1000_api.h>
110 #include <dev/netif/ig_hal/e1000_82571.h>
111 #include <dev/netif/emx/if_emx.h>
114 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
116 if (sc->rss_debug >= lvl) \
117 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
119 #else /* !EMX_RSS_DEBUG */
120 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
121 #endif /* EMX_RSS_DEBUG */
123 #define EMX_TX_SERIALIZE 1
124 #define EMX_RX_SERIALIZE 2
126 #define EMX_NAME "Intel(R) PRO/1000 "
128 #define EMX_DEVICE(id) \
129 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
130 #define EMX_DEVICE_NULL { 0, 0, NULL }
132 static const struct emx_device {
137 EMX_DEVICE(82571EB_COPPER),
138 EMX_DEVICE(82571EB_FIBER),
139 EMX_DEVICE(82571EB_SERDES),
140 EMX_DEVICE(82571EB_SERDES_DUAL),
141 EMX_DEVICE(82571EB_SERDES_QUAD),
142 EMX_DEVICE(82571EB_QUAD_COPPER),
143 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
144 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
145 EMX_DEVICE(82571EB_QUAD_FIBER),
146 EMX_DEVICE(82571PT_QUAD_COPPER),
148 EMX_DEVICE(82572EI_COPPER),
149 EMX_DEVICE(82572EI_FIBER),
150 EMX_DEVICE(82572EI_SERDES),
154 EMX_DEVICE(82573E_IAMT),
157 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
158 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
159 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
160 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
165 /* required last entry */
169 static int emx_probe(device_t);
170 static int emx_attach(device_t);
171 static int emx_detach(device_t);
172 static int emx_shutdown(device_t);
173 static int emx_suspend(device_t);
174 static int emx_resume(device_t);
176 static void emx_init(void *);
177 static void emx_stop(struct emx_softc *);
178 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
179 static void emx_start(struct ifnet *);
181 static void emx_qpoll(struct ifnet *, struct ifpoll_info *);
183 static void emx_watchdog(struct ifnet *);
184 static void emx_media_status(struct ifnet *, struct ifmediareq *);
185 static int emx_media_change(struct ifnet *);
186 static void emx_timer(void *);
187 static void emx_serialize(struct ifnet *, enum ifnet_serialize);
188 static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
189 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
191 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
195 static void emx_intr(void *);
196 static void emx_intr_mask(void *);
197 static void emx_intr_body(struct emx_softc *, boolean_t);
198 static void emx_rxeof(struct emx_softc *, int, int);
199 static void emx_txeof(struct emx_softc *);
200 static void emx_tx_collect(struct emx_softc *);
201 static void emx_tx_purge(struct emx_softc *);
202 static void emx_enable_intr(struct emx_softc *);
203 static void emx_disable_intr(struct emx_softc *);
205 static int emx_dma_alloc(struct emx_softc *);
206 static void emx_dma_free(struct emx_softc *);
207 static void emx_init_tx_ring(struct emx_softc *);
208 static int emx_init_rx_ring(struct emx_softc *, struct emx_rxdata *);
209 static void emx_free_rx_ring(struct emx_softc *, struct emx_rxdata *);
210 static int emx_create_tx_ring(struct emx_softc *);
211 static int emx_create_rx_ring(struct emx_softc *, struct emx_rxdata *);
212 static void emx_destroy_tx_ring(struct emx_softc *, int);
213 static void emx_destroy_rx_ring(struct emx_softc *,
214 struct emx_rxdata *, int);
215 static int emx_newbuf(struct emx_softc *, struct emx_rxdata *, int, int);
216 static int emx_encap(struct emx_softc *, struct mbuf **);
217 static int emx_txcsum(struct emx_softc *, struct mbuf *,
218 uint32_t *, uint32_t *);
219 static int emx_tso_pullup(struct emx_softc *, struct mbuf **);
220 static int emx_tso_setup(struct emx_softc *, struct mbuf *,
221 uint32_t *, uint32_t *);
223 static int emx_is_valid_eaddr(const uint8_t *);
224 static int emx_reset(struct emx_softc *);
225 static void emx_setup_ifp(struct emx_softc *);
226 static void emx_init_tx_unit(struct emx_softc *);
227 static void emx_init_rx_unit(struct emx_softc *);
228 static void emx_update_stats(struct emx_softc *);
229 static void emx_set_promisc(struct emx_softc *);
230 static void emx_disable_promisc(struct emx_softc *);
231 static void emx_set_multi(struct emx_softc *);
232 static void emx_update_link_status(struct emx_softc *);
233 static void emx_smartspeed(struct emx_softc *);
234 static void emx_set_itr(struct emx_softc *, uint32_t);
235 static void emx_disable_aspm(struct emx_softc *);
237 static void emx_print_debug_info(struct emx_softc *);
238 static void emx_print_nvm_info(struct emx_softc *);
239 static void emx_print_hw_stats(struct emx_softc *);
241 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
242 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
243 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
244 static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
245 static void emx_add_sysctl(struct emx_softc *);
247 static void emx_serialize_skipmain(struct emx_softc *);
248 static void emx_deserialize_skipmain(struct emx_softc *);
250 /* Management and WOL Support */
251 static void emx_get_mgmt(struct emx_softc *);
252 static void emx_rel_mgmt(struct emx_softc *);
253 static void emx_get_hw_control(struct emx_softc *);
254 static void emx_rel_hw_control(struct emx_softc *);
255 static void emx_enable_wol(device_t);
257 static device_method_t emx_methods[] = {
258 /* Device interface */
259 DEVMETHOD(device_probe, emx_probe),
260 DEVMETHOD(device_attach, emx_attach),
261 DEVMETHOD(device_detach, emx_detach),
262 DEVMETHOD(device_shutdown, emx_shutdown),
263 DEVMETHOD(device_suspend, emx_suspend),
264 DEVMETHOD(device_resume, emx_resume),
268 static driver_t emx_driver = {
271 sizeof(struct emx_softc),
274 static devclass_t emx_devclass;
276 DECLARE_DUMMY_MODULE(if_emx);
277 MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
278 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
283 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
284 static int emx_rxd = EMX_DEFAULT_RXD;
285 static int emx_txd = EMX_DEFAULT_TXD;
286 static int emx_smart_pwr_down = 0;
287 static int emx_rxr = 0;
289 /* Controls whether promiscuous also shows bad packets */
290 static int emx_debug_sbp = 0;
292 static int emx_82573_workaround = 1;
293 static int emx_msi_enable = 1;
295 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
296 TUNABLE_INT("hw.emx.rxd", &emx_rxd);
297 TUNABLE_INT("hw.emx.rxr", &emx_rxr);
298 TUNABLE_INT("hw.emx.txd", &emx_txd);
299 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
300 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
301 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
302 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
304 /* Global used in WOL setup with multiport cards */
305 static int emx_global_quad_port_a = 0;
307 /* Set this to one to display debug statistics */
308 static int emx_display_debug_stats = 0;
310 #if !defined(KTR_IF_EMX)
311 #define KTR_IF_EMX KTR_ALL
313 KTR_INFO_MASTER(if_emx);
314 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin");
315 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end");
316 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet");
317 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet");
318 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean");
319 #define logif(name) KTR_LOG(if_emx_ ## name)
322 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
324 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
325 /* DD bit must be cleared */
326 rxd->rxd_staterr = 0;
330 emx_rxcsum(uint32_t staterr, struct mbuf *mp)
332 /* Ignore Checksum bit is set */
333 if (staterr & E1000_RXD_STAT_IXSM)
336 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
338 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
340 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
341 E1000_RXD_STAT_TCPCS) {
342 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
344 CSUM_FRAG_NOT_CHECKED;
345 mp->m_pkthdr.csum_data = htons(0xffff);
349 static __inline struct pktinfo *
350 emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
351 uint32_t mrq, uint32_t hash, uint32_t staterr)
353 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
354 case EMX_RXDMRQ_IPV4_TCP:
355 pi->pi_netisr = NETISR_IP;
357 pi->pi_l3proto = IPPROTO_TCP;
360 case EMX_RXDMRQ_IPV6_TCP:
361 pi->pi_netisr = NETISR_IPV6;
363 pi->pi_l3proto = IPPROTO_TCP;
366 case EMX_RXDMRQ_IPV4:
367 if (staterr & E1000_RXD_STAT_IXSM)
371 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
372 E1000_RXD_STAT_TCPCS) {
373 pi->pi_netisr = NETISR_IP;
375 pi->pi_l3proto = IPPROTO_UDP;
383 m->m_flags |= M_HASH;
384 m->m_pkthdr.hash = toeplitz_hash(hash);
389 emx_probe(device_t dev)
391 const struct emx_device *d;
394 vid = pci_get_vendor(dev);
395 did = pci_get_device(dev);
397 for (d = emx_devices; d->desc != NULL; ++d) {
398 if (vid == d->vid && did == d->did) {
399 device_set_desc(dev, d->desc);
400 device_set_async_attach(dev, TRUE);
408 emx_attach(device_t dev)
410 struct emx_softc *sc = device_get_softc(dev);
411 struct ifnet *ifp = &sc->arpcom.ac_if;
412 int error = 0, i, throttle, msi_enable;
414 uint16_t eeprom_data, device_id, apme_mask;
415 driver_intr_t *intr_func;
417 lwkt_serialize_init(&sc->main_serialize);
418 lwkt_serialize_init(&sc->tx_serialize);
419 for (i = 0; i < EMX_NRX_RING; ++i)
420 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
423 sc->serializes[i++] = &sc->main_serialize;
424 sc->serializes[i++] = &sc->tx_serialize;
425 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
426 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
427 KKASSERT(i == EMX_NSERIALIZE);
429 callout_init_mp(&sc->timer);
431 sc->dev = sc->osdep.dev = dev;
434 * Determine hardware and mac type
436 sc->hw.vendor_id = pci_get_vendor(dev);
437 sc->hw.device_id = pci_get_device(dev);
438 sc->hw.revision_id = pci_get_revid(dev);
439 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
440 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
442 if (e1000_set_mac_type(&sc->hw))
446 * Pullup extra 4bytes into the first data segment, see:
447 * 82571/82572 specification update errata #7
450 * 4bytes instead of 2bytes, which are mentioned in the errata,
451 * are pulled; mainly to keep rest of the data properly aligned.
453 if (sc->hw.mac.type == e1000_82571 || sc->hw.mac.type == e1000_82572)
454 sc->flags |= EMX_FLAG_TSO_PULLEX;
456 /* Enable bus mastering */
457 pci_enable_busmaster(dev);
462 sc->memory_rid = EMX_BAR_MEM;
463 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
464 &sc->memory_rid, RF_ACTIVE);
465 if (sc->memory == NULL) {
466 device_printf(dev, "Unable to allocate bus resource: memory\n");
470 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
471 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
473 /* XXX This is quite goofy, it is not actually used */
474 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
477 * Don't enable MSI-X on 82574, see:
478 * 82574 specification update errata #15
480 * Don't enable MSI on 82571/82572, see:
481 * 82571/82572 specification update errata #63
483 msi_enable = emx_msi_enable;
485 (sc->hw.mac.type == e1000_82571 ||
486 sc->hw.mac.type == e1000_82572))
492 sc->intr_type = pci_alloc_1intr(dev, msi_enable,
493 &sc->intr_rid, &intr_flags);
495 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
498 unshared = device_getenv_int(dev, "irq.unshared", 0);
500 sc->flags |= EMX_FLAG_SHARED_INTR;
502 device_printf(dev, "IRQ shared\n");
504 intr_flags &= ~RF_SHAREABLE;
506 device_printf(dev, "IRQ unshared\n");
510 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
512 if (sc->intr_res == NULL) {
513 device_printf(dev, "Unable to allocate bus resource: "
519 /* Save PCI command register for Shared Code */
520 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
521 sc->hw.back = &sc->osdep;
523 /* Do Shared Code initialization */
524 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
525 device_printf(dev, "Setup of Shared code failed\n");
529 e1000_get_bus_info(&sc->hw);
531 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
532 sc->hw.phy.autoneg_wait_to_complete = FALSE;
533 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
536 * Interrupt throttle rate
538 throttle = device_getenv_int(dev, "int_throttle_ceil",
539 emx_int_throttle_ceil);
541 sc->int_throttle_ceil = 0;
544 throttle = EMX_DEFAULT_ITR;
546 /* Recalculate the tunable value to get the exact frequency. */
547 throttle = 1000000000 / 256 / throttle;
549 /* Upper 16bits of ITR is reserved and should be zero */
550 if (throttle & 0xffff0000)
551 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
553 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
556 e1000_init_script_state_82541(&sc->hw, TRUE);
557 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
560 if (sc->hw.phy.media_type == e1000_media_type_copper) {
561 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
562 sc->hw.phy.disable_polarity_correction = FALSE;
563 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
566 /* Set the frame limits assuming standard ethernet sized frames. */
567 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
568 sc->min_frame_size = ETHER_MIN_LEN;
570 /* This controls when hardware reports transmit completion status. */
571 sc->hw.mac.report_tx_early = 1;
573 /* Calculate # of RX rings */
574 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr);
575 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, EMX_NRX_RING);
577 /* Allocate RX/TX rings' busdma(9) stuffs */
578 error = emx_dma_alloc(sc);
582 /* Allocate multicast array memory. */
583 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
586 /* Indicate SOL/IDER usage */
587 if (e1000_check_reset_block(&sc->hw)) {
589 "PHY reset is blocked due to SOL/IDER session.\n");
593 * Start from a known state, this is important in reading the
594 * nvm and mac from that.
596 e1000_reset_hw(&sc->hw);
598 /* Make sure we have a good EEPROM before we read from it */
599 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
601 * Some PCI-E parts fail the first check due to
602 * the link being in sleep state, call it again,
603 * if it fails a second time its a real issue.
605 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
607 "The EEPROM Checksum Is Not Valid\n");
613 /* Copy the permanent MAC address out of the EEPROM */
614 if (e1000_read_mac_addr(&sc->hw) < 0) {
615 device_printf(dev, "EEPROM read error while reading MAC"
620 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
621 device_printf(dev, "Invalid MAC address\n");
626 /* Determine if we have to control management hardware */
627 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw);
632 apme_mask = EMX_EEPROM_APME;
634 switch (sc->hw.mac.type) {
641 case e1000_80003es2lan:
642 if (sc->hw.bus.func == 1) {
643 e1000_read_nvm(&sc->hw,
644 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
646 e1000_read_nvm(&sc->hw,
647 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
652 e1000_read_nvm(&sc->hw,
653 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
656 if (eeprom_data & apme_mask)
657 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
660 * We have the eeprom settings, now apply the special cases
661 * where the eeprom may be wrong or the board won't support
662 * wake on lan on a particular port
664 device_id = pci_get_device(dev);
666 case E1000_DEV_ID_82571EB_FIBER:
668 * Wake events only supported on port A for dual fiber
669 * regardless of eeprom setting
671 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
676 case E1000_DEV_ID_82571EB_QUAD_COPPER:
677 case E1000_DEV_ID_82571EB_QUAD_FIBER:
678 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
679 /* if quad port sc, disable WoL on all but port A */
680 if (emx_global_quad_port_a != 0)
682 /* Reset for multiple quad port adapters */
683 if (++emx_global_quad_port_a == 4)
684 emx_global_quad_port_a = 0;
688 /* XXX disable wol */
691 /* Setup OS specific network interface */
694 /* Add sysctl tree, must after em_setup_ifp() */
697 /* Reset the hardware */
698 error = emx_reset(sc);
700 device_printf(dev, "Unable to reset the hardware\n");
704 /* Initialize statistics */
705 emx_update_stats(sc);
707 sc->hw.mac.get_link_status = 1;
708 emx_update_link_status(sc);
710 sc->spare_tx_desc = EMX_TX_SPARE;
713 * Keep following relationship between spare_tx_desc, oact_tx_desc
715 * (spare_tx_desc + EMX_TX_RESERVED) <=
716 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs
718 sc->oact_tx_desc = sc->num_tx_desc / 8;
719 if (sc->oact_tx_desc > EMX_TX_OACTIVE_MAX)
720 sc->oact_tx_desc = EMX_TX_OACTIVE_MAX;
721 if (sc->oact_tx_desc < sc->spare_tx_desc + EMX_TX_RESERVED)
722 sc->oact_tx_desc = sc->spare_tx_desc + EMX_TX_RESERVED;
724 sc->tx_int_nsegs = sc->num_tx_desc / 16;
725 if (sc->tx_int_nsegs < sc->oact_tx_desc)
726 sc->tx_int_nsegs = sc->oact_tx_desc;
728 /* Non-AMT based hardware can now take control from firmware */
729 if (sc->has_manage && !sc->has_amt)
730 emx_get_hw_control(sc);
733 * Missing Interrupt Following ICR read:
735 * 82571/82572 specification update errata #76
736 * 82573 specification update errata #31
737 * 82574 specification update errata #12
739 intr_func = emx_intr;
740 if ((sc->flags & EMX_FLAG_SHARED_INTR) &&
741 (sc->hw.mac.type == e1000_82571 ||
742 sc->hw.mac.type == e1000_82572 ||
743 sc->hw.mac.type == e1000_82573 ||
744 sc->hw.mac.type == e1000_82574))
745 intr_func = emx_intr_mask;
747 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc,
748 &sc->intr_tag, &sc->main_serialize);
750 device_printf(dev, "Failed to register interrupt handler");
751 ether_ifdetach(&sc->arpcom.ac_if);
755 ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
756 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
764 emx_detach(device_t dev)
766 struct emx_softc *sc = device_get_softc(dev);
768 if (device_is_attached(dev)) {
769 struct ifnet *ifp = &sc->arpcom.ac_if;
771 ifnet_serialize_all(ifp);
775 e1000_phy_hw_reset(&sc->hw);
778 emx_rel_hw_control(sc);
781 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
782 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
786 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
788 ifnet_deserialize_all(ifp);
792 emx_rel_hw_control(sc);
794 bus_generic_detach(dev);
796 if (sc->intr_res != NULL) {
797 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
801 if (sc->intr_type == PCI_INTR_TYPE_MSI)
802 pci_release_msi(dev);
804 if (sc->memory != NULL) {
805 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
811 /* Free sysctl tree */
812 if (sc->sysctl_tree != NULL)
813 sysctl_ctx_free(&sc->sysctl_ctx);
819 emx_shutdown(device_t dev)
821 return emx_suspend(dev);
825 emx_suspend(device_t dev)
827 struct emx_softc *sc = device_get_softc(dev);
828 struct ifnet *ifp = &sc->arpcom.ac_if;
830 ifnet_serialize_all(ifp);
835 emx_rel_hw_control(sc);
838 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
839 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
843 ifnet_deserialize_all(ifp);
845 return bus_generic_suspend(dev);
849 emx_resume(device_t dev)
851 struct emx_softc *sc = device_get_softc(dev);
852 struct ifnet *ifp = &sc->arpcom.ac_if;
854 ifnet_serialize_all(ifp);
860 ifnet_deserialize_all(ifp);
862 return bus_generic_resume(dev);
866 emx_start(struct ifnet *ifp)
868 struct emx_softc *sc = ifp->if_softc;
871 ASSERT_SERIALIZED(&sc->tx_serialize);
873 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
876 if (!sc->link_active) {
877 ifq_purge(&ifp->if_snd);
881 while (!ifq_is_empty(&ifp->if_snd)) {
882 /* Now do we at least have a minimal? */
883 if (EMX_IS_OACTIVE(sc)) {
885 if (EMX_IS_OACTIVE(sc)) {
886 ifp->if_flags |= IFF_OACTIVE;
887 sc->no_tx_desc_avail1++;
893 m_head = ifq_dequeue(&ifp->if_snd, NULL);
897 if (emx_encap(sc, &m_head)) {
903 /* Send a copy of the frame to the BPF listener */
904 ETHER_BPF_MTAP(ifp, m_head);
906 /* Set timeout in case hardware has problems transmitting. */
907 ifp->if_timer = EMX_TX_TIMEOUT;
912 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
914 struct emx_softc *sc = ifp->if_softc;
915 struct ifreq *ifr = (struct ifreq *)data;
916 uint16_t eeprom_data = 0;
917 int max_frame_size, mask, reinit;
920 ASSERT_IFNET_SERIALIZED_ALL(ifp);
924 switch (sc->hw.mac.type) {
927 * 82573 only supports jumbo frames
928 * if ASPM is disabled.
930 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
932 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
933 max_frame_size = ETHER_MAX_LEN;
938 /* Limit Jumbo Frame size */
942 case e1000_80003es2lan:
943 max_frame_size = 9234;
947 max_frame_size = MAX_JUMBO_FRAME_SIZE;
950 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
956 ifp->if_mtu = ifr->ifr_mtu;
957 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
960 if (ifp->if_flags & IFF_RUNNING)
965 if (ifp->if_flags & IFF_UP) {
966 if ((ifp->if_flags & IFF_RUNNING)) {
967 if ((ifp->if_flags ^ sc->if_flags) &
968 (IFF_PROMISC | IFF_ALLMULTI)) {
969 emx_disable_promisc(sc);
975 } else if (ifp->if_flags & IFF_RUNNING) {
978 sc->if_flags = ifp->if_flags;
983 if (ifp->if_flags & IFF_RUNNING) {
984 emx_disable_intr(sc);
987 if (!(ifp->if_flags & IFF_NPOLLING))
994 /* Check SOL/IDER usage */
995 if (e1000_check_reset_block(&sc->hw)) {
996 device_printf(sc->dev, "Media change is"
997 " blocked due to SOL/IDER session.\n");
1003 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
1008 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1009 if (mask & IFCAP_RXCSUM) {
1010 ifp->if_capenable ^= IFCAP_RXCSUM;
1013 if (mask & IFCAP_VLAN_HWTAGGING) {
1014 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1017 if (mask & IFCAP_TXCSUM) {
1018 ifp->if_capenable ^= IFCAP_TXCSUM;
1019 if (ifp->if_capenable & IFCAP_TXCSUM)
1020 ifp->if_hwassist |= EMX_CSUM_FEATURES;
1022 ifp->if_hwassist &= ~EMX_CSUM_FEATURES;
1024 if (mask & IFCAP_TSO) {
1025 ifp->if_capenable ^= IFCAP_TSO;
1026 if (ifp->if_capenable & IFCAP_TSO)
1027 ifp->if_hwassist |= CSUM_TSO;
1029 ifp->if_hwassist &= ~CSUM_TSO;
1031 if (mask & IFCAP_RSS)
1032 ifp->if_capenable ^= IFCAP_RSS;
1033 if (reinit && (ifp->if_flags & IFF_RUNNING))
1038 error = ether_ioctl(ifp, command, data);
1045 emx_watchdog(struct ifnet *ifp)
1047 struct emx_softc *sc = ifp->if_softc;
1049 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1052 * The timer is set to 5 every time start queues a packet.
1053 * Then txeof keeps resetting it as long as it cleans at
1054 * least one descriptor.
1055 * Finally, anytime all descriptors are clean the timer is
1059 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) ==
1060 E1000_READ_REG(&sc->hw, E1000_TDH(0))) {
1062 * If we reach here, all TX jobs are completed and
1063 * the TX engine should have been idled for some time.
1064 * We don't need to call if_devstart() here.
1066 ifp->if_flags &= ~IFF_OACTIVE;
1072 * If we are in this routine because of pause frames, then
1073 * don't reset the hardware.
1075 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1076 ifp->if_timer = EMX_TX_TIMEOUT;
1080 if (e1000_check_for_link(&sc->hw) == 0)
1081 if_printf(ifp, "watchdog timeout -- resetting\n");
1084 sc->watchdog_events++;
1088 if (!ifq_is_empty(&ifp->if_snd))
1095 struct emx_softc *sc = xsc;
1096 struct ifnet *ifp = &sc->arpcom.ac_if;
1097 device_t dev = sc->dev;
1101 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1106 * Packet Buffer Allocation (PBA)
1107 * Writing PBA sets the receive portion of the buffer
1108 * the remainder is used for the transmit buffer.
1110 switch (sc->hw.mac.type) {
1111 /* Total Packet Buffer on these is 48K */
1114 case e1000_80003es2lan:
1115 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1118 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1119 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1123 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1127 /* Devices before 82547 had a Packet Buffer of 64K. */
1128 if (sc->max_frame_size > 8192)
1129 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1131 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1133 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1135 /* Get the latest mac address, User can use a LAA */
1136 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1138 /* Put the address into the Receive Address Array */
1139 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1142 * With the 82571 sc, RAR[0] may be overwritten
1143 * when the other port is reset, we make a duplicate
1144 * in RAR[14] for that eventuality, this assures
1145 * the interface continues to function.
1147 if (sc->hw.mac.type == e1000_82571) {
1148 e1000_set_laa_state_82571(&sc->hw, TRUE);
1149 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1150 E1000_RAR_ENTRIES - 1);
1153 /* Initialize the hardware */
1154 if (emx_reset(sc)) {
1155 device_printf(dev, "Unable to reset the hardware\n");
1156 /* XXX emx_stop()? */
1159 emx_update_link_status(sc);
1161 /* Setup VLAN support, basic and offload if available */
1162 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1164 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1167 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1168 ctrl |= E1000_CTRL_VME;
1169 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1172 /* Configure for OS presence */
1175 /* Prepare transmit descriptors and buffers */
1176 emx_init_tx_ring(sc);
1177 emx_init_tx_unit(sc);
1179 /* Setup Multicast table */
1182 /* Prepare receive descriptors and buffers */
1183 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1184 if (emx_init_rx_ring(sc, &sc->rx_data[i])) {
1186 "Could not setup receive structures\n");
1191 emx_init_rx_unit(sc);
1193 /* Don't lose promiscuous settings */
1194 emx_set_promisc(sc);
1196 ifp->if_flags |= IFF_RUNNING;
1197 ifp->if_flags &= ~IFF_OACTIVE;
1199 callout_reset(&sc->timer, hz, emx_timer, sc);
1200 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1202 /* MSI/X configuration for 82574 */
1203 if (sc->hw.mac.type == e1000_82574) {
1206 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1207 tmp |= E1000_CTRL_EXT_PBA_CLR;
1208 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1211 * Set the IVAR - interrupt vector routing.
1212 * Each nibble represents a vector, high bit
1213 * is enable, other 3 bits are the MSIX table
1214 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1215 * Link (other) to 2, hence the magic number.
1217 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1220 #ifdef IFPOLL_ENABLE
1222 * Only enable interrupts if we are not polling, make sure
1223 * they are off otherwise.
1225 if (ifp->if_flags & IFF_NPOLLING)
1226 emx_disable_intr(sc);
1228 #endif /* IFPOLL_ENABLE */
1229 emx_enable_intr(sc);
1231 /* AMT based hardware can now take control from firmware */
1232 if (sc->has_manage && sc->has_amt)
1233 emx_get_hw_control(sc);
1235 /* Don't reset the phy next time init gets called */
1236 sc->hw.phy.reset_disable = TRUE;
1242 emx_intr_body(xsc, TRUE);
1246 emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted)
1248 struct ifnet *ifp = &sc->arpcom.ac_if;
1252 ASSERT_SERIALIZED(&sc->main_serialize);
1254 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1256 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
1262 * XXX: some laptops trigger several spurious interrupts
1263 * on emx(4) when in the resume cycle. The ICR register
1264 * reports all-ones value in this case. Processing such
1265 * interrupts would lead to a freeze. I don't know why.
1267 if (reg_icr == 0xffffffff) {
1272 if (ifp->if_flags & IFF_RUNNING) {
1274 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1277 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1278 lwkt_serialize_enter(
1279 &sc->rx_data[i].rx_serialize);
1280 emx_rxeof(sc, i, -1);
1281 lwkt_serialize_exit(
1282 &sc->rx_data[i].rx_serialize);
1285 if (reg_icr & E1000_ICR_TXDW) {
1286 lwkt_serialize_enter(&sc->tx_serialize);
1288 if (!ifq_is_empty(&ifp->if_snd))
1290 lwkt_serialize_exit(&sc->tx_serialize);
1294 /* Link status change */
1295 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1296 emx_serialize_skipmain(sc);
1298 callout_stop(&sc->timer);
1299 sc->hw.mac.get_link_status = 1;
1300 emx_update_link_status(sc);
1302 /* Deal with TX cruft when link lost */
1305 callout_reset(&sc->timer, hz, emx_timer, sc);
1307 emx_deserialize_skipmain(sc);
1310 if (reg_icr & E1000_ICR_RXO)
1317 emx_intr_mask(void *xsc)
1319 struct emx_softc *sc = xsc;
1321 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
1324 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1325 * so don't check it.
1327 emx_intr_body(sc, FALSE);
1328 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
1332 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1334 struct emx_softc *sc = ifp->if_softc;
1336 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1338 emx_update_link_status(sc);
1340 ifmr->ifm_status = IFM_AVALID;
1341 ifmr->ifm_active = IFM_ETHER;
1343 if (!sc->link_active)
1346 ifmr->ifm_status |= IFM_ACTIVE;
1348 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1349 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1350 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1352 switch (sc->link_speed) {
1354 ifmr->ifm_active |= IFM_10_T;
1357 ifmr->ifm_active |= IFM_100_TX;
1361 ifmr->ifm_active |= IFM_1000_T;
1364 if (sc->link_duplex == FULL_DUPLEX)
1365 ifmr->ifm_active |= IFM_FDX;
1367 ifmr->ifm_active |= IFM_HDX;
1372 emx_media_change(struct ifnet *ifp)
1374 struct emx_softc *sc = ifp->if_softc;
1375 struct ifmedia *ifm = &sc->media;
1377 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1379 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1382 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1384 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1385 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1391 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1392 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1396 sc->hw.mac.autoneg = FALSE;
1397 sc->hw.phy.autoneg_advertised = 0;
1398 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1399 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1401 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1405 sc->hw.mac.autoneg = FALSE;
1406 sc->hw.phy.autoneg_advertised = 0;
1407 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1408 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1410 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1414 if_printf(ifp, "Unsupported media type\n");
1419 * As the speed/duplex settings my have changed we need to
1422 sc->hw.phy.reset_disable = FALSE;
1430 emx_encap(struct emx_softc *sc, struct mbuf **m_headp)
1432 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1434 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
1435 struct e1000_tx_desc *ctxd = NULL;
1436 struct mbuf *m_head = *m_headp;
1437 uint32_t txd_upper, txd_lower, cmd = 0;
1438 int maxsegs, nsegs, i, j, first, last = 0, error;
1440 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1441 error = emx_tso_pullup(sc, m_headp);
1447 txd_upper = txd_lower = 0;
1450 * Capture the first descriptor index, this descriptor
1451 * will have the index of the EOP which is the only one
1452 * that now gets a DONE bit writeback.
1454 first = sc->next_avail_tx_desc;
1455 tx_buffer = &sc->tx_buf[first];
1456 tx_buffer_mapped = tx_buffer;
1457 map = tx_buffer->map;
1459 maxsegs = sc->num_tx_desc_avail - EMX_TX_RESERVED;
1460 KASSERT(maxsegs >= sc->spare_tx_desc, ("not enough spare TX desc"));
1461 if (maxsegs > EMX_MAX_SCATTER)
1462 maxsegs = EMX_MAX_SCATTER;
1464 error = bus_dmamap_load_mbuf_defrag(sc->txtag, map, m_headp,
1465 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1467 if (error == ENOBUFS)
1468 sc->mbuf_alloc_failed++;
1470 sc->no_tx_dma_setup++;
1476 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE);
1479 sc->tx_nsegs += nsegs;
1481 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1482 /* TSO will consume one TX desc */
1483 sc->tx_nsegs += emx_tso_setup(sc, m_head,
1484 &txd_upper, &txd_lower);
1485 } else if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1486 /* TX csum offloading will consume one TX desc */
1487 sc->tx_nsegs += emx_txcsum(sc, m_head, &txd_upper, &txd_lower);
1489 i = sc->next_avail_tx_desc;
1491 /* Set up our transmit descriptors */
1492 for (j = 0; j < nsegs; j++) {
1493 tx_buffer = &sc->tx_buf[i];
1494 ctxd = &sc->tx_desc_base[i];
1496 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1497 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1498 txd_lower | segs[j].ds_len);
1499 ctxd->upper.data = htole32(txd_upper);
1502 if (++i == sc->num_tx_desc)
1506 sc->next_avail_tx_desc = i;
1508 KKASSERT(sc->num_tx_desc_avail > nsegs);
1509 sc->num_tx_desc_avail -= nsegs;
1511 /* Handle VLAN tag */
1512 if (m_head->m_flags & M_VLANTAG) {
1513 /* Set the vlan id. */
1514 ctxd->upper.fields.special =
1515 htole16(m_head->m_pkthdr.ether_vlantag);
1517 /* Tell hardware to add tag */
1518 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1521 tx_buffer->m_head = m_head;
1522 tx_buffer_mapped->map = tx_buffer->map;
1523 tx_buffer->map = map;
1525 if (sc->tx_nsegs >= sc->tx_int_nsegs) {
1529 * Report Status (RS) is turned on
1530 * every tx_int_nsegs descriptors.
1532 cmd = E1000_TXD_CMD_RS;
1535 * Keep track of the descriptor, which will
1536 * be written back by hardware.
1538 sc->tx_dd[sc->tx_dd_tail] = last;
1539 EMX_INC_TXDD_IDX(sc->tx_dd_tail);
1540 KKASSERT(sc->tx_dd_tail != sc->tx_dd_head);
1544 * Last Descriptor of Packet needs End Of Packet (EOP)
1546 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1549 * Advance the Transmit Descriptor Tail (TDT), this tells
1550 * the E1000 that this frame is available to transmit.
1552 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), i);
1558 emx_set_promisc(struct emx_softc *sc)
1560 struct ifnet *ifp = &sc->arpcom.ac_if;
1563 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1565 if (ifp->if_flags & IFF_PROMISC) {
1566 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1567 /* Turn this on if you want to see bad packets */
1569 reg_rctl |= E1000_RCTL_SBP;
1570 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1571 } else if (ifp->if_flags & IFF_ALLMULTI) {
1572 reg_rctl |= E1000_RCTL_MPE;
1573 reg_rctl &= ~E1000_RCTL_UPE;
1574 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1579 emx_disable_promisc(struct emx_softc *sc)
1583 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1585 reg_rctl &= ~E1000_RCTL_UPE;
1586 reg_rctl &= ~E1000_RCTL_MPE;
1587 reg_rctl &= ~E1000_RCTL_SBP;
1588 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1592 emx_set_multi(struct emx_softc *sc)
1594 struct ifnet *ifp = &sc->arpcom.ac_if;
1595 struct ifmultiaddr *ifma;
1596 uint32_t reg_rctl = 0;
1601 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1603 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1604 if (ifma->ifma_addr->sa_family != AF_LINK)
1607 if (mcnt == EMX_MCAST_ADDR_MAX)
1610 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1611 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1615 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1616 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1617 reg_rctl |= E1000_RCTL_MPE;
1618 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1620 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1625 * This routine checks for link status and updates statistics.
1628 emx_timer(void *xsc)
1630 struct emx_softc *sc = xsc;
1631 struct ifnet *ifp = &sc->arpcom.ac_if;
1633 ifnet_serialize_all(ifp);
1635 emx_update_link_status(sc);
1636 emx_update_stats(sc);
1638 /* Reset LAA into RAR[0] on 82571 */
1639 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1640 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1642 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1643 emx_print_hw_stats(sc);
1647 callout_reset(&sc->timer, hz, emx_timer, sc);
1649 ifnet_deserialize_all(ifp);
1653 emx_update_link_status(struct emx_softc *sc)
1655 struct e1000_hw *hw = &sc->hw;
1656 struct ifnet *ifp = &sc->arpcom.ac_if;
1657 device_t dev = sc->dev;
1658 uint32_t link_check = 0;
1660 /* Get the cached link value or read phy for real */
1661 switch (hw->phy.media_type) {
1662 case e1000_media_type_copper:
1663 if (hw->mac.get_link_status) {
1664 /* Do the work to read phy */
1665 e1000_check_for_link(hw);
1666 link_check = !hw->mac.get_link_status;
1667 if (link_check) /* ESB2 fix */
1668 e1000_cfg_on_link_up(hw);
1674 case e1000_media_type_fiber:
1675 e1000_check_for_link(hw);
1676 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1679 case e1000_media_type_internal_serdes:
1680 e1000_check_for_link(hw);
1681 link_check = sc->hw.mac.serdes_has_link;
1684 case e1000_media_type_unknown:
1689 /* Now check for a transition */
1690 if (link_check && sc->link_active == 0) {
1691 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1695 * Check if we should enable/disable SPEED_MODE bit on
1698 if (sc->link_speed != SPEED_1000 &&
1699 (hw->mac.type == e1000_82571 ||
1700 hw->mac.type == e1000_82572)) {
1703 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1704 tarc0 &= ~EMX_TARC_SPEED_MODE;
1705 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1708 device_printf(dev, "Link is up %d Mbps %s\n",
1710 ((sc->link_duplex == FULL_DUPLEX) ?
1711 "Full Duplex" : "Half Duplex"));
1713 sc->link_active = 1;
1715 ifp->if_baudrate = sc->link_speed * 1000000;
1716 ifp->if_link_state = LINK_STATE_UP;
1717 if_link_state_change(ifp);
1718 } else if (!link_check && sc->link_active == 1) {
1719 ifp->if_baudrate = sc->link_speed = 0;
1720 sc->link_duplex = 0;
1722 device_printf(dev, "Link is Down\n");
1723 sc->link_active = 0;
1725 /* Link down, disable watchdog */
1728 ifp->if_link_state = LINK_STATE_DOWN;
1729 if_link_state_change(ifp);
1734 emx_stop(struct emx_softc *sc)
1736 struct ifnet *ifp = &sc->arpcom.ac_if;
1739 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1741 emx_disable_intr(sc);
1743 callout_stop(&sc->timer);
1745 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1749 * Disable multiple receive queues.
1752 * We should disable multiple receive queues before
1753 * resetting the hardware.
1755 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1757 e1000_reset_hw(&sc->hw);
1758 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1760 for (i = 0; i < sc->num_tx_desc; i++) {
1761 struct emx_txbuf *tx_buffer = &sc->tx_buf[i];
1763 if (tx_buffer->m_head != NULL) {
1764 bus_dmamap_unload(sc->txtag, tx_buffer->map);
1765 m_freem(tx_buffer->m_head);
1766 tx_buffer->m_head = NULL;
1770 for (i = 0; i < sc->rx_ring_cnt; ++i)
1771 emx_free_rx_ring(sc, &sc->rx_data[i]);
1775 sc->csum_iphlen = 0;
1778 sc->csum_pktlen = 0;
1786 emx_reset(struct emx_softc *sc)
1788 device_t dev = sc->dev;
1789 uint16_t rx_buffer_size;
1791 /* Set up smart power down as default off on newer adapters. */
1792 if (!emx_smart_pwr_down &&
1793 (sc->hw.mac.type == e1000_82571 ||
1794 sc->hw.mac.type == e1000_82572)) {
1795 uint16_t phy_tmp = 0;
1797 /* Speed up time to link by disabling smart power down. */
1798 e1000_read_phy_reg(&sc->hw,
1799 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1800 phy_tmp &= ~IGP02E1000_PM_SPD;
1801 e1000_write_phy_reg(&sc->hw,
1802 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1806 * These parameters control the automatic generation (Tx) and
1807 * response (Rx) to Ethernet PAUSE frames.
1808 * - High water mark should allow for at least two frames to be
1809 * received after sending an XOFF.
1810 * - Low water mark works best when it is very near the high water mark.
1811 * This allows the receiver to restart by sending XON when it has
1812 * drained a bit. Here we use an arbitary value of 1500 which will
1813 * restart after one full frame is pulled from the buffer. There
1814 * could be several smaller frames in the buffer and if so they will
1815 * not trigger the XON until their total number reduces the buffer
1817 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1819 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1821 sc->hw.fc.high_water = rx_buffer_size -
1822 roundup2(sc->max_frame_size, 1024);
1823 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1825 if (sc->hw.mac.type == e1000_80003es2lan)
1826 sc->hw.fc.pause_time = 0xFFFF;
1828 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1829 sc->hw.fc.send_xon = TRUE;
1830 sc->hw.fc.requested_mode = e1000_fc_full;
1832 /* Issue a global reset */
1833 e1000_reset_hw(&sc->hw);
1834 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1835 emx_disable_aspm(sc);
1837 if (e1000_init_hw(&sc->hw) < 0) {
1838 device_printf(dev, "Hardware Initialization Failed\n");
1842 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1843 e1000_get_phy_info(&sc->hw);
1844 e1000_check_for_link(&sc->hw);
1850 emx_setup_ifp(struct emx_softc *sc)
1852 struct ifnet *ifp = &sc->arpcom.ac_if;
1854 if_initname(ifp, device_get_name(sc->dev),
1855 device_get_unit(sc->dev));
1857 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1858 ifp->if_init = emx_init;
1859 ifp->if_ioctl = emx_ioctl;
1860 ifp->if_start = emx_start;
1861 #ifdef IFPOLL_ENABLE
1862 ifp->if_qpoll = emx_qpoll;
1864 ifp->if_watchdog = emx_watchdog;
1865 ifp->if_serialize = emx_serialize;
1866 ifp->if_deserialize = emx_deserialize;
1867 ifp->if_tryserialize = emx_tryserialize;
1869 ifp->if_serialize_assert = emx_serialize_assert;
1871 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);
1872 ifq_set_ready(&ifp->if_snd);
1874 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1876 ifp->if_capabilities = IFCAP_HWCSUM |
1877 IFCAP_VLAN_HWTAGGING |
1880 if (sc->rx_ring_cnt > 1)
1881 ifp->if_capabilities |= IFCAP_RSS;
1882 ifp->if_capenable = ifp->if_capabilities;
1883 ifp->if_hwassist = EMX_CSUM_FEATURES | CSUM_TSO;
1886 * Tell the upper layer(s) we support long frames.
1888 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1891 * Specify the media types supported by this sc and register
1892 * callbacks to update media and link information
1894 ifmedia_init(&sc->media, IFM_IMASK,
1895 emx_media_change, emx_media_status);
1896 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1897 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1898 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1900 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1902 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1903 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1905 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1906 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1908 if (sc->hw.phy.type != e1000_phy_ife) {
1909 ifmedia_add(&sc->media,
1910 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1911 ifmedia_add(&sc->media,
1912 IFM_ETHER | IFM_1000_T, 0, NULL);
1915 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1916 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1920 * Workaround for SmartSpeed on 82541 and 82547 controllers
1923 emx_smartspeed(struct emx_softc *sc)
1927 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
1928 sc->hw.mac.autoneg == 0 ||
1929 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
1932 if (sc->smartspeed == 0) {
1934 * If Master/Slave config fault is asserted twice,
1935 * we assume back-to-back
1937 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1938 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
1940 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1941 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
1942 e1000_read_phy_reg(&sc->hw,
1943 PHY_1000T_CTRL, &phy_tmp);
1944 if (phy_tmp & CR_1000T_MS_ENABLE) {
1945 phy_tmp &= ~CR_1000T_MS_ENABLE;
1946 e1000_write_phy_reg(&sc->hw,
1947 PHY_1000T_CTRL, phy_tmp);
1949 if (sc->hw.mac.autoneg &&
1950 !e1000_phy_setup_autoneg(&sc->hw) &&
1951 !e1000_read_phy_reg(&sc->hw,
1952 PHY_CONTROL, &phy_tmp)) {
1953 phy_tmp |= MII_CR_AUTO_NEG_EN |
1954 MII_CR_RESTART_AUTO_NEG;
1955 e1000_write_phy_reg(&sc->hw,
1956 PHY_CONTROL, phy_tmp);
1961 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
1962 /* If still no link, perhaps using 2/3 pair cable */
1963 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
1964 phy_tmp |= CR_1000T_MS_ENABLE;
1965 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
1966 if (sc->hw.mac.autoneg &&
1967 !e1000_phy_setup_autoneg(&sc->hw) &&
1968 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
1969 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
1970 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
1974 /* Restart process after EMX_SMARTSPEED_MAX iterations */
1975 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
1980 emx_create_tx_ring(struct emx_softc *sc)
1982 device_t dev = sc->dev;
1983 struct emx_txbuf *tx_buffer;
1984 int error, i, tsize, ntxd;
1987 * Validate number of transmit descriptors. It must not exceed
1988 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
1990 ntxd = device_getenv_int(dev, "txd", emx_txd);
1991 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
1992 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) {
1993 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
1994 EMX_DEFAULT_TXD, ntxd);
1995 sc->num_tx_desc = EMX_DEFAULT_TXD;
1997 sc->num_tx_desc = ntxd;
2001 * Allocate Transmit Descriptor ring
2003 tsize = roundup2(sc->num_tx_desc * sizeof(struct e1000_tx_desc),
2005 sc->tx_desc_base = bus_dmamem_coherent_any(sc->parent_dtag,
2006 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
2007 &sc->tx_desc_dtag, &sc->tx_desc_dmap,
2008 &sc->tx_desc_paddr);
2009 if (sc->tx_desc_base == NULL) {
2010 device_printf(dev, "Unable to allocate tx_desc memory\n");
2014 sc->tx_buf = kmalloc(sizeof(struct emx_txbuf) * sc->num_tx_desc,
2015 M_DEVBUF, M_WAITOK | M_ZERO);
2018 * Create DMA tags for tx buffers
2020 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2021 1, 0, /* alignment, bounds */
2022 BUS_SPACE_MAXADDR, /* lowaddr */
2023 BUS_SPACE_MAXADDR, /* highaddr */
2024 NULL, NULL, /* filter, filterarg */
2025 EMX_TSO_SIZE, /* maxsize */
2026 EMX_MAX_SCATTER, /* nsegments */
2027 EMX_MAX_SEGSIZE, /* maxsegsize */
2028 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2029 BUS_DMA_ONEBPAGE, /* flags */
2032 device_printf(dev, "Unable to allocate TX DMA tag\n");
2033 kfree(sc->tx_buf, M_DEVBUF);
2039 * Create DMA maps for tx buffers
2041 for (i = 0; i < sc->num_tx_desc; i++) {
2042 tx_buffer = &sc->tx_buf[i];
2044 error = bus_dmamap_create(sc->txtag,
2045 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2048 device_printf(dev, "Unable to create TX DMA map\n");
2049 emx_destroy_tx_ring(sc, i);
2057 emx_init_tx_ring(struct emx_softc *sc)
2059 /* Clear the old ring contents */
2060 bzero(sc->tx_desc_base,
2061 sizeof(struct e1000_tx_desc) * sc->num_tx_desc);
2064 sc->next_avail_tx_desc = 0;
2065 sc->next_tx_to_clean = 0;
2066 sc->num_tx_desc_avail = sc->num_tx_desc;
2070 emx_init_tx_unit(struct emx_softc *sc)
2072 uint32_t tctl, tarc, tipg = 0;
2075 /* Setup the Base and Length of the Tx Descriptor Ring */
2076 bus_addr = sc->tx_desc_paddr;
2077 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0),
2078 sc->num_tx_desc * sizeof(struct e1000_tx_desc));
2079 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0),
2080 (uint32_t)(bus_addr >> 32));
2081 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0),
2082 (uint32_t)bus_addr);
2083 /* Setup the HW Tx Head and Tail descriptor pointers */
2084 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0);
2085 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0);
2087 /* Set the default values for the Tx Inter Packet Gap timer */
2088 switch (sc->hw.mac.type) {
2089 case e1000_80003es2lan:
2090 tipg = DEFAULT_82543_TIPG_IPGR1;
2091 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2092 E1000_TIPG_IPGR2_SHIFT;
2096 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2097 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2098 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2100 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2101 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2102 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2106 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2108 /* NOTE: 0 is not allowed for TIDV */
2109 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2110 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2112 if (sc->hw.mac.type == e1000_82571 ||
2113 sc->hw.mac.type == e1000_82572) {
2114 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2115 tarc |= EMX_TARC_SPEED_MODE;
2116 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2117 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2118 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2120 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2121 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2123 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2126 /* Program the Transmit Control Register */
2127 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2128 tctl &= ~E1000_TCTL_CT;
2129 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2130 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2131 tctl |= E1000_TCTL_MULR;
2133 /* This write will effectively turn on the transmit unit. */
2134 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2138 emx_destroy_tx_ring(struct emx_softc *sc, int ndesc)
2140 struct emx_txbuf *tx_buffer;
2143 /* Free Transmit Descriptor ring */
2144 if (sc->tx_desc_base) {
2145 bus_dmamap_unload(sc->tx_desc_dtag, sc->tx_desc_dmap);
2146 bus_dmamem_free(sc->tx_desc_dtag, sc->tx_desc_base,
2148 bus_dma_tag_destroy(sc->tx_desc_dtag);
2150 sc->tx_desc_base = NULL;
2153 if (sc->tx_buf == NULL)
2156 for (i = 0; i < ndesc; i++) {
2157 tx_buffer = &sc->tx_buf[i];
2159 KKASSERT(tx_buffer->m_head == NULL);
2160 bus_dmamap_destroy(sc->txtag, tx_buffer->map);
2162 bus_dma_tag_destroy(sc->txtag);
2164 kfree(sc->tx_buf, M_DEVBUF);
2169 * The offload context needs to be set when we transfer the first
2170 * packet of a particular protocol (TCP/UDP). This routine has been
2171 * enhanced to deal with inserted VLAN headers.
2173 * If the new packet's ether header length, ip header length and
2174 * csum offloading type are same as the previous packet, we should
2175 * avoid allocating a new csum context descriptor; mainly to take
2176 * advantage of the pipeline effect of the TX data read request.
2178 * This function returns number of TX descrptors allocated for
2182 emx_txcsum(struct emx_softc *sc, struct mbuf *mp,
2183 uint32_t *txd_upper, uint32_t *txd_lower)
2185 struct e1000_context_desc *TXD;
2186 int curr_txd, ehdrlen, csum_flags;
2187 uint32_t cmd, hdr_len, ip_hlen;
2189 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2190 ip_hlen = mp->m_pkthdr.csum_iphlen;
2191 ehdrlen = mp->m_pkthdr.csum_lhlen;
2193 if (sc->csum_lhlen == ehdrlen && sc->csum_iphlen == ip_hlen &&
2194 sc->csum_flags == csum_flags) {
2196 * Same csum offload context as the previous packets;
2199 *txd_upper = sc->csum_txd_upper;
2200 *txd_lower = sc->csum_txd_lower;
2205 * Setup a new csum offload context.
2208 curr_txd = sc->next_avail_tx_desc;
2209 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd];
2213 /* Setup of IP header checksum. */
2214 if (csum_flags & CSUM_IP) {
2216 * Start offset for header checksum calculation.
2217 * End offset for header checksum calculation.
2218 * Offset of place to put the checksum.
2220 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2221 TXD->lower_setup.ip_fields.ipcse =
2222 htole16(ehdrlen + ip_hlen - 1);
2223 TXD->lower_setup.ip_fields.ipcso =
2224 ehdrlen + offsetof(struct ip, ip_sum);
2225 cmd |= E1000_TXD_CMD_IP;
2226 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2228 hdr_len = ehdrlen + ip_hlen;
2230 if (csum_flags & CSUM_TCP) {
2232 * Start offset for payload checksum calculation.
2233 * End offset for payload checksum calculation.
2234 * Offset of place to put the checksum.
2236 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2237 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2238 TXD->upper_setup.tcp_fields.tucso =
2239 hdr_len + offsetof(struct tcphdr, th_sum);
2240 cmd |= E1000_TXD_CMD_TCP;
2241 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2242 } else if (csum_flags & CSUM_UDP) {
2244 * Start offset for header checksum calculation.
2245 * End offset for header checksum calculation.
2246 * Offset of place to put the checksum.
2248 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2249 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2250 TXD->upper_setup.tcp_fields.tucso =
2251 hdr_len + offsetof(struct udphdr, uh_sum);
2252 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2255 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2256 E1000_TXD_DTYP_D; /* Data descr */
2258 /* Save the information for this csum offloading context */
2259 sc->csum_lhlen = ehdrlen;
2260 sc->csum_iphlen = ip_hlen;
2261 sc->csum_flags = csum_flags;
2262 sc->csum_txd_upper = *txd_upper;
2263 sc->csum_txd_lower = *txd_lower;
2265 TXD->tcp_seg_setup.data = htole32(0);
2266 TXD->cmd_and_length =
2267 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2269 if (++curr_txd == sc->num_tx_desc)
2272 KKASSERT(sc->num_tx_desc_avail > 0);
2273 sc->num_tx_desc_avail--;
2275 sc->next_avail_tx_desc = curr_txd;
2280 emx_txeof(struct emx_softc *sc)
2282 struct ifnet *ifp = &sc->arpcom.ac_if;
2283 struct emx_txbuf *tx_buffer;
2284 int first, num_avail;
2286 if (sc->tx_dd_head == sc->tx_dd_tail)
2289 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2292 num_avail = sc->num_tx_desc_avail;
2293 first = sc->next_tx_to_clean;
2295 while (sc->tx_dd_head != sc->tx_dd_tail) {
2296 int dd_idx = sc->tx_dd[sc->tx_dd_head];
2297 struct e1000_tx_desc *tx_desc;
2299 tx_desc = &sc->tx_desc_base[dd_idx];
2300 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2301 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2303 if (++dd_idx == sc->num_tx_desc)
2306 while (first != dd_idx) {
2311 tx_buffer = &sc->tx_buf[first];
2312 if (tx_buffer->m_head) {
2314 bus_dmamap_unload(sc->txtag,
2316 m_freem(tx_buffer->m_head);
2317 tx_buffer->m_head = NULL;
2320 if (++first == sc->num_tx_desc)
2327 sc->next_tx_to_clean = first;
2328 sc->num_tx_desc_avail = num_avail;
2330 if (sc->tx_dd_head == sc->tx_dd_tail) {
2335 if (!EMX_IS_OACTIVE(sc)) {
2336 ifp->if_flags &= ~IFF_OACTIVE;
2338 /* All clean, turn off the timer */
2339 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2345 emx_tx_collect(struct emx_softc *sc)
2347 struct ifnet *ifp = &sc->arpcom.ac_if;
2348 struct emx_txbuf *tx_buffer;
2349 int tdh, first, num_avail, dd_idx = -1;
2351 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2354 tdh = E1000_READ_REG(&sc->hw, E1000_TDH(0));
2355 if (tdh == sc->next_tx_to_clean)
2358 if (sc->tx_dd_head != sc->tx_dd_tail)
2359 dd_idx = sc->tx_dd[sc->tx_dd_head];
2361 num_avail = sc->num_tx_desc_avail;
2362 first = sc->next_tx_to_clean;
2364 while (first != tdh) {
2369 tx_buffer = &sc->tx_buf[first];
2370 if (tx_buffer->m_head) {
2372 bus_dmamap_unload(sc->txtag,
2374 m_freem(tx_buffer->m_head);
2375 tx_buffer->m_head = NULL;
2378 if (first == dd_idx) {
2379 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2380 if (sc->tx_dd_head == sc->tx_dd_tail) {
2385 dd_idx = sc->tx_dd[sc->tx_dd_head];
2389 if (++first == sc->num_tx_desc)
2392 sc->next_tx_to_clean = first;
2393 sc->num_tx_desc_avail = num_avail;
2395 if (!EMX_IS_OACTIVE(sc)) {
2396 ifp->if_flags &= ~IFF_OACTIVE;
2398 /* All clean, turn off the timer */
2399 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2405 * When Link is lost sometimes there is work still in the TX ring
2406 * which will result in a watchdog, rather than allow that do an
2407 * attempted cleanup and then reinit here. Note that this has been
2408 * seens mostly with fiber adapters.
2411 emx_tx_purge(struct emx_softc *sc)
2413 struct ifnet *ifp = &sc->arpcom.ac_if;
2415 if (!sc->link_active && ifp->if_timer) {
2417 if (ifp->if_timer) {
2418 if_printf(ifp, "Link lost, TX pending, reinit\n");
2426 emx_newbuf(struct emx_softc *sc, struct emx_rxdata *rdata, int i, int init)
2429 bus_dma_segment_t seg;
2431 struct emx_rxbuf *rx_buffer;
2434 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2436 rdata->mbuf_cluster_failed++;
2438 if_printf(&sc->arpcom.ac_if,
2439 "Unable to allocate RX mbuf\n");
2443 m->m_len = m->m_pkthdr.len = MCLBYTES;
2445 if (sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2446 m_adj(m, ETHER_ALIGN);
2448 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2449 rdata->rx_sparemap, m,
2450 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2454 if_printf(&sc->arpcom.ac_if,
2455 "Unable to load RX mbuf\n");
2460 rx_buffer = &rdata->rx_buf[i];
2461 if (rx_buffer->m_head != NULL)
2462 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2464 map = rx_buffer->map;
2465 rx_buffer->map = rdata->rx_sparemap;
2466 rdata->rx_sparemap = map;
2468 rx_buffer->m_head = m;
2469 rx_buffer->paddr = seg.ds_addr;
2471 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
2476 emx_create_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2478 device_t dev = sc->dev;
2479 struct emx_rxbuf *rx_buffer;
2480 int i, error, rsize, nrxd;
2483 * Validate number of receive descriptors. It must not exceed
2484 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2486 nrxd = device_getenv_int(dev, "rxd", emx_rxd);
2487 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2488 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) {
2489 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
2490 EMX_DEFAULT_RXD, nrxd);
2491 rdata->num_rx_desc = EMX_DEFAULT_RXD;
2493 rdata->num_rx_desc = nrxd;
2497 * Allocate Receive Descriptor ring
2499 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
2501 rdata->rx_desc = bus_dmamem_coherent_any(sc->parent_dtag,
2502 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2503 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2504 &rdata->rx_desc_paddr);
2505 if (rdata->rx_desc == NULL) {
2506 device_printf(dev, "Unable to allocate rx_desc memory\n");
2510 rdata->rx_buf = kmalloc(sizeof(struct emx_rxbuf) * rdata->num_rx_desc,
2511 M_DEVBUF, M_WAITOK | M_ZERO);
2514 * Create DMA tag for rx buffers
2516 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2517 1, 0, /* alignment, bounds */
2518 BUS_SPACE_MAXADDR, /* lowaddr */
2519 BUS_SPACE_MAXADDR, /* highaddr */
2520 NULL, NULL, /* filter, filterarg */
2521 MCLBYTES, /* maxsize */
2523 MCLBYTES, /* maxsegsize */
2524 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2527 device_printf(dev, "Unable to allocate RX DMA tag\n");
2528 kfree(rdata->rx_buf, M_DEVBUF);
2529 rdata->rx_buf = NULL;
2534 * Create spare DMA map for rx buffers
2536 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2537 &rdata->rx_sparemap);
2539 device_printf(dev, "Unable to create spare RX DMA map\n");
2540 bus_dma_tag_destroy(rdata->rxtag);
2541 kfree(rdata->rx_buf, M_DEVBUF);
2542 rdata->rx_buf = NULL;
2547 * Create DMA maps for rx buffers
2549 for (i = 0; i < rdata->num_rx_desc; i++) {
2550 rx_buffer = &rdata->rx_buf[i];
2552 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2555 device_printf(dev, "Unable to create RX DMA map\n");
2556 emx_destroy_rx_ring(sc, rdata, i);
2564 emx_free_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2568 for (i = 0; i < rdata->num_rx_desc; i++) {
2569 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
2571 if (rx_buffer->m_head != NULL) {
2572 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2573 m_freem(rx_buffer->m_head);
2574 rx_buffer->m_head = NULL;
2578 if (rdata->fmp != NULL)
2579 m_freem(rdata->fmp);
2585 emx_init_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2589 /* Reset descriptor ring */
2590 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
2592 /* Allocate new ones. */
2593 for (i = 0; i < rdata->num_rx_desc; i++) {
2594 error = emx_newbuf(sc, rdata, i, 1);
2599 /* Setup our descriptor pointers */
2600 rdata->next_rx_desc_to_check = 0;
2606 emx_init_rx_unit(struct emx_softc *sc)
2608 struct ifnet *ifp = &sc->arpcom.ac_if;
2610 uint32_t rctl, itr, rfctl;
2614 * Make sure receives are disabled while setting
2615 * up the descriptor ring
2617 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2618 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2621 * Set the interrupt throttling rate. Value is calculated
2622 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2624 if (sc->int_throttle_ceil)
2625 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2628 emx_set_itr(sc, itr);
2630 /* Use extended RX descriptor */
2631 rfctl = E1000_RFCTL_EXTEN;
2633 /* Disable accelerated ackknowledge */
2634 if (sc->hw.mac.type == e1000_82574)
2635 rfctl |= E1000_RFCTL_ACK_DIS;
2637 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
2640 * Receive Checksum Offload for TCP and UDP
2642 * Checksum offloading is also enabled if multiple receive
2643 * queue is to be supported, since we need it to figure out
2646 if ((ifp->if_capenable & IFCAP_RXCSUM) ||
2647 sc->rx_ring_cnt > 1) {
2650 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2654 * PCSD must be enabled to enable multiple
2657 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2659 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2663 * Configure multiple receive queue (RSS)
2665 if (sc->rx_ring_cnt > 1) {
2666 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2669 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING,
2670 ("invalid number of RX ring (%d)", sc->rx_ring_cnt));
2674 * When we reach here, RSS has already been disabled
2675 * in emx_stop(), so we could safely configure RSS key
2676 * and redirect table.
2682 toeplitz_get_key(key, sizeof(key));
2683 for (i = 0; i < EMX_NRSSRK; ++i) {
2686 rssrk = EMX_RSSRK_VAL(key, i);
2687 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2689 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2693 * Configure RSS redirect table in following fashion:
2694 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2697 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2700 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT;
2701 reta |= q << (8 * i);
2703 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2705 for (i = 0; i < EMX_NRETA; ++i)
2706 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
2709 * Enable multiple receive queues.
2710 * Enable IPv4 RSS standard hash functions.
2711 * Disable RSS interrupt.
2713 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2714 E1000_MRQC_ENABLE_RSS_2Q |
2715 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2716 E1000_MRQC_RSS_FIELD_IPV4);
2720 * XXX TEMPORARY WORKAROUND: on some systems with 82573
2721 * long latencies are observed, like Lenovo X60. This
2722 * change eliminates the problem, but since having positive
2723 * values in RDTR is a known source of problems on other
2724 * platforms another solution is being sought.
2726 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
2727 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
2728 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
2731 for (i = 0; i < sc->rx_ring_cnt; ++i) {
2732 struct emx_rxdata *rdata = &sc->rx_data[i];
2735 * Setup the Base and Length of the Rx Descriptor Ring
2737 bus_addr = rdata->rx_desc_paddr;
2738 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
2739 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
2740 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
2741 (uint32_t)(bus_addr >> 32));
2742 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
2743 (uint32_t)bus_addr);
2746 * Setup the HW Rx Head and Tail Descriptor Pointers
2748 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
2749 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
2750 sc->rx_data[i].num_rx_desc - 1);
2753 /* Setup the Receive Control Register */
2754 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2755 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2756 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
2757 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2759 /* Make sure VLAN Filters are off */
2760 rctl &= ~E1000_RCTL_VFE;
2762 /* Don't store bad paket */
2763 rctl &= ~E1000_RCTL_SBP;
2766 rctl |= E1000_RCTL_SZ_2048;
2768 if (ifp->if_mtu > ETHERMTU)
2769 rctl |= E1000_RCTL_LPE;
2771 rctl &= ~E1000_RCTL_LPE;
2773 /* Enable Receives */
2774 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
2778 emx_destroy_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata, int ndesc)
2780 struct emx_rxbuf *rx_buffer;
2783 /* Free Receive Descriptor ring */
2784 if (rdata->rx_desc) {
2785 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
2786 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
2787 rdata->rx_desc_dmap);
2788 bus_dma_tag_destroy(rdata->rx_desc_dtag);
2790 rdata->rx_desc = NULL;
2793 if (rdata->rx_buf == NULL)
2796 for (i = 0; i < ndesc; i++) {
2797 rx_buffer = &rdata->rx_buf[i];
2799 KKASSERT(rx_buffer->m_head == NULL);
2800 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
2802 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
2803 bus_dma_tag_destroy(rdata->rxtag);
2805 kfree(rdata->rx_buf, M_DEVBUF);
2806 rdata->rx_buf = NULL;
2810 emx_rxeof(struct emx_softc *sc, int ring_idx, int count)
2812 struct emx_rxdata *rdata = &sc->rx_data[ring_idx];
2813 struct ifnet *ifp = &sc->arpcom.ac_if;
2815 emx_rxdesc_t *current_desc;
2819 i = rdata->next_rx_desc_to_check;
2820 current_desc = &rdata->rx_desc[i];
2821 staterr = le32toh(current_desc->rxd_staterr);
2823 if (!(staterr & E1000_RXD_STAT_DD))
2826 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2827 struct pktinfo *pi = NULL, pi0;
2828 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
2829 struct mbuf *m = NULL;
2834 mp = rx_buf->m_head;
2837 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
2838 * needs to access the last received byte in the mbuf.
2840 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
2841 BUS_DMASYNC_POSTREAD);
2843 len = le16toh(current_desc->rxd_length);
2844 if (staterr & E1000_RXD_STAT_EOP) {
2851 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2853 uint32_t mrq, rss_hash;
2856 * Save several necessary information,
2857 * before emx_newbuf() destroy it.
2859 if ((staterr & E1000_RXD_STAT_VP) && eop)
2860 vlan = le16toh(current_desc->rxd_vlan);
2862 mrq = le32toh(current_desc->rxd_mrq);
2863 rss_hash = le32toh(current_desc->rxd_rss);
2865 EMX_RSS_DPRINTF(sc, 10,
2866 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
2867 ring_idx, mrq, rss_hash);
2869 if (emx_newbuf(sc, rdata, i, 0) != 0) {
2874 /* Assign correct length to the current fragment */
2877 if (rdata->fmp == NULL) {
2878 mp->m_pkthdr.len = len;
2879 rdata->fmp = mp; /* Store the first mbuf */
2883 * Chain mbuf's together
2885 rdata->lmp->m_next = mp;
2886 rdata->lmp = rdata->lmp->m_next;
2887 rdata->fmp->m_pkthdr.len += len;
2891 rdata->fmp->m_pkthdr.rcvif = ifp;
2894 if (ifp->if_capenable & IFCAP_RXCSUM)
2895 emx_rxcsum(staterr, rdata->fmp);
2897 if (staterr & E1000_RXD_STAT_VP) {
2898 rdata->fmp->m_pkthdr.ether_vlantag =
2900 rdata->fmp->m_flags |= M_VLANTAG;
2906 if (ifp->if_capenable & IFCAP_RSS) {
2907 pi = emx_rssinfo(m, &pi0, mrq,
2910 #ifdef EMX_RSS_DEBUG
2917 emx_setup_rxdesc(current_desc, rx_buf);
2918 if (rdata->fmp != NULL) {
2919 m_freem(rdata->fmp);
2927 ether_input_pkt(ifp, m, pi);
2929 /* Advance our pointers to the next descriptor. */
2930 if (++i == rdata->num_rx_desc)
2933 current_desc = &rdata->rx_desc[i];
2934 staterr = le32toh(current_desc->rxd_staterr);
2936 rdata->next_rx_desc_to_check = i;
2938 /* Advance the E1000's Receive Queue "Tail Pointer". */
2940 i = rdata->num_rx_desc - 1;
2941 E1000_WRITE_REG(&sc->hw, E1000_RDT(ring_idx), i);
2945 emx_enable_intr(struct emx_softc *sc)
2947 uint32_t ims_mask = IMS_ENABLE_MASK;
2949 lwkt_serialize_handler_enable(&sc->main_serialize);
2952 if (sc->hw.mac.type == e1000_82574) {
2953 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
2954 ims_mask |= EM_MSIX_MASK;
2957 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
2961 emx_disable_intr(struct emx_softc *sc)
2963 if (sc->hw.mac.type == e1000_82574)
2964 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
2965 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2967 lwkt_serialize_handler_disable(&sc->main_serialize);
2971 * Bit of a misnomer, what this really means is
2972 * to enable OS management of the system... aka
2973 * to disable special hardware management features
2976 emx_get_mgmt(struct emx_softc *sc)
2978 /* A shared code workaround */
2979 if (sc->has_manage) {
2980 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2981 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2983 /* disable hardware interception of ARP */
2984 manc &= ~(E1000_MANC_ARP_EN);
2986 /* enable receiving management packets to the host */
2987 manc |= E1000_MANC_EN_MNG2HOST;
2988 #define E1000_MNG2HOST_PORT_623 (1 << 5)
2989 #define E1000_MNG2HOST_PORT_664 (1 << 6)
2990 manc2h |= E1000_MNG2HOST_PORT_623;
2991 manc2h |= E1000_MNG2HOST_PORT_664;
2992 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2994 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2999 * Give control back to hardware management
3000 * controller if there is one.
3003 emx_rel_mgmt(struct emx_softc *sc)
3005 if (sc->has_manage) {
3006 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3008 /* re-enable hardware interception of ARP */
3009 manc |= E1000_MANC_ARP_EN;
3010 manc &= ~E1000_MANC_EN_MNG2HOST;
3012 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3017 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3018 * For ASF and Pass Through versions of f/w this means that
3019 * the driver is loaded. For AMT version (only with 82573)
3020 * of the f/w this means that the network i/f is open.
3023 emx_get_hw_control(struct emx_softc *sc)
3025 /* Let firmware know the driver has taken over */
3026 if (sc->hw.mac.type == e1000_82573) {
3029 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3030 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3031 swsm | E1000_SWSM_DRV_LOAD);
3035 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3036 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3037 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3043 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3044 * For ASF and Pass Through versions of f/w this means that the
3045 * driver is no longer loaded. For AMT version (only with 82573)
3046 * of the f/w this means that the network i/f is closed.
3049 emx_rel_hw_control(struct emx_softc *sc)
3051 if (!sc->control_hw)
3055 /* Let firmware taken over control of h/w */
3056 if (sc->hw.mac.type == e1000_82573) {
3059 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3060 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3061 swsm & ~E1000_SWSM_DRV_LOAD);
3065 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3066 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3067 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3072 emx_is_valid_eaddr(const uint8_t *addr)
3074 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3076 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3083 * Enable PCI Wake On Lan capability
3086 emx_enable_wol(device_t dev)
3088 uint16_t cap, status;
3091 /* First find the capabilities pointer*/
3092 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3094 /* Read the PM Capabilities */
3095 id = pci_read_config(dev, cap, 1);
3096 if (id != PCIY_PMG) /* Something wrong */
3100 * OK, we have the power capabilities,
3101 * so now get the status register
3103 cap += PCIR_POWER_STATUS;
3104 status = pci_read_config(dev, cap, 2);
3105 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3106 pci_write_config(dev, cap, status, 2);
3110 emx_update_stats(struct emx_softc *sc)
3112 struct ifnet *ifp = &sc->arpcom.ac_if;
3114 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3115 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3116 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3117 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3119 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3120 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3121 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3122 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3124 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3125 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3126 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3127 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3128 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3129 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3130 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3131 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3132 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3133 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3134 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3135 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3136 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3137 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3138 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3139 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3140 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3141 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3142 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3143 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3145 /* For the 64-bit byte counters the low dword must be read first. */
3146 /* Both registers clear on the read of the high dword */
3148 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3149 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3151 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3152 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3153 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3154 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3155 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3157 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3158 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3160 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3161 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3162 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3163 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3164 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3165 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3166 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3167 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3168 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3169 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3171 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3172 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3173 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3174 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3175 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3176 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3178 ifp->if_collisions = sc->stats.colc;
3181 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc +
3182 sc->stats.crcerrs + sc->stats.algnerrc +
3183 sc->stats.ruc + sc->stats.roc +
3184 sc->stats.mpc + sc->stats.cexterr;
3187 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol +
3188 sc->watchdog_events;
3192 emx_print_debug_info(struct emx_softc *sc)
3194 device_t dev = sc->dev;
3195 uint8_t *hw_addr = sc->hw.hw_addr;
3197 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3198 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3199 E1000_READ_REG(&sc->hw, E1000_CTRL),
3200 E1000_READ_REG(&sc->hw, E1000_RCTL));
3201 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3202 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3203 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3204 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3205 sc->hw.fc.high_water, sc->hw.fc.low_water);
3206 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3207 E1000_READ_REG(&sc->hw, E1000_TIDV),
3208 E1000_READ_REG(&sc->hw, E1000_TADV));
3209 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3210 E1000_READ_REG(&sc->hw, E1000_RDTR),
3211 E1000_READ_REG(&sc->hw, E1000_RADV));
3212 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3213 E1000_READ_REG(&sc->hw, E1000_TDH(0)),
3214 E1000_READ_REG(&sc->hw, E1000_TDT(0)));
3215 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3216 E1000_READ_REG(&sc->hw, E1000_RDH(0)),
3217 E1000_READ_REG(&sc->hw, E1000_RDT(0)));
3218 device_printf(dev, "Num Tx descriptors avail = %d\n",
3219 sc->num_tx_desc_avail);
3220 device_printf(dev, "Tx Descriptors not avail1 = %ld\n",
3221 sc->no_tx_desc_avail1);
3222 device_printf(dev, "Tx Descriptors not avail2 = %ld\n",
3223 sc->no_tx_desc_avail2);
3224 device_printf(dev, "Std mbuf failed = %ld\n",
3225 sc->mbuf_alloc_failed);
3226 device_printf(dev, "Std mbuf cluster failed = %ld\n",
3227 sc->rx_data[0].mbuf_cluster_failed);
3228 device_printf(dev, "Driver dropped packets = %ld\n",
3230 device_printf(dev, "Driver tx dma failure in encap = %ld\n",
3231 sc->no_tx_dma_setup);
3233 device_printf(dev, "TSO segments %lu\n", sc->tso_segments);
3234 device_printf(dev, "TSO ctx reused %lu\n", sc->tso_ctx_reused);
3238 emx_print_hw_stats(struct emx_softc *sc)
3240 device_t dev = sc->dev;
3242 device_printf(dev, "Excessive collisions = %lld\n",
3243 (long long)sc->stats.ecol);
3244 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3245 device_printf(dev, "Symbol errors = %lld\n",
3246 (long long)sc->stats.symerrs);
3248 device_printf(dev, "Sequence errors = %lld\n",
3249 (long long)sc->stats.sec);
3250 device_printf(dev, "Defer count = %lld\n",
3251 (long long)sc->stats.dc);
3252 device_printf(dev, "Missed Packets = %lld\n",
3253 (long long)sc->stats.mpc);
3254 device_printf(dev, "Receive No Buffers = %lld\n",
3255 (long long)sc->stats.rnbc);
3256 /* RLEC is inaccurate on some hardware, calculate our own. */
3257 device_printf(dev, "Receive Length Errors = %lld\n",
3258 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3259 device_printf(dev, "Receive errors = %lld\n",
3260 (long long)sc->stats.rxerrc);
3261 device_printf(dev, "Crc errors = %lld\n",
3262 (long long)sc->stats.crcerrs);
3263 device_printf(dev, "Alignment errors = %lld\n",
3264 (long long)sc->stats.algnerrc);
3265 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3266 (long long)sc->stats.cexterr);
3267 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3268 device_printf(dev, "watchdog timeouts = %ld\n",
3269 sc->watchdog_events);
3270 device_printf(dev, "XON Rcvd = %lld\n",
3271 (long long)sc->stats.xonrxc);
3272 device_printf(dev, "XON Xmtd = %lld\n",
3273 (long long)sc->stats.xontxc);
3274 device_printf(dev, "XOFF Rcvd = %lld\n",
3275 (long long)sc->stats.xoffrxc);
3276 device_printf(dev, "XOFF Xmtd = %lld\n",
3277 (long long)sc->stats.xofftxc);
3278 device_printf(dev, "Good Packets Rcvd = %lld\n",
3279 (long long)sc->stats.gprc);
3280 device_printf(dev, "Good Packets Xmtd = %lld\n",
3281 (long long)sc->stats.gptc);
3285 emx_print_nvm_info(struct emx_softc *sc)
3287 uint16_t eeprom_data;
3290 /* Its a bit crude, but it gets the job done */
3291 kprintf("\nInterface EEPROM Dump:\n");
3292 kprintf("Offset\n0x0000 ");
3293 for (i = 0, j = 0; i < 32; i++, j++) {
3294 if (j == 8) { /* Make the offset block */
3296 kprintf("\n0x00%x0 ",row);
3298 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3299 kprintf("%04x ", eeprom_data);
3305 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3307 struct emx_softc *sc;
3312 error = sysctl_handle_int(oidp, &result, 0, req);
3313 if (error || !req->newptr)
3316 sc = (struct emx_softc *)arg1;
3317 ifp = &sc->arpcom.ac_if;
3319 ifnet_serialize_all(ifp);
3322 emx_print_debug_info(sc);
3325 * This value will cause a hex dump of the
3326 * first 32 16-bit words of the EEPROM to
3330 emx_print_nvm_info(sc);
3332 ifnet_deserialize_all(ifp);
3338 emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3343 error = sysctl_handle_int(oidp, &result, 0, req);
3344 if (error || !req->newptr)
3348 struct emx_softc *sc = (struct emx_softc *)arg1;
3349 struct ifnet *ifp = &sc->arpcom.ac_if;
3351 ifnet_serialize_all(ifp);
3352 emx_print_hw_stats(sc);
3353 ifnet_deserialize_all(ifp);
3359 emx_add_sysctl(struct emx_softc *sc)
3361 #ifdef EMX_RSS_DEBUG
3366 sysctl_ctx_init(&sc->sysctl_ctx);
3367 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
3368 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
3369 device_get_nameunit(sc->dev),
3371 if (sc->sysctl_tree == NULL) {
3372 device_printf(sc->dev, "can't add sysctl node\n");
3376 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3377 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3378 emx_sysctl_debug_info, "I", "Debug Information");
3380 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3381 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3382 emx_sysctl_stats, "I", "Statistics");
3384 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3385 OID_AUTO, "rxd", CTLFLAG_RD,
3386 &sc->rx_data[0].num_rx_desc, 0, NULL);
3387 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3388 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL);
3390 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3391 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW,
3392 sc, 0, emx_sysctl_int_throttle, "I",
3393 "interrupt throttling rate");
3394 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3395 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW,
3396 sc, 0, emx_sysctl_int_tx_nsegs, "I",
3397 "# segments per TX interrupt");
3399 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3400 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD,
3401 &sc->rx_ring_cnt, 0, "RX ring count");
3403 #ifdef EMX_RSS_DEBUG
3404 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3405 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3406 0, "RSS debug level");
3407 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3408 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i);
3409 SYSCTL_ADD_UINT(&sc->sysctl_ctx,
3410 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
3412 &sc->rx_data[i].rx_pkts, 0, "RXed packets");
3418 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3420 struct emx_softc *sc = (void *)arg1;
3421 struct ifnet *ifp = &sc->arpcom.ac_if;
3422 int error, throttle;
3424 throttle = sc->int_throttle_ceil;
3425 error = sysctl_handle_int(oidp, &throttle, 0, req);
3426 if (error || req->newptr == NULL)
3428 if (throttle < 0 || throttle > 1000000000 / 256)
3433 * Set the interrupt throttling rate in 256ns increments,
3434 * recalculate sysctl value assignment to get exact frequency.
3436 throttle = 1000000000 / 256 / throttle;
3438 /* Upper 16bits of ITR is reserved and should be zero */
3439 if (throttle & 0xffff0000)
3443 ifnet_serialize_all(ifp);
3446 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3448 sc->int_throttle_ceil = 0;
3450 if (ifp->if_flags & IFF_RUNNING)
3451 emx_set_itr(sc, throttle);
3453 ifnet_deserialize_all(ifp);
3456 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3457 sc->int_throttle_ceil);
3463 emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS)
3465 struct emx_softc *sc = (void *)arg1;
3466 struct ifnet *ifp = &sc->arpcom.ac_if;
3469 segs = sc->tx_int_nsegs;
3470 error = sysctl_handle_int(oidp, &segs, 0, req);
3471 if (error || req->newptr == NULL)
3476 ifnet_serialize_all(ifp);
3479 * Don't allow int_tx_nsegs to become:
3480 * o Less the oact_tx_desc
3481 * o Too large that no TX desc will cause TX interrupt to
3482 * be generated (OACTIVE will never recover)
3483 * o Too small that will cause tx_dd[] overflow
3485 if (segs < sc->oact_tx_desc ||
3486 segs >= sc->num_tx_desc - sc->oact_tx_desc ||
3487 segs < sc->num_tx_desc / EMX_TXDD_SAFE) {
3491 sc->tx_int_nsegs = segs;
3494 ifnet_deserialize_all(ifp);
3500 emx_dma_alloc(struct emx_softc *sc)
3505 * Create top level busdma tag
3507 error = bus_dma_tag_create(NULL, 1, 0,
3508 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3510 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3511 0, &sc->parent_dtag);
3513 device_printf(sc->dev, "could not create top level DMA tag\n");
3518 * Allocate transmit descriptors ring and buffers
3520 error = emx_create_tx_ring(sc);
3522 device_printf(sc->dev, "Could not setup transmit structures\n");
3527 * Allocate receive descriptors ring and buffers
3529 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3530 error = emx_create_rx_ring(sc, &sc->rx_data[i]);
3532 device_printf(sc->dev,
3533 "Could not setup receive structures\n");
3541 emx_dma_free(struct emx_softc *sc)
3545 emx_destroy_tx_ring(sc, sc->num_tx_desc);
3547 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3548 emx_destroy_rx_ring(sc, &sc->rx_data[i],
3549 sc->rx_data[i].num_rx_desc);
3552 /* Free top level busdma tag */
3553 if (sc->parent_dtag != NULL)
3554 bus_dma_tag_destroy(sc->parent_dtag);
3558 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3560 struct emx_softc *sc = ifp->if_softc;
3562 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE,
3563 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
3567 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3569 struct emx_softc *sc = ifp->if_softc;
3571 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE,
3572 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
3576 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3578 struct emx_softc *sc = ifp->if_softc;
3580 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE,
3581 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
3585 emx_serialize_skipmain(struct emx_softc *sc)
3587 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3591 emx_deserialize_skipmain(struct emx_softc *sc)
3593 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3599 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3600 boolean_t serialized)
3602 struct emx_softc *sc = ifp->if_softc;
3604 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE,
3605 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz, serialized);
3608 #endif /* INVARIANTS */
3610 #ifdef IFPOLL_ENABLE
3613 emx_qpoll_status(struct ifnet *ifp, int pollhz __unused)
3615 struct emx_softc *sc = ifp->if_softc;
3618 ASSERT_SERIALIZED(&sc->main_serialize);
3620 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3621 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3622 emx_serialize_skipmain(sc);
3624 callout_stop(&sc->timer);
3625 sc->hw.mac.get_link_status = 1;
3626 emx_update_link_status(sc);
3627 callout_reset(&sc->timer, hz, emx_timer, sc);
3629 emx_deserialize_skipmain(sc);
3634 emx_qpoll_tx(struct ifnet *ifp, void *arg __unused, int cycle __unused)
3636 struct emx_softc *sc = ifp->if_softc;
3638 ASSERT_SERIALIZED(&sc->tx_serialize);
3641 if (!ifq_is_empty(&ifp->if_snd))
3646 emx_qpoll_rx(struct ifnet *ifp, void *arg, int cycle)
3648 struct emx_softc *sc = ifp->if_softc;
3649 struct emx_rxdata *rdata = arg;
3651 ASSERT_SERIALIZED(&rdata->rx_serialize);
3653 emx_rxeof(sc, rdata - sc->rx_data, cycle);
3657 emx_qpoll(struct ifnet *ifp, struct ifpoll_info *info)
3659 struct emx_softc *sc = ifp->if_softc;
3661 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3666 info->ifpi_status.status_func = emx_qpoll_status;
3667 info->ifpi_status.serializer = &sc->main_serialize;
3669 info->ifpi_tx[0].poll_func = emx_qpoll_tx;
3670 info->ifpi_tx[0].arg = NULL;
3671 info->ifpi_tx[0].serializer = &sc->tx_serialize;
3673 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3674 info->ifpi_rx[i].poll_func = emx_qpoll_rx;
3675 info->ifpi_rx[i].arg = &sc->rx_data[i];
3676 info->ifpi_rx[i].serializer =
3677 &sc->rx_data[i].rx_serialize;
3680 if (ifp->if_flags & IFF_RUNNING)
3681 emx_disable_intr(sc);
3682 } else if (ifp->if_flags & IFF_RUNNING) {
3683 emx_enable_intr(sc);
3687 #endif /* IFPOLL_ENABLE */
3690 emx_set_itr(struct emx_softc *sc, uint32_t itr)
3692 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr);
3693 if (sc->hw.mac.type == e1000_82574) {
3697 * When using MSIX interrupts we need to
3698 * throttle using the EITR register
3700 for (i = 0; i < 4; ++i)
3701 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr);
3706 * Disable the L0s, 82574L Errata #20
3709 emx_disable_aspm(struct emx_softc *sc)
3711 uint16_t link_cap, link_ctrl, disable;
3712 uint8_t pcie_ptr, reg;
3713 device_t dev = sc->dev;
3715 switch (sc->hw.mac.type) {
3720 * 82573 specification update
3721 * errata #8 disable L0s
3722 * errata #41 disable L1
3724 * 82571/82572 specification update
3725 # errata #13 disable L1
3726 * errata #68 disable L0s
3728 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1;
3733 * 82574 specification update errata #20
3735 * There is no need to disable L1
3737 disable = PCIEM_LNKCTL_ASPM_L0S;
3744 pcie_ptr = pci_get_pciecap_ptr(dev);
3748 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2);
3749 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0)
3753 if_printf(&sc->arpcom.ac_if, "disable ASPM %#02x\n", disable);
3755 reg = pcie_ptr + PCIER_LINKCTRL;
3756 link_ctrl = pci_read_config(dev, reg, 2);
3757 link_ctrl &= ~disable;
3758 pci_write_config(dev, reg, link_ctrl, 2);
3762 emx_tso_pullup(struct emx_softc *sc, struct mbuf **mp)
3764 int iphlen, hoff, thoff, ex = 0;
3768 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
3770 iphlen = m->m_pkthdr.csum_iphlen;
3771 thoff = m->m_pkthdr.csum_thlen;
3772 hoff = m->m_pkthdr.csum_lhlen;
3774 KASSERT(iphlen > 0, ("invalid ip hlen"));
3775 KASSERT(thoff > 0, ("invalid tcp hlen"));
3776 KASSERT(hoff > 0, ("invalid ether hlen"));
3778 if (sc->flags & EMX_FLAG_TSO_PULLEX)
3781 if (m->m_len < hoff + iphlen + thoff + ex) {
3782 m = m_pullup(m, hoff + iphlen + thoff + ex);
3793 emx_tso_setup(struct emx_softc *sc, struct mbuf *mp,
3794 uint32_t *txd_upper, uint32_t *txd_lower)
3796 struct e1000_context_desc *TXD;
3797 int hoff, iphlen, thoff, hlen;
3798 int mss, pktlen, curr_txd;
3801 #ifdef EMX_TSO_DEBUG
3805 iphlen = mp->m_pkthdr.csum_iphlen;
3806 thoff = mp->m_pkthdr.csum_thlen;
3807 hoff = mp->m_pkthdr.csum_lhlen;
3808 mss = mp->m_pkthdr.tso_segsz;
3809 pktlen = mp->m_pkthdr.len;
3811 ip = mtodoff(mp, struct ip *, hoff);
3814 if (sc->csum_flags == CSUM_TSO &&
3815 sc->csum_iphlen == iphlen &&
3816 sc->csum_lhlen == hoff &&
3817 sc->csum_thlen == thoff &&
3818 sc->csum_mss == mss &&
3819 sc->csum_pktlen == pktlen) {
3820 *txd_upper = sc->csum_txd_upper;
3821 *txd_lower = sc->csum_txd_lower;
3822 #ifdef EMX_TSO_DEBUG
3823 sc->tso_ctx_reused++;
3827 hlen = hoff + iphlen + thoff;
3830 * Setup a new TSO context.
3833 curr_txd = sc->next_avail_tx_desc;
3834 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd];
3836 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
3837 E1000_TXD_DTYP_D | /* Data descr type */
3838 E1000_TXD_CMD_TSE; /* Do TSE on this packet */
3840 /* IP and/or TCP header checksum calculation and insertion. */
3841 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8;
3844 * Start offset for header checksum calculation.
3845 * End offset for header checksum calculation.
3846 * Offset of place put the checksum.
3848 TXD->lower_setup.ip_fields.ipcss = hoff;
3849 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1);
3850 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum);
3853 * Start offset for payload checksum calculation.
3854 * End offset for payload checksum calculation.
3855 * Offset of place to put the checksum.
3857 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen;
3858 TXD->upper_setup.tcp_fields.tucse = 0;
3859 TXD->upper_setup.tcp_fields.tucso =
3860 hoff + iphlen + offsetof(struct tcphdr, th_sum);
3863 * Payload size per packet w/o any headers.
3864 * Length of all headers up to payload.
3866 TXD->tcp_seg_setup.fields.mss = htole16(mss);
3867 TXD->tcp_seg_setup.fields.hdr_len = hlen;
3868 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS |
3869 E1000_TXD_CMD_DEXT | /* Extended descr */
3870 E1000_TXD_CMD_TSE | /* TSE context */
3871 E1000_TXD_CMD_IP | /* Do IP csum */
3872 E1000_TXD_CMD_TCP | /* Do TCP checksum */
3873 (pktlen - hlen)); /* Total len */
3875 /* Save the information for this TSO context */
3876 sc->csum_flags = CSUM_TSO;
3877 sc->csum_lhlen = hoff;
3878 sc->csum_iphlen = iphlen;
3879 sc->csum_thlen = thoff;
3881 sc->csum_pktlen = pktlen;
3882 sc->csum_txd_upper = *txd_upper;
3883 sc->csum_txd_lower = *txd_lower;
3885 if (++curr_txd == sc->num_tx_desc)
3888 KKASSERT(sc->num_tx_desc_avail > 0);
3889 sc->num_tx_desc_avail--;
3891 sc->next_avail_tx_desc = curr_txd;