2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 #include "opt_ifpoll.h"
70 #include <sys/param.h>
72 #include <sys/endian.h>
73 #include <sys/interrupt.h>
74 #include <sys/kernel.h>
76 #include <sys/malloc.h>
80 #include <sys/serialize.h>
81 #include <sys/serialize2.h>
82 #include <sys/socket.h>
83 #include <sys/sockio.h>
84 #include <sys/sysctl.h>
85 #include <sys/systm.h>
88 #include <net/ethernet.h>
90 #include <net/if_arp.h>
91 #include <net/if_dl.h>
92 #include <net/if_media.h>
93 #include <net/ifq_var.h>
94 #include <net/toeplitz.h>
95 #include <net/toeplitz2.h>
96 #include <net/vlan/if_vlan_var.h>
97 #include <net/vlan/if_vlan_ether.h>
98 #include <net/if_poll.h>
100 #include <netinet/in_systm.h>
101 #include <netinet/in.h>
102 #include <netinet/ip.h>
103 #include <netinet/tcp.h>
104 #include <netinet/udp.h>
106 #include <bus/pci/pcivar.h>
107 #include <bus/pci/pcireg.h>
109 #include <dev/netif/ig_hal/e1000_api.h>
110 #include <dev/netif/ig_hal/e1000_82571.h>
111 #include <dev/netif/emx/if_emx.h>
114 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
116 if (sc->rss_debug >= lvl) \
117 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
119 #else /* !EMX_RSS_DEBUG */
120 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
121 #endif /* EMX_RSS_DEBUG */
123 #define EMX_TX_SERIALIZE 1
124 #define EMX_RX_SERIALIZE 2
126 #define EMX_NAME "Intel(R) PRO/1000 "
128 #define EMX_DEVICE(id) \
129 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
130 #define EMX_DEVICE_NULL { 0, 0, NULL }
132 static const struct emx_device {
137 EMX_DEVICE(82571EB_COPPER),
138 EMX_DEVICE(82571EB_FIBER),
139 EMX_DEVICE(82571EB_SERDES),
140 EMX_DEVICE(82571EB_SERDES_DUAL),
141 EMX_DEVICE(82571EB_SERDES_QUAD),
142 EMX_DEVICE(82571EB_QUAD_COPPER),
143 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
144 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
145 EMX_DEVICE(82571EB_QUAD_FIBER),
146 EMX_DEVICE(82571PT_QUAD_COPPER),
148 EMX_DEVICE(82572EI_COPPER),
149 EMX_DEVICE(82572EI_FIBER),
150 EMX_DEVICE(82572EI_SERDES),
154 EMX_DEVICE(82573E_IAMT),
157 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
158 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
159 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
160 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
165 /* required last entry */
169 static int emx_probe(device_t);
170 static int emx_attach(device_t);
171 static int emx_detach(device_t);
172 static int emx_shutdown(device_t);
173 static int emx_suspend(device_t);
174 static int emx_resume(device_t);
176 static void emx_init(void *);
177 static void emx_stop(struct emx_softc *);
178 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
179 static void emx_start(struct ifnet *);
181 static void emx_npoll(struct ifnet *, struct ifpoll_info *);
182 static void emx_npoll_status(struct ifnet *);
183 static void emx_npoll_tx(struct ifnet *, void *, int);
184 static void emx_npoll_rx(struct ifnet *, void *, int);
186 static void emx_watchdog(struct ifnet *);
187 static void emx_media_status(struct ifnet *, struct ifmediareq *);
188 static int emx_media_change(struct ifnet *);
189 static void emx_timer(void *);
190 static void emx_serialize(struct ifnet *, enum ifnet_serialize);
191 static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
192 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
194 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
198 static void emx_intr(void *);
199 static void emx_intr_mask(void *);
200 static void emx_intr_body(struct emx_softc *, boolean_t);
201 static void emx_rxeof(struct emx_softc *, int, int);
202 static void emx_txeof(struct emx_softc *);
203 static void emx_tx_collect(struct emx_softc *);
204 static void emx_tx_purge(struct emx_softc *);
205 static void emx_enable_intr(struct emx_softc *);
206 static void emx_disable_intr(struct emx_softc *);
208 static int emx_dma_alloc(struct emx_softc *);
209 static void emx_dma_free(struct emx_softc *);
210 static void emx_init_tx_ring(struct emx_softc *);
211 static int emx_init_rx_ring(struct emx_softc *, struct emx_rxdata *);
212 static void emx_free_rx_ring(struct emx_softc *, struct emx_rxdata *);
213 static int emx_create_tx_ring(struct emx_softc *);
214 static int emx_create_rx_ring(struct emx_softc *, struct emx_rxdata *);
215 static void emx_destroy_tx_ring(struct emx_softc *, int);
216 static void emx_destroy_rx_ring(struct emx_softc *,
217 struct emx_rxdata *, int);
218 static int emx_newbuf(struct emx_softc *, struct emx_rxdata *, int, int);
219 static int emx_encap(struct emx_softc *, struct mbuf **);
220 static int emx_txcsum(struct emx_softc *, struct mbuf *,
221 uint32_t *, uint32_t *);
222 static int emx_tso_pullup(struct emx_softc *, struct mbuf **);
223 static int emx_tso_setup(struct emx_softc *, struct mbuf *,
224 uint32_t *, uint32_t *);
226 static int emx_is_valid_eaddr(const uint8_t *);
227 static int emx_reset(struct emx_softc *);
228 static void emx_setup_ifp(struct emx_softc *);
229 static void emx_init_tx_unit(struct emx_softc *);
230 static void emx_init_rx_unit(struct emx_softc *);
231 static void emx_update_stats(struct emx_softc *);
232 static void emx_set_promisc(struct emx_softc *);
233 static void emx_disable_promisc(struct emx_softc *);
234 static void emx_set_multi(struct emx_softc *);
235 static void emx_update_link_status(struct emx_softc *);
236 static void emx_smartspeed(struct emx_softc *);
237 static void emx_set_itr(struct emx_softc *, uint32_t);
238 static void emx_disable_aspm(struct emx_softc *);
240 static void emx_print_debug_info(struct emx_softc *);
241 static void emx_print_nvm_info(struct emx_softc *);
242 static void emx_print_hw_stats(struct emx_softc *);
244 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
245 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
246 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
247 static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
249 static int emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
250 static int emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
252 static void emx_add_sysctl(struct emx_softc *);
254 static void emx_serialize_skipmain(struct emx_softc *);
255 static void emx_deserialize_skipmain(struct emx_softc *);
257 /* Management and WOL Support */
258 static void emx_get_mgmt(struct emx_softc *);
259 static void emx_rel_mgmt(struct emx_softc *);
260 static void emx_get_hw_control(struct emx_softc *);
261 static void emx_rel_hw_control(struct emx_softc *);
262 static void emx_enable_wol(device_t);
264 static device_method_t emx_methods[] = {
265 /* Device interface */
266 DEVMETHOD(device_probe, emx_probe),
267 DEVMETHOD(device_attach, emx_attach),
268 DEVMETHOD(device_detach, emx_detach),
269 DEVMETHOD(device_shutdown, emx_shutdown),
270 DEVMETHOD(device_suspend, emx_suspend),
271 DEVMETHOD(device_resume, emx_resume),
275 static driver_t emx_driver = {
278 sizeof(struct emx_softc),
281 static devclass_t emx_devclass;
283 DECLARE_DUMMY_MODULE(if_emx);
284 MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
285 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
290 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
291 static int emx_rxd = EMX_DEFAULT_RXD;
292 static int emx_txd = EMX_DEFAULT_TXD;
293 static int emx_smart_pwr_down = 0;
294 static int emx_rxr = 0;
296 /* Controls whether promiscuous also shows bad packets */
297 static int emx_debug_sbp = 0;
299 static int emx_82573_workaround = 1;
300 static int emx_msi_enable = 1;
302 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
303 TUNABLE_INT("hw.emx.rxd", &emx_rxd);
304 TUNABLE_INT("hw.emx.rxr", &emx_rxr);
305 TUNABLE_INT("hw.emx.txd", &emx_txd);
306 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
307 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
308 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
309 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
311 /* Global used in WOL setup with multiport cards */
312 static int emx_global_quad_port_a = 0;
314 /* Set this to one to display debug statistics */
315 static int emx_display_debug_stats = 0;
317 #if !defined(KTR_IF_EMX)
318 #define KTR_IF_EMX KTR_ALL
320 KTR_INFO_MASTER(if_emx);
321 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin");
322 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end");
323 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet");
324 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet");
325 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean");
326 #define logif(name) KTR_LOG(if_emx_ ## name)
329 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
331 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
332 /* DD bit must be cleared */
333 rxd->rxd_staterr = 0;
337 emx_rxcsum(uint32_t staterr, struct mbuf *mp)
339 /* Ignore Checksum bit is set */
340 if (staterr & E1000_RXD_STAT_IXSM)
343 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
345 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
347 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
348 E1000_RXD_STAT_TCPCS) {
349 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
351 CSUM_FRAG_NOT_CHECKED;
352 mp->m_pkthdr.csum_data = htons(0xffff);
356 static __inline struct pktinfo *
357 emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
358 uint32_t mrq, uint32_t hash, uint32_t staterr)
360 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
361 case EMX_RXDMRQ_IPV4_TCP:
362 pi->pi_netisr = NETISR_IP;
364 pi->pi_l3proto = IPPROTO_TCP;
367 case EMX_RXDMRQ_IPV6_TCP:
368 pi->pi_netisr = NETISR_IPV6;
370 pi->pi_l3proto = IPPROTO_TCP;
373 case EMX_RXDMRQ_IPV4:
374 if (staterr & E1000_RXD_STAT_IXSM)
378 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
379 E1000_RXD_STAT_TCPCS) {
380 pi->pi_netisr = NETISR_IP;
382 pi->pi_l3proto = IPPROTO_UDP;
390 m->m_flags |= M_HASH;
391 m->m_pkthdr.hash = toeplitz_hash(hash);
396 emx_probe(device_t dev)
398 const struct emx_device *d;
401 vid = pci_get_vendor(dev);
402 did = pci_get_device(dev);
404 for (d = emx_devices; d->desc != NULL; ++d) {
405 if (vid == d->vid && did == d->did) {
406 device_set_desc(dev, d->desc);
407 device_set_async_attach(dev, TRUE);
415 emx_attach(device_t dev)
417 struct emx_softc *sc = device_get_softc(dev);
418 struct ifnet *ifp = &sc->arpcom.ac_if;
419 int error = 0, i, throttle, msi_enable;
421 uint16_t eeprom_data, device_id, apme_mask;
422 driver_intr_t *intr_func;
424 int offset, offset_def;
428 * Initialize serializers
430 lwkt_serialize_init(&sc->main_serialize);
431 lwkt_serialize_init(&sc->tx_serialize);
432 for (i = 0; i < EMX_NRX_RING; ++i)
433 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
436 * Initialize serializer array
439 sc->serializes[i++] = &sc->main_serialize;
441 KKASSERT(i == EMX_TX_SERIALIZE);
442 sc->serializes[i++] = &sc->tx_serialize;
444 KKASSERT(i == EMX_RX_SERIALIZE);
445 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
446 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
447 KKASSERT(i == EMX_NSERIALIZE);
449 callout_init_mp(&sc->timer);
451 sc->dev = sc->osdep.dev = dev;
454 * Determine hardware and mac type
456 sc->hw.vendor_id = pci_get_vendor(dev);
457 sc->hw.device_id = pci_get_device(dev);
458 sc->hw.revision_id = pci_get_revid(dev);
459 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
460 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
462 if (e1000_set_mac_type(&sc->hw))
466 * Pullup extra 4bytes into the first data segment, see:
467 * 82571/82572 specification update errata #7
470 * 4bytes instead of 2bytes, which are mentioned in the errata,
471 * are pulled; mainly to keep rest of the data properly aligned.
473 if (sc->hw.mac.type == e1000_82571 || sc->hw.mac.type == e1000_82572)
474 sc->flags |= EMX_FLAG_TSO_PULLEX;
476 /* Enable bus mastering */
477 pci_enable_busmaster(dev);
482 sc->memory_rid = EMX_BAR_MEM;
483 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
484 &sc->memory_rid, RF_ACTIVE);
485 if (sc->memory == NULL) {
486 device_printf(dev, "Unable to allocate bus resource: memory\n");
490 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
491 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
493 /* XXX This is quite goofy, it is not actually used */
494 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
497 * Don't enable MSI-X on 82574, see:
498 * 82574 specification update errata #15
500 * Don't enable MSI on 82571/82572, see:
501 * 82571/82572 specification update errata #63
503 msi_enable = emx_msi_enable;
505 (sc->hw.mac.type == e1000_82571 ||
506 sc->hw.mac.type == e1000_82572))
512 sc->intr_type = pci_alloc_1intr(dev, msi_enable,
513 &sc->intr_rid, &intr_flags);
515 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
518 unshared = device_getenv_int(dev, "irq.unshared", 0);
520 sc->flags |= EMX_FLAG_SHARED_INTR;
522 device_printf(dev, "IRQ shared\n");
524 intr_flags &= ~RF_SHAREABLE;
526 device_printf(dev, "IRQ unshared\n");
530 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
532 if (sc->intr_res == NULL) {
533 device_printf(dev, "Unable to allocate bus resource: "
539 /* Save PCI command register for Shared Code */
540 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
541 sc->hw.back = &sc->osdep;
543 /* Do Shared Code initialization */
544 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
545 device_printf(dev, "Setup of Shared code failed\n");
549 e1000_get_bus_info(&sc->hw);
551 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
552 sc->hw.phy.autoneg_wait_to_complete = FALSE;
553 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
556 * Interrupt throttle rate
558 throttle = device_getenv_int(dev, "int_throttle_ceil",
559 emx_int_throttle_ceil);
561 sc->int_throttle_ceil = 0;
564 throttle = EMX_DEFAULT_ITR;
566 /* Recalculate the tunable value to get the exact frequency. */
567 throttle = 1000000000 / 256 / throttle;
569 /* Upper 16bits of ITR is reserved and should be zero */
570 if (throttle & 0xffff0000)
571 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
573 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
576 e1000_init_script_state_82541(&sc->hw, TRUE);
577 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
580 if (sc->hw.phy.media_type == e1000_media_type_copper) {
581 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
582 sc->hw.phy.disable_polarity_correction = FALSE;
583 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
586 /* Set the frame limits assuming standard ethernet sized frames. */
587 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
588 sc->min_frame_size = ETHER_MIN_LEN;
590 /* This controls when hardware reports transmit completion status. */
591 sc->hw.mac.report_tx_early = 1;
593 /* Calculate # of RX rings */
594 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr);
595 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, EMX_NRX_RING);
597 /* Allocate RX/TX rings' busdma(9) stuffs */
598 error = emx_dma_alloc(sc);
602 /* Allocate multicast array memory. */
603 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
606 /* Indicate SOL/IDER usage */
607 if (e1000_check_reset_block(&sc->hw)) {
609 "PHY reset is blocked due to SOL/IDER session.\n");
613 * Start from a known state, this is important in reading the
614 * nvm and mac from that.
616 e1000_reset_hw(&sc->hw);
618 /* Make sure we have a good EEPROM before we read from it */
619 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
621 * Some PCI-E parts fail the first check due to
622 * the link being in sleep state, call it again,
623 * if it fails a second time its a real issue.
625 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
627 "The EEPROM Checksum Is Not Valid\n");
633 /* Copy the permanent MAC address out of the EEPROM */
634 if (e1000_read_mac_addr(&sc->hw) < 0) {
635 device_printf(dev, "EEPROM read error while reading MAC"
640 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
641 device_printf(dev, "Invalid MAC address\n");
646 /* Determine if we have to control management hardware */
647 if (e1000_enable_mng_pass_thru(&sc->hw))
648 sc->flags |= EMX_FLAG_HAS_MGMT;
653 apme_mask = EMX_EEPROM_APME;
655 switch (sc->hw.mac.type) {
657 sc->flags |= EMX_FLAG_HAS_AMT;
662 case e1000_80003es2lan:
663 if (sc->hw.bus.func == 1) {
664 e1000_read_nvm(&sc->hw,
665 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
667 e1000_read_nvm(&sc->hw,
668 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
673 e1000_read_nvm(&sc->hw,
674 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
677 if (eeprom_data & apme_mask)
678 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
681 * We have the eeprom settings, now apply the special cases
682 * where the eeprom may be wrong or the board won't support
683 * wake on lan on a particular port
685 device_id = pci_get_device(dev);
687 case E1000_DEV_ID_82571EB_FIBER:
689 * Wake events only supported on port A for dual fiber
690 * regardless of eeprom setting
692 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
697 case E1000_DEV_ID_82571EB_QUAD_COPPER:
698 case E1000_DEV_ID_82571EB_QUAD_FIBER:
699 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
700 /* if quad port sc, disable WoL on all but port A */
701 if (emx_global_quad_port_a != 0)
703 /* Reset for multiple quad port adapters */
704 if (++emx_global_quad_port_a == 4)
705 emx_global_quad_port_a = 0;
709 /* XXX disable wol */
714 * NPOLLING RX CPU offset
716 if (sc->rx_ring_cnt == ncpus2) {
719 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
720 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
721 if (offset >= ncpus2 ||
722 offset % sc->rx_ring_cnt != 0) {
723 device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
728 sc->rx_npoll_off = offset;
731 * NPOLLING TX CPU offset
733 offset_def = sc->rx_npoll_off;
734 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
735 if (offset >= ncpus2) {
736 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
740 sc->tx_npoll_off = offset;
743 /* Setup OS specific network interface */
746 /* Add sysctl tree, must after em_setup_ifp() */
749 /* Reset the hardware */
750 error = emx_reset(sc);
752 device_printf(dev, "Unable to reset the hardware\n");
756 /* Initialize statistics */
757 emx_update_stats(sc);
759 sc->hw.mac.get_link_status = 1;
760 emx_update_link_status(sc);
762 sc->spare_tx_desc = EMX_TX_SPARE;
765 * Keep following relationship between spare_tx_desc, oact_tx_desc
767 * (spare_tx_desc + EMX_TX_RESERVED) <=
768 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs
770 sc->oact_tx_desc = sc->num_tx_desc / 8;
771 if (sc->oact_tx_desc > EMX_TX_OACTIVE_MAX)
772 sc->oact_tx_desc = EMX_TX_OACTIVE_MAX;
773 if (sc->oact_tx_desc < sc->spare_tx_desc + EMX_TX_RESERVED)
774 sc->oact_tx_desc = sc->spare_tx_desc + EMX_TX_RESERVED;
776 sc->tx_int_nsegs = sc->num_tx_desc / 16;
777 if (sc->tx_int_nsegs < sc->oact_tx_desc)
778 sc->tx_int_nsegs = sc->oact_tx_desc;
780 /* Non-AMT based hardware can now take control from firmware */
781 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
783 emx_get_hw_control(sc);
786 * Missing Interrupt Following ICR read:
788 * 82571/82572 specification update errata #76
789 * 82573 specification update errata #31
790 * 82574 specification update errata #12
792 intr_func = emx_intr;
793 if ((sc->flags & EMX_FLAG_SHARED_INTR) &&
794 (sc->hw.mac.type == e1000_82571 ||
795 sc->hw.mac.type == e1000_82572 ||
796 sc->hw.mac.type == e1000_82573 ||
797 sc->hw.mac.type == e1000_82574))
798 intr_func = emx_intr_mask;
800 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc,
801 &sc->intr_tag, &sc->main_serialize);
803 device_printf(dev, "Failed to register interrupt handler");
804 ether_ifdetach(&sc->arpcom.ac_if);
808 ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
809 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
817 emx_detach(device_t dev)
819 struct emx_softc *sc = device_get_softc(dev);
821 if (device_is_attached(dev)) {
822 struct ifnet *ifp = &sc->arpcom.ac_if;
824 ifnet_serialize_all(ifp);
828 e1000_phy_hw_reset(&sc->hw);
831 emx_rel_hw_control(sc);
834 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
835 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
839 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
841 ifnet_deserialize_all(ifp);
844 } else if (sc->memory != NULL) {
845 emx_rel_hw_control(sc);
847 bus_generic_detach(dev);
849 if (sc->intr_res != NULL) {
850 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
854 if (sc->intr_type == PCI_INTR_TYPE_MSI)
855 pci_release_msi(dev);
857 if (sc->memory != NULL) {
858 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
864 /* Free sysctl tree */
865 if (sc->sysctl_tree != NULL)
866 sysctl_ctx_free(&sc->sysctl_ctx);
869 kfree(sc->mta, M_DEVBUF);
875 emx_shutdown(device_t dev)
877 return emx_suspend(dev);
881 emx_suspend(device_t dev)
883 struct emx_softc *sc = device_get_softc(dev);
884 struct ifnet *ifp = &sc->arpcom.ac_if;
886 ifnet_serialize_all(ifp);
891 emx_rel_hw_control(sc);
894 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
895 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
899 ifnet_deserialize_all(ifp);
901 return bus_generic_suspend(dev);
905 emx_resume(device_t dev)
907 struct emx_softc *sc = device_get_softc(dev);
908 struct ifnet *ifp = &sc->arpcom.ac_if;
910 ifnet_serialize_all(ifp);
916 ifnet_deserialize_all(ifp);
918 return bus_generic_resume(dev);
922 emx_start(struct ifnet *ifp)
924 struct emx_softc *sc = ifp->if_softc;
927 ASSERT_SERIALIZED(&sc->tx_serialize);
929 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
932 if (!sc->link_active) {
933 ifq_purge(&ifp->if_snd);
937 while (!ifq_is_empty(&ifp->if_snd)) {
938 /* Now do we at least have a minimal? */
939 if (EMX_IS_OACTIVE(sc)) {
941 if (EMX_IS_OACTIVE(sc)) {
942 ifp->if_flags |= IFF_OACTIVE;
948 m_head = ifq_dequeue(&ifp->if_snd, NULL);
952 if (emx_encap(sc, &m_head)) {
958 /* Send a copy of the frame to the BPF listener */
959 ETHER_BPF_MTAP(ifp, m_head);
961 /* Set timeout in case hardware has problems transmitting. */
962 ifp->if_timer = EMX_TX_TIMEOUT;
967 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
969 struct emx_softc *sc = ifp->if_softc;
970 struct ifreq *ifr = (struct ifreq *)data;
971 uint16_t eeprom_data = 0;
972 int max_frame_size, mask, reinit;
975 ASSERT_IFNET_SERIALIZED_ALL(ifp);
979 switch (sc->hw.mac.type) {
982 * 82573 only supports jumbo frames
983 * if ASPM is disabled.
985 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
987 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
988 max_frame_size = ETHER_MAX_LEN;
993 /* Limit Jumbo Frame size */
997 case e1000_80003es2lan:
998 max_frame_size = 9234;
1002 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1005 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
1011 ifp->if_mtu = ifr->ifr_mtu;
1012 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
1015 if (ifp->if_flags & IFF_RUNNING)
1020 if (ifp->if_flags & IFF_UP) {
1021 if ((ifp->if_flags & IFF_RUNNING)) {
1022 if ((ifp->if_flags ^ sc->if_flags) &
1023 (IFF_PROMISC | IFF_ALLMULTI)) {
1024 emx_disable_promisc(sc);
1025 emx_set_promisc(sc);
1030 } else if (ifp->if_flags & IFF_RUNNING) {
1033 sc->if_flags = ifp->if_flags;
1038 if (ifp->if_flags & IFF_RUNNING) {
1039 emx_disable_intr(sc);
1041 #ifdef IFPOLL_ENABLE
1042 if (!(ifp->if_flags & IFF_NPOLLING))
1044 emx_enable_intr(sc);
1049 /* Check SOL/IDER usage */
1050 if (e1000_check_reset_block(&sc->hw)) {
1051 device_printf(sc->dev, "Media change is"
1052 " blocked due to SOL/IDER session.\n");
1058 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
1063 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1064 if (mask & IFCAP_RXCSUM) {
1065 ifp->if_capenable ^= IFCAP_RXCSUM;
1068 if (mask & IFCAP_VLAN_HWTAGGING) {
1069 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1072 if (mask & IFCAP_TXCSUM) {
1073 ifp->if_capenable ^= IFCAP_TXCSUM;
1074 if (ifp->if_capenable & IFCAP_TXCSUM)
1075 ifp->if_hwassist |= EMX_CSUM_FEATURES;
1077 ifp->if_hwassist &= ~EMX_CSUM_FEATURES;
1079 if (mask & IFCAP_TSO) {
1080 ifp->if_capenable ^= IFCAP_TSO;
1081 if (ifp->if_capenable & IFCAP_TSO)
1082 ifp->if_hwassist |= CSUM_TSO;
1084 ifp->if_hwassist &= ~CSUM_TSO;
1086 if (mask & IFCAP_RSS)
1087 ifp->if_capenable ^= IFCAP_RSS;
1088 if (reinit && (ifp->if_flags & IFF_RUNNING))
1093 error = ether_ioctl(ifp, command, data);
1100 emx_watchdog(struct ifnet *ifp)
1102 struct emx_softc *sc = ifp->if_softc;
1104 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1107 * The timer is set to 5 every time start queues a packet.
1108 * Then txeof keeps resetting it as long as it cleans at
1109 * least one descriptor.
1110 * Finally, anytime all descriptors are clean the timer is
1114 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) ==
1115 E1000_READ_REG(&sc->hw, E1000_TDH(0))) {
1117 * If we reach here, all TX jobs are completed and
1118 * the TX engine should have been idled for some time.
1119 * We don't need to call if_devstart() here.
1121 ifp->if_flags &= ~IFF_OACTIVE;
1127 * If we are in this routine because of pause frames, then
1128 * don't reset the hardware.
1130 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1131 ifp->if_timer = EMX_TX_TIMEOUT;
1135 if (e1000_check_for_link(&sc->hw) == 0)
1136 if_printf(ifp, "watchdog timeout -- resetting\n");
1142 if (!ifq_is_empty(&ifp->if_snd))
1149 struct emx_softc *sc = xsc;
1150 struct ifnet *ifp = &sc->arpcom.ac_if;
1151 device_t dev = sc->dev;
1155 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1160 * Packet Buffer Allocation (PBA)
1161 * Writing PBA sets the receive portion of the buffer
1162 * the remainder is used for the transmit buffer.
1164 switch (sc->hw.mac.type) {
1165 /* Total Packet Buffer on these is 48K */
1168 case e1000_80003es2lan:
1169 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1172 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1173 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1177 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1181 /* Devices before 82547 had a Packet Buffer of 64K. */
1182 if (sc->max_frame_size > 8192)
1183 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1185 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1187 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1189 /* Get the latest mac address, User can use a LAA */
1190 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1192 /* Put the address into the Receive Address Array */
1193 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1196 * With the 82571 sc, RAR[0] may be overwritten
1197 * when the other port is reset, we make a duplicate
1198 * in RAR[14] for that eventuality, this assures
1199 * the interface continues to function.
1201 if (sc->hw.mac.type == e1000_82571) {
1202 e1000_set_laa_state_82571(&sc->hw, TRUE);
1203 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1204 E1000_RAR_ENTRIES - 1);
1207 /* Initialize the hardware */
1208 if (emx_reset(sc)) {
1209 device_printf(dev, "Unable to reset the hardware\n");
1210 /* XXX emx_stop()? */
1213 emx_update_link_status(sc);
1215 /* Setup VLAN support, basic and offload if available */
1216 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1218 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1221 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1222 ctrl |= E1000_CTRL_VME;
1223 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1226 /* Configure for OS presence */
1229 /* Prepare transmit descriptors and buffers */
1230 emx_init_tx_ring(sc);
1231 emx_init_tx_unit(sc);
1233 /* Setup Multicast table */
1236 /* Prepare receive descriptors and buffers */
1237 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1238 if (emx_init_rx_ring(sc, &sc->rx_data[i])) {
1240 "Could not setup receive structures\n");
1245 emx_init_rx_unit(sc);
1247 /* Don't lose promiscuous settings */
1248 emx_set_promisc(sc);
1250 ifp->if_flags |= IFF_RUNNING;
1251 ifp->if_flags &= ~IFF_OACTIVE;
1253 callout_reset(&sc->timer, hz, emx_timer, sc);
1254 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1256 /* MSI/X configuration for 82574 */
1257 if (sc->hw.mac.type == e1000_82574) {
1260 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1261 tmp |= E1000_CTRL_EXT_PBA_CLR;
1262 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1265 * Set the IVAR - interrupt vector routing.
1266 * Each nibble represents a vector, high bit
1267 * is enable, other 3 bits are the MSIX table
1268 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1269 * Link (other) to 2, hence the magic number.
1271 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1274 #ifdef IFPOLL_ENABLE
1276 * Only enable interrupts if we are not polling, make sure
1277 * they are off otherwise.
1279 if (ifp->if_flags & IFF_NPOLLING)
1280 emx_disable_intr(sc);
1282 #endif /* IFPOLL_ENABLE */
1283 emx_enable_intr(sc);
1285 /* AMT based hardware can now take control from firmware */
1286 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
1287 (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT))
1288 emx_get_hw_control(sc);
1290 /* Don't reset the phy next time init gets called */
1291 sc->hw.phy.reset_disable = TRUE;
1297 emx_intr_body(xsc, TRUE);
1301 emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted)
1303 struct ifnet *ifp = &sc->arpcom.ac_if;
1307 ASSERT_SERIALIZED(&sc->main_serialize);
1309 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1311 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
1317 * XXX: some laptops trigger several spurious interrupts
1318 * on emx(4) when in the resume cycle. The ICR register
1319 * reports all-ones value in this case. Processing such
1320 * interrupts would lead to a freeze. I don't know why.
1322 if (reg_icr == 0xffffffff) {
1327 if (ifp->if_flags & IFF_RUNNING) {
1329 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1332 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1333 lwkt_serialize_enter(
1334 &sc->rx_data[i].rx_serialize);
1335 emx_rxeof(sc, i, -1);
1336 lwkt_serialize_exit(
1337 &sc->rx_data[i].rx_serialize);
1340 if (reg_icr & E1000_ICR_TXDW) {
1341 lwkt_serialize_enter(&sc->tx_serialize);
1343 if (!ifq_is_empty(&ifp->if_snd))
1345 lwkt_serialize_exit(&sc->tx_serialize);
1349 /* Link status change */
1350 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1351 emx_serialize_skipmain(sc);
1353 callout_stop(&sc->timer);
1354 sc->hw.mac.get_link_status = 1;
1355 emx_update_link_status(sc);
1357 /* Deal with TX cruft when link lost */
1360 callout_reset(&sc->timer, hz, emx_timer, sc);
1362 emx_deserialize_skipmain(sc);
1365 if (reg_icr & E1000_ICR_RXO)
1372 emx_intr_mask(void *xsc)
1374 struct emx_softc *sc = xsc;
1376 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
1379 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1380 * so don't check it.
1382 emx_intr_body(sc, FALSE);
1383 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
1387 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1389 struct emx_softc *sc = ifp->if_softc;
1391 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1393 emx_update_link_status(sc);
1395 ifmr->ifm_status = IFM_AVALID;
1396 ifmr->ifm_active = IFM_ETHER;
1398 if (!sc->link_active)
1401 ifmr->ifm_status |= IFM_ACTIVE;
1403 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1404 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1405 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1407 switch (sc->link_speed) {
1409 ifmr->ifm_active |= IFM_10_T;
1412 ifmr->ifm_active |= IFM_100_TX;
1416 ifmr->ifm_active |= IFM_1000_T;
1419 if (sc->link_duplex == FULL_DUPLEX)
1420 ifmr->ifm_active |= IFM_FDX;
1422 ifmr->ifm_active |= IFM_HDX;
1427 emx_media_change(struct ifnet *ifp)
1429 struct emx_softc *sc = ifp->if_softc;
1430 struct ifmedia *ifm = &sc->media;
1432 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1434 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1437 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1439 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1440 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1446 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1447 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1451 sc->hw.mac.autoneg = FALSE;
1452 sc->hw.phy.autoneg_advertised = 0;
1453 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1454 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1456 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1460 sc->hw.mac.autoneg = FALSE;
1461 sc->hw.phy.autoneg_advertised = 0;
1462 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1463 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1465 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1469 if_printf(ifp, "Unsupported media type\n");
1474 * As the speed/duplex settings my have changed we need to
1477 sc->hw.phy.reset_disable = FALSE;
1485 emx_encap(struct emx_softc *sc, struct mbuf **m_headp)
1487 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1489 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
1490 struct e1000_tx_desc *ctxd = NULL;
1491 struct mbuf *m_head = *m_headp;
1492 uint32_t txd_upper, txd_lower, cmd = 0;
1493 int maxsegs, nsegs, i, j, first, last = 0, error;
1495 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1496 error = emx_tso_pullup(sc, m_headp);
1502 txd_upper = txd_lower = 0;
1505 * Capture the first descriptor index, this descriptor
1506 * will have the index of the EOP which is the only one
1507 * that now gets a DONE bit writeback.
1509 first = sc->next_avail_tx_desc;
1510 tx_buffer = &sc->tx_buf[first];
1511 tx_buffer_mapped = tx_buffer;
1512 map = tx_buffer->map;
1514 maxsegs = sc->num_tx_desc_avail - EMX_TX_RESERVED;
1515 KASSERT(maxsegs >= sc->spare_tx_desc, ("not enough spare TX desc"));
1516 if (maxsegs > EMX_MAX_SCATTER)
1517 maxsegs = EMX_MAX_SCATTER;
1519 error = bus_dmamap_load_mbuf_defrag(sc->txtag, map, m_headp,
1520 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1526 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE);
1529 sc->tx_nsegs += nsegs;
1531 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1532 /* TSO will consume one TX desc */
1533 sc->tx_nsegs += emx_tso_setup(sc, m_head,
1534 &txd_upper, &txd_lower);
1535 } else if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1536 /* TX csum offloading will consume one TX desc */
1537 sc->tx_nsegs += emx_txcsum(sc, m_head, &txd_upper, &txd_lower);
1539 i = sc->next_avail_tx_desc;
1541 /* Set up our transmit descriptors */
1542 for (j = 0; j < nsegs; j++) {
1543 tx_buffer = &sc->tx_buf[i];
1544 ctxd = &sc->tx_desc_base[i];
1546 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1547 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1548 txd_lower | segs[j].ds_len);
1549 ctxd->upper.data = htole32(txd_upper);
1552 if (++i == sc->num_tx_desc)
1556 sc->next_avail_tx_desc = i;
1558 KKASSERT(sc->num_tx_desc_avail > nsegs);
1559 sc->num_tx_desc_avail -= nsegs;
1561 /* Handle VLAN tag */
1562 if (m_head->m_flags & M_VLANTAG) {
1563 /* Set the vlan id. */
1564 ctxd->upper.fields.special =
1565 htole16(m_head->m_pkthdr.ether_vlantag);
1567 /* Tell hardware to add tag */
1568 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1571 tx_buffer->m_head = m_head;
1572 tx_buffer_mapped->map = tx_buffer->map;
1573 tx_buffer->map = map;
1575 if (sc->tx_nsegs >= sc->tx_int_nsegs) {
1579 * Report Status (RS) is turned on
1580 * every tx_int_nsegs descriptors.
1582 cmd = E1000_TXD_CMD_RS;
1585 * Keep track of the descriptor, which will
1586 * be written back by hardware.
1588 sc->tx_dd[sc->tx_dd_tail] = last;
1589 EMX_INC_TXDD_IDX(sc->tx_dd_tail);
1590 KKASSERT(sc->tx_dd_tail != sc->tx_dd_head);
1594 * Last Descriptor of Packet needs End Of Packet (EOP)
1596 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1599 * Advance the Transmit Descriptor Tail (TDT), this tells
1600 * the E1000 that this frame is available to transmit.
1602 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), i);
1608 emx_set_promisc(struct emx_softc *sc)
1610 struct ifnet *ifp = &sc->arpcom.ac_if;
1613 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1615 if (ifp->if_flags & IFF_PROMISC) {
1616 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1617 /* Turn this on if you want to see bad packets */
1619 reg_rctl |= E1000_RCTL_SBP;
1620 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1621 } else if (ifp->if_flags & IFF_ALLMULTI) {
1622 reg_rctl |= E1000_RCTL_MPE;
1623 reg_rctl &= ~E1000_RCTL_UPE;
1624 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1629 emx_disable_promisc(struct emx_softc *sc)
1633 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1635 reg_rctl &= ~E1000_RCTL_UPE;
1636 reg_rctl &= ~E1000_RCTL_MPE;
1637 reg_rctl &= ~E1000_RCTL_SBP;
1638 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1642 emx_set_multi(struct emx_softc *sc)
1644 struct ifnet *ifp = &sc->arpcom.ac_if;
1645 struct ifmultiaddr *ifma;
1646 uint32_t reg_rctl = 0;
1651 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1653 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1654 if (ifma->ifma_addr->sa_family != AF_LINK)
1657 if (mcnt == EMX_MCAST_ADDR_MAX)
1660 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1661 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1665 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1666 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1667 reg_rctl |= E1000_RCTL_MPE;
1668 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1670 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1675 * This routine checks for link status and updates statistics.
1678 emx_timer(void *xsc)
1680 struct emx_softc *sc = xsc;
1681 struct ifnet *ifp = &sc->arpcom.ac_if;
1683 lwkt_serialize_enter(&sc->main_serialize);
1685 emx_update_link_status(sc);
1686 emx_update_stats(sc);
1688 /* Reset LAA into RAR[0] on 82571 */
1689 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1690 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1692 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1693 emx_print_hw_stats(sc);
1697 callout_reset(&sc->timer, hz, emx_timer, sc);
1699 lwkt_serialize_exit(&sc->main_serialize);
1703 emx_update_link_status(struct emx_softc *sc)
1705 struct e1000_hw *hw = &sc->hw;
1706 struct ifnet *ifp = &sc->arpcom.ac_if;
1707 device_t dev = sc->dev;
1708 uint32_t link_check = 0;
1710 /* Get the cached link value or read phy for real */
1711 switch (hw->phy.media_type) {
1712 case e1000_media_type_copper:
1713 if (hw->mac.get_link_status) {
1714 /* Do the work to read phy */
1715 e1000_check_for_link(hw);
1716 link_check = !hw->mac.get_link_status;
1717 if (link_check) /* ESB2 fix */
1718 e1000_cfg_on_link_up(hw);
1724 case e1000_media_type_fiber:
1725 e1000_check_for_link(hw);
1726 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1729 case e1000_media_type_internal_serdes:
1730 e1000_check_for_link(hw);
1731 link_check = sc->hw.mac.serdes_has_link;
1734 case e1000_media_type_unknown:
1739 /* Now check for a transition */
1740 if (link_check && sc->link_active == 0) {
1741 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1745 * Check if we should enable/disable SPEED_MODE bit on
1748 if (sc->link_speed != SPEED_1000 &&
1749 (hw->mac.type == e1000_82571 ||
1750 hw->mac.type == e1000_82572)) {
1753 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1754 tarc0 &= ~EMX_TARC_SPEED_MODE;
1755 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1758 device_printf(dev, "Link is up %d Mbps %s\n",
1760 ((sc->link_duplex == FULL_DUPLEX) ?
1761 "Full Duplex" : "Half Duplex"));
1763 sc->link_active = 1;
1765 ifp->if_baudrate = sc->link_speed * 1000000;
1766 ifp->if_link_state = LINK_STATE_UP;
1767 if_link_state_change(ifp);
1768 } else if (!link_check && sc->link_active == 1) {
1769 ifp->if_baudrate = sc->link_speed = 0;
1770 sc->link_duplex = 0;
1772 device_printf(dev, "Link is Down\n");
1773 sc->link_active = 0;
1775 /* Link down, disable watchdog */
1778 ifp->if_link_state = LINK_STATE_DOWN;
1779 if_link_state_change(ifp);
1784 emx_stop(struct emx_softc *sc)
1786 struct ifnet *ifp = &sc->arpcom.ac_if;
1789 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1791 emx_disable_intr(sc);
1793 callout_stop(&sc->timer);
1795 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1799 * Disable multiple receive queues.
1802 * We should disable multiple receive queues before
1803 * resetting the hardware.
1805 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1807 e1000_reset_hw(&sc->hw);
1808 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1810 for (i = 0; i < sc->num_tx_desc; i++) {
1811 struct emx_txbuf *tx_buffer = &sc->tx_buf[i];
1813 if (tx_buffer->m_head != NULL) {
1814 bus_dmamap_unload(sc->txtag, tx_buffer->map);
1815 m_freem(tx_buffer->m_head);
1816 tx_buffer->m_head = NULL;
1820 for (i = 0; i < sc->rx_ring_cnt; ++i)
1821 emx_free_rx_ring(sc, &sc->rx_data[i]);
1825 sc->csum_iphlen = 0;
1828 sc->csum_pktlen = 0;
1836 emx_reset(struct emx_softc *sc)
1838 device_t dev = sc->dev;
1839 uint16_t rx_buffer_size;
1841 /* Set up smart power down as default off on newer adapters. */
1842 if (!emx_smart_pwr_down &&
1843 (sc->hw.mac.type == e1000_82571 ||
1844 sc->hw.mac.type == e1000_82572)) {
1845 uint16_t phy_tmp = 0;
1847 /* Speed up time to link by disabling smart power down. */
1848 e1000_read_phy_reg(&sc->hw,
1849 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1850 phy_tmp &= ~IGP02E1000_PM_SPD;
1851 e1000_write_phy_reg(&sc->hw,
1852 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1856 * These parameters control the automatic generation (Tx) and
1857 * response (Rx) to Ethernet PAUSE frames.
1858 * - High water mark should allow for at least two frames to be
1859 * received after sending an XOFF.
1860 * - Low water mark works best when it is very near the high water mark.
1861 * This allows the receiver to restart by sending XON when it has
1862 * drained a bit. Here we use an arbitary value of 1500 which will
1863 * restart after one full frame is pulled from the buffer. There
1864 * could be several smaller frames in the buffer and if so they will
1865 * not trigger the XON until their total number reduces the buffer
1867 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1869 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1871 sc->hw.fc.high_water = rx_buffer_size -
1872 roundup2(sc->max_frame_size, 1024);
1873 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1875 if (sc->hw.mac.type == e1000_80003es2lan)
1876 sc->hw.fc.pause_time = 0xFFFF;
1878 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1879 sc->hw.fc.send_xon = TRUE;
1880 sc->hw.fc.requested_mode = e1000_fc_full;
1882 /* Issue a global reset */
1883 e1000_reset_hw(&sc->hw);
1884 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1885 emx_disable_aspm(sc);
1887 if (e1000_init_hw(&sc->hw) < 0) {
1888 device_printf(dev, "Hardware Initialization Failed\n");
1892 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1893 e1000_get_phy_info(&sc->hw);
1894 e1000_check_for_link(&sc->hw);
1900 emx_setup_ifp(struct emx_softc *sc)
1902 struct ifnet *ifp = &sc->arpcom.ac_if;
1904 if_initname(ifp, device_get_name(sc->dev),
1905 device_get_unit(sc->dev));
1907 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1908 ifp->if_init = emx_init;
1909 ifp->if_ioctl = emx_ioctl;
1910 ifp->if_start = emx_start;
1911 #ifdef IFPOLL_ENABLE
1912 ifp->if_npoll = emx_npoll;
1914 ifp->if_watchdog = emx_watchdog;
1915 ifp->if_serialize = emx_serialize;
1916 ifp->if_deserialize = emx_deserialize;
1917 ifp->if_tryserialize = emx_tryserialize;
1919 ifp->if_serialize_assert = emx_serialize_assert;
1921 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);
1922 ifq_set_ready(&ifp->if_snd);
1924 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1926 ifp->if_capabilities = IFCAP_HWCSUM |
1927 IFCAP_VLAN_HWTAGGING |
1930 if (sc->rx_ring_cnt > 1)
1931 ifp->if_capabilities |= IFCAP_RSS;
1932 ifp->if_capenable = ifp->if_capabilities;
1933 ifp->if_hwassist = EMX_CSUM_FEATURES | CSUM_TSO;
1936 * Tell the upper layer(s) we support long frames.
1938 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1941 * Specify the media types supported by this sc and register
1942 * callbacks to update media and link information
1944 ifmedia_init(&sc->media, IFM_IMASK,
1945 emx_media_change, emx_media_status);
1946 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1947 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1948 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1950 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1952 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1953 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1955 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1956 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1958 if (sc->hw.phy.type != e1000_phy_ife) {
1959 ifmedia_add(&sc->media,
1960 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1961 ifmedia_add(&sc->media,
1962 IFM_ETHER | IFM_1000_T, 0, NULL);
1965 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1966 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1970 * Workaround for SmartSpeed on 82541 and 82547 controllers
1973 emx_smartspeed(struct emx_softc *sc)
1977 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
1978 sc->hw.mac.autoneg == 0 ||
1979 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
1982 if (sc->smartspeed == 0) {
1984 * If Master/Slave config fault is asserted twice,
1985 * we assume back-to-back
1987 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1988 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
1990 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1991 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
1992 e1000_read_phy_reg(&sc->hw,
1993 PHY_1000T_CTRL, &phy_tmp);
1994 if (phy_tmp & CR_1000T_MS_ENABLE) {
1995 phy_tmp &= ~CR_1000T_MS_ENABLE;
1996 e1000_write_phy_reg(&sc->hw,
1997 PHY_1000T_CTRL, phy_tmp);
1999 if (sc->hw.mac.autoneg &&
2000 !e1000_phy_setup_autoneg(&sc->hw) &&
2001 !e1000_read_phy_reg(&sc->hw,
2002 PHY_CONTROL, &phy_tmp)) {
2003 phy_tmp |= MII_CR_AUTO_NEG_EN |
2004 MII_CR_RESTART_AUTO_NEG;
2005 e1000_write_phy_reg(&sc->hw,
2006 PHY_CONTROL, phy_tmp);
2011 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
2012 /* If still no link, perhaps using 2/3 pair cable */
2013 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
2014 phy_tmp |= CR_1000T_MS_ENABLE;
2015 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
2016 if (sc->hw.mac.autoneg &&
2017 !e1000_phy_setup_autoneg(&sc->hw) &&
2018 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
2019 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2020 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
2024 /* Restart process after EMX_SMARTSPEED_MAX iterations */
2025 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
2030 emx_create_tx_ring(struct emx_softc *sc)
2032 device_t dev = sc->dev;
2033 struct emx_txbuf *tx_buffer;
2034 int error, i, tsize, ntxd;
2037 * Validate number of transmit descriptors. It must not exceed
2038 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2040 ntxd = device_getenv_int(dev, "txd", emx_txd);
2041 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
2042 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) {
2043 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
2044 EMX_DEFAULT_TXD, ntxd);
2045 sc->num_tx_desc = EMX_DEFAULT_TXD;
2047 sc->num_tx_desc = ntxd;
2051 * Allocate Transmit Descriptor ring
2053 tsize = roundup2(sc->num_tx_desc * sizeof(struct e1000_tx_desc),
2055 sc->tx_desc_base = bus_dmamem_coherent_any(sc->parent_dtag,
2056 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
2057 &sc->tx_desc_dtag, &sc->tx_desc_dmap,
2058 &sc->tx_desc_paddr);
2059 if (sc->tx_desc_base == NULL) {
2060 device_printf(dev, "Unable to allocate tx_desc memory\n");
2064 sc->tx_buf = kmalloc(sizeof(struct emx_txbuf) * sc->num_tx_desc,
2065 M_DEVBUF, M_WAITOK | M_ZERO);
2068 * Create DMA tags for tx buffers
2070 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2071 1, 0, /* alignment, bounds */
2072 BUS_SPACE_MAXADDR, /* lowaddr */
2073 BUS_SPACE_MAXADDR, /* highaddr */
2074 NULL, NULL, /* filter, filterarg */
2075 EMX_TSO_SIZE, /* maxsize */
2076 EMX_MAX_SCATTER, /* nsegments */
2077 EMX_MAX_SEGSIZE, /* maxsegsize */
2078 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2079 BUS_DMA_ONEBPAGE, /* flags */
2082 device_printf(dev, "Unable to allocate TX DMA tag\n");
2083 kfree(sc->tx_buf, M_DEVBUF);
2089 * Create DMA maps for tx buffers
2091 for (i = 0; i < sc->num_tx_desc; i++) {
2092 tx_buffer = &sc->tx_buf[i];
2094 error = bus_dmamap_create(sc->txtag,
2095 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2098 device_printf(dev, "Unable to create TX DMA map\n");
2099 emx_destroy_tx_ring(sc, i);
2107 emx_init_tx_ring(struct emx_softc *sc)
2109 /* Clear the old ring contents */
2110 bzero(sc->tx_desc_base,
2111 sizeof(struct e1000_tx_desc) * sc->num_tx_desc);
2114 sc->next_avail_tx_desc = 0;
2115 sc->next_tx_to_clean = 0;
2116 sc->num_tx_desc_avail = sc->num_tx_desc;
2120 emx_init_tx_unit(struct emx_softc *sc)
2122 uint32_t tctl, tarc, tipg = 0;
2125 /* Setup the Base and Length of the Tx Descriptor Ring */
2126 bus_addr = sc->tx_desc_paddr;
2127 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0),
2128 sc->num_tx_desc * sizeof(struct e1000_tx_desc));
2129 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0),
2130 (uint32_t)(bus_addr >> 32));
2131 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0),
2132 (uint32_t)bus_addr);
2133 /* Setup the HW Tx Head and Tail descriptor pointers */
2134 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0);
2135 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0);
2137 /* Set the default values for the Tx Inter Packet Gap timer */
2138 switch (sc->hw.mac.type) {
2139 case e1000_80003es2lan:
2140 tipg = DEFAULT_82543_TIPG_IPGR1;
2141 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2142 E1000_TIPG_IPGR2_SHIFT;
2146 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2147 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2148 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2150 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2151 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2152 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2156 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2158 /* NOTE: 0 is not allowed for TIDV */
2159 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2160 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2162 if (sc->hw.mac.type == e1000_82571 ||
2163 sc->hw.mac.type == e1000_82572) {
2164 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2165 tarc |= EMX_TARC_SPEED_MODE;
2166 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2167 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2168 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2170 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2171 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2173 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2176 /* Program the Transmit Control Register */
2177 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2178 tctl &= ~E1000_TCTL_CT;
2179 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2180 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2181 tctl |= E1000_TCTL_MULR;
2183 /* This write will effectively turn on the transmit unit. */
2184 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2188 emx_destroy_tx_ring(struct emx_softc *sc, int ndesc)
2190 struct emx_txbuf *tx_buffer;
2193 /* Free Transmit Descriptor ring */
2194 if (sc->tx_desc_base) {
2195 bus_dmamap_unload(sc->tx_desc_dtag, sc->tx_desc_dmap);
2196 bus_dmamem_free(sc->tx_desc_dtag, sc->tx_desc_base,
2198 bus_dma_tag_destroy(sc->tx_desc_dtag);
2200 sc->tx_desc_base = NULL;
2203 if (sc->tx_buf == NULL)
2206 for (i = 0; i < ndesc; i++) {
2207 tx_buffer = &sc->tx_buf[i];
2209 KKASSERT(tx_buffer->m_head == NULL);
2210 bus_dmamap_destroy(sc->txtag, tx_buffer->map);
2212 bus_dma_tag_destroy(sc->txtag);
2214 kfree(sc->tx_buf, M_DEVBUF);
2219 * The offload context needs to be set when we transfer the first
2220 * packet of a particular protocol (TCP/UDP). This routine has been
2221 * enhanced to deal with inserted VLAN headers.
2223 * If the new packet's ether header length, ip header length and
2224 * csum offloading type are same as the previous packet, we should
2225 * avoid allocating a new csum context descriptor; mainly to take
2226 * advantage of the pipeline effect of the TX data read request.
2228 * This function returns number of TX descrptors allocated for
2232 emx_txcsum(struct emx_softc *sc, struct mbuf *mp,
2233 uint32_t *txd_upper, uint32_t *txd_lower)
2235 struct e1000_context_desc *TXD;
2236 int curr_txd, ehdrlen, csum_flags;
2237 uint32_t cmd, hdr_len, ip_hlen;
2239 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2240 ip_hlen = mp->m_pkthdr.csum_iphlen;
2241 ehdrlen = mp->m_pkthdr.csum_lhlen;
2243 if (sc->csum_lhlen == ehdrlen && sc->csum_iphlen == ip_hlen &&
2244 sc->csum_flags == csum_flags) {
2246 * Same csum offload context as the previous packets;
2249 *txd_upper = sc->csum_txd_upper;
2250 *txd_lower = sc->csum_txd_lower;
2255 * Setup a new csum offload context.
2258 curr_txd = sc->next_avail_tx_desc;
2259 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd];
2263 /* Setup of IP header checksum. */
2264 if (csum_flags & CSUM_IP) {
2266 * Start offset for header checksum calculation.
2267 * End offset for header checksum calculation.
2268 * Offset of place to put the checksum.
2270 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2271 TXD->lower_setup.ip_fields.ipcse =
2272 htole16(ehdrlen + ip_hlen - 1);
2273 TXD->lower_setup.ip_fields.ipcso =
2274 ehdrlen + offsetof(struct ip, ip_sum);
2275 cmd |= E1000_TXD_CMD_IP;
2276 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2278 hdr_len = ehdrlen + ip_hlen;
2280 if (csum_flags & CSUM_TCP) {
2282 * Start offset for payload checksum calculation.
2283 * End offset for payload checksum calculation.
2284 * Offset of place to put the checksum.
2286 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2287 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2288 TXD->upper_setup.tcp_fields.tucso =
2289 hdr_len + offsetof(struct tcphdr, th_sum);
2290 cmd |= E1000_TXD_CMD_TCP;
2291 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2292 } else if (csum_flags & CSUM_UDP) {
2294 * Start offset for header checksum calculation.
2295 * End offset for header checksum calculation.
2296 * Offset of place to put the checksum.
2298 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2299 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2300 TXD->upper_setup.tcp_fields.tucso =
2301 hdr_len + offsetof(struct udphdr, uh_sum);
2302 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2305 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2306 E1000_TXD_DTYP_D; /* Data descr */
2308 /* Save the information for this csum offloading context */
2309 sc->csum_lhlen = ehdrlen;
2310 sc->csum_iphlen = ip_hlen;
2311 sc->csum_flags = csum_flags;
2312 sc->csum_txd_upper = *txd_upper;
2313 sc->csum_txd_lower = *txd_lower;
2315 TXD->tcp_seg_setup.data = htole32(0);
2316 TXD->cmd_and_length =
2317 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2319 if (++curr_txd == sc->num_tx_desc)
2322 KKASSERT(sc->num_tx_desc_avail > 0);
2323 sc->num_tx_desc_avail--;
2325 sc->next_avail_tx_desc = curr_txd;
2330 emx_txeof(struct emx_softc *sc)
2332 struct ifnet *ifp = &sc->arpcom.ac_if;
2333 struct emx_txbuf *tx_buffer;
2334 int first, num_avail;
2336 if (sc->tx_dd_head == sc->tx_dd_tail)
2339 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2342 num_avail = sc->num_tx_desc_avail;
2343 first = sc->next_tx_to_clean;
2345 while (sc->tx_dd_head != sc->tx_dd_tail) {
2346 int dd_idx = sc->tx_dd[sc->tx_dd_head];
2347 struct e1000_tx_desc *tx_desc;
2349 tx_desc = &sc->tx_desc_base[dd_idx];
2350 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2351 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2353 if (++dd_idx == sc->num_tx_desc)
2356 while (first != dd_idx) {
2361 tx_buffer = &sc->tx_buf[first];
2362 if (tx_buffer->m_head) {
2364 bus_dmamap_unload(sc->txtag,
2366 m_freem(tx_buffer->m_head);
2367 tx_buffer->m_head = NULL;
2370 if (++first == sc->num_tx_desc)
2377 sc->next_tx_to_clean = first;
2378 sc->num_tx_desc_avail = num_avail;
2380 if (sc->tx_dd_head == sc->tx_dd_tail) {
2385 if (!EMX_IS_OACTIVE(sc)) {
2386 ifp->if_flags &= ~IFF_OACTIVE;
2388 /* All clean, turn off the timer */
2389 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2395 emx_tx_collect(struct emx_softc *sc)
2397 struct ifnet *ifp = &sc->arpcom.ac_if;
2398 struct emx_txbuf *tx_buffer;
2399 int tdh, first, num_avail, dd_idx = -1;
2401 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2404 tdh = E1000_READ_REG(&sc->hw, E1000_TDH(0));
2405 if (tdh == sc->next_tx_to_clean)
2408 if (sc->tx_dd_head != sc->tx_dd_tail)
2409 dd_idx = sc->tx_dd[sc->tx_dd_head];
2411 num_avail = sc->num_tx_desc_avail;
2412 first = sc->next_tx_to_clean;
2414 while (first != tdh) {
2419 tx_buffer = &sc->tx_buf[first];
2420 if (tx_buffer->m_head) {
2422 bus_dmamap_unload(sc->txtag,
2424 m_freem(tx_buffer->m_head);
2425 tx_buffer->m_head = NULL;
2428 if (first == dd_idx) {
2429 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2430 if (sc->tx_dd_head == sc->tx_dd_tail) {
2435 dd_idx = sc->tx_dd[sc->tx_dd_head];
2439 if (++first == sc->num_tx_desc)
2442 sc->next_tx_to_clean = first;
2443 sc->num_tx_desc_avail = num_avail;
2445 if (!EMX_IS_OACTIVE(sc)) {
2446 ifp->if_flags &= ~IFF_OACTIVE;
2448 /* All clean, turn off the timer */
2449 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2455 * When Link is lost sometimes there is work still in the TX ring
2456 * which will result in a watchdog, rather than allow that do an
2457 * attempted cleanup and then reinit here. Note that this has been
2458 * seens mostly with fiber adapters.
2461 emx_tx_purge(struct emx_softc *sc)
2463 struct ifnet *ifp = &sc->arpcom.ac_if;
2465 if (!sc->link_active && ifp->if_timer) {
2467 if (ifp->if_timer) {
2468 if_printf(ifp, "Link lost, TX pending, reinit\n");
2476 emx_newbuf(struct emx_softc *sc, struct emx_rxdata *rdata, int i, int init)
2479 bus_dma_segment_t seg;
2481 struct emx_rxbuf *rx_buffer;
2484 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2487 if_printf(&sc->arpcom.ac_if,
2488 "Unable to allocate RX mbuf\n");
2492 m->m_len = m->m_pkthdr.len = MCLBYTES;
2494 if (sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2495 m_adj(m, ETHER_ALIGN);
2497 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2498 rdata->rx_sparemap, m,
2499 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2503 if_printf(&sc->arpcom.ac_if,
2504 "Unable to load RX mbuf\n");
2509 rx_buffer = &rdata->rx_buf[i];
2510 if (rx_buffer->m_head != NULL)
2511 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2513 map = rx_buffer->map;
2514 rx_buffer->map = rdata->rx_sparemap;
2515 rdata->rx_sparemap = map;
2517 rx_buffer->m_head = m;
2518 rx_buffer->paddr = seg.ds_addr;
2520 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
2525 emx_create_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2527 device_t dev = sc->dev;
2528 struct emx_rxbuf *rx_buffer;
2529 int i, error, rsize, nrxd;
2532 * Validate number of receive descriptors. It must not exceed
2533 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2535 nrxd = device_getenv_int(dev, "rxd", emx_rxd);
2536 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2537 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) {
2538 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
2539 EMX_DEFAULT_RXD, nrxd);
2540 rdata->num_rx_desc = EMX_DEFAULT_RXD;
2542 rdata->num_rx_desc = nrxd;
2546 * Allocate Receive Descriptor ring
2548 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
2550 rdata->rx_desc = bus_dmamem_coherent_any(sc->parent_dtag,
2551 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2552 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2553 &rdata->rx_desc_paddr);
2554 if (rdata->rx_desc == NULL) {
2555 device_printf(dev, "Unable to allocate rx_desc memory\n");
2559 rdata->rx_buf = kmalloc(sizeof(struct emx_rxbuf) * rdata->num_rx_desc,
2560 M_DEVBUF, M_WAITOK | M_ZERO);
2563 * Create DMA tag for rx buffers
2565 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2566 1, 0, /* alignment, bounds */
2567 BUS_SPACE_MAXADDR, /* lowaddr */
2568 BUS_SPACE_MAXADDR, /* highaddr */
2569 NULL, NULL, /* filter, filterarg */
2570 MCLBYTES, /* maxsize */
2572 MCLBYTES, /* maxsegsize */
2573 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2576 device_printf(dev, "Unable to allocate RX DMA tag\n");
2577 kfree(rdata->rx_buf, M_DEVBUF);
2578 rdata->rx_buf = NULL;
2583 * Create spare DMA map for rx buffers
2585 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2586 &rdata->rx_sparemap);
2588 device_printf(dev, "Unable to create spare RX DMA map\n");
2589 bus_dma_tag_destroy(rdata->rxtag);
2590 kfree(rdata->rx_buf, M_DEVBUF);
2591 rdata->rx_buf = NULL;
2596 * Create DMA maps for rx buffers
2598 for (i = 0; i < rdata->num_rx_desc; i++) {
2599 rx_buffer = &rdata->rx_buf[i];
2601 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2604 device_printf(dev, "Unable to create RX DMA map\n");
2605 emx_destroy_rx_ring(sc, rdata, i);
2613 emx_free_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2617 for (i = 0; i < rdata->num_rx_desc; i++) {
2618 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
2620 if (rx_buffer->m_head != NULL) {
2621 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2622 m_freem(rx_buffer->m_head);
2623 rx_buffer->m_head = NULL;
2627 if (rdata->fmp != NULL)
2628 m_freem(rdata->fmp);
2634 emx_init_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2638 /* Reset descriptor ring */
2639 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
2641 /* Allocate new ones. */
2642 for (i = 0; i < rdata->num_rx_desc; i++) {
2643 error = emx_newbuf(sc, rdata, i, 1);
2648 /* Setup our descriptor pointers */
2649 rdata->next_rx_desc_to_check = 0;
2655 emx_init_rx_unit(struct emx_softc *sc)
2657 struct ifnet *ifp = &sc->arpcom.ac_if;
2659 uint32_t rctl, itr, rfctl;
2663 * Make sure receives are disabled while setting
2664 * up the descriptor ring
2666 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2667 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2670 * Set the interrupt throttling rate. Value is calculated
2671 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2673 if (sc->int_throttle_ceil)
2674 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2677 emx_set_itr(sc, itr);
2679 /* Use extended RX descriptor */
2680 rfctl = E1000_RFCTL_EXTEN;
2682 /* Disable accelerated ackknowledge */
2683 if (sc->hw.mac.type == e1000_82574)
2684 rfctl |= E1000_RFCTL_ACK_DIS;
2686 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
2689 * Receive Checksum Offload for TCP and UDP
2691 * Checksum offloading is also enabled if multiple receive
2692 * queue is to be supported, since we need it to figure out
2695 if ((ifp->if_capenable & IFCAP_RXCSUM) ||
2696 sc->rx_ring_cnt > 1) {
2699 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2703 * PCSD must be enabled to enable multiple
2706 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2708 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2712 * Configure multiple receive queue (RSS)
2714 if (sc->rx_ring_cnt > 1) {
2715 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2718 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING,
2719 ("invalid number of RX ring (%d)", sc->rx_ring_cnt));
2723 * When we reach here, RSS has already been disabled
2724 * in emx_stop(), so we could safely configure RSS key
2725 * and redirect table.
2731 toeplitz_get_key(key, sizeof(key));
2732 for (i = 0; i < EMX_NRSSRK; ++i) {
2735 rssrk = EMX_RSSRK_VAL(key, i);
2736 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2738 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2742 * Configure RSS redirect table in following fashion:
2743 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2746 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2749 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT;
2750 reta |= q << (8 * i);
2752 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2754 for (i = 0; i < EMX_NRETA; ++i)
2755 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
2758 * Enable multiple receive queues.
2759 * Enable IPv4 RSS standard hash functions.
2760 * Disable RSS interrupt.
2762 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2763 E1000_MRQC_ENABLE_RSS_2Q |
2764 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2765 E1000_MRQC_RSS_FIELD_IPV4);
2769 * XXX TEMPORARY WORKAROUND: on some systems with 82573
2770 * long latencies are observed, like Lenovo X60. This
2771 * change eliminates the problem, but since having positive
2772 * values in RDTR is a known source of problems on other
2773 * platforms another solution is being sought.
2775 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
2776 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
2777 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
2780 for (i = 0; i < sc->rx_ring_cnt; ++i) {
2781 struct emx_rxdata *rdata = &sc->rx_data[i];
2784 * Setup the Base and Length of the Rx Descriptor Ring
2786 bus_addr = rdata->rx_desc_paddr;
2787 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
2788 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
2789 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
2790 (uint32_t)(bus_addr >> 32));
2791 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
2792 (uint32_t)bus_addr);
2795 * Setup the HW Rx Head and Tail Descriptor Pointers
2797 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
2798 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
2799 sc->rx_data[i].num_rx_desc - 1);
2802 /* Setup the Receive Control Register */
2803 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2804 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2805 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
2806 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2808 /* Make sure VLAN Filters are off */
2809 rctl &= ~E1000_RCTL_VFE;
2811 /* Don't store bad paket */
2812 rctl &= ~E1000_RCTL_SBP;
2815 rctl |= E1000_RCTL_SZ_2048;
2817 if (ifp->if_mtu > ETHERMTU)
2818 rctl |= E1000_RCTL_LPE;
2820 rctl &= ~E1000_RCTL_LPE;
2822 /* Enable Receives */
2823 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
2827 emx_destroy_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata, int ndesc)
2829 struct emx_rxbuf *rx_buffer;
2832 /* Free Receive Descriptor ring */
2833 if (rdata->rx_desc) {
2834 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
2835 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
2836 rdata->rx_desc_dmap);
2837 bus_dma_tag_destroy(rdata->rx_desc_dtag);
2839 rdata->rx_desc = NULL;
2842 if (rdata->rx_buf == NULL)
2845 for (i = 0; i < ndesc; i++) {
2846 rx_buffer = &rdata->rx_buf[i];
2848 KKASSERT(rx_buffer->m_head == NULL);
2849 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
2851 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
2852 bus_dma_tag_destroy(rdata->rxtag);
2854 kfree(rdata->rx_buf, M_DEVBUF);
2855 rdata->rx_buf = NULL;
2859 emx_rxeof(struct emx_softc *sc, int ring_idx, int count)
2861 struct emx_rxdata *rdata = &sc->rx_data[ring_idx];
2862 struct ifnet *ifp = &sc->arpcom.ac_if;
2864 emx_rxdesc_t *current_desc;
2868 i = rdata->next_rx_desc_to_check;
2869 current_desc = &rdata->rx_desc[i];
2870 staterr = le32toh(current_desc->rxd_staterr);
2872 if (!(staterr & E1000_RXD_STAT_DD))
2875 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2876 struct pktinfo *pi = NULL, pi0;
2877 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
2878 struct mbuf *m = NULL;
2883 mp = rx_buf->m_head;
2886 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
2887 * needs to access the last received byte in the mbuf.
2889 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
2890 BUS_DMASYNC_POSTREAD);
2892 len = le16toh(current_desc->rxd_length);
2893 if (staterr & E1000_RXD_STAT_EOP) {
2900 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2902 uint32_t mrq, rss_hash;
2905 * Save several necessary information,
2906 * before emx_newbuf() destroy it.
2908 if ((staterr & E1000_RXD_STAT_VP) && eop)
2909 vlan = le16toh(current_desc->rxd_vlan);
2911 mrq = le32toh(current_desc->rxd_mrq);
2912 rss_hash = le32toh(current_desc->rxd_rss);
2914 EMX_RSS_DPRINTF(sc, 10,
2915 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
2916 ring_idx, mrq, rss_hash);
2918 if (emx_newbuf(sc, rdata, i, 0) != 0) {
2923 /* Assign correct length to the current fragment */
2926 if (rdata->fmp == NULL) {
2927 mp->m_pkthdr.len = len;
2928 rdata->fmp = mp; /* Store the first mbuf */
2932 * Chain mbuf's together
2934 rdata->lmp->m_next = mp;
2935 rdata->lmp = rdata->lmp->m_next;
2936 rdata->fmp->m_pkthdr.len += len;
2940 rdata->fmp->m_pkthdr.rcvif = ifp;
2943 if (ifp->if_capenable & IFCAP_RXCSUM)
2944 emx_rxcsum(staterr, rdata->fmp);
2946 if (staterr & E1000_RXD_STAT_VP) {
2947 rdata->fmp->m_pkthdr.ether_vlantag =
2949 rdata->fmp->m_flags |= M_VLANTAG;
2955 if (ifp->if_capenable & IFCAP_RSS) {
2956 pi = emx_rssinfo(m, &pi0, mrq,
2959 #ifdef EMX_RSS_DEBUG
2966 emx_setup_rxdesc(current_desc, rx_buf);
2967 if (rdata->fmp != NULL) {
2968 m_freem(rdata->fmp);
2976 ether_input_pkt(ifp, m, pi);
2978 /* Advance our pointers to the next descriptor. */
2979 if (++i == rdata->num_rx_desc)
2982 current_desc = &rdata->rx_desc[i];
2983 staterr = le32toh(current_desc->rxd_staterr);
2985 rdata->next_rx_desc_to_check = i;
2987 /* Advance the E1000's Receive Queue "Tail Pointer". */
2989 i = rdata->num_rx_desc - 1;
2990 E1000_WRITE_REG(&sc->hw, E1000_RDT(ring_idx), i);
2994 emx_enable_intr(struct emx_softc *sc)
2996 uint32_t ims_mask = IMS_ENABLE_MASK;
2998 lwkt_serialize_handler_enable(&sc->main_serialize);
3001 if (sc->hw.mac.type == e1000_82574) {
3002 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
3003 ims_mask |= EM_MSIX_MASK;
3006 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
3010 emx_disable_intr(struct emx_softc *sc)
3012 if (sc->hw.mac.type == e1000_82574)
3013 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
3014 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
3016 lwkt_serialize_handler_disable(&sc->main_serialize);
3020 * Bit of a misnomer, what this really means is
3021 * to enable OS management of the system... aka
3022 * to disable special hardware management features
3025 emx_get_mgmt(struct emx_softc *sc)
3027 /* A shared code workaround */
3028 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3029 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
3030 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3032 /* disable hardware interception of ARP */
3033 manc &= ~(E1000_MANC_ARP_EN);
3035 /* enable receiving management packets to the host */
3036 manc |= E1000_MANC_EN_MNG2HOST;
3037 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3038 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3039 manc2h |= E1000_MNG2HOST_PORT_623;
3040 manc2h |= E1000_MNG2HOST_PORT_664;
3041 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3043 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3048 * Give control back to hardware management
3049 * controller if there is one.
3052 emx_rel_mgmt(struct emx_softc *sc)
3054 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3055 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3057 /* re-enable hardware interception of ARP */
3058 manc |= E1000_MANC_ARP_EN;
3059 manc &= ~E1000_MANC_EN_MNG2HOST;
3061 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3066 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3067 * For ASF and Pass Through versions of f/w this means that
3068 * the driver is loaded. For AMT version (only with 82573)
3069 * of the f/w this means that the network i/f is open.
3072 emx_get_hw_control(struct emx_softc *sc)
3074 /* Let firmware know the driver has taken over */
3075 if (sc->hw.mac.type == e1000_82573) {
3078 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3079 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3080 swsm | E1000_SWSM_DRV_LOAD);
3084 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3085 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3086 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3088 sc->flags |= EMX_FLAG_HW_CTRL;
3092 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3093 * For ASF and Pass Through versions of f/w this means that the
3094 * driver is no longer loaded. For AMT version (only with 82573)
3095 * of the f/w this means that the network i/f is closed.
3098 emx_rel_hw_control(struct emx_softc *sc)
3100 if ((sc->flags & EMX_FLAG_HW_CTRL) == 0)
3102 sc->flags &= ~EMX_FLAG_HW_CTRL;
3104 /* Let firmware taken over control of h/w */
3105 if (sc->hw.mac.type == e1000_82573) {
3108 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3109 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3110 swsm & ~E1000_SWSM_DRV_LOAD);
3114 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3115 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3116 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3121 emx_is_valid_eaddr(const uint8_t *addr)
3123 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3125 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3132 * Enable PCI Wake On Lan capability
3135 emx_enable_wol(device_t dev)
3137 uint16_t cap, status;
3140 /* First find the capabilities pointer*/
3141 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3143 /* Read the PM Capabilities */
3144 id = pci_read_config(dev, cap, 1);
3145 if (id != PCIY_PMG) /* Something wrong */
3149 * OK, we have the power capabilities,
3150 * so now get the status register
3152 cap += PCIR_POWER_STATUS;
3153 status = pci_read_config(dev, cap, 2);
3154 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3155 pci_write_config(dev, cap, status, 2);
3159 emx_update_stats(struct emx_softc *sc)
3161 struct ifnet *ifp = &sc->arpcom.ac_if;
3163 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3164 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3165 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3166 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3168 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3169 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3170 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3171 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3173 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3174 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3175 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3176 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3177 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3178 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3179 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3180 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3181 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3182 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3183 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3184 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3185 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3186 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3187 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3188 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3189 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3190 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3191 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3192 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3194 /* For the 64-bit byte counters the low dword must be read first. */
3195 /* Both registers clear on the read of the high dword */
3197 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3198 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3200 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3201 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3202 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3203 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3204 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3206 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3207 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3209 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3210 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3211 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3212 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3213 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3214 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3215 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3216 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3217 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3218 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3220 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3221 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3222 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3223 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3224 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3225 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3227 ifp->if_collisions = sc->stats.colc;
3230 ifp->if_ierrors = sc->stats.rxerrc +
3231 sc->stats.crcerrs + sc->stats.algnerrc +
3232 sc->stats.ruc + sc->stats.roc +
3233 sc->stats.mpc + sc->stats.cexterr;
3236 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol;
3240 emx_print_debug_info(struct emx_softc *sc)
3242 device_t dev = sc->dev;
3243 uint8_t *hw_addr = sc->hw.hw_addr;
3245 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3246 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3247 E1000_READ_REG(&sc->hw, E1000_CTRL),
3248 E1000_READ_REG(&sc->hw, E1000_RCTL));
3249 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3250 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3251 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3252 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3253 sc->hw.fc.high_water, sc->hw.fc.low_water);
3254 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3255 E1000_READ_REG(&sc->hw, E1000_TIDV),
3256 E1000_READ_REG(&sc->hw, E1000_TADV));
3257 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3258 E1000_READ_REG(&sc->hw, E1000_RDTR),
3259 E1000_READ_REG(&sc->hw, E1000_RADV));
3260 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3261 E1000_READ_REG(&sc->hw, E1000_TDH(0)),
3262 E1000_READ_REG(&sc->hw, E1000_TDT(0)));
3263 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3264 E1000_READ_REG(&sc->hw, E1000_RDH(0)),
3265 E1000_READ_REG(&sc->hw, E1000_RDT(0)));
3266 device_printf(dev, "Num Tx descriptors avail = %d\n",
3267 sc->num_tx_desc_avail);
3269 device_printf(dev, "TSO segments %lu\n", sc->tso_segments);
3270 device_printf(dev, "TSO ctx reused %lu\n", sc->tso_ctx_reused);
3274 emx_print_hw_stats(struct emx_softc *sc)
3276 device_t dev = sc->dev;
3278 device_printf(dev, "Excessive collisions = %lld\n",
3279 (long long)sc->stats.ecol);
3280 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3281 device_printf(dev, "Symbol errors = %lld\n",
3282 (long long)sc->stats.symerrs);
3284 device_printf(dev, "Sequence errors = %lld\n",
3285 (long long)sc->stats.sec);
3286 device_printf(dev, "Defer count = %lld\n",
3287 (long long)sc->stats.dc);
3288 device_printf(dev, "Missed Packets = %lld\n",
3289 (long long)sc->stats.mpc);
3290 device_printf(dev, "Receive No Buffers = %lld\n",
3291 (long long)sc->stats.rnbc);
3292 /* RLEC is inaccurate on some hardware, calculate our own. */
3293 device_printf(dev, "Receive Length Errors = %lld\n",
3294 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3295 device_printf(dev, "Receive errors = %lld\n",
3296 (long long)sc->stats.rxerrc);
3297 device_printf(dev, "Crc errors = %lld\n",
3298 (long long)sc->stats.crcerrs);
3299 device_printf(dev, "Alignment errors = %lld\n",
3300 (long long)sc->stats.algnerrc);
3301 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3302 (long long)sc->stats.cexterr);
3303 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3304 device_printf(dev, "XON Rcvd = %lld\n",
3305 (long long)sc->stats.xonrxc);
3306 device_printf(dev, "XON Xmtd = %lld\n",
3307 (long long)sc->stats.xontxc);
3308 device_printf(dev, "XOFF Rcvd = %lld\n",
3309 (long long)sc->stats.xoffrxc);
3310 device_printf(dev, "XOFF Xmtd = %lld\n",
3311 (long long)sc->stats.xofftxc);
3312 device_printf(dev, "Good Packets Rcvd = %lld\n",
3313 (long long)sc->stats.gprc);
3314 device_printf(dev, "Good Packets Xmtd = %lld\n",
3315 (long long)sc->stats.gptc);
3319 emx_print_nvm_info(struct emx_softc *sc)
3321 uint16_t eeprom_data;
3324 /* Its a bit crude, but it gets the job done */
3325 kprintf("\nInterface EEPROM Dump:\n");
3326 kprintf("Offset\n0x0000 ");
3327 for (i = 0, j = 0; i < 32; i++, j++) {
3328 if (j == 8) { /* Make the offset block */
3330 kprintf("\n0x00%x0 ",row);
3332 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3333 kprintf("%04x ", eeprom_data);
3339 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3341 struct emx_softc *sc;
3346 error = sysctl_handle_int(oidp, &result, 0, req);
3347 if (error || !req->newptr)
3350 sc = (struct emx_softc *)arg1;
3351 ifp = &sc->arpcom.ac_if;
3353 ifnet_serialize_all(ifp);
3356 emx_print_debug_info(sc);
3359 * This value will cause a hex dump of the
3360 * first 32 16-bit words of the EEPROM to
3364 emx_print_nvm_info(sc);
3366 ifnet_deserialize_all(ifp);
3372 emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3377 error = sysctl_handle_int(oidp, &result, 0, req);
3378 if (error || !req->newptr)
3382 struct emx_softc *sc = (struct emx_softc *)arg1;
3383 struct ifnet *ifp = &sc->arpcom.ac_if;
3385 ifnet_serialize_all(ifp);
3386 emx_print_hw_stats(sc);
3387 ifnet_deserialize_all(ifp);
3393 emx_add_sysctl(struct emx_softc *sc)
3395 #ifdef EMX_RSS_DEBUG
3400 sysctl_ctx_init(&sc->sysctl_ctx);
3401 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
3402 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
3403 device_get_nameunit(sc->dev),
3405 if (sc->sysctl_tree == NULL) {
3406 device_printf(sc->dev, "can't add sysctl node\n");
3410 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3411 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3412 emx_sysctl_debug_info, "I", "Debug Information");
3414 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3415 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3416 emx_sysctl_stats, "I", "Statistics");
3418 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3419 OID_AUTO, "rxd", CTLFLAG_RD,
3420 &sc->rx_data[0].num_rx_desc, 0, NULL);
3421 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3422 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL);
3424 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3425 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW,
3426 sc, 0, emx_sysctl_int_throttle, "I",
3427 "interrupt throttling rate");
3428 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3429 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW,
3430 sc, 0, emx_sysctl_int_tx_nsegs, "I",
3431 "# segments per TX interrupt");
3433 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3434 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD,
3435 &sc->rx_ring_cnt, 0, "RX ring count");
3437 #ifdef IFPOLL_ENABLE
3438 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3439 OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
3440 sc, 0, emx_sysctl_npoll_rxoff, "I",
3441 "NPOLLING RX cpu offset");
3442 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3443 OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
3444 sc, 0, emx_sysctl_npoll_txoff, "I",
3445 "NPOLLING TX cpu offset");
3448 #ifdef EMX_RSS_DEBUG
3449 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3450 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3451 0, "RSS debug level");
3452 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3453 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i);
3454 SYSCTL_ADD_UINT(&sc->sysctl_ctx,
3455 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
3457 &sc->rx_data[i].rx_pkts, 0, "RXed packets");
3463 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3465 struct emx_softc *sc = (void *)arg1;
3466 struct ifnet *ifp = &sc->arpcom.ac_if;
3467 int error, throttle;
3469 throttle = sc->int_throttle_ceil;
3470 error = sysctl_handle_int(oidp, &throttle, 0, req);
3471 if (error || req->newptr == NULL)
3473 if (throttle < 0 || throttle > 1000000000 / 256)
3478 * Set the interrupt throttling rate in 256ns increments,
3479 * recalculate sysctl value assignment to get exact frequency.
3481 throttle = 1000000000 / 256 / throttle;
3483 /* Upper 16bits of ITR is reserved and should be zero */
3484 if (throttle & 0xffff0000)
3488 ifnet_serialize_all(ifp);
3491 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3493 sc->int_throttle_ceil = 0;
3495 if (ifp->if_flags & IFF_RUNNING)
3496 emx_set_itr(sc, throttle);
3498 ifnet_deserialize_all(ifp);
3501 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3502 sc->int_throttle_ceil);
3508 emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS)
3510 struct emx_softc *sc = (void *)arg1;
3511 struct ifnet *ifp = &sc->arpcom.ac_if;
3514 segs = sc->tx_int_nsegs;
3515 error = sysctl_handle_int(oidp, &segs, 0, req);
3516 if (error || req->newptr == NULL)
3521 ifnet_serialize_all(ifp);
3524 * Don't allow int_tx_nsegs to become:
3525 * o Less the oact_tx_desc
3526 * o Too large that no TX desc will cause TX interrupt to
3527 * be generated (OACTIVE will never recover)
3528 * o Too small that will cause tx_dd[] overflow
3530 if (segs < sc->oact_tx_desc ||
3531 segs >= sc->num_tx_desc - sc->oact_tx_desc ||
3532 segs < sc->num_tx_desc / EMX_TXDD_SAFE) {
3536 sc->tx_int_nsegs = segs;
3539 ifnet_deserialize_all(ifp);
3544 #ifdef IFPOLL_ENABLE
3547 emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3549 struct emx_softc *sc = (void *)arg1;
3550 struct ifnet *ifp = &sc->arpcom.ac_if;
3553 off = sc->rx_npoll_off;
3554 error = sysctl_handle_int(oidp, &off, 0, req);
3555 if (error || req->newptr == NULL)
3560 ifnet_serialize_all(ifp);
3561 if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3565 sc->rx_npoll_off = off;
3567 ifnet_deserialize_all(ifp);
3573 emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3575 struct emx_softc *sc = (void *)arg1;
3576 struct ifnet *ifp = &sc->arpcom.ac_if;
3579 off = sc->tx_npoll_off;
3580 error = sysctl_handle_int(oidp, &off, 0, req);
3581 if (error || req->newptr == NULL)
3586 ifnet_serialize_all(ifp);
3587 if (off >= ncpus2) {
3591 sc->tx_npoll_off = off;
3593 ifnet_deserialize_all(ifp);
3598 #endif /* IFPOLL_ENABLE */
3601 emx_dma_alloc(struct emx_softc *sc)
3606 * Create top level busdma tag
3608 error = bus_dma_tag_create(NULL, 1, 0,
3609 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3611 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3612 0, &sc->parent_dtag);
3614 device_printf(sc->dev, "could not create top level DMA tag\n");
3619 * Allocate transmit descriptors ring and buffers
3621 error = emx_create_tx_ring(sc);
3623 device_printf(sc->dev, "Could not setup transmit structures\n");
3628 * Allocate receive descriptors ring and buffers
3630 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3631 error = emx_create_rx_ring(sc, &sc->rx_data[i]);
3633 device_printf(sc->dev,
3634 "Could not setup receive structures\n");
3642 emx_dma_free(struct emx_softc *sc)
3646 emx_destroy_tx_ring(sc, sc->num_tx_desc);
3648 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3649 emx_destroy_rx_ring(sc, &sc->rx_data[i],
3650 sc->rx_data[i].num_rx_desc);
3653 /* Free top level busdma tag */
3654 if (sc->parent_dtag != NULL)
3655 bus_dma_tag_destroy(sc->parent_dtag);
3659 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3661 struct emx_softc *sc = ifp->if_softc;
3663 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE,
3664 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
3668 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3670 struct emx_softc *sc = ifp->if_softc;
3672 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE,
3673 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
3677 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3679 struct emx_softc *sc = ifp->if_softc;
3681 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE,
3682 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
3686 emx_serialize_skipmain(struct emx_softc *sc)
3688 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3692 emx_deserialize_skipmain(struct emx_softc *sc)
3694 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3700 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3701 boolean_t serialized)
3703 struct emx_softc *sc = ifp->if_softc;
3705 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE,
3706 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz, serialized);
3709 #endif /* INVARIANTS */
3711 #ifdef IFPOLL_ENABLE
3714 emx_npoll_status(struct ifnet *ifp)
3716 struct emx_softc *sc = ifp->if_softc;
3719 ASSERT_SERIALIZED(&sc->main_serialize);
3721 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3722 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3723 callout_stop(&sc->timer);
3724 sc->hw.mac.get_link_status = 1;
3725 emx_update_link_status(sc);
3726 callout_reset(&sc->timer, hz, emx_timer, sc);
3731 emx_npoll_tx(struct ifnet *ifp, void *arg __unused, int cycle __unused)
3733 struct emx_softc *sc = ifp->if_softc;
3735 ASSERT_SERIALIZED(&sc->tx_serialize);
3738 if (!ifq_is_empty(&ifp->if_snd))
3743 emx_npoll_rx(struct ifnet *ifp, void *arg, int cycle)
3745 struct emx_softc *sc = ifp->if_softc;
3746 struct emx_rxdata *rdata = arg;
3748 ASSERT_SERIALIZED(&rdata->rx_serialize);
3750 emx_rxeof(sc, rdata - sc->rx_data, cycle);
3754 emx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3756 struct emx_softc *sc = ifp->if_softc;
3758 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3763 info->ifpi_status.status_func = emx_npoll_status;
3764 info->ifpi_status.serializer = &sc->main_serialize;
3766 off = sc->tx_npoll_off;
3767 KKASSERT(off < ncpus2);
3768 info->ifpi_tx[off].poll_func = emx_npoll_tx;
3769 info->ifpi_tx[off].arg = NULL;
3770 info->ifpi_tx[off].serializer = &sc->tx_serialize;
3772 off = sc->rx_npoll_off;
3773 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3774 struct emx_rxdata *rdata = &sc->rx_data[i];
3777 KKASSERT(idx < ncpus2);
3778 info->ifpi_rx[idx].poll_func = emx_npoll_rx;
3779 info->ifpi_rx[idx].arg = rdata;
3780 info->ifpi_rx[idx].serializer = &rdata->rx_serialize;
3783 if (ifp->if_flags & IFF_RUNNING)
3784 emx_disable_intr(sc);
3785 ifp->if_npoll_cpuid = sc->tx_npoll_off;
3787 if (ifp->if_flags & IFF_RUNNING)
3788 emx_enable_intr(sc);
3789 ifp->if_npoll_cpuid = -1;
3793 #endif /* IFPOLL_ENABLE */
3796 emx_set_itr(struct emx_softc *sc, uint32_t itr)
3798 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr);
3799 if (sc->hw.mac.type == e1000_82574) {
3803 * When using MSIX interrupts we need to
3804 * throttle using the EITR register
3806 for (i = 0; i < 4; ++i)
3807 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr);
3812 * Disable the L0s, 82574L Errata #20
3815 emx_disable_aspm(struct emx_softc *sc)
3817 uint16_t link_cap, link_ctrl, disable;
3818 uint8_t pcie_ptr, reg;
3819 device_t dev = sc->dev;
3821 switch (sc->hw.mac.type) {
3826 * 82573 specification update
3827 * errata #8 disable L0s
3828 * errata #41 disable L1
3830 * 82571/82572 specification update
3831 # errata #13 disable L1
3832 * errata #68 disable L0s
3834 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1;
3839 * 82574 specification update errata #20
3841 * There is no need to disable L1
3843 disable = PCIEM_LNKCTL_ASPM_L0S;
3850 pcie_ptr = pci_get_pciecap_ptr(dev);
3854 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2);
3855 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0)
3859 if_printf(&sc->arpcom.ac_if, "disable ASPM %#02x\n", disable);
3861 reg = pcie_ptr + PCIER_LINKCTRL;
3862 link_ctrl = pci_read_config(dev, reg, 2);
3863 link_ctrl &= ~disable;
3864 pci_write_config(dev, reg, link_ctrl, 2);
3868 emx_tso_pullup(struct emx_softc *sc, struct mbuf **mp)
3870 int iphlen, hoff, thoff, ex = 0;
3875 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
3877 iphlen = m->m_pkthdr.csum_iphlen;
3878 thoff = m->m_pkthdr.csum_thlen;
3879 hoff = m->m_pkthdr.csum_lhlen;
3881 KASSERT(iphlen > 0, ("invalid ip hlen"));
3882 KASSERT(thoff > 0, ("invalid tcp hlen"));
3883 KASSERT(hoff > 0, ("invalid ether hlen"));
3885 if (sc->flags & EMX_FLAG_TSO_PULLEX)
3888 if (m->m_len < hoff + iphlen + thoff + ex) {
3889 m = m_pullup(m, hoff + iphlen + thoff + ex);
3896 ip = mtodoff(m, struct ip *, hoff);
3903 emx_tso_setup(struct emx_softc *sc, struct mbuf *mp,
3904 uint32_t *txd_upper, uint32_t *txd_lower)
3906 struct e1000_context_desc *TXD;
3907 int hoff, iphlen, thoff, hlen;
3908 int mss, pktlen, curr_txd;
3910 #ifdef EMX_TSO_DEBUG
3914 iphlen = mp->m_pkthdr.csum_iphlen;
3915 thoff = mp->m_pkthdr.csum_thlen;
3916 hoff = mp->m_pkthdr.csum_lhlen;
3917 mss = mp->m_pkthdr.tso_segsz;
3918 pktlen = mp->m_pkthdr.len;
3920 if (sc->csum_flags == CSUM_TSO &&
3921 sc->csum_iphlen == iphlen &&
3922 sc->csum_lhlen == hoff &&
3923 sc->csum_thlen == thoff &&
3924 sc->csum_mss == mss &&
3925 sc->csum_pktlen == pktlen) {
3926 *txd_upper = sc->csum_txd_upper;
3927 *txd_lower = sc->csum_txd_lower;
3928 #ifdef EMX_TSO_DEBUG
3929 sc->tso_ctx_reused++;
3933 hlen = hoff + iphlen + thoff;
3936 * Setup a new TSO context.
3939 curr_txd = sc->next_avail_tx_desc;
3940 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd];
3942 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
3943 E1000_TXD_DTYP_D | /* Data descr type */
3944 E1000_TXD_CMD_TSE; /* Do TSE on this packet */
3946 /* IP and/or TCP header checksum calculation and insertion. */
3947 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8;
3950 * Start offset for header checksum calculation.
3951 * End offset for header checksum calculation.
3952 * Offset of place put the checksum.
3954 TXD->lower_setup.ip_fields.ipcss = hoff;
3955 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1);
3956 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum);
3959 * Start offset for payload checksum calculation.
3960 * End offset for payload checksum calculation.
3961 * Offset of place to put the checksum.
3963 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen;
3964 TXD->upper_setup.tcp_fields.tucse = 0;
3965 TXD->upper_setup.tcp_fields.tucso =
3966 hoff + iphlen + offsetof(struct tcphdr, th_sum);
3969 * Payload size per packet w/o any headers.
3970 * Length of all headers up to payload.
3972 TXD->tcp_seg_setup.fields.mss = htole16(mss);
3973 TXD->tcp_seg_setup.fields.hdr_len = hlen;
3974 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS |
3975 E1000_TXD_CMD_DEXT | /* Extended descr */
3976 E1000_TXD_CMD_TSE | /* TSE context */
3977 E1000_TXD_CMD_IP | /* Do IP csum */
3978 E1000_TXD_CMD_TCP | /* Do TCP checksum */
3979 (pktlen - hlen)); /* Total len */
3981 /* Save the information for this TSO context */
3982 sc->csum_flags = CSUM_TSO;
3983 sc->csum_lhlen = hoff;
3984 sc->csum_iphlen = iphlen;
3985 sc->csum_thlen = thoff;
3987 sc->csum_pktlen = pktlen;
3988 sc->csum_txd_upper = *txd_upper;
3989 sc->csum_txd_lower = *txd_lower;
3991 if (++curr_txd == sc->num_tx_desc)
3994 KKASSERT(sc->num_tx_desc_avail > 0);
3995 sc->num_tx_desc_avail--;
3997 sc->next_avail_tx_desc = curr_txd;