2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <william.paul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.5.2.2 2001/12/14 19:49:23 jlemon Exp $
34 * $DragonFly: src/sys/dev/netif/lge/if_lge.c,v 1.42 2008/08/17 04:32:33 sephe Exp $
38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public
39 * documentation not available, but ask me nicely.
41 * Written by Bill Paul <william.paul@windriver.com>
46 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs.
47 * It's a 64-bit PCI part that supports TCP/IP checksum offload,
48 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There
49 * are three supported methods for data transfer between host and
50 * NIC: programmed I/O, traditional scatter/gather DMA and Packet
51 * Propulsion Technology (tm) DMA. The latter mechanism is a form
52 * of double buffer DMA where the packet data is copied to a
53 * pre-allocated DMA buffer who's physical address has been loaded
54 * into a table at device initialization time. The rationale is that
55 * the virtual to physical address translation needed for normal
56 * scatter/gather DMA is more expensive than the data copy needed
57 * for double buffering. This may be true in Windows NT and the like,
58 * but it isn't true for us, at least on the x86 arch. This driver
59 * uses the scatter/gather I/O method for both TX and RX.
61 * The LXT1001 only supports TCP/IP checksum offload on receive.
62 * Also, the VLAN tagging is done using a 16-entry table which allows
63 * the chip to perform hardware filtering based on VLAN tags. Sadly,
64 * our vlan support doesn't currently play well with this kind of
68 * - Jeff James at Intel, for arranging to have the LXT1001 manual
69 * released (at long last)
70 * - Beny Chen at D-Link, for actually sending it to me
71 * - Brad Short and Keith Alexis at SMC, for sending me sample
72 * SMC9462SX and SMC9462TX adapters for testing
73 * - Paul Saab at Y!, for not killing me (though it remains to be seen
74 * if in fact he did me much of a favor)
77 #include <sys/param.h>
78 #include <sys/systm.h>
79 #include <sys/sockio.h>
81 #include <sys/malloc.h>
82 #include <sys/kernel.h>
83 #include <sys/interrupt.h>
84 #include <sys/socket.h>
85 #include <sys/serialize.h>
86 #include <sys/thread2.h>
89 #include <net/ifq_var.h>
90 #include <net/if_arp.h>
91 #include <net/ethernet.h>
92 #include <net/if_dl.h>
93 #include <net/if_media.h>
97 #include <vm/vm.h> /* for vtophys */
98 #include <vm/pmap.h> /* for vtophys */
100 #include <sys/rman.h>
102 #include <dev/netif/mii_layer/mii.h>
103 #include <dev/netif/mii_layer/miivar.h>
105 #include <bus/pci/pcidevs.h>
106 #include <bus/pci/pcireg.h>
107 #include <bus/pci/pcivar.h>
109 #define LGE_USEIOSPACE
111 #include "if_lgereg.h"
113 /* "controller miibus0" required. See GENERIC if you get errors here. */
114 #include "miibus_if.h"
117 * Various supported device vendors/types and their names.
119 static struct lge_type lge_devs[] = {
120 { PCI_VENDOR_LEVELONE, PCI_PRODUCT_LEVELONE_LXT1001,
121 "Level 1 Gigabit Ethernet" },
125 static int lge_probe(device_t);
126 static int lge_attach(device_t);
127 static int lge_detach(device_t);
129 static int lge_alloc_jumbo_mem(struct lge_softc *);
130 static void lge_free_jumbo_mem(struct lge_softc *);
131 static struct lge_jslot
132 *lge_jalloc(struct lge_softc *);
133 static void lge_jfree(void *);
134 static void lge_jref(void *);
136 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *,
138 static int lge_encap(struct lge_softc *, struct mbuf *, uint32_t *);
139 static void lge_rxeof(struct lge_softc *, int);
140 static void lge_rxeoc(struct lge_softc *);
141 static void lge_txeof(struct lge_softc *);
142 static void lge_intr(void *);
143 static void lge_tick(void *);
144 static void lge_tick_serialized(void *);
145 static void lge_start(struct ifnet *);
146 static int lge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
147 static void lge_init(void *);
148 static void lge_stop(struct lge_softc *);
149 static void lge_watchdog(struct ifnet *);
150 static void lge_shutdown(device_t);
151 static int lge_ifmedia_upd(struct ifnet *);
152 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
154 static void lge_eeprom_getword(struct lge_softc *, int, uint16_t *);
155 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int);
157 static int lge_miibus_readreg(device_t, int, int);
158 static int lge_miibus_writereg(device_t, int, int, int);
159 static void lge_miibus_statchg(device_t);
161 static void lge_setmulti(struct lge_softc *);
162 static void lge_reset(struct lge_softc *);
163 static int lge_list_rx_init(struct lge_softc *);
164 static int lge_list_tx_init(struct lge_softc *);
166 #ifdef LGE_USEIOSPACE
167 #define LGE_RES SYS_RES_IOPORT
168 #define LGE_RID LGE_PCI_LOIO
170 #define LGE_RES SYS_RES_MEMORY
171 #define LGE_RID LGE_PCI_LOMEM
174 static device_method_t lge_methods[] = {
175 /* Device interface */
176 DEVMETHOD(device_probe, lge_probe),
177 DEVMETHOD(device_attach, lge_attach),
178 DEVMETHOD(device_detach, lge_detach),
179 DEVMETHOD(device_shutdown, lge_shutdown),
182 DEVMETHOD(bus_print_child, bus_generic_print_child),
183 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
186 DEVMETHOD(miibus_readreg, lge_miibus_readreg),
187 DEVMETHOD(miibus_writereg, lge_miibus_writereg),
188 DEVMETHOD(miibus_statchg, lge_miibus_statchg),
193 static DEFINE_CLASS_0(lge, lge_driver, lge_methods, sizeof(struct lge_softc));
194 static devclass_t lge_devclass;
196 DECLARE_DUMMY_MODULE(if_lge);
197 DRIVER_MODULE(if_lge, pci, lge_driver, lge_devclass, 0, 0);
198 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0);
200 #define LGE_SETBIT(sc, reg, x) \
201 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
203 #define LGE_CLRBIT(sc, reg, x) \
204 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
207 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | (x))
210 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~(x))
213 * Read a word of data stored in the EEPROM at address 'addr.'
216 lge_eeprom_getword(struct lge_softc *sc, int addr, uint16_t *dest)
221 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|
222 LGE_EECTL_SINGLEACCESS | ((addr >> 1) << 8));
224 for (i = 0; i < LGE_TIMEOUT; i++) {
225 if ((CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ) == 0)
229 if (i == LGE_TIMEOUT) {
230 kprintf("lge%d: EEPROM read timed out\n", sc->lge_unit);
234 val = CSR_READ_4(sc, LGE_EEDATA);
237 *dest = (val >> 16) & 0xFFFF;
239 *dest = val & 0xFFFF;
243 * Read a sequence of words from the EEPROM.
246 lge_read_eeprom(struct lge_softc *sc, caddr_t dest, int off, int cnt)
249 uint16_t word = 0, *ptr;
251 for (i = 0; i < cnt; i++) {
252 lge_eeprom_getword(sc, off + i, &word);
253 ptr = (uint16_t *)(dest + (i * 2));
259 lge_miibus_readreg(device_t dev, int phy, int reg)
261 struct lge_softc *sc = device_get_softc(dev);
265 * If we have a non-PCS PHY, pretend that the internal
266 * autoneg stuff at PHY address 0 isn't there so that
267 * the miibus code will find only the GMII PHY.
269 if (sc->lge_pcs == 0 && phy == 0)
272 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
274 for (i = 0; i < LGE_TIMEOUT; i++) {
275 if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0)
279 if (i == LGE_TIMEOUT) {
280 kprintf("lge%d: PHY read timed out\n", sc->lge_unit);
284 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
288 lge_miibus_writereg(device_t dev, int phy, int reg, int data)
290 struct lge_softc *sc = device_get_softc(dev);
293 CSR_WRITE_4(sc, LGE_GMIICTL,
294 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
296 for (i = 0; i < LGE_TIMEOUT; i++) {
297 if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0)
301 if (i == LGE_TIMEOUT) {
302 kprintf("lge%d: PHY write timed out\n", sc->lge_unit);
310 lge_miibus_statchg(device_t dev)
312 struct lge_softc *sc = device_get_softc(dev);
313 struct mii_data *mii = device_get_softc(sc->lge_miibus);
315 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED);
316 switch (IFM_SUBTYPE(mii->mii_media_active)) {
319 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
322 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100);
325 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10);
329 * Choose something, even if it's wrong. Clearing
330 * all the bits will hose autoneg on the internal
333 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
337 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
338 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
340 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
344 lge_setmulti(struct lge_softc *sc)
346 struct ifnet *ifp = &sc->arpcom.ac_if;
347 struct ifmultiaddr *ifma;
348 uint32_t h = 0, hashes[2] = { 0, 0 };
350 /* Make sure multicast hash table is enabled. */
351 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_MCAST);
353 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
354 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);
355 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);
359 /* first, zot all the existing hash bits */
360 CSR_WRITE_4(sc, LGE_MAR0, 0);
361 CSR_WRITE_4(sc, LGE_MAR1, 0);
363 /* now program new ones */
364 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
365 if (ifma->ifma_addr->sa_family != AF_LINK)
367 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
368 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
370 hashes[0] |= (1 << h);
372 hashes[1] |= (1 << (h - 32));
375 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]);
376 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]);
382 lge_reset(struct lge_softc *sc)
386 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0 | LGE_MODE1_SOFTRST);
388 for (i = 0; i < LGE_TIMEOUT; i++) {
389 if ((CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST) == 0)
393 if (i == LGE_TIMEOUT)
394 kprintf("lge%d: reset never completed\n", sc->lge_unit);
396 /* Wait a little while for the chip to get its brains in order. */
401 * Probe for a Level 1 chip. Check the PCI vendor and device
402 * IDs against our list and return a device name if we find a match.
405 lge_probe(device_t dev)
408 uint16_t vendor, product;
410 vendor = pci_get_vendor(dev);
411 product = pci_get_device(dev);
413 for (t = lge_devs; t->lge_name != NULL; t++) {
414 if (vendor == t->lge_vid && product == t->lge_did) {
415 device_set_desc(dev, t->lge_name);
424 * Attach the interface. Allocate softc structures, do ifmedia
425 * setup and ethernet/BPF attach.
428 lge_attach(device_t dev)
430 uint8_t eaddr[ETHER_ADDR_LEN];
431 struct lge_softc *sc;
433 int unit, error = 0, rid;
435 sc = device_get_softc(dev);
436 unit = device_get_unit(dev);
437 callout_init(&sc->lge_stat_timer);
438 lwkt_serialize_init(&sc->lge_jslot_serializer);
441 * Handle power management nonsense.
443 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
444 uint32_t iobase, membase, irq;
446 /* Save important PCI config data. */
447 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4);
448 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4);
449 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4);
451 /* Reset the power state. */
452 device_printf(dev, "chip is in D%d power mode "
453 "-- setting to D0\n", pci_get_powerstate(dev));
455 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
457 /* Restore PCI config data. */
458 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4);
459 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4);
460 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4);
463 pci_enable_busmaster(dev);
466 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE);
468 if (sc->lge_res == NULL) {
469 kprintf("lge%d: couldn't map ports/memory\n", unit);
474 sc->lge_btag = rman_get_bustag(sc->lge_res);
475 sc->lge_bhandle = rman_get_bushandle(sc->lge_res);
477 /* Allocate interrupt */
479 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
480 RF_SHAREABLE | RF_ACTIVE);
482 if (sc->lge_irq == NULL) {
483 kprintf("lge%d: couldn't map interrupt\n", unit);
488 /* Reset the adapter. */
492 * Get station address from the EEPROM.
494 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1);
495 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1);
496 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1);
500 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF,
501 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
503 if (sc->lge_ldata == NULL) {
504 kprintf("lge%d: no memory for list buffers!\n", unit);
509 /* Try to allocate memory for jumbo buffers. */
510 if (lge_alloc_jumbo_mem(sc)) {
511 kprintf("lge%d: jumbo buffer allocation failed\n",
517 ifp = &sc->arpcom.ac_if;
519 if_initname(ifp, "lge", unit);
520 ifp->if_mtu = ETHERMTU;
521 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
522 ifp->if_ioctl = lge_ioctl;
523 ifp->if_start = lge_start;
524 ifp->if_watchdog = lge_watchdog;
525 ifp->if_init = lge_init;
526 ifp->if_baudrate = 1000000000;
527 ifq_set_maxlen(&ifp->if_snd, LGE_TX_LIST_CNT - 1);
528 ifq_set_ready(&ifp->if_snd);
529 ifp->if_capabilities = IFCAP_RXCSUM;
530 ifp->if_capenable = ifp->if_capabilities;
532 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)
540 if (mii_phy_probe(dev, &sc->lge_miibus,
541 lge_ifmedia_upd, lge_ifmedia_sts)) {
542 kprintf("lge%d: MII without any PHY!\n", sc->lge_unit);
548 * Call MI attach routine.
550 ether_ifattach(ifp, eaddr, NULL);
552 error = bus_setup_intr(dev, sc->lge_irq, INTR_MPSAFE,
553 lge_intr, sc, &sc->lge_intrhand,
557 kprintf("lge%d: couldn't set up irq\n", unit);
561 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->lge_irq));
562 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
572 lge_detach(device_t dev)
574 struct lge_softc *sc= device_get_softc(dev);
575 struct ifnet *ifp = &sc->arpcom.ac_if;
577 if (device_is_attached(dev)) {
578 lwkt_serialize_enter(ifp->if_serializer);
581 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
582 lwkt_serialize_exit(ifp->if_serializer);
588 device_delete_child(dev, sc->lge_miibus);
589 bus_generic_detach(dev);
592 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
594 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
597 contigfree(sc->lge_ldata, sizeof(struct lge_list_data),
599 lge_free_jumbo_mem(sc);
605 * Initialize the transmit descriptors.
608 lge_list_tx_init(struct lge_softc *sc)
610 struct lge_list_data *ld;
611 struct lge_ring_data *cd;
616 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
617 ld->lge_tx_list[i].lge_mbuf = NULL;
618 ld->lge_tx_list[i].lge_ctl = 0;
621 cd->lge_tx_prod = cd->lge_tx_cons = 0;
628 * Initialize the RX descriptors and allocate mbufs for them. Note that
629 * we arralge the descriptors in a closed ring, so that the last descriptor
630 * points back to the first.
633 lge_list_rx_init(struct lge_softc *sc)
635 struct lge_list_data *ld;
636 struct lge_ring_data *cd;
642 cd->lge_rx_prod = cd->lge_rx_cons = 0;
644 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
646 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
647 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
649 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS)
653 /* Clear possible 'rx command queue empty' interrupt. */
654 CSR_READ_4(sc, LGE_ISR);
660 * Initialize an RX descriptor and attach an MBUF cluster.
663 lge_newbuf(struct lge_softc *sc, struct lge_rx_desc *c, struct mbuf *m)
665 struct mbuf *m_new = NULL;
666 struct lge_jslot *buf;
669 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
671 kprintf("lge%d: no memory for rx list "
672 "-- packet dropped!\n", sc->lge_unit);
676 /* Allocate the jumbo buffer */
677 buf = lge_jalloc(sc);
680 kprintf("lge%d: jumbo allocation failed "
681 "-- packet dropped!\n", sc->lge_unit);
686 /* Attach the buffer to the mbuf */
687 m_new->m_ext.ext_arg = buf;
688 m_new->m_ext.ext_buf = buf->lge_buf;
689 m_new->m_ext.ext_free = lge_jfree;
690 m_new->m_ext.ext_ref = lge_jref;
691 m_new->m_ext.ext_size = LGE_JUMBO_FRAMELEN;
693 m_new->m_data = m_new->m_ext.ext_buf;
694 m_new->m_flags |= M_EXT;
695 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
698 m_new->m_len = m_new->m_pkthdr.len = LGE_JLEN;
699 m_new->m_data = m_new->m_ext.ext_buf;
703 * Adjust alignment so packet payload begins on a
704 * longword boundary. Mandatory for Alpha, useful on
707 m_adj(m_new, ETHER_ALIGN);
710 c->lge_fragptr_hi = 0;
711 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t));
712 c->lge_fraglen = m_new->m_len;
713 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1);
717 * Put this buffer in the RX command FIFO. To do this,
718 * we just write the physical address of the descriptor
719 * into the RX descriptor address registers. Note that
720 * there are two registers, one high DWORD and one low
721 * DWORD, which lets us specify a 64-bit address if
722 * desired. We only use a 32-bit address for now.
723 * Writing to the low DWORD register is what actually
724 * causes the command to be issued, so we do that
727 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c));
728 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT);
734 lge_alloc_jumbo_mem(struct lge_softc *sc)
736 struct lge_jslot *entry;
740 /* Grab a big chunk o' storage. */
741 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF,
742 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
744 if (sc->lge_cdata.lge_jumbo_buf == NULL) {
745 kprintf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit);
749 SLIST_INIT(&sc->lge_jfree_listhead);
752 * Now divide it up into 9K pieces and save the addresses
755 ptr = sc->lge_cdata.lge_jumbo_buf;
756 for (i = 0; i < LGE_JSLOTS; i++) {
757 entry = &sc->lge_cdata.lge_jslots[i];
759 entry->lge_buf = ptr;
760 entry->lge_inuse = 0;
762 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jslot_link);
770 lge_free_jumbo_mem(struct lge_softc *sc)
772 if (sc->lge_cdata.lge_jumbo_buf)
773 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF);
777 * Allocate a jumbo buffer.
779 static struct lge_jslot *
780 lge_jalloc(struct lge_softc *sc)
782 struct lge_jslot *entry;
784 lwkt_serialize_enter(&sc->lge_jslot_serializer);
785 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
787 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jslot_link);
788 entry->lge_inuse = 1;
791 kprintf("lge%d: no free jumbo buffers\n", sc->lge_unit);
794 lwkt_serialize_exit(&sc->lge_jslot_serializer);
799 * Adjust usage count on a jumbo buffer. In general this doesn't
800 * get used much because our jumbo buffers don't get passed around
801 * a lot, but it's implemented for correctness.
806 struct lge_jslot *entry = (struct lge_jslot *)arg;
807 struct lge_softc *sc = entry->lge_sc;
809 if (&sc->lge_cdata.lge_jslots[entry->lge_slot] != entry)
810 panic("lge_jref: asked to reference buffer "
811 "that we don't manage!");
812 else if (entry->lge_inuse == 0)
813 panic("lge_jref: buffer already free!");
815 atomic_add_int(&entry->lge_inuse, 1);
819 * Release a jumbo buffer.
824 struct lge_jslot *entry = (struct lge_jslot *)arg;
825 struct lge_softc *sc = entry->lge_sc;
828 panic("lge_jfree: can't find softc pointer!");
830 if (&sc->lge_cdata.lge_jslots[entry->lge_slot] != entry) {
831 panic("lge_jfree: asked to free buffer that we don't manage!");
832 } else if (entry->lge_inuse == 0) {
833 panic("lge_jfree: buffer already free!");
835 lwkt_serialize_enter(&sc->lge_jslot_serializer);
836 atomic_subtract_int(&entry->lge_inuse, 1);
837 if (entry->lge_inuse == 0) {
838 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
841 lwkt_serialize_exit(&sc->lge_jslot_serializer);
846 * A frame has been uploaded: pass the resulting mbuf chain up to
847 * the higher level protocols.
850 lge_rxeof(struct lge_softc *sc, int cnt)
852 struct ifnet *ifp = &sc->arpcom.ac_if;
854 struct lge_rx_desc *cur_rx;
855 int c, i, total_len = 0;
856 uint32_t rxsts, rxctl;
859 /* Find out how many frames were processed. */
861 i = sc->lge_cdata.lge_rx_cons;
865 struct mbuf *m0 = NULL;
867 cur_rx = &sc->lge_ldata->lge_rx_list[i];
868 rxctl = cur_rx->lge_ctl;
869 rxsts = cur_rx->lge_sts;
870 m = cur_rx->lge_mbuf;
871 cur_rx->lge_mbuf = NULL;
872 total_len = LGE_RXBYTES(cur_rx);
873 LGE_INC(i, LGE_RX_LIST_CNT);
877 * If an error occurs, update stats, clear the
878 * status word and leave the mbuf cluster in place:
879 * it should simply get re-used next time this descriptor
880 * comes up in the ring.
882 if (rxctl & LGE_RXCTL_ERRMASK) {
884 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
888 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) {
889 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
890 total_len + ETHER_ALIGN, 0, ifp, NULL);
891 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
893 kprintf("lge%d: no receive buffers "
894 "available -- packet dropped!\n",
899 m_adj(m0, ETHER_ALIGN);
902 m->m_pkthdr.rcvif = ifp;
903 m->m_pkthdr.len = m->m_len = total_len;
908 /* Do IP checksum checking. */
909 if (rxsts & LGE_RXSTS_ISIP)
910 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
911 if (!(rxsts & LGE_RXSTS_IPCSUMERR))
912 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
913 if ((rxsts & LGE_RXSTS_ISTCP &&
914 !(rxsts & LGE_RXSTS_TCPCSUMERR)) ||
915 (rxsts & LGE_RXSTS_ISUDP &&
916 !(rxsts & LGE_RXSTS_UDPCSUMERR))) {
917 m->m_pkthdr.csum_flags |=
918 CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
919 CSUM_FRAG_NOT_CHECKED;
920 m->m_pkthdr.csum_data = 0xffff;
923 ifp->if_input(ifp, m);
926 sc->lge_cdata.lge_rx_cons = i;
930 lge_rxeoc(struct lge_softc *sc)
932 struct ifnet *ifp = &sc->arpcom.ac_if;
934 ifp->if_flags &= ~IFF_RUNNING;
939 * A frame was downloaded to the chip. It's safe for us to clean up
943 lge_txeof(struct lge_softc *sc)
945 struct ifnet *ifp = &sc->arpcom.ac_if;
946 struct lge_tx_desc *cur_tx = NULL;
947 uint32_t idx, txdone;
949 /* Clear the timeout timer. */
953 * Go through our tx list and free mbufs for those
954 * frames that have been transmitted.
956 idx = sc->lge_cdata.lge_tx_cons;
957 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
959 while (idx != sc->lge_cdata.lge_tx_prod && txdone) {
960 cur_tx = &sc->lge_ldata->lge_tx_list[idx];
963 if (cur_tx->lge_mbuf != NULL) {
964 m_freem(cur_tx->lge_mbuf);
965 cur_tx->lge_mbuf = NULL;
970 LGE_INC(idx, LGE_TX_LIST_CNT);
974 sc->lge_cdata.lge_tx_cons = idx;
977 ifp->if_flags &= ~IFF_OACTIVE;
983 struct lge_softc *sc = xsc;
984 struct ifnet *ifp = &sc->arpcom.ac_if;
986 lwkt_serialize_enter(ifp->if_serializer);
987 lge_tick_serialized(xsc);
988 lwkt_serialize_exit(ifp->if_serializer);
992 lge_tick_serialized(void *xsc)
994 struct lge_softc *sc = xsc;
995 struct mii_data *mii;
996 struct ifnet *ifp = &sc->arpcom.ac_if;
998 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS);
999 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1000 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS);
1001 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1003 if (!sc->lge_link) {
1004 mii = device_get_softc(sc->lge_miibus);
1007 if (mii->mii_media_status & IFM_ACTIVE &&
1008 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1010 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX||
1011 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
1012 kprintf("lge%d: gigabit link up\n",
1014 if (!ifq_is_empty(&ifp->if_snd))
1019 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc);
1025 struct lge_softc *sc = arg;
1026 struct ifnet *ifp = &sc->arpcom.ac_if;
1029 /* Supress unwanted interrupts */
1030 if ((ifp->if_flags & IFF_UP) == 0) {
1037 * Reading the ISR register clears all interrupts, and
1038 * clears the 'interrupts enabled' bit in the IMR
1041 status = CSR_READ_4(sc, LGE_ISR);
1043 if ((status & LGE_INTRS) == 0)
1046 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE)))
1049 if (status & LGE_ISR_RXDMA_DONE)
1050 lge_rxeof(sc, LGE_RX_DMACNT(status));
1052 if (status & LGE_ISR_RXCMDFIFO_EMPTY)
1055 if (status & LGE_ISR_PHY_INTR) {
1057 callout_stop(&sc->lge_stat_timer);
1058 lge_tick_serialized(sc);
1062 /* Re-enable interrupts. */
1063 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB);
1065 if (!ifq_is_empty(&ifp->if_snd))
1070 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1071 * pointers to the fragment pointers.
1074 lge_encap(struct lge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1076 struct lge_frag *f = NULL;
1077 struct lge_tx_desc *cur_tx;
1079 int frag = 0, tot_len = 0;
1082 * Start packing the mbufs in this chain into
1083 * the fragment pointers. Stop when we run out
1084 * of fragments or hit the end of the mbuf chain.
1087 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx];
1090 for (m = m_head; m != NULL; m = m->m_next) {
1091 if (m->m_len != 0) {
1092 if (frag == LGE_FRAG_CNT)
1095 tot_len += m->m_len;
1096 f = &cur_tx->lge_frags[frag];
1097 f->lge_fraglen = m->m_len;
1098 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t));
1099 f->lge_fragptr_hi = 0;
1103 /* Caller should make sure that 'm_head' is not excessive fragmented */
1104 KASSERT(m == NULL, ("too many fragments\n"));
1106 cur_tx->lge_mbuf = m_head;
1107 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len;
1108 LGE_INC((*txidx), LGE_TX_LIST_CNT);
1110 /* Queue for transmit */
1111 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx));
1117 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1118 * to the mbuf data regions directly in the transmit lists. We also save a
1119 * copy of the pointers since the transmit list fragment pointers are
1120 * physical addresses.
1124 lge_start(struct ifnet *ifp)
1126 struct lge_softc *sc = ifp->if_softc;
1127 struct mbuf *m_head = NULL, *m_defragged;
1131 if (!sc->lge_link) {
1132 ifq_purge(&ifp->if_snd);
1136 idx = sc->lge_cdata.lge_tx_prod;
1138 if (ifp->if_flags & IFF_OACTIVE)
1142 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) {
1146 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) {
1147 ifp->if_flags |= IFF_OACTIVE;
1152 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1158 for (m = m_head; m != NULL; m = m->m_next)
1160 if (frags > LGE_FRAG_CNT) {
1161 if (m_defragged != NULL) {
1163 * Even after defragmentation, there
1164 * are still too many fragments, so
1171 m_defragged = m_defrag(m_head, MB_DONTWAIT);
1172 if (m_defragged == NULL) {
1176 m_head = m_defragged;
1178 /* Recount # of fragments */
1182 lge_encap(sc, m_head, &idx);
1185 BPF_MTAP(ifp, m_head);
1191 sc->lge_cdata.lge_tx_prod = idx;
1194 * Set a timeout in case the chip goes out to lunch.
1202 struct lge_softc *sc = xsc;
1203 struct ifnet *ifp = &sc->arpcom.ac_if;
1204 struct mii_data *mii;
1206 if (ifp->if_flags & IFF_RUNNING)
1210 * Cancel pending I/O and free all RX/TX buffers.
1215 mii = device_get_softc(sc->lge_miibus);
1217 /* Set MAC address */
1218 CSR_WRITE_4(sc, LGE_PAR0, *(uint32_t *)(&sc->arpcom.ac_enaddr[0]));
1219 CSR_WRITE_4(sc, LGE_PAR1, *(uint32_t *)(&sc->arpcom.ac_enaddr[4]));
1221 /* Init circular RX list. */
1222 if (lge_list_rx_init(sc) == ENOBUFS) {
1223 kprintf("lge%d: initialization failed: no "
1224 "memory for rx buffers\n", sc->lge_unit);
1230 * Init tx descriptors.
1232 lge_list_tx_init(sc);
1234 /* Set initial value for MODE1 register. */
1235 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST |
1236 LGE_MODE1_TX_CRC | LGE_MODE1_TXPAD |
1237 LGE_MODE1_RX_FLOWCTL | LGE_MODE1_SETRST_CTL0 |
1238 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_SETRST_CTL2);
1240 /* If we want promiscuous mode, set the allframes bit. */
1241 if (ifp->if_flags & IFF_PROMISC) {
1242 CSR_WRITE_4(sc, LGE_MODE1,
1243 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_PROMISC);
1245 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC);
1249 * Set the capture broadcast bit to capture broadcast frames.
1251 if (ifp->if_flags & IFF_BROADCAST) {
1252 CSR_WRITE_4(sc, LGE_MODE1,
1253 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_BCAST);
1255 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST);
1258 /* Packet padding workaround? */
1259 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD);
1261 /* No error frames */
1262 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS);
1264 /* Receive large frames */
1265 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_GIANTS);
1267 /* Workaround: disable RX/TX flow control */
1268 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL);
1269 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL);
1271 /* Make sure to strip CRC from received frames */
1272 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC);
1274 /* Turn off magic packet mode */
1275 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB);
1277 /* Turn off all VLAN stuff */
1278 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX | LGE_MODE1_VLAN_TX |
1279 LGE_MODE1_VLAN_STRIP | LGE_MODE1_VLAN_INSERT);
1281 /* Workarond: FIFO overflow */
1282 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
1283 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);
1286 * Load the multicast filter.
1291 * Enable hardware checksum validation for all received IPv4
1292 * packets, do not reject packets with bad checksums.
1294 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM |
1295 LGE_MODE2_RX_TCPCSUM | LGE_MODE2_RX_UDPCSUM |
1296 LGE_MODE2_RX_ERRCSUM);
1299 * Enable the delivery of PHY interrupts based on
1300 * link/speed/duplex status chalges.
1302 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0 | LGE_MODE1_GMIIPOLL);
1304 /* Enable receiver and transmitter. */
1305 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
1306 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_ENB);
1308 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0);
1309 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_TX_ENB);
1312 * Enable interrupts.
1314 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0 |
1315 LGE_IMR_SETRST_CTL1 | LGE_IMR_INTR_ENB|LGE_INTRS);
1317 lge_ifmedia_upd(ifp);
1319 ifp->if_flags |= IFF_RUNNING;
1320 ifp->if_flags &= ~IFF_OACTIVE;
1322 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc);
1326 * Set media options.
1329 lge_ifmedia_upd(struct ifnet *ifp)
1331 struct lge_softc *sc = ifp->if_softc;
1332 struct mii_data *mii = device_get_softc(sc->lge_miibus);
1335 if (mii->mii_instance) {
1336 struct mii_softc *miisc;
1337 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1338 mii_phy_reset(miisc);
1346 * Report current media status.
1349 lge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1351 struct lge_softc *sc = ifp->if_softc;
1352 struct mii_data *mii;
1354 mii = device_get_softc(sc->lge_miibus);
1356 ifmr->ifm_active = mii->mii_media_active;
1357 ifmr->ifm_status = mii->mii_media_status;
1361 lge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1363 struct lge_softc *sc = ifp->if_softc;
1364 struct ifreq *ifr = (struct ifreq *) data;
1365 struct mii_data *mii;
1370 if (ifr->ifr_mtu > LGE_JUMBO_MTU)
1373 ifp->if_mtu = ifr->ifr_mtu;
1376 if (ifp->if_flags & IFF_UP) {
1377 if (ifp->if_flags & IFF_RUNNING &&
1378 ifp->if_flags & IFF_PROMISC &&
1379 !(sc->lge_if_flags & IFF_PROMISC)) {
1380 CSR_WRITE_4(sc, LGE_MODE1,
1381 LGE_MODE1_SETRST_CTL1|
1382 LGE_MODE1_RX_PROMISC);
1383 } else if (ifp->if_flags & IFF_RUNNING &&
1384 !(ifp->if_flags & IFF_PROMISC) &&
1385 sc->lge_if_flags & IFF_PROMISC) {
1386 CSR_WRITE_4(sc, LGE_MODE1,
1387 LGE_MODE1_RX_PROMISC);
1389 ifp->if_flags &= ~IFF_RUNNING;
1393 if (ifp->if_flags & IFF_RUNNING)
1396 sc->lge_if_flags = ifp->if_flags;
1406 mii = device_get_softc(sc->lge_miibus);
1407 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1410 error = ether_ioctl(ifp, command, data);
1418 lge_watchdog(struct ifnet *ifp)
1420 struct lge_softc *sc = ifp->if_softc;
1423 kprintf("lge%d: watchdog timeout\n", sc->lge_unit);
1427 ifp->if_flags &= ~IFF_RUNNING;
1430 if (!ifq_is_empty(&ifp->if_snd))
1435 * Stop the adapter and free any mbufs allocated to the
1439 lge_stop(struct lge_softc *sc)
1441 struct ifnet *ifp = &sc->arpcom.ac_if;
1445 callout_stop(&sc->lge_stat_timer);
1446 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB);
1448 /* Disable receiver and transmitter. */
1449 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);
1453 * Free data in the RX lists.
1455 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
1456 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) {
1457 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf);
1458 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL;
1461 bzero(&sc->lge_ldata->lge_rx_list, sizeof(sc->lge_ldata->lge_rx_list));
1464 * Free the TX list buffers.
1466 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
1467 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) {
1468 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf);
1469 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL;
1473 bzero(&sc->lge_ldata->lge_tx_list, sizeof(sc->lge_ldata->lge_tx_list));
1475 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1479 * Stop all chip I/O so that the kernel's probe routines don't
1480 * get confused by errant DMAs when rebooting.
1483 lge_shutdown(device_t dev)
1485 struct lge_softc *sc = device_get_softc(dev);