sys/dev/netif/bge/if_bge.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  */
  35
  36 /*
  37  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  38  *
  39  * Written by Bill Paul <wpaul@windriver.com>
  40  * Senior Engineer, Wind River Systems
  41  */
  42
  43 /*
  44  * The Broadcom BCM5700 is based on technology originally developed by
  45  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  46  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  47  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  48  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  49  * frames, highly configurable RX filtering, and 16 RX and TX queues
  50  * (which, along with RX filter rules, can be used for QOS applications).
  51  * Other features, such as TCP segmentation, may be available as part
  52  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  53  * firmware images can be stored in hardware and need not be compiled
  54  * into the driver.
  55  *
  56  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  57  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  58  *
  59  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  60  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  61  * does not support external SSRAM.
  62  *
  63  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  64  * brand name, which is functionally similar but lacks PCI-X support.
  65  *
  66  * Without external SSRAM, you can only have at most 4 TX rings,
  67  * and the use of the mini RX ring is disabled. This seems to imply
  68  * that these features are simply not available on the BCM5701. As a
  69  * result, this driver does not implement any support for the mini RX
  70  * ring.
  71  */
  72
  73 #include "opt_polling.h"
  74
  75 #include <sys/param.h>
  76 #include <sys/bus.h>
  77 #include <sys/endian.h>
  78 #include <sys/kernel.h>
  79 #include <sys/ktr.h>
  80 #include <sys/interrupt.h>
  81 #include <sys/mbuf.h>
  82 #include <sys/malloc.h>
  83 #include <sys/queue.h>
  84 #include <sys/rman.h>
  85 #include <sys/serialize.h>
  86 #include <sys/socket.h>
  87 #include <sys/sockio.h>
  88 #include <sys/sysctl.h>
  89
  90 #include <net/bpf.h>
  91 #include <net/ethernet.h>
  92 #include <net/if.h>
  93 #include <net/if_arp.h>
  94 #include <net/if_dl.h>
  95 #include <net/if_media.h>
  96 #include <net/if_types.h>
  97 #include <net/ifq_var.h>
  98 #include <net/vlan/if_vlan_var.h>
  99 #include <net/vlan/if_vlan_ether.h>
 100
 101 #include <dev/netif/mii_layer/mii.h>
 102 #include <dev/netif/mii_layer/miivar.h>
 103 #include <dev/netif/mii_layer/brgphyreg.h>
 104
 105 #include <bus/pci/pcidevs.h>
 106 #include <bus/pci/pcireg.h>
 107 #include <bus/pci/pcivar.h>
 108
 109 #include <dev/netif/bge/if_bgereg.h>
 110
 111 /* "device miibus" required.  See GENERIC if you get errors here. */
 112 #include "miibus_if.h"
 113
 114 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP)
 115 #define BGE_MIN_FRAME           60
 116
 117 static const struct bge_type bge_devs[] = {
 118         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
 119                 "3COM 3C996 Gigabit Ethernet" },
 120
 121         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 122                 "Alteon BCM5700 Gigabit Ethernet" },
 123         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
 124                 "Alteon BCM5701 Gigabit Ethernet" },
 125
 126         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
 127                 "Altima AC1000 Gigabit Ethernet" },
 128         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
 129                 "Altima AC1002 Gigabit Ethernet" },
 130         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
 131                 "Altima AC9100 Gigabit Ethernet" },
 132
 133         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
 134                 "Apple BCM5701 Gigabit Ethernet" },
 135
 136         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
 137                 "Broadcom BCM5700 Gigabit Ethernet" },
 138         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
 139                 "Broadcom BCM5701 Gigabit Ethernet" },
 140         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
 141                 "Broadcom BCM5702 Gigabit Ethernet" },
 142         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
 143                 "Broadcom BCM5702X Gigabit Ethernet" },
 144         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
 145                 "Broadcom BCM5702 Gigabit Ethernet" },
 146         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
 147                 "Broadcom BCM5703 Gigabit Ethernet" },
 148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
 149                 "Broadcom BCM5703X Gigabit Ethernet" },
 150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
 151                 "Broadcom BCM5703 Gigabit Ethernet" },
 152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
 153                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
 154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
 155                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
 157                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
 159                 "Broadcom BCM5705 Gigabit Ethernet" },
 160         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
 161                 "Broadcom BCM5705F Gigabit Ethernet" },
 162         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
 163                 "Broadcom BCM5705K Gigabit Ethernet" },
 164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
 165                 "Broadcom BCM5705M Gigabit Ethernet" },
 166         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
 167                 "Broadcom BCM5705M Gigabit Ethernet" },
 168         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
 169                 "Broadcom BCM5714C Gigabit Ethernet" },
 170         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
 171                 "Broadcom BCM5714S Gigabit Ethernet" },
 172         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
 173                 "Broadcom BCM5715 Gigabit Ethernet" },
 174         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
 175                 "Broadcom BCM5715S Gigabit Ethernet" },
 176         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
 177                 "Broadcom BCM5720 Gigabit Ethernet" },
 178         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
 179                 "Broadcom BCM5721 Gigabit Ethernet" },
 180         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
 181                 "Broadcom BCM5722 Gigabit Ethernet" },
 182         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723,
 183                 "Broadcom BCM5723 Gigabit Ethernet" },
 184         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
 185                 "Broadcom BCM5750 Gigabit Ethernet" },
 186         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
 187                 "Broadcom BCM5750M Gigabit Ethernet" },
 188         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
 189                 "Broadcom BCM5751 Gigabit Ethernet" },
 190         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
 191                 "Broadcom BCM5751F Gigabit Ethernet" },
 192         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
 193                 "Broadcom BCM5751M Gigabit Ethernet" },
 194         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
 195                 "Broadcom BCM5752 Gigabit Ethernet" },
 196         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
 197                 "Broadcom BCM5752M Gigabit Ethernet" },
 198         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
 199                 "Broadcom BCM5753 Gigabit Ethernet" },
 200         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
 201                 "Broadcom BCM5753F Gigabit Ethernet" },
 202         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
 203                 "Broadcom BCM5753M Gigabit Ethernet" },
 204         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
 205                 "Broadcom BCM5754 Gigabit Ethernet" },
 206         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
 207                 "Broadcom BCM5754M Gigabit Ethernet" },
 208         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
 209                 "Broadcom BCM5755 Gigabit Ethernet" },
 210         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
 211                 "Broadcom BCM5755M Gigabit Ethernet" },
 212         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
 213                 "Broadcom BCM5756 Gigabit Ethernet" },
 214         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761,
 215                 "Broadcom BCM5761 Gigabit Ethernet" },
 216         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E,
 217                 "Broadcom BCM5761E Gigabit Ethernet" },
 218         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S,
 219                 "Broadcom BCM5761S Gigabit Ethernet" },
 220         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE,
 221                 "Broadcom BCM5761SE Gigabit Ethernet" },
 222         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764,
 223                 "Broadcom BCM5764 Gigabit Ethernet" },
 224         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
 225                 "Broadcom BCM5780 Gigabit Ethernet" },
 226         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
 227                 "Broadcom BCM5780S Gigabit Ethernet" },
 228         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
 229                 "Broadcom BCM5781 Gigabit Ethernet" },
 230         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
 231                 "Broadcom BCM5782 Gigabit Ethernet" },
 232         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784,
 233                 "Broadcom BCM5784 Gigabit Ethernet" },
 234         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F,
 235                 "Broadcom BCM5785F Gigabit Ethernet" },
 236         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G,
 237                 "Broadcom BCM5785G Gigabit Ethernet" },
 238         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
 239                 "Broadcom BCM5786 Gigabit Ethernet" },
 240         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
 241                 "Broadcom BCM5787 Gigabit Ethernet" },
 242         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
 243                 "Broadcom BCM5787F Gigabit Ethernet" },
 244         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
 245                 "Broadcom BCM5787M Gigabit Ethernet" },
 246         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
 247                 "Broadcom BCM5788 Gigabit Ethernet" },
 248         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
 249                 "Broadcom BCM5789 Gigabit Ethernet" },
 250         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
 251                 "Broadcom BCM5901 Fast Ethernet" },
 252         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
 253                 "Broadcom BCM5901A2 Fast Ethernet" },
 254         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
 255                 "Broadcom BCM5903M Fast Ethernet" },
 256         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
 257                 "Broadcom BCM5906 Fast Ethernet"},
 258         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
 259                 "Broadcom BCM5906M Fast Ethernet"},
 260         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760,
 261                 "Broadcom BCM57760 Gigabit Ethernet"},
 262         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780,
 263                 "Broadcom BCM57780 Gigabit Ethernet"},
 264         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788,
 265                 "Broadcom BCM57788 Gigabit Ethernet"},
 266         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790,
 267                 "Broadcom BCM57790 Gigabit Ethernet"},
 268         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
 269                 "SysKonnect Gigabit Ethernet" },
 270
 271         { 0, 0, NULL }
 272 };
 273
 274 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 275 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 276 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 277 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 278 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 279 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
 280 #define BGE_IS_5788(sc)                 ((sc)->bge_flags & BGE_FLAG_5788)
 281
 282 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 283
 284 static int      bge_probe(device_t);
 285 static int      bge_attach(device_t);
 286 static int      bge_detach(device_t);
 287 static void     bge_txeof(struct bge_softc *);
 288 static void     bge_rxeof(struct bge_softc *);
 289
 290 static void     bge_tick(void *);
 291 static void     bge_stats_update(struct bge_softc *);
 292 static void     bge_stats_update_regs(struct bge_softc *);
 293 static struct mbuf *
 294                 bge_defrag_shortdma(struct mbuf *);
 295 static int      bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 296
 297 #ifdef DEVICE_POLLING
 298 static void     bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 299 #endif
 300 static void     bge_intr(void *);
 301 static void     bge_enable_intr(struct bge_softc *);
 302 static void     bge_disable_intr(struct bge_softc *);
 303 static void     bge_start(struct ifnet *);
 304 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 305 static void     bge_init(void *);
 306 static void     bge_stop(struct bge_softc *);
 307 static void     bge_watchdog(struct ifnet *);
 308 static void     bge_shutdown(device_t);
 309 static int      bge_suspend(device_t);
 310 static int      bge_resume(device_t);
 311 static int      bge_ifmedia_upd(struct ifnet *);
 312 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 313
 314 static uint8_t  bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 315 static int      bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 316
 317 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
 318 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
 319
 320 static void     bge_setmulti(struct bge_softc *);
 321 static void     bge_setpromisc(struct bge_softc *);
 322
 323 static int      bge_alloc_jumbo_mem(struct bge_softc *);
 324 static void     bge_free_jumbo_mem(struct bge_softc *);
 325 static struct bge_jslot
 326                 *bge_jalloc(struct bge_softc *);
 327 static void     bge_jfree(void *);
 328 static void     bge_jref(void *);
 329 static int      bge_newbuf_std(struct bge_softc *, int, int);
 330 static int      bge_newbuf_jumbo(struct bge_softc *, int, int);
 331 static void     bge_setup_rxdesc_std(struct bge_softc *, int);
 332 static void     bge_setup_rxdesc_jumbo(struct bge_softc *, int);
 333 static int      bge_init_rx_ring_std(struct bge_softc *);
 334 static void     bge_free_rx_ring_std(struct bge_softc *);
 335 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
 336 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
 337 static void     bge_free_tx_ring(struct bge_softc *);
 338 static int      bge_init_tx_ring(struct bge_softc *);
 339
 340 static int      bge_chipinit(struct bge_softc *);
 341 static int      bge_blockinit(struct bge_softc *);
 342 static void     bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
 343
 344 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
 345 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
 346 #ifdef notdef
 347 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
 348 #endif
 349 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
 350 static void     bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
 351 static void     bge_writembx(struct bge_softc *, int, int);
 352
 353 static int      bge_miibus_readreg(device_t, int, int);
 354 static int      bge_miibus_writereg(device_t, int, int, int);
 355 static void     bge_miibus_statchg(device_t);
 356 static void     bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
 357 static void     bge_tbi_link_upd(struct bge_softc *, uint32_t);
 358 static void     bge_copper_link_upd(struct bge_softc *, uint32_t);
 359 static void     bge_autopoll_link_upd(struct bge_softc *, uint32_t);
 360
 361 static void     bge_reset(struct bge_softc *);
 362
 363 static int      bge_dma_alloc(struct bge_softc *);
 364 static void     bge_dma_free(struct bge_softc *);
 365 static int      bge_dma_block_alloc(struct bge_softc *, bus_size_t,
 366                                     bus_dma_tag_t *, bus_dmamap_t *,
 367                                     void **, bus_addr_t *);
 368 static void     bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 369
 370 static int      bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 371 static int      bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 372 static int      bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 373 static int      bge_get_eaddr(struct bge_softc *, uint8_t[]);
 374
 375 static void     bge_coal_change(struct bge_softc *);
 376 static int      bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 377 static int      bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 378 static int      bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 379 static int      bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 380 static int      bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
 381
 382 /*
 383  * Set following tunable to 1 for some IBM blade servers with the DNLK
 384  * switch module. Auto negotiation is broken for those configurations.
 385  */
 386 static int      bge_fake_autoneg = 0;
 387 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
 388
 389 /* Interrupt moderation control variables. */
 390 static int      bge_rx_coal_ticks = 100;        /* usec */
 391 static int      bge_tx_coal_ticks = 1023;       /* usec */
 392 static int      bge_rx_max_coal_bds = 80;
 393 static int      bge_tx_max_coal_bds = 128;
 394
 395 TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
 396 TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
 397 TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
 398 TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
 399
 400 #if !defined(KTR_IF_BGE)
 401 #define KTR_IF_BGE      KTR_ALL
 402 #endif
 403 KTR_INFO_MASTER(if_bge);
 404 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr");
 405 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt");
 406 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt");
 407 #define logif(name)     KTR_LOG(if_bge_ ## name)
 408
 409 static device_method_t bge_methods[] = {
 410         /* Device interface */
 411         DEVMETHOD(device_probe,         bge_probe),
 412         DEVMETHOD(device_attach,        bge_attach),
 413         DEVMETHOD(device_detach,        bge_detach),
 414         DEVMETHOD(device_shutdown,      bge_shutdown),
 415         DEVMETHOD(device_suspend,       bge_suspend),
 416         DEVMETHOD(device_resume,        bge_resume),
 417
 418         /* bus interface */
 419         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 420         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 421
 422         /* MII interface */
 423         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 424         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 425         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 426
 427         { 0, 0 }
 428 };
 429
 430 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
 431 static devclass_t bge_devclass;
 432
 433 DECLARE_DUMMY_MODULE(if_bge);
 434 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL);
 435 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL);
 436
 437 static uint32_t
 438 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
 439 {
 440         device_t dev = sc->bge_dev;
 441         uint32_t val;
 442
 443         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 444             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 445                 return 0;
 446
 447         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 448         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 449         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 450         return (val);
 451 }
 452
 453 static void
 454 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 455 {
 456         device_t dev = sc->bge_dev;
 457
 458         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 459             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 460                 return;
 461
 462         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 463         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 464         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 465 }
 466
 467 #ifdef notdef
 468 static uint32_t
 469 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
 470 {
 471         device_t dev = sc->bge_dev;
 472
 473         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 474         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 475 }
 476 #endif
 477
 478 static void
 479 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 480 {
 481         device_t dev = sc->bge_dev;
 482
 483         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 484         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 485 }
 486
 487 static void
 488 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
 489 {
 490         CSR_WRITE_4(sc, off, val);
 491 }
 492
 493 static void
 494 bge_writembx(struct bge_softc *sc, int off, int val)
 495 {
 496         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 497                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 498
 499         CSR_WRITE_4(sc, off, val);
 500         if (sc->bge_mbox_reorder)
 501                 CSR_READ_4(sc, off);
 502 }
 503
 504 static uint8_t
 505 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 506 {
 507         uint32_t access, byte = 0;
 508         int i;
 509
 510         /* Lock. */
 511         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 512         for (i = 0; i < 8000; i++) {
 513                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 514                         break;
 515                 DELAY(20);
 516         }
 517         if (i == 8000)
 518                 return (1);
 519
 520         /* Enable access. */
 521         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 522         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 523
 524         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 525         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 526         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 527                 DELAY(10);
 528                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 529                         DELAY(10);
 530                         break;
 531                 }
 532         }
 533
 534         if (i == BGE_TIMEOUT * 10) {
 535                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
 536                 return (1);
 537         }
 538
 539         /* Get result. */
 540         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 541
 542         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 543
 544         /* Disable access. */
 545         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 546
 547         /* Unlock. */
 548         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 549         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 550
 551         return (0);
 552 }
 553
 554 /*
 555  * Read a sequence of bytes from NVRAM.
 556  */
 557 static int
 558 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 559 {
 560         int err = 0, i;
 561         uint8_t byte = 0;
 562
 563         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 564                 return (1);
 565
 566         for (i = 0; i < cnt; i++) {
 567                 err = bge_nvram_getbyte(sc, off + i, &byte);
 568                 if (err)
 569                         break;
 570                 *(dest + i) = byte;
 571         }
 572
 573         return (err ? 1 : 0);
 574 }
 575
 576 /*
 577  * Read a byte of data stored in the EEPROM at address 'addr.' The
 578  * BCM570x supports both the traditional bitbang interface and an
 579  * auto access interface for reading the EEPROM. We use the auto
 580  * access method.
 581  */
 582 static uint8_t
 583 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
 584 {
 585         int i;
 586         uint32_t byte = 0;
 587
 588         /*
 589          * Enable use of auto EEPROM access so we can avoid
 590          * having to use the bitbang method.
 591          */
 592         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 593
 594         /* Reset the EEPROM, load the clock period. */
 595         CSR_WRITE_4(sc, BGE_EE_ADDR,
 596             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 597         DELAY(20);
 598
 599         /* Issue the read EEPROM command. */
 600         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 601
 602         /* Wait for completion */
 603         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 604                 DELAY(10);
 605                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 606                         break;
 607         }
 608
 609         if (i == BGE_TIMEOUT) {
 610                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 611                 return(1);
 612         }
 613
 614         /* Get result. */
 615         byte = CSR_READ_4(sc, BGE_EE_DATA);
 616
 617         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 618
 619         return(0);
 620 }
 621
 622 /*
 623  * Read a sequence of bytes from the EEPROM.
 624  */
 625 static int
 626 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
 627 {
 628         size_t i;
 629         int err;
 630         uint8_t byte;
 631
 632         for (byte = 0, err = 0, i = 0; i < len; i++) {
 633                 err = bge_eeprom_getbyte(sc, off + i, &byte);
 634                 if (err)
 635                         break;
 636                 *(dest + i) = byte;
 637         }
 638
 639         return(err ? 1 : 0);
 640 }
 641
 642 static int
 643 bge_miibus_readreg(device_t dev, int phy, int reg)
 644 {
 645         struct bge_softc *sc = device_get_softc(dev);
 646         uint32_t val;
 647         int i;
 648
 649         KASSERT(phy == sc->bge_phyno,
 650             ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
 651
 652         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 653         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
 654                 CSR_WRITE_4(sc, BGE_MI_MODE,
 655                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 656                 DELAY(80);
 657         }
 658
 659         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 660             BGE_MIPHY(phy) | BGE_MIREG(reg));
 661
 662         /* Poll for the PHY register access to complete. */
 663         for (i = 0; i < BGE_TIMEOUT; i++) {
 664                 DELAY(10);
 665                 val = CSR_READ_4(sc, BGE_MI_COMM);
 666                 if ((val & BGE_MICOMM_BUSY) == 0) {
 667                         DELAY(5);
 668                         val = CSR_READ_4(sc, BGE_MI_COMM);
 669                         break;
 670                 }
 671         }
 672         if (i == BGE_TIMEOUT) {
 673                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
 674                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
 675                 val = 0;
 676         }
 677
 678         /* Restore the autopoll bit if necessary. */
 679         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
 680                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
 681                 DELAY(80);
 682         }
 683
 684         if (val & BGE_MICOMM_READFAIL)
 685                 return 0;
 686
 687         return (val & 0xFFFF);
 688 }
 689
 690 static int
 691 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 692 {
 693         struct bge_softc *sc = device_get_softc(dev);
 694         int i;
 695
 696         KASSERT(phy == sc->bge_phyno,
 697             ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
 698
 699         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 700             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 701                return 0;
 702
 703         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 704         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
 705                 CSR_WRITE_4(sc, BGE_MI_MODE,
 706                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 707                 DELAY(80);
 708         }
 709
 710         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 711             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 712
 713         for (i = 0; i < BGE_TIMEOUT; i++) {
 714                 DELAY(10);
 715                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 716                         DELAY(5);
 717                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 718                         break;
 719                 }
 720         }
 721         if (i == BGE_TIMEOUT) {
 722                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
 723                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
 724         }
 725
 726         /* Restore the autopoll bit if necessary. */
 727         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
 728                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
 729                 DELAY(80);
 730         }
 731
 732         return 0;
 733 }
 734
 735 static void
 736 bge_miibus_statchg(device_t dev)
 737 {
 738         struct bge_softc *sc;
 739         struct mii_data *mii;
 740
 741         sc = device_get_softc(dev);
 742         mii = device_get_softc(sc->bge_miibus);
 743
 744         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 745             (IFM_ACTIVE | IFM_AVALID)) {
 746                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 747                 case IFM_10_T:
 748                 case IFM_100_TX:
 749                         sc->bge_link = 1;
 750                         break;
 751                 case IFM_1000_T:
 752                 case IFM_1000_SX:
 753                 case IFM_2500_SX:
 754                         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 755                                 sc->bge_link = 1;
 756                         else
 757                                 sc->bge_link = 0;
 758                         break;
 759                 default:
 760                         sc->bge_link = 0;
 761                         break;
 762                 }
 763         } else {
 764                 sc->bge_link = 0;
 765         }
 766         if (sc->bge_link == 0)
 767                 return;
 768
 769         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 770         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 771             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
 772                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 773         } else {
 774                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 775         }
 776
 777         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 778                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 779         } else {
 780                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 781         }
 782 }
 783
 784 /*
 785  * Memory management for jumbo frames.
 786  */
 787 static int
 788 bge_alloc_jumbo_mem(struct bge_softc *sc)
 789 {
 790         struct ifnet *ifp = &sc->arpcom.ac_if;
 791         struct bge_jslot *entry;
 792         uint8_t *ptr;
 793         bus_addr_t paddr;
 794         int i, error;
 795
 796         /*
 797          * Create tag for jumbo mbufs.
 798          * This is really a bit of a kludge. We allocate a special
 799          * jumbo buffer pool which (thanks to the way our DMA
 800          * memory allocation works) will consist of contiguous
 801          * pages. This means that even though a jumbo buffer might
 802          * be larger than a page size, we don't really need to
 803          * map it into more than one DMA segment. However, the
 804          * default mbuf tag will result in multi-segment mappings,
 805          * so we have to create a special jumbo mbuf tag that
 806          * lets us get away with mapping the jumbo buffers as
 807          * a single segment. I think eventually the driver should
 808          * be changed so that it uses ordinary mbufs and cluster
 809          * buffers, i.e. jumbo frames can span multiple DMA
 810          * descriptors. But that's a project for another day.
 811          */
 812
 813         /*
 814          * Create DMA stuffs for jumbo RX ring.
 815          */
 816         error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 817                                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
 818                                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
 819                                     (void *)&sc->bge_ldata.bge_rx_jumbo_ring,
 820                                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
 821         if (error) {
 822                 if_printf(ifp, "could not create jumbo RX ring\n");
 823                 return error;
 824         }
 825
 826         /*
 827          * Create DMA stuffs for jumbo buffer block.
 828          */
 829         error = bge_dma_block_alloc(sc, BGE_JMEM,
 830                                     &sc->bge_cdata.bge_jumbo_tag,
 831                                     &sc->bge_cdata.bge_jumbo_map,
 832                                     (void **)&sc->bge_ldata.bge_jumbo_buf,
 833                                     &paddr);
 834         if (error) {
 835                 if_printf(ifp, "could not create jumbo buffer\n");
 836                 return error;
 837         }
 838
 839         SLIST_INIT(&sc->bge_jfree_listhead);
 840
 841         /*
 842          * Now divide it up into 9K pieces and save the addresses
 843          * in an array. Note that we play an evil trick here by using
 844          * the first few bytes in the buffer to hold the the address
 845          * of the softc structure for this interface. This is because
 846          * bge_jfree() needs it, but it is called by the mbuf management
 847          * code which will not pass it to us explicitly.
 848          */
 849         for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
 850                 entry = &sc->bge_cdata.bge_jslots[i];
 851                 entry->bge_sc = sc;
 852                 entry->bge_buf = ptr;
 853                 entry->bge_paddr = paddr;
 854                 entry->bge_inuse = 0;
 855                 entry->bge_slot = i;
 856                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 857
 858                 ptr += BGE_JLEN;
 859                 paddr += BGE_JLEN;
 860         }
 861         return 0;
 862 }
 863
 864 static void
 865 bge_free_jumbo_mem(struct bge_softc *sc)
 866 {
 867         /* Destroy jumbo RX ring. */
 868         bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 869                            sc->bge_cdata.bge_rx_jumbo_ring_map,
 870                            sc->bge_ldata.bge_rx_jumbo_ring);
 871
 872         /* Destroy jumbo buffer block. */
 873         bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
 874                            sc->bge_cdata.bge_jumbo_map,
 875                            sc->bge_ldata.bge_jumbo_buf);
 876 }
 877
 878 /*
 879  * Allocate a jumbo buffer.
 880  */
 881 static struct bge_jslot *
 882 bge_jalloc(struct bge_softc *sc)
 883 {
 884         struct bge_jslot *entry;
 885
 886         lwkt_serialize_enter(&sc->bge_jslot_serializer);
 887         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
 888         if (entry) {
 889                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
 890                 entry->bge_inuse = 1;
 891         } else {
 892                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 893         }
 894         lwkt_serialize_exit(&sc->bge_jslot_serializer);
 895         return(entry);
 896 }
 897
 898 /*
 899  * Adjust usage count on a jumbo buffer.
 900  */
 901 static void
 902 bge_jref(void *arg)
 903 {
 904         struct bge_jslot *entry = (struct bge_jslot *)arg;
 905         struct bge_softc *sc = entry->bge_sc;
 906
 907         if (sc == NULL)
 908                 panic("bge_jref: can't find softc pointer!");
 909
 910         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 911                 panic("bge_jref: asked to reference buffer "
 912                     "that we don't manage!");
 913         } else if (entry->bge_inuse == 0) {
 914                 panic("bge_jref: buffer already free!");
 915         } else {
 916                 atomic_add_int(&entry->bge_inuse, 1);
 917         }
 918 }
 919
 920 /*
 921  * Release a jumbo buffer.
 922  */
 923 static void
 924 bge_jfree(void *arg)
 925 {
 926         struct bge_jslot *entry = (struct bge_jslot *)arg;
 927         struct bge_softc *sc = entry->bge_sc;
 928
 929         if (sc == NULL)
 930                 panic("bge_jfree: can't find softc pointer!");
 931
 932         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 933                 panic("bge_jfree: asked to free buffer that we don't manage!");
 934         } else if (entry->bge_inuse == 0) {
 935                 panic("bge_jfree: buffer already free!");
 936         } else {
 937                 /*
 938                  * Possible MP race to 0, use the serializer.  The atomic insn
 939                  * is still needed for races against bge_jref().
 940                  */
 941                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
 942                 atomic_subtract_int(&entry->bge_inuse, 1);
 943                 if (entry->bge_inuse == 0) {
 944                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
 945                                           entry, jslot_link);
 946                 }
 947                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
 948         }
 949 }
 950
 951
 952 /*
 953  * Intialize a standard receive ring descriptor.
 954  */
 955 static int
 956 bge_newbuf_std(struct bge_softc *sc, int i, int init)
 957 {
 958         struct mbuf *m_new = NULL;
 959         bus_dma_segment_t seg;
 960         bus_dmamap_t map;
 961         int error, nsegs;
 962
 963         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 964         if (m_new == NULL)
 965                 return ENOBUFS;
 966         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 967
 968         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 969                 m_adj(m_new, ETHER_ALIGN);
 970
 971         error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag,
 972                         sc->bge_cdata.bge_rx_tmpmap, m_new,
 973                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
 974         if (error) {
 975                 m_freem(m_new);
 976                 return error;
 977         }
 978
 979         if (!init) {
 980                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 981                                 sc->bge_cdata.bge_rx_std_dmamap[i],
 982                                 BUS_DMASYNC_POSTREAD);
 983                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
 984                         sc->bge_cdata.bge_rx_std_dmamap[i]);
 985         }
 986
 987         map = sc->bge_cdata.bge_rx_tmpmap;
 988         sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i];
 989         sc->bge_cdata.bge_rx_std_dmamap[i] = map;
 990
 991         sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new;
 992         sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr;
 993
 994         bge_setup_rxdesc_std(sc, i);
 995         return 0;
 996 }
 997
 998 static void
 999 bge_setup_rxdesc_std(struct bge_softc *sc, int i)
1000 {
1001         struct bge_rxchain *rc;
1002         struct bge_rx_bd *r;
1003
1004         rc = &sc->bge_cdata.bge_rx_std_chain[i];
1005         r = &sc->bge_ldata.bge_rx_std_ring[i];
1006
1007         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1008         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1009         r->bge_len = rc->bge_mbuf->m_len;
1010         r->bge_idx = i;
1011         r->bge_flags = BGE_RXBDFLAG_END;
1012 }
1013
1014 /*
1015  * Initialize a jumbo receive ring descriptor. This allocates
1016  * a jumbo buffer from the pool managed internally by the driver.
1017  */
1018 static int
1019 bge_newbuf_jumbo(struct bge_softc *sc, int i, int init)
1020 {
1021         struct mbuf *m_new = NULL;
1022         struct bge_jslot *buf;
1023         bus_addr_t paddr;
1024
1025         /* Allocate the mbuf. */
1026         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1027         if (m_new == NULL)
1028                 return ENOBUFS;
1029
1030         /* Allocate the jumbo buffer */
1031         buf = bge_jalloc(sc);
1032         if (buf == NULL) {
1033                 m_freem(m_new);
1034                 return ENOBUFS;
1035         }
1036
1037         /* Attach the buffer to the mbuf. */
1038         m_new->m_ext.ext_arg = buf;
1039         m_new->m_ext.ext_buf = buf->bge_buf;
1040         m_new->m_ext.ext_free = bge_jfree;
1041         m_new->m_ext.ext_ref = bge_jref;
1042         m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
1043
1044         m_new->m_flags |= M_EXT;
1045
1046         m_new->m_data = m_new->m_ext.ext_buf;
1047         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1048
1049         paddr = buf->bge_paddr;
1050         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
1051                 m_adj(m_new, ETHER_ALIGN);
1052                 paddr += ETHER_ALIGN;
1053         }
1054
1055         /* Save necessary information */
1056         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new;
1057         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr;
1058
1059         /* Set up the descriptor. */
1060         bge_setup_rxdesc_jumbo(sc, i);
1061         return 0;
1062 }
1063
1064 static void
1065 bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i)
1066 {
1067         struct bge_rx_bd *r;
1068         struct bge_rxchain *rc;
1069
1070         r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1071         rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1072
1073         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1074         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1075         r->bge_len = rc->bge_mbuf->m_len;
1076         r->bge_idx = i;
1077         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
1078 }
1079
1080 static int
1081 bge_init_rx_ring_std(struct bge_softc *sc)
1082 {
1083         int i, error;
1084
1085         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1086                 error = bge_newbuf_std(sc, i, 1);
1087                 if (error)
1088                         return error;
1089         };
1090
1091         sc->bge_std = BGE_STD_RX_RING_CNT - 1;
1092         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1093
1094         return(0);
1095 }
1096
1097 static void
1098 bge_free_rx_ring_std(struct bge_softc *sc)
1099 {
1100         int i;
1101
1102         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1103                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i];
1104
1105                 if (rc->bge_mbuf != NULL) {
1106                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1107                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
1108                         m_freem(rc->bge_mbuf);
1109                         rc->bge_mbuf = NULL;
1110                 }
1111                 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
1112                     sizeof(struct bge_rx_bd));
1113         }
1114 }
1115
1116 static int
1117 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1118 {
1119         struct bge_rcb *rcb;
1120         int i, error;
1121
1122         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1123                 error = bge_newbuf_jumbo(sc, i, 1);
1124                 if (error)
1125                         return error;
1126         };
1127
1128         sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
1129
1130         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1131         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1132         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1133
1134         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1135
1136         return(0);
1137 }
1138
1139 static void
1140 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1141 {
1142         int i;
1143
1144         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1145                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1146
1147                 if (rc->bge_mbuf != NULL) {
1148                         m_freem(rc->bge_mbuf);
1149                         rc->bge_mbuf = NULL;
1150                 }
1151                 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1152                     sizeof(struct bge_rx_bd));
1153         }
1154 }
1155
1156 static void
1157 bge_free_tx_ring(struct bge_softc *sc)
1158 {
1159         int i;
1160
1161         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1162                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1163                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1164                                           sc->bge_cdata.bge_tx_dmamap[i]);
1165                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1166                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1167                 }
1168                 bzero(&sc->bge_ldata.bge_tx_ring[i],
1169                     sizeof(struct bge_tx_bd));
1170         }
1171 }
1172
1173 static int
1174 bge_init_tx_ring(struct bge_softc *sc)
1175 {
1176         sc->bge_txcnt = 0;
1177         sc->bge_tx_saved_considx = 0;
1178         sc->bge_tx_prodidx = 0;
1179
1180         /* Initialize transmit producer index for host-memory send ring. */
1181         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1182
1183         /* 5700 b2 errata */
1184         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1185                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1186
1187         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1188         /* 5700 b2 errata */
1189         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1190                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1191
1192         return(0);
1193 }
1194
1195 static void
1196 bge_setmulti(struct bge_softc *sc)
1197 {
1198         struct ifnet *ifp;
1199         struct ifmultiaddr *ifma;
1200         uint32_t hashes[4] = { 0, 0, 0, 0 };
1201         int h, i;
1202
1203         ifp = &sc->arpcom.ac_if;
1204
1205         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1206                 for (i = 0; i < 4; i++)
1207                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1208                 return;
1209         }
1210
1211         /* First, zot all the existing filters. */
1212         for (i = 0; i < 4; i++)
1213                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1214
1215         /* Now program new ones. */
1216         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1217                 if (ifma->ifma_addr->sa_family != AF_LINK)
1218                         continue;
1219                 h = ether_crc32_le(
1220                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1221                     ETHER_ADDR_LEN) & 0x7f;
1222                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1223         }
1224
1225         for (i = 0; i < 4; i++)
1226                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1227 }
1228
1229 /*
1230  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1231  * self-test results.
1232  */
1233 static int
1234 bge_chipinit(struct bge_softc *sc)
1235 {
1236         int i;
1237         uint32_t dma_rw_ctl;
1238         uint16_t val;
1239
1240         /* Set endian type before we access any non-PCI registers. */
1241         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1242
1243         /* Clear the MAC control register */
1244         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1245
1246         /*
1247          * Clear the MAC statistics block in the NIC's
1248          * internal memory.
1249          */
1250         for (i = BGE_STATS_BLOCK;
1251             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1252                 BGE_MEMWIN_WRITE(sc, i, 0);
1253
1254         for (i = BGE_STATUS_BLOCK;
1255             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1256                 BGE_MEMWIN_WRITE(sc, i, 0);
1257
1258         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1259                 /*
1260                  * Fix data corruption caused by non-qword write with WB.
1261                  * Fix master abort in PCI mode.
1262                  * Fix PCI latency timer.
1263                  */
1264                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1265                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1266                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1267         }
1268
1269         /* Set up the PCI DMA control register. */
1270         if (sc->bge_flags & BGE_FLAG_PCIE) {
1271                 /* PCI Express */
1272                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1273                     (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1274                     (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1275         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1276                 /* PCI-X bus */
1277                 if (BGE_IS_5714_FAMILY(sc)) {
1278                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1279                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1280                         /* XXX magic values, Broadcom-supplied Linux driver */
1281                         if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1282                                 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1283                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1284                         } else {
1285                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1286                         }
1287                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1288                         /*
1289                          * In the BCM5703, the DMA read watermark should
1290                          * be set to less than or equal to the maximum
1291                          * memory read byte count of the PCI-X command
1292                          * register.
1293                          */
1294                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1295                             (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1296                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1297                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1298                         /*
1299                          * The 5704 uses a different encoding of read/write
1300                          * watermarks.
1301                          */
1302                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1303                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1304                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1305                 } else {
1306                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1307                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1308                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1309                             (0x0F);
1310                 }
1311
1312                 /*
1313                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1314                  * for hardware bugs.
1315                  */
1316                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1317                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1318                         uint32_t tmp;
1319
1320                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1321                         if (tmp == 0x6 || tmp == 0x7)
1322                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1323                 }
1324         } else {
1325                 /* Conventional PCI bus */
1326                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1327                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1328                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1329                     (0x0F);
1330         }
1331
1332         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1333             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1334             sc->bge_asicrev == BGE_ASICREV_BCM5705)
1335                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1336         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1337
1338         /*
1339          * Set up general mode register.
1340          */
1341         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1342             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1343             BGE_MODECTL_TX_NO_PHDR_CSUM);
1344
1345         /*
1346          * BCM5701 B5 have a bug causing data corruption when using
1347          * 64-bit DMA reads, which can be terminated early and then
1348          * completed later as 32-bit accesses, in combination with
1349          * certain bridges.
1350          */
1351         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1352             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1353                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1354
1355         /*
1356          * Disable memory write invalidate.  Apparently it is not supported
1357          * properly by these devices.
1358          */
1359         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1360
1361         /* Set the timer prescaler (always 66Mhz) */
1362         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1363
1364         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1365                 DELAY(40);      /* XXX */
1366
1367                 /* Put PHY into ready state */
1368                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1369                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1370                 DELAY(40);
1371         }
1372
1373         return(0);
1374 }
1375
1376 static int
1377 bge_blockinit(struct bge_softc *sc)
1378 {
1379         struct bge_rcb *rcb;
1380         bus_size_t vrcb;
1381         bge_hostaddr taddr;
1382         uint32_t val;
1383         int i, limit;
1384
1385         /*
1386          * Initialize the memory window pointer register so that
1387          * we can access the first 32K of internal NIC RAM. This will
1388          * allow us to set up the TX send ring RCBs and the RX return
1389          * ring RCBs, plus other things which live in NIC memory.
1390          */
1391         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1392
1393         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1394
1395         if (!BGE_IS_5705_PLUS(sc)) {
1396                 /* Configure mbuf memory pool */
1397                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1398                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1399                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1400                 else
1401                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1402
1403                 /* Configure DMA resource pool */
1404                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1405                     BGE_DMA_DESCRIPTORS);
1406                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1407         }
1408
1409         /* Configure mbuf pool watermarks */
1410         if (!BGE_IS_5705_PLUS(sc)) {
1411                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1412                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1413                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1414         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1415                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1416                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1417                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1418         } else {
1419                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1420                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1421                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1422         }
1423
1424         /* Configure DMA resource watermarks */
1425         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1426         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1427
1428         /* Enable buffer manager */
1429         CSR_WRITE_4(sc, BGE_BMAN_MODE,
1430             BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1431
1432         /* Poll for buffer manager start indication */
1433         for (i = 0; i < BGE_TIMEOUT; i++) {
1434                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1435                         break;
1436                 DELAY(10);
1437         }
1438
1439         if (i == BGE_TIMEOUT) {
1440                 if_printf(&sc->arpcom.ac_if,
1441                           "buffer manager failed to start\n");
1442                 return(ENXIO);
1443         }
1444
1445         /* Enable flow-through queues */
1446         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1447         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1448
1449         /* Wait until queue initialization is complete */
1450         for (i = 0; i < BGE_TIMEOUT; i++) {
1451                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1452                         break;
1453                 DELAY(10);
1454         }
1455
1456         if (i == BGE_TIMEOUT) {
1457                 if_printf(&sc->arpcom.ac_if,
1458                           "flow-through queue init failed\n");
1459                 return(ENXIO);
1460         }
1461
1462         /*
1463          * Summary of rings supported by the controller:
1464          *
1465          * Standard Receive Producer Ring
1466          * - This ring is used to feed receive buffers for "standard"
1467          *   sized frames (typically 1536 bytes) to the controller.
1468          *
1469          * Jumbo Receive Producer Ring
1470          * - This ring is used to feed receive buffers for jumbo sized
1471          *   frames (i.e. anything bigger than the "standard" frames)
1472          *   to the controller.
1473          *
1474          * Mini Receive Producer Ring
1475          * - This ring is used to feed receive buffers for "mini"
1476          *   sized frames to the controller.
1477          * - This feature required external memory for the controller
1478          *   but was never used in a production system.  Should always
1479          *   be disabled.
1480          *
1481          * Receive Return Ring
1482          * - After the controller has placed an incoming frame into a
1483          *   receive buffer that buffer is moved into a receive return
1484          *   ring.  The driver is then responsible to passing the
1485          *   buffer up to the stack.  Many versions of the controller
1486          *   support multiple RR rings.
1487          *
1488          * Send Ring
1489          * - This ring is used for outgoing frames.  Many versions of
1490          *   the controller support multiple send rings.
1491          */
1492
1493         /* Initialize the standard receive producer ring control block. */
1494         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1495         rcb->bge_hostaddr.bge_addr_lo =
1496             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1497         rcb->bge_hostaddr.bge_addr_hi =
1498             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1499         if (BGE_IS_5705_PLUS(sc)) {
1500                 /*
1501                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1502                  * Bits 15-2 : Reserved (should be 0)
1503                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1504                  * Bit 0     : Reserved
1505                  */
1506                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1507         } else {
1508                 /*
1509                  * Ring size is always XXX entries
1510                  * Bits 31-16: Maximum RX frame size
1511                  * Bits 15-2 : Reserved (should be 0)
1512                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1513                  * Bit 0     : Reserved
1514                  */
1515                 rcb->bge_maxlen_flags =
1516                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1517         }
1518         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1519         /* Write the standard receive producer ring control block. */
1520         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1521         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1522         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1523         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1524         /* Reset the standard receive producer ring producer index. */
1525         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1526
1527         /*
1528          * Initialize the jumbo RX producer ring control
1529          * block.  We set the 'ring disabled' bit in the
1530          * flags field until we're actually ready to start
1531          * using this ring (i.e. once we set the MTU
1532          * high enough to require it).
1533          */
1534         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1535                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1536                 /* Get the jumbo receive producer ring RCB parameters. */
1537                 rcb->bge_hostaddr.bge_addr_lo =
1538                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1539                 rcb->bge_hostaddr.bge_addr_hi =
1540                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1541                 rcb->bge_maxlen_flags =
1542                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1543                     BGE_RCB_FLAG_RING_DISABLED);
1544                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1545                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1546                     rcb->bge_hostaddr.bge_addr_hi);
1547                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1548                     rcb->bge_hostaddr.bge_addr_lo);
1549                 /* Program the jumbo receive producer ring RCB parameters. */
1550                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1551                     rcb->bge_maxlen_flags);
1552                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1553                 /* Reset the jumbo receive producer ring producer index. */
1554                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1555         }
1556
1557         /* Disable the mini receive producer ring RCB. */
1558         if (BGE_IS_5700_FAMILY(sc)) {
1559                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1560                 rcb->bge_maxlen_flags =
1561                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1562                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1563                     rcb->bge_maxlen_flags);
1564                 /* Reset the mini receive producer ring producer index. */
1565                 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1566         }
1567
1568         /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
1569         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1570             (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
1571              sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
1572              sc->bge_chipid == BGE_CHIPID_BCM5906_A2)) {
1573                 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
1574                     (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
1575         }
1576
1577         /*
1578          * The BD ring replenish thresholds control how often the
1579          * hardware fetches new BD's from the producer rings in host
1580          * memory.  Setting the value too low on a busy system can
1581          * starve the hardware and recue the throughpout.
1582          *
1583          * Set the BD ring replentish thresholds. The recommended
1584          * values are 1/8th the number of descriptors allocated to
1585          * each ring.
1586          */
1587         if (BGE_IS_5705_PLUS(sc))
1588                 val = 8;
1589         else
1590                 val = BGE_STD_RX_RING_CNT / 8;
1591         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1592         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1593                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1594                     BGE_JUMBO_RX_RING_CNT/8);
1595         }
1596
1597         /*
1598          * Disable all send rings by setting the 'ring disabled' bit
1599          * in the flags field of all the TX send ring control blocks,
1600          * located in NIC memory.
1601          */
1602         if (!BGE_IS_5705_PLUS(sc)) {
1603                 /* 5700 to 5704 had 16 send rings. */
1604                 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
1605         } else {
1606                 limit = 1;
1607         }
1608         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1609         for (i = 0; i < limit; i++) {
1610                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1611                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1612                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1613                 vrcb += sizeof(struct bge_rcb);
1614         }
1615
1616         /* Configure send ring RCB 0 (we use only the first ring) */
1617         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1618         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1619         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1620         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1621         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1622             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1623         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1624             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1625
1626         /*
1627          * Disable all receive return rings by setting the
1628          * 'ring diabled' bit in the flags field of all the receive
1629          * return ring control blocks, located in NIC memory.
1630          */
1631         if (!BGE_IS_5705_PLUS(sc))
1632                 limit = BGE_RX_RINGS_MAX;
1633         else if (sc->bge_asicrev == BGE_ASICREV_BCM5755)
1634                 limit = 4;
1635         else
1636                 limit = 1;
1637         /* Disable all receive return rings. */
1638         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1639         for (i = 0; i < limit; i++) {
1640                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1641                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1642                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1643                     BGE_RCB_FLAG_RING_DISABLED);
1644                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1645                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1646                     (i * (sizeof(uint64_t))), 0);
1647                 vrcb += sizeof(struct bge_rcb);
1648         }
1649
1650         /*
1651          * Set up receive return ring 0.  Note that the NIC address
1652          * for RX return rings is 0x0.  The return rings live entirely
1653          * within the host, so the nicaddr field in the RCB isn't used.
1654          */
1655         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1656         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1657         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1658         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1659         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1660         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1661             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1662
1663         /* Set random backoff seed for TX */
1664         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1665             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1666             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1667             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1668             BGE_TX_BACKOFF_SEED_MASK);
1669
1670         /* Set inter-packet gap */
1671         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1672
1673         /*
1674          * Specify which ring to use for packets that don't match
1675          * any RX rules.
1676          */
1677         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1678
1679         /*
1680          * Configure number of RX lists. One interrupt distribution
1681          * list, sixteen active lists, one bad frames class.
1682          */
1683         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1684
1685         /* Inialize RX list placement stats mask. */
1686         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1687         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1688
1689         /* Disable host coalescing until we get it set up */
1690         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1691
1692         /* Poll to make sure it's shut down. */
1693         for (i = 0; i < BGE_TIMEOUT; i++) {
1694                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1695                         break;
1696                 DELAY(10);
1697         }
1698
1699         if (i == BGE_TIMEOUT) {
1700                 if_printf(&sc->arpcom.ac_if,
1701                           "host coalescing engine failed to idle\n");
1702                 return(ENXIO);
1703         }
1704
1705         /* Set up host coalescing defaults */
1706         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1707         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1708         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1709         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1710         if (!BGE_IS_5705_PLUS(sc)) {
1711                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1712                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1713         }
1714         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1715         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1716
1717         /* Set up address of statistics block */
1718         if (!BGE_IS_5705_PLUS(sc)) {
1719                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1720                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1721                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1722                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1723
1724                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1725                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1726                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1727         }
1728
1729         /* Set up address of status block */
1730         bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
1731         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1732             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1733         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1734             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1735
1736         /*
1737          * Set up status block partail update size.
1738          *
1739          * Because only single TX ring, RX produce ring and Rx return ring
1740          * are used, ask device to update only minimum part of status block
1741          * except for BCM5700 AX/BX, whose status block partial update size
1742          * can't be configured.
1743          */
1744         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1745             sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
1746                 /* XXX Actually reserved on BCM5700 AX/BX */
1747                 val = BGE_STATBLKSZ_FULL;
1748         } else {
1749                 val = BGE_STATBLKSZ_32BYTE;
1750         }
1751
1752         /* Turn on host coalescing state machine */
1753         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1754
1755         /* Turn on RX BD completion state machine and enable attentions */
1756         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1757             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1758
1759         /* Turn on RX list placement state machine */
1760         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1761
1762         /* Turn on RX list selector state machine. */
1763         if (!BGE_IS_5705_PLUS(sc))
1764                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1765
1766         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1767             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1768             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1769             BGE_MACMODE_FRMHDR_DMA_ENB;
1770
1771         if (sc->bge_flags & BGE_FLAG_TBI)
1772                 val |= BGE_PORTMODE_TBI;
1773         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
1774                 val |= BGE_PORTMODE_GMII;
1775         else
1776                 val |= BGE_PORTMODE_MII;
1777
1778         /* Turn on DMA, clear stats */
1779         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1780
1781         /* Set misc. local control, enable interrupts on attentions */
1782         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1783
1784 #ifdef notdef
1785         /* Assert GPIO pins for PHY reset */
1786         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1787             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1788         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1789             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1790 #endif
1791
1792         /* Turn on DMA completion state machine */
1793         if (!BGE_IS_5705_PLUS(sc))
1794                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1795
1796         /* Turn on write DMA state machine */
1797         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1798         if (BGE_IS_5755_PLUS(sc)) {
1799                 /* Enable host coalescing bug fix. */
1800                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1801         }
1802         if (sc->bge_asicrev == BGE_ASICREV_BCM5785) {
1803                 /* Request larger DMA burst size to get better performance. */
1804                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1805         }
1806         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1807         DELAY(40);
1808
1809         if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
1810             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1811             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1812             sc->bge_asicrev == BGE_ASICREV_BCM57780) {
1813                 /*
1814                  * Enable fix for read DMA FIFO overruns.
1815                  * The fix is to limit the number of RX BDs
1816                  * the hardware would fetch at a fime.
1817                  */
1818                 val = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
1819                 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
1820                     val| BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1821         }
1822
1823         /* Turn on read DMA state machine */
1824         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1825         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1826             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1827             sc->bge_asicrev == BGE_ASICREV_BCM57780)
1828                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1829                   BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1830                   BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1831         if (sc->bge_flags & BGE_FLAG_PCIE)
1832                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1833         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1834         DELAY(40);
1835
1836         /* Turn on RX data completion state machine */
1837         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1838
1839         /* Turn on RX BD initiator state machine */
1840         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1841
1842         /* Turn on RX data and RX BD initiator state machine */
1843         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1844
1845         /* Turn on Mbuf cluster free state machine */
1846         if (!BGE_IS_5705_PLUS(sc))
1847                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1848
1849         /* Turn on send BD completion state machine */
1850         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1851
1852         /* Turn on send data completion state machine */
1853         val = BGE_SDCMODE_ENABLE;
1854         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1855                 val |= BGE_SDCMODE_CDELAY;
1856         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1857
1858         /* Turn on send data initiator state machine */
1859         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1860
1861         /* Turn on send BD initiator state machine */
1862         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1863
1864         /* Turn on send BD selector state machine */
1865         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1866
1867         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1868         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1869             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1870
1871         /* ack/clear link change events */
1872         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1873             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1874             BGE_MACSTAT_LINK_CHANGED);
1875         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1876
1877         /*
1878          * Enable attention when the link has changed state for
1879          * devices that use auto polling.
1880          */
1881         if (sc->bge_flags & BGE_FLAG_TBI) {
1882                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1883         } else {
1884                 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
1885                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1886                         DELAY(80);
1887                 }
1888                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1889                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1890                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1891                             BGE_EVTENB_MI_INTERRUPT);
1892                 }
1893         }
1894
1895         /*
1896          * Clear any pending link state attention.
1897          * Otherwise some link state change events may be lost until attention
1898          * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1899          * It's not necessary on newer BCM chips - perhaps enabling link
1900          * state change attentions implies clearing pending attention.
1901          */
1902         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1903             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1904             BGE_MACSTAT_LINK_CHANGED);
1905
1906         /* Enable link state change attentions. */
1907         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1908
1909         return(0);
1910 }
1911
1912 /*
1913  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1914  * against our list and return its name if we find a match. Note
1915  * that since the Broadcom controller contains VPD support, we
1916  * can get the device name string from the controller itself instead
1917  * of the compiled-in string. This is a little slow, but it guarantees
1918  * we'll always announce the right product name.
1919  */
1920 static int
1921 bge_probe(device_t dev)
1922 {
1923         const struct bge_type *t;
1924         uint16_t product, vendor;
1925
1926         product = pci_get_device(dev);
1927         vendor = pci_get_vendor(dev);
1928
1929         for (t = bge_devs; t->bge_name != NULL; t++) {
1930                 if (vendor == t->bge_vid && product == t->bge_did)
1931                         break;
1932         }
1933         if (t->bge_name == NULL)
1934                 return(ENXIO);
1935
1936         device_set_desc(dev, t->bge_name);
1937         return(0);
1938 }
1939
1940 static int
1941 bge_attach(device_t dev)
1942 {
1943         struct ifnet *ifp;
1944         struct bge_softc *sc;
1945         uint32_t hwcfg = 0, misccfg;
1946         int error = 0, rid, capmask;
1947         uint8_t ether_addr[ETHER_ADDR_LEN];
1948         uint16_t product, vendor;
1949
1950         sc = device_get_softc(dev);
1951         sc->bge_dev = dev;
1952         callout_init(&sc->bge_stat_timer);
1953         lwkt_serialize_init(&sc->bge_jslot_serializer);
1954
1955 #ifndef BURN_BRIDGES
1956         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1957                 uint32_t irq, mem;
1958
1959                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1960                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1961
1962                 device_printf(dev, "chip is in D%d power mode "
1963                     "-- setting to D0\n", pci_get_powerstate(dev));
1964
1965                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1966
1967                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1968                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1969         }
1970 #endif  /* !BURN_BRIDGE */
1971
1972         /*
1973          * Map control/status registers.
1974          */
1975         pci_enable_busmaster(dev);
1976
1977         rid = BGE_PCI_BAR0;
1978         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1979             RF_ACTIVE);
1980
1981         if (sc->bge_res == NULL) {
1982                 device_printf(dev, "couldn't map memory\n");
1983                 return ENXIO;
1984         }
1985
1986         sc->bge_btag = rman_get_bustag(sc->bge_res);
1987         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1988
1989         /* Save various chip information */
1990         sc->bge_chipid =
1991             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1992             BGE_PCIMISCCTL_ASICREV_SHIFT;
1993         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
1994                 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
1995         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1996         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1997
1998         /* Save chipset family. */
1999         switch (sc->bge_asicrev) {
2000         case BGE_ASICREV_BCM5755:
2001         case BGE_ASICREV_BCM5761:
2002         case BGE_ASICREV_BCM5784:
2003         case BGE_ASICREV_BCM5785:
2004         case BGE_ASICREV_BCM5787:
2005         case BGE_ASICREV_BCM57780:
2006             sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2007                 BGE_FLAG_5705_PLUS;
2008             break;
2009
2010         case BGE_ASICREV_BCM5700:
2011         case BGE_ASICREV_BCM5701:
2012         case BGE_ASICREV_BCM5703:
2013         case BGE_ASICREV_BCM5704:
2014                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2015                 break;
2016
2017         case BGE_ASICREV_BCM5714_A0:
2018         case BGE_ASICREV_BCM5780:
2019         case BGE_ASICREV_BCM5714:
2020                 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
2021                 /* Fall through */
2022
2023         case BGE_ASICREV_BCM5750:
2024         case BGE_ASICREV_BCM5752:
2025         case BGE_ASICREV_BCM5906:
2026                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2027                 /* Fall through */
2028
2029         case BGE_ASICREV_BCM5705:
2030                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2031                 break;
2032         }
2033
2034         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
2035                 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
2036
2037         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
2038         if (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2039             (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2040              misccfg == BGE_MISCCFG_BOARD_ID_5788M))
2041                 sc->bge_flags |= BGE_FLAG_5788;
2042
2043         /* BCM5755 or higher and BCM5906 have short DMA bug. */
2044         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
2045                 sc->bge_flags |= BGE_FLAG_SHORTDMA;
2046
2047         /*
2048          * Set various quirk flags.
2049          */
2050
2051         product = pci_get_device(dev);
2052         vendor = pci_get_vendor(dev);
2053
2054         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2055              sc->bge_asicrev == BGE_ASICREV_BCM5701) &&
2056             pci_get_subvendor(dev) == PCI_VENDOR_DELL)
2057                 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
2058
2059         capmask = MII_CAPMASK_DEFAULT;
2060         if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
2061              (misccfg == 0x4000 || misccfg == 0x8000)) ||
2062             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2063              vendor == PCI_VENDOR_BROADCOM &&
2064              (product == PCI_PRODUCT_BROADCOM_BCM5901 ||
2065               product == PCI_PRODUCT_BROADCOM_BCM5901A2 ||
2066               product == PCI_PRODUCT_BROADCOM_BCM5705F)) ||
2067             (vendor == PCI_VENDOR_BROADCOM &&
2068              (product == PCI_PRODUCT_BROADCOM_BCM5751F ||
2069               product == PCI_PRODUCT_BROADCOM_BCM5753F ||
2070               product == PCI_PRODUCT_BROADCOM_BCM5787F)) ||
2071             product == PCI_PRODUCT_BROADCOM_BCM57790 ||
2072             sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2073                 /* 10/100 only */
2074                 capmask &= ~BMSR_EXTSTAT;
2075         }
2076
2077         sc->bge_phy_flags |= BGE_PHY_WIRESPEED;
2078         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2079             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2080              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2081               sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
2082             sc->bge_asicrev == BGE_ASICREV_BCM5906)
2083                 sc->bge_phy_flags &= ~BGE_PHY_WIRESPEED;
2084
2085         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2086             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2087                 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
2088
2089         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2090             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2091                 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
2092
2093         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2094                 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
2095
2096         if (BGE_IS_5705_PLUS(sc) &&
2097             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2098             /* sc->bge_asicrev != BGE_ASICREV_BCM5717 && */
2099             sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2100             /* sc->bge_asicrev != BGE_ASICREV_BCM57765 && */
2101             sc->bge_asicrev != BGE_ASICREV_BCM57780) {
2102                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2103                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2104                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2105                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2106                         if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
2107                             product != PCI_PRODUCT_BROADCOM_BCM5756)
2108                                 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
2109                         if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
2110                                 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
2111                 } else {
2112                         sc->bge_phy_flags |= BGE_PHY_BER_BUG;
2113                 }
2114         }
2115
2116         /* Identify the chips that use an CPMU. */
2117         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2118             sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2119             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2120             sc->bge_asicrev == BGE_ASICREV_BCM57780)
2121                 sc->bge_flags |= BGE_FLAG_CPMU;
2122         if (sc->bge_flags & BGE_FLAG_CPMU)
2123                 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
2124         else
2125                 sc->bge_mi_mode = BGE_MIMODE_BASE;
2126
2127         /* Enable auto polling for BCM570[0-5]. */
2128         if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
2129                 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
2130
2131         /* Allocate interrupt */
2132         rid = 0;
2133
2134         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2135             RF_SHAREABLE | RF_ACTIVE);
2136
2137         if (sc->bge_irq == NULL) {
2138                 device_printf(dev, "couldn't map interrupt\n");
2139                 error = ENXIO;
2140                 goto fail;
2141         }
2142
2143         /*
2144          * Check if this is a PCI-X or PCI Express device.
2145          */
2146         if (BGE_IS_5705_PLUS(sc)) {
2147                 if (pci_is_pcie(dev)) {
2148                         sc->bge_flags |= BGE_FLAG_PCIE;
2149                         sc->bge_pciecap = pci_get_pciecap_ptr(sc->bge_dev);
2150                         pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
2151                 }
2152         } else {
2153                 /*
2154                  * Check if the device is in PCI-X Mode.
2155                  * (This bit is not valid on PCI Express controllers.)
2156                  */
2157                 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
2158                     BGE_PCISTATE_PCI_BUSMODE) == 0) {
2159                         sc->bge_flags |= BGE_FLAG_PCIX;
2160                         sc->bge_pcixcap = pci_get_pcixcap_ptr(sc->bge_dev);
2161                         sc->bge_mbox_reorder = device_getenv_int(sc->bge_dev,
2162                             "mbox_reorder", 0);
2163                 }
2164         }
2165
2166         device_printf(dev, "CHIP ID 0x%08x; "
2167                       "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
2168                       sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
2169                       (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
2170                       : ((sc->bge_flags & BGE_FLAG_PCIE) ?
2171                         "PCI-E" : "PCI"));
2172
2173         /*
2174          * The 40bit DMA bug applies to the 5714/5715 controllers and is
2175          * not actually a MAC controller bug but an issue with the embedded
2176          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2177          */
2178         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
2179                 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT;
2180
2181         ifp = &sc->arpcom.ac_if;
2182         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2183
2184         /* Try to reset the chip. */
2185         bge_reset(sc);
2186
2187         if (bge_chipinit(sc)) {
2188                 device_printf(dev, "chip initialization failed\n");
2189                 error = ENXIO;
2190                 goto fail;
2191         }
2192
2193         /*
2194          * Get station address
2195          */
2196         error = bge_get_eaddr(sc, ether_addr);
2197         if (error) {
2198                 device_printf(dev, "failed to read station address\n");
2199                 goto fail;
2200         }
2201
2202         /* 5705/5750 limits RX return ring to 512 entries. */
2203         if (BGE_IS_5705_PLUS(sc))
2204                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2205         else
2206                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2207
2208         error = bge_dma_alloc(sc);
2209         if (error)
2210                 goto fail;
2211
2212         /* Set default tuneable values. */
2213         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2214         sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
2215         sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
2216         sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
2217         sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
2218
2219         /* Set up ifnet structure */
2220         ifp->if_softc = sc;
2221         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2222         ifp->if_ioctl = bge_ioctl;
2223         ifp->if_start = bge_start;
2224 #ifdef DEVICE_POLLING
2225         ifp->if_poll = bge_poll;
2226 #endif
2227         ifp->if_watchdog = bge_watchdog;
2228         ifp->if_init = bge_init;
2229         ifp->if_mtu = ETHERMTU;
2230         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2231         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2232         ifq_set_ready(&ifp->if_snd);
2233
2234         /*
2235          * 5700 B0 chips do not support checksumming correctly due
2236          * to hardware bugs.
2237          */
2238         if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
2239                 ifp->if_capabilities |= IFCAP_HWCSUM;
2240                 ifp->if_hwassist = BGE_CSUM_FEATURES;
2241         }
2242         ifp->if_capenable = ifp->if_capabilities;
2243
2244         /*
2245          * Figure out what sort of media we have by checking the
2246          * hardware config word in the first 32k of NIC internal memory,
2247          * or fall back to examining the EEPROM if necessary.
2248          * Note: on some BCM5700 cards, this value appears to be unset.
2249          * If that's the case, we have to rely on identifying the NIC
2250          * by its PCI subsystem ID, as we do below for the SysKonnect
2251          * SK-9D41.
2252          */
2253         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2254                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2255         else {
2256                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2257                                     sizeof(hwcfg))) {
2258                         device_printf(dev, "failed to read EEPROM\n");
2259                         error = ENXIO;
2260                         goto fail;
2261                 }
2262                 hwcfg = ntohl(hwcfg);
2263         }
2264
2265         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2266         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
2267             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
2268                 if (BGE_IS_5714_FAMILY(sc))
2269                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
2270                 else
2271                         sc->bge_flags |= BGE_FLAG_TBI;
2272         }
2273
2274         /*
2275          * Broadcom's own driver always assumes the internal
2276          * PHY is at GMII address 1.  On some chips, the PHY responds
2277          * to accesses at all addresses, which could cause us to
2278          * bogusly attach the PHY 32 times at probe type.  Always
2279          * restricting the lookup to address 1 is simpler than
2280          * trying to figure out which chips revisions should be
2281          * special-cased.
2282          */
2283         sc->bge_phyno = 1;
2284
2285         if (sc->bge_flags & BGE_FLAG_TBI) {
2286                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
2287                     bge_ifmedia_upd, bge_ifmedia_sts);
2288                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2289                 ifmedia_add(&sc->bge_ifmedia,
2290                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2291                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2292                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
2293                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2294         } else {
2295                 struct mii_probe_args mii_args;
2296
2297                 mii_probe_args_init(&mii_args, bge_ifmedia_upd, bge_ifmedia_sts);
2298                 mii_args.mii_probemask = 1 << sc->bge_phyno;
2299                 mii_args.mii_capmask = capmask;
2300
2301                 error = mii_probe(dev, &sc->bge_miibus, &mii_args);
2302                 if (error) {
2303                         device_printf(dev, "MII without any PHY!\n");
2304                         goto fail;
2305                 }
2306         }
2307
2308         /*
2309          * When using the BCM5701 in PCI-X mode, data corruption has
2310          * been observed in the first few bytes of some received packets.
2311          * Aligning the packet buffer in memory eliminates the corruption.
2312          * Unfortunately, this misaligns the packet payloads.  On platforms
2313          * which do not support unaligned accesses, we will realign the
2314          * payloads by copying the received packets.
2315          */
2316         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2317             (sc->bge_flags & BGE_FLAG_PCIX))
2318                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2319
2320         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2321             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2322                 sc->bge_link_upd = bge_bcm5700_link_upd;
2323                 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
2324         } else if (sc->bge_flags & BGE_FLAG_TBI) {
2325                 sc->bge_link_upd = bge_tbi_link_upd;
2326                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2327         } else if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2328                 sc->bge_link_upd = bge_autopoll_link_upd;
2329                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2330         } else {
2331                 sc->bge_link_upd = bge_copper_link_upd;
2332                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2333         }
2334
2335         /*
2336          * Create sysctl nodes.
2337          */
2338         sysctl_ctx_init(&sc->bge_sysctl_ctx);
2339         sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
2340                                               SYSCTL_STATIC_CHILDREN(_hw),
2341                                               OID_AUTO,
2342                                               device_get_nameunit(dev),
2343                                               CTLFLAG_RD, 0, "");
2344         if (sc->bge_sysctl_tree == NULL) {
2345                 device_printf(dev, "can't add sysctl node\n");
2346                 error = ENXIO;
2347                 goto fail;
2348         }
2349
2350         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2351                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2352                         OID_AUTO, "rx_coal_ticks",
2353                         CTLTYPE_INT | CTLFLAG_RW,
2354                         sc, 0, bge_sysctl_rx_coal_ticks, "I",
2355                         "Receive coalescing ticks (usec).");
2356         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2357                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2358                         OID_AUTO, "tx_coal_ticks",
2359                         CTLTYPE_INT | CTLFLAG_RW,
2360                         sc, 0, bge_sysctl_tx_coal_ticks, "I",
2361                         "Transmit coalescing ticks (usec).");
2362         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2363                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2364                         OID_AUTO, "rx_max_coal_bds",
2365                         CTLTYPE_INT | CTLFLAG_RW,
2366                         sc, 0, bge_sysctl_rx_max_coal_bds, "I",
2367                         "Receive max coalesced BD count.");
2368         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2369                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2370                         OID_AUTO, "tx_max_coal_bds",
2371                         CTLTYPE_INT | CTLFLAG_RW,
2372                         sc, 0, bge_sysctl_tx_max_coal_bds, "I",
2373                         "Transmit max coalesced BD count.");
2374
2375         if (sc->bge_flags & BGE_FLAG_PCIE) {
2376                 /*
2377                  * A common design characteristic for many Broadcom
2378                  * client controllers is that they only support a
2379                  * single outstanding DMA read operation on the PCIe
2380                  * bus. This means that it will take twice as long to
2381                  * fetch a TX frame that is split into header and
2382                  * payload buffers as it does to fetch a single,
2383                  * contiguous TX frame (2 reads vs. 1 read). For these
2384                  * controllers, coalescing buffers to reduce the number
2385                  * of memory reads is effective way to get maximum
2386                  * performance(about 940Mbps).  Without collapsing TX
2387                  * buffers the maximum TCP bulk transfer performance
2388                  * is about 850Mbps. However forcing coalescing mbufs
2389                  * consumes a lot of CPU cycles, so leave it off by
2390                  * default.
2391                  */
2392                 SYSCTL_ADD_INT(&sc->bge_sysctl_ctx,
2393                                SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2394                                OID_AUTO, "force_defrag", CTLFLAG_RW,
2395                                &sc->bge_force_defrag, 0,
2396                                "Force defragment on TX path");
2397         }
2398
2399         /*
2400          * Call MI attach routine.
2401          */
2402         ether_ifattach(ifp, ether_addr, NULL);
2403
2404         error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE,
2405                                bge_intr, sc, &sc->bge_intrhand,
2406                                ifp->if_serializer);
2407         if (error) {
2408                 ether_ifdetach(ifp);
2409                 device_printf(dev, "couldn't set up irq\n");
2410                 goto fail;
2411         }
2412
2413         ifp->if_cpuid = rman_get_cpuid(sc->bge_irq);
2414         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2415
2416         return(0);
2417 fail:
2418         bge_detach(dev);
2419         return(error);
2420 }
2421
2422 static int
2423 bge_detach(device_t dev)
2424 {
2425         struct bge_softc *sc = device_get_softc(dev);
2426
2427         if (device_is_attached(dev)) {
2428                 struct ifnet *ifp = &sc->arpcom.ac_if;
2429
2430                 lwkt_serialize_enter(ifp->if_serializer);
2431                 bge_stop(sc);
2432                 bge_reset(sc);
2433                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2434                 lwkt_serialize_exit(ifp->if_serializer);
2435
2436                 ether_ifdetach(ifp);
2437         }
2438
2439         if (sc->bge_flags & BGE_FLAG_TBI)
2440                 ifmedia_removeall(&sc->bge_ifmedia);
2441         if (sc->bge_miibus)
2442                 device_delete_child(dev, sc->bge_miibus);
2443         bus_generic_detach(dev);
2444
2445         if (sc->bge_irq != NULL)
2446                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
2447
2448         if (sc->bge_res != NULL)
2449                 bus_release_resource(dev, SYS_RES_MEMORY,
2450                     BGE_PCI_BAR0, sc->bge_res);
2451
2452         if (sc->bge_sysctl_tree != NULL)
2453                 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2454
2455         bge_dma_free(sc);
2456
2457         return 0;
2458 }
2459
2460 static void
2461 bge_reset(struct bge_softc *sc)
2462 {
2463         device_t dev;
2464         uint32_t cachesize, command, pcistate, reset;
2465         void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2466         int i, val = 0;
2467
2468         dev = sc->bge_dev;
2469
2470         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2471             sc->bge_asicrev != BGE_ASICREV_BCM5906) {
2472                 if (sc->bge_flags & BGE_FLAG_PCIE)
2473                         write_op = bge_writemem_direct;
2474                 else
2475                         write_op = bge_writemem_ind;
2476         } else {
2477                 write_op = bge_writereg_ind;
2478         }
2479
2480         /* Save some important PCI state. */
2481         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2482         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2483         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2484
2485         pci_write_config(dev, BGE_PCI_MISC_CTL,
2486             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2487             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2488
2489         /* Disable fastboot on controllers that support it. */
2490         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2491             BGE_IS_5755_PLUS(sc)) {
2492                 if (bootverbose)
2493                         if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2494                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2495         }
2496
2497         /*
2498          * Write the magic number to SRAM at offset 0xB50.
2499          * When firmware finishes its initialization it will
2500          * write ~BGE_MAGIC_NUMBER to the same location.
2501          */
2502         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2503
2504         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2505
2506         /* XXX: Broadcom Linux driver. */
2507         if (sc->bge_flags & BGE_FLAG_PCIE) {
2508                 if (CSR_READ_4(sc, 0x7e2c) == 0x60)     /* PCIE 1.0 */
2509                         CSR_WRITE_4(sc, 0x7e2c, 0x20);
2510                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2511                         /* Prevent PCIE link training during global reset */
2512                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2513                         reset |= (1<<29);
2514                 }
2515         }
2516
2517         /*
2518          * Set GPHY Power Down Override to leave GPHY
2519          * powered up in D0 uninitialized.
2520          */
2521         if (BGE_IS_5705_PLUS(sc) && (sc->bge_flags & BGE_FLAG_CPMU) == 0)
2522                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2523
2524         /* Issue global reset */
2525         write_op(sc, BGE_MISC_CFG, reset);
2526
2527         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2528                 uint32_t status, ctrl;
2529
2530                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2531                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2532                     status | BGE_VCPU_STATUS_DRV_RESET);
2533                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2534                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2535                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2536         }
2537
2538         DELAY(1000);
2539
2540         /* XXX: Broadcom Linux driver. */
2541         if (sc->bge_flags & BGE_FLAG_PCIE) {
2542                 uint16_t devctl;
2543
2544                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2545                         uint32_t v;
2546
2547                         DELAY(500000); /* wait for link training to complete */
2548                         v = pci_read_config(dev, 0xc4, 4);
2549                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
2550                 }
2551
2552                 /* Clear enable no snoop and disable relaxed ordering. */
2553                 devctl = pci_read_config(dev,
2554                     sc->bge_pciecap + PCIER_DEVCTRL, 2);
2555                 devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2556                 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVCTRL,
2557                     devctl, 2);
2558
2559                 /* Clear error status. */
2560                 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVSTS,
2561                     PCIEM_DEVSTS_CORR_ERR |
2562                     PCIEM_DEVSTS_NFATAL_ERR |
2563                     PCIEM_DEVSTS_FATAL_ERR |
2564                     PCIEM_DEVSTS_UNSUPP_REQ, 2);
2565         }
2566
2567         /* Reset some of the PCI state that got zapped by reset */
2568         pci_write_config(dev, BGE_PCI_MISC_CTL,
2569             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2570             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2571         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2572         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2573         write_op(sc, BGE_MISC_CFG, (65 << 1));
2574
2575         /*
2576          * Disable PCI-X relaxed ordering to ensure status block update
2577          * comes first then packet buffer DMA. Otherwise driver may
2578          * read stale status block.
2579          */
2580         if (sc->bge_flags & BGE_FLAG_PCIX) {
2581                 uint16_t devctl;
2582
2583                 devctl = pci_read_config(dev,
2584                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
2585                 devctl &= ~PCIXM_COMMAND_ERO;
2586                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
2587                         devctl &= ~PCIXM_COMMAND_MAX_READ;
2588                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2589                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2590                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
2591                             PCIXM_COMMAND_MAX_READ);
2592                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2593                 }
2594                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
2595                     devctl, 2);
2596         }
2597
2598         /* Enable memory arbiter. */
2599         if (BGE_IS_5714_FAMILY(sc)) {
2600                 uint32_t val;
2601
2602                 val = CSR_READ_4(sc, BGE_MARB_MODE);
2603                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2604         } else {
2605                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2606         }
2607
2608         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2609                 for (i = 0; i < BGE_TIMEOUT; i++) {
2610                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2611                         if (val & BGE_VCPU_STATUS_INIT_DONE)
2612                                 break;
2613                         DELAY(100);
2614                 }
2615                 if (i == BGE_TIMEOUT) {
2616                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2617                         return;
2618                 }
2619         } else {
2620                 /*
2621                  * Poll until we see the 1's complement of the magic number.
2622                  * This indicates that the firmware initialization
2623                  * is complete.
2624                  */
2625                 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
2626                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2627                         if (val == ~BGE_MAGIC_NUMBER)
2628                                 break;
2629                         DELAY(10);
2630                 }
2631                 if (i == BGE_FIRMWARE_TIMEOUT) {
2632                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
2633                                   "timed out, found 0x%08x\n", val);
2634                         return;
2635                 }
2636         }
2637
2638         /*
2639          * XXX Wait for the value of the PCISTATE register to
2640          * return to its original pre-reset state. This is a
2641          * fairly good indicator of reset completion. If we don't
2642          * wait for the reset to fully complete, trying to read
2643          * from the device's non-PCI registers may yield garbage
2644          * results.
2645          */
2646         for (i = 0; i < BGE_TIMEOUT; i++) {
2647                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2648                         break;
2649                 DELAY(10);
2650         }
2651
2652         /* Fix up byte swapping */
2653         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2654             BGE_MODECTL_BYTESWAP_DATA);
2655
2656         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2657
2658         /*
2659          * The 5704 in TBI mode apparently needs some special
2660          * adjustment to insure the SERDES drive level is set
2661          * to 1.2V.
2662          */
2663         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2664             (sc->bge_flags & BGE_FLAG_TBI)) {
2665                 uint32_t serdescfg;
2666
2667                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2668                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2669                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2670         }
2671
2672         /* XXX: Broadcom Linux driver. */
2673         if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2674             sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
2675             sc->bge_asicrev != BGE_ASICREV_BCM5785) {
2676                 uint32_t v;
2677
2678                 /* Enable Data FIFO protection. */
2679                 v = CSR_READ_4(sc, 0x7c00);
2680                 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2681         }
2682
2683         DELAY(10000);
2684 }
2685
2686 /*
2687  * Frame reception handling. This is called if there's a frame
2688  * on the receive return list.
2689  *
2690  * Note: we have to be able to handle two possibilities here:
2691  * 1) the frame is from the jumbo recieve ring
2692  * 2) the frame is from the standard receive ring
2693  */
2694
2695 static void
2696 bge_rxeof(struct bge_softc *sc)
2697 {
2698         struct ifnet *ifp;
2699         int stdcnt = 0, jumbocnt = 0;
2700
2701         if (sc->bge_rx_saved_considx ==
2702             sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2703                 return;
2704
2705         ifp = &sc->arpcom.ac_if;
2706
2707         while (sc->bge_rx_saved_considx !=
2708                sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2709                 struct bge_rx_bd        *cur_rx;
2710                 uint32_t                rxidx;
2711                 struct mbuf             *m = NULL;
2712                 uint16_t                vlan_tag = 0;
2713                 int                     have_tag = 0;
2714
2715                 cur_rx =
2716             &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2717
2718                 rxidx = cur_rx->bge_idx;
2719                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2720                 logif(rx_pkt);
2721
2722                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2723                         have_tag = 1;
2724                         vlan_tag = cur_rx->bge_vlan_tag;
2725                 }
2726
2727                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2728                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2729                         jumbocnt++;
2730
2731                         if (rxidx != sc->bge_jumbo) {
2732                                 ifp->if_ierrors++;
2733                                 if_printf(ifp, "sw jumbo index(%d) "
2734                                     "and hw jumbo index(%d) mismatch, drop!\n",
2735                                     sc->bge_jumbo, rxidx);
2736                                 bge_setup_rxdesc_jumbo(sc, rxidx);
2737                                 continue;
2738                         }
2739
2740                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf;
2741                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2742                                 ifp->if_ierrors++;
2743                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2744                                 continue;
2745                         }
2746                         if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) {
2747                                 ifp->if_ierrors++;
2748                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2749                                 continue;
2750                         }
2751                 } else {
2752                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2753                         stdcnt++;
2754
2755                         if (rxidx != sc->bge_std) {
2756                                 ifp->if_ierrors++;
2757                                 if_printf(ifp, "sw std index(%d) "
2758                                     "and hw std index(%d) mismatch, drop!\n",
2759                                     sc->bge_std, rxidx);
2760                                 bge_setup_rxdesc_std(sc, rxidx);
2761                                 continue;
2762                         }
2763
2764                         m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf;
2765                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2766                                 ifp->if_ierrors++;
2767                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2768                                 continue;
2769                         }
2770                         if (bge_newbuf_std(sc, sc->bge_std, 0)) {
2771                                 ifp->if_ierrors++;
2772                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2773                                 continue;
2774                         }
2775                 }
2776
2777                 ifp->if_ipackets++;
2778 #if !defined(__i386__) && !defined(__x86_64__)
2779                 /*
2780                  * The x86 allows unaligned accesses, but for other
2781                  * platforms we must make sure the payload is aligned.
2782                  */
2783                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2784                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2785                             cur_rx->bge_len);
2786                         m->m_data += ETHER_ALIGN;
2787                 }
2788 #endif
2789                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2790                 m->m_pkthdr.rcvif = ifp;
2791
2792                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2793                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2794                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2795                                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2796                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2797                         }
2798                         if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
2799                             m->m_pkthdr.len >= BGE_MIN_FRAME) {
2800                                 m->m_pkthdr.csum_data =
2801                                         cur_rx->bge_tcp_udp_csum;
2802                                 m->m_pkthdr.csum_flags |=
2803                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2804                         }
2805                 }
2806
2807                 /*
2808                  * If we received a packet with a vlan tag, pass it
2809                  * to vlan_input() instead of ether_input().
2810                  */
2811                 if (have_tag) {
2812                         m->m_flags |= M_VLANTAG;
2813                         m->m_pkthdr.ether_vlantag = vlan_tag;
2814                         have_tag = vlan_tag = 0;
2815                 }
2816                 ifp->if_input(ifp, m);
2817         }
2818
2819         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2820         if (stdcnt)
2821                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2822         if (jumbocnt)
2823                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2824 }
2825
2826 static void
2827 bge_txeof(struct bge_softc *sc)
2828 {
2829         struct bge_tx_bd *cur_tx = NULL;
2830         struct ifnet *ifp;
2831
2832         if (sc->bge_tx_saved_considx ==
2833             sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2834                 return;
2835
2836         ifp = &sc->arpcom.ac_if;
2837
2838         /*
2839          * Go through our tx ring and free mbufs for those
2840          * frames that have been sent.
2841          */
2842         while (sc->bge_tx_saved_considx !=
2843                sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2844                 uint32_t idx = 0;
2845
2846                 idx = sc->bge_tx_saved_considx;
2847                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2848                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2849                         ifp->if_opackets++;
2850                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2851                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
2852                             sc->bge_cdata.bge_tx_dmamap[idx]);
2853                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2854                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2855                 }
2856                 sc->bge_txcnt--;
2857                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2858                 logif(tx_pkt);
2859         }
2860
2861         if (cur_tx != NULL &&
2862             (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2863             (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2864                 ifp->if_flags &= ~IFF_OACTIVE;
2865
2866         if (sc->bge_txcnt == 0)
2867                 ifp->if_timer = 0;
2868
2869         if (!ifq_is_empty(&ifp->if_snd))
2870                 if_devstart(ifp);
2871 }
2872
2873 #ifdef DEVICE_POLLING
2874
2875 static void
2876 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2877 {
2878         struct bge_softc *sc = ifp->if_softc;
2879         uint32_t status;
2880
2881         switch(cmd) {
2882         case POLL_REGISTER:
2883                 bge_disable_intr(sc);
2884                 break;
2885         case POLL_DEREGISTER:
2886                 bge_enable_intr(sc);
2887                 break;
2888         case POLL_AND_CHECK_STATUS:
2889                 /*
2890                  * Process link state changes.
2891                  */
2892                 status = CSR_READ_4(sc, BGE_MAC_STS);
2893                 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2894                         sc->bge_link_evt = 0;
2895                         sc->bge_link_upd(sc, status);
2896                 }
2897                 /* fall through */
2898         case POLL_ONLY:
2899                 if (ifp->if_flags & IFF_RUNNING) {
2900                         bge_rxeof(sc);
2901                         bge_txeof(sc);
2902                 }
2903                 break;
2904         }
2905 }
2906
2907 #endif
2908
2909 static void
2910 bge_intr(void *xsc)
2911 {
2912         struct bge_softc *sc = xsc;
2913         struct ifnet *ifp = &sc->arpcom.ac_if;
2914         uint32_t status;
2915
2916         logif(intr);
2917
2918         /*
2919          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
2920          * disable interrupts by writing nonzero like we used to, since with
2921          * our current organization this just gives complications and
2922          * pessimizations for re-enabling interrupts.  We used to have races
2923          * instead of the necessary complications.  Disabling interrupts
2924          * would just reduce the chance of a status update while we are
2925          * running (by switching to the interrupt-mode coalescence
2926          * parameters), but this chance is already very low so it is more
2927          * efficient to get another interrupt than prevent it.
2928          *
2929          * We do the ack first to ensure another interrupt if there is a
2930          * status update after the ack.  We don't check for the status
2931          * changing later because it is more efficient to get another
2932          * interrupt than prevent it, not quite as above (not checking is
2933          * a smaller optimization than not toggling the interrupt enable,
2934          * since checking doesn't involve PCI accesses and toggling require
2935          * the status check).  So toggling would probably be a pessimization
2936          * even with MSI.  It would only be needed for using a task queue.
2937          */
2938         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
2939
2940         /*
2941          * Process link state changes.
2942          */
2943         status = CSR_READ_4(sc, BGE_MAC_STS);
2944         if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2945                 sc->bge_link_evt = 0;
2946                 sc->bge_link_upd(sc, status);
2947         }
2948
2949         if (ifp->if_flags & IFF_RUNNING) {
2950                 /* Check RX return ring producer/consumer */
2951                 bge_rxeof(sc);
2952
2953                 /* Check TX ring producer/consumer */
2954                 bge_txeof(sc);
2955         }
2956
2957         if (sc->bge_coal_chg)
2958                 bge_coal_change(sc);
2959 }
2960
2961 static void
2962 bge_tick(void *xsc)
2963 {
2964         struct bge_softc *sc = xsc;
2965         struct ifnet *ifp = &sc->arpcom.ac_if;
2966
2967         lwkt_serialize_enter(ifp->if_serializer);
2968
2969         if (BGE_IS_5705_PLUS(sc))
2970                 bge_stats_update_regs(sc);
2971         else
2972                 bge_stats_update(sc);
2973
2974         if (sc->bge_flags & BGE_FLAG_TBI) {
2975                 /*
2976                  * Since in TBI mode auto-polling can't be used we should poll
2977                  * link status manually. Here we register pending link event
2978                  * and trigger interrupt.
2979                  */
2980                 sc->bge_link_evt++;
2981                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2982                     BGE_IS_5788(sc))
2983                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
2984                 else
2985                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
2986         } else if (!sc->bge_link) {
2987                 mii_tick(device_get_softc(sc->bge_miibus));
2988         }
2989
2990         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2991
2992         lwkt_serialize_exit(ifp->if_serializer);
2993 }
2994
2995 static void
2996 bge_stats_update_regs(struct bge_softc *sc)
2997 {
2998         struct ifnet *ifp = &sc->arpcom.ac_if;
2999         struct bge_mac_stats_regs stats;
3000         uint32_t *s;
3001         int i;
3002
3003         s = (uint32_t *)&stats;
3004         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
3005                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
3006                 s++;
3007         }
3008
3009         ifp->if_collisions +=
3010            (stats.dot3StatsSingleCollisionFrames +
3011            stats.dot3StatsMultipleCollisionFrames +
3012            stats.dot3StatsExcessiveCollisions +
3013            stats.dot3StatsLateCollisions) -
3014            ifp->if_collisions;
3015 }
3016
3017 static void
3018 bge_stats_update(struct bge_softc *sc)
3019 {
3020         struct ifnet *ifp = &sc->arpcom.ac_if;
3021         bus_size_t stats;
3022
3023         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3024
3025 #define READ_STAT(sc, stats, stat)      \
3026         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3027
3028         ifp->if_collisions +=
3029            (READ_STAT(sc, stats,
3030                 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
3031             READ_STAT(sc, stats,
3032                 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
3033             READ_STAT(sc, stats,
3034                 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
3035             READ_STAT(sc, stats,
3036                 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
3037            ifp->if_collisions;
3038
3039 #undef READ_STAT
3040
3041 #ifdef notdef
3042         ifp->if_collisions +=
3043            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
3044            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
3045            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
3046            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
3047            ifp->if_collisions;
3048 #endif
3049 }
3050
3051 /*
3052  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
3053  * pointers to descriptors.
3054  */
3055 static int
3056 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
3057 {
3058         struct bge_tx_bd *d = NULL;
3059         uint16_t csum_flags = 0;
3060         bus_dma_segment_t segs[BGE_NSEG_NEW];
3061         bus_dmamap_t map;
3062         int error, maxsegs, nsegs, idx, i;
3063         struct mbuf *m_head = *m_head0, *m_new;
3064
3065         if (m_head->m_pkthdr.csum_flags) {
3066                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3067                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3068                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
3069                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3070                 if (m_head->m_flags & M_LASTFRAG)
3071                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3072                 else if (m_head->m_flags & M_FRAG)
3073                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3074         }
3075
3076         idx = *txidx;
3077         map = sc->bge_cdata.bge_tx_dmamap[idx];
3078
3079         maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
3080         KASSERT(maxsegs >= BGE_NSEG_SPARE,
3081                 ("not enough segments %d", maxsegs));
3082
3083         if (maxsegs > BGE_NSEG_NEW)
3084                 maxsegs = BGE_NSEG_NEW;
3085
3086         /*
3087          * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
3088          * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
3089          * but when such padded frames employ the bge IP/TCP checksum
3090          * offload, the hardware checksum assist gives incorrect results
3091          * (possibly from incorporating its own padding into the UDP/TCP
3092          * checksum; who knows).  If we pad such runts with zeros, the
3093          * onboard checksum comes out correct.
3094          */
3095         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
3096             m_head->m_pkthdr.len < BGE_MIN_FRAME) {
3097                 error = m_devpad(m_head, BGE_MIN_FRAME);
3098                 if (error)
3099                         goto back;
3100         }
3101
3102         if ((sc->bge_flags & BGE_FLAG_SHORTDMA) && m_head->m_next != NULL) {
3103                 m_new = bge_defrag_shortdma(m_head);
3104                 if (m_new == NULL) {
3105                         error = ENOBUFS;
3106                         goto back;
3107                 }
3108                 *m_head0 = m_head = m_new;
3109         }
3110         if (sc->bge_force_defrag && (sc->bge_flags & BGE_FLAG_PCIE) &&
3111             m_head->m_next != NULL) {
3112                 /*
3113                  * Forcefully defragment mbuf chain to overcome hardware
3114                  * limitation which only support a single outstanding
3115                  * DMA read operation.  If it fails, keep moving on using
3116                  * the original mbuf chain.
3117                  */
3118                 m_new = m_defrag(m_head, MB_DONTWAIT);
3119                 if (m_new != NULL)
3120                         *m_head0 = m_head = m_new;
3121         }
3122
3123         error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map,
3124                         m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3125         if (error)
3126                 goto back;
3127
3128         m_head = *m_head0;
3129         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
3130
3131         for (i = 0; ; i++) {
3132                 d = &sc->bge_ldata.bge_tx_ring[idx];
3133
3134                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3135                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3136                 d->bge_len = segs[i].ds_len;
3137                 d->bge_flags = csum_flags;
3138
3139                 if (i == nsegs - 1)
3140                         break;
3141                 BGE_INC(idx, BGE_TX_RING_CNT);
3142         }
3143         /* Mark the last segment as end of packet... */
3144         d->bge_flags |= BGE_TXBDFLAG_END;
3145
3146         /* Set vlan tag to the first segment of the packet. */
3147         d = &sc->bge_ldata.bge_tx_ring[*txidx];
3148         if (m_head->m_flags & M_VLANTAG) {
3149                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3150                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
3151         } else {
3152                 d->bge_vlan_tag = 0;
3153         }
3154
3155         /*
3156          * Insure that the map for this transmission is placed at
3157          * the array index of the last descriptor in this chain.
3158          */
3159         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
3160         sc->bge_cdata.bge_tx_dmamap[idx] = map;
3161         sc->bge_cdata.bge_tx_chain[idx] = m_head;
3162         sc->bge_txcnt += nsegs;
3163
3164         BGE_INC(idx, BGE_TX_RING_CNT);
3165         *txidx = idx;
3166 back:
3167         if (error) {
3168                 m_freem(*m_head0);
3169                 *m_head0 = NULL;
3170         }
3171         return error;
3172 }
3173
3174 /*
3175  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3176  * to the mbuf data regions directly in the transmit descriptors.
3177  */
3178 static void
3179 bge_start(struct ifnet *ifp)
3180 {
3181         struct bge_softc *sc = ifp->if_softc;
3182         struct mbuf *m_head = NULL;
3183         uint32_t prodidx;
3184         int need_trans;
3185
3186         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
3187                 return;
3188
3189         prodidx = sc->bge_tx_prodidx;
3190
3191         need_trans = 0;
3192         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
3193                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3194                 if (m_head == NULL)
3195                         break;
3196
3197                 /*
3198                  * XXX
3199                  * The code inside the if() block is never reached since we
3200                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
3201                  * requests to checksum TCP/UDP in a fragmented packet.
3202                  *
3203                  * XXX
3204                  * safety overkill.  If this is a fragmented packet chain
3205                  * with delayed TCP/UDP checksums, then only encapsulate
3206                  * it if we have enough descriptors to handle the entire
3207                  * chain at once.
3208                  * (paranoia -- may not actually be needed)
3209                  */
3210                 if ((m_head->m_flags & M_FIRSTFRAG) &&
3211                     (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
3212                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3213                             m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
3214                                 ifp->if_flags |= IFF_OACTIVE;
3215                                 ifq_prepend(&ifp->if_snd, m_head);
3216                                 break;
3217                         }
3218                 }
3219
3220                 /*
3221                  * Sanity check: avoid coming within BGE_NSEG_RSVD
3222                  * descriptors of the end of the ring.  Also make
3223                  * sure there are BGE_NSEG_SPARE descriptors for
3224                  * jumbo buffers' defragmentation.
3225                  */
3226                 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3227                     (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
3228                         ifp->if_flags |= IFF_OACTIVE;
3229                         ifq_prepend(&ifp->if_snd, m_head);
3230                         break;
3231                 }
3232
3233                 /*
3234                  * Pack the data into the transmit ring. If we
3235                  * don't have room, set the OACTIVE flag and wait
3236                  * for the NIC to drain the ring.
3237                  */
3238                 if (bge_encap(sc, &m_head, &prodidx)) {
3239                         ifp->if_flags |= IFF_OACTIVE;
3240                         ifp->if_oerrors++;
3241                         break;
3242                 }
3243                 need_trans = 1;
3244
3245                 ETHER_BPF_MTAP(ifp, m_head);
3246         }
3247
3248         if (!need_trans)
3249                 return;
3250
3251         /* Transmit */
3252         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3253         /* 5700 b2 errata */
3254         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
3255                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3256
3257         sc->bge_tx_prodidx = prodidx;
3258
3259         /*
3260          * Set a timeout in case the chip goes out to lunch.
3261          */
3262         ifp->if_timer = 5;
3263 }
3264
3265 static void
3266 bge_init(void *xsc)
3267 {
3268         struct bge_softc *sc = xsc;
3269         struct ifnet *ifp = &sc->arpcom.ac_if;
3270         uint16_t *m;
3271         uint32_t mode;
3272
3273         ASSERT_SERIALIZED(ifp->if_serializer);
3274
3275         /* Cancel pending I/O and flush buffers. */
3276         bge_stop(sc);
3277         bge_reset(sc);
3278         bge_chipinit(sc);
3279
3280         /*
3281          * Init the various state machines, ring
3282          * control blocks and firmware.
3283          */
3284         if (bge_blockinit(sc)) {
3285                 if_printf(ifp, "initialization failure\n");
3286                 bge_stop(sc);
3287                 return;
3288         }
3289
3290         /* Specify MTU. */
3291         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3292             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3293
3294         /* Load our MAC address. */
3295         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3296         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3297         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3298
3299         /* Enable or disable promiscuous mode as needed. */
3300         bge_setpromisc(sc);
3301
3302         /* Program multicast filter. */
3303         bge_setmulti(sc);
3304
3305         /* Init RX ring. */
3306         if (bge_init_rx_ring_std(sc)) {
3307                 if_printf(ifp, "RX ring initialization failed\n");
3308                 bge_stop(sc);
3309                 return;
3310         }
3311
3312         /*
3313          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3314          * memory to insure that the chip has in fact read the first
3315          * entry of the ring.
3316          */
3317         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3318                 uint32_t                v, i;
3319                 for (i = 0; i < 10; i++) {
3320                         DELAY(20);
3321                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3322                         if (v == (MCLBYTES - ETHER_ALIGN))
3323                                 break;
3324                 }
3325                 if (i == 10)
3326                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
3327         }
3328
3329         /* Init jumbo RX ring. */
3330         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3331                 if (bge_init_rx_ring_jumbo(sc)) {
3332                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
3333                         bge_stop(sc);
3334                         return;
3335                 }
3336         }
3337
3338         /* Init our RX return ring index */
3339         sc->bge_rx_saved_considx = 0;
3340
3341         /* Init TX ring. */
3342         bge_init_tx_ring(sc);
3343
3344         /* Enable TX MAC state machine lockup fix. */
3345         mode = CSR_READ_4(sc, BGE_TX_MODE);
3346         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3347                 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3348         /* Turn on transmitter */
3349         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3350
3351         /* Turn on receiver */
3352         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3353
3354         /*
3355          * Set the number of good frames to receive after RX MBUF
3356          * Low Watermark has been reached.  After the RX MAC receives
3357          * this number of frames, it will drop subsequent incoming
3358          * frames until the MBUF High Watermark is reached.
3359          */
3360         CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3361
3362         /* Tell firmware we're alive. */
3363         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3364
3365         /* Enable host interrupts if polling(4) is not enabled. */
3366         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
3367 #ifdef DEVICE_POLLING
3368         if (ifp->if_flags & IFF_POLLING)
3369                 bge_disable_intr(sc);
3370         else
3371 #endif
3372         bge_enable_intr(sc);
3373
3374         bge_ifmedia_upd(ifp);
3375
3376         ifp->if_flags |= IFF_RUNNING;
3377         ifp->if_flags &= ~IFF_OACTIVE;
3378
3379         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3380 }
3381
3382 /*
3383  * Set media options.
3384  */
3385 static int
3386 bge_ifmedia_upd(struct ifnet *ifp)
3387 {
3388         struct bge_softc *sc = ifp->if_softc;
3389
3390         /* If this is a 1000baseX NIC, enable the TBI port. */
3391         if (sc->bge_flags & BGE_FLAG_TBI) {
3392                 struct ifmedia *ifm = &sc->bge_ifmedia;
3393
3394                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3395                         return(EINVAL);
3396
3397                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3398                 case IFM_AUTO:
3399                         /*
3400                          * The BCM5704 ASIC appears to have a special
3401                          * mechanism for programming the autoneg
3402                          * advertisement registers in TBI mode.
3403                          */
3404                         if (!bge_fake_autoneg &&
3405                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3406                                 uint32_t sgdig;
3407
3408                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3409                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3410                                 sgdig |= BGE_SGDIGCFG_AUTO |
3411                                          BGE_SGDIGCFG_PAUSE_CAP |
3412                                          BGE_SGDIGCFG_ASYM_PAUSE;
3413                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3414                                             sgdig | BGE_SGDIGCFG_SEND);
3415                                 DELAY(5);
3416                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3417                         }
3418                         break;
3419                 case IFM_1000_SX:
3420                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3421                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3422                                     BGE_MACMODE_HALF_DUPLEX);
3423                         } else {
3424                                 BGE_SETBIT(sc, BGE_MAC_MODE,
3425                                     BGE_MACMODE_HALF_DUPLEX);
3426                         }
3427                         break;
3428                 default:
3429                         return(EINVAL);
3430                 }
3431         } else {
3432                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3433
3434                 sc->bge_link_evt++;
3435                 sc->bge_link = 0;
3436                 if (mii->mii_instance) {
3437                         struct mii_softc *miisc;
3438
3439                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3440                                 mii_phy_reset(miisc);
3441                 }
3442                 mii_mediachg(mii);
3443
3444                 /*
3445                  * Force an interrupt so that we will call bge_link_upd
3446                  * if needed and clear any pending link state attention.
3447                  * Without this we are not getting any further interrupts
3448                  * for link state changes and thus will not UP the link and
3449                  * not be able to send in bge_start.  The only way to get
3450                  * things working was to receive a packet and get an RX
3451                  * intr.
3452                  *
3453                  * bge_tick should help for fiber cards and we might not
3454                  * need to do this here if BGE_FLAG_TBI is set but as
3455                  * we poll for fiber anyway it should not harm.
3456                  */
3457                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3458                     BGE_IS_5788(sc))
3459                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3460                 else
3461                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3462         }
3463         return(0);
3464 }
3465
3466 /*
3467  * Report current media status.
3468  */
3469 static void
3470 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3471 {
3472         struct bge_softc *sc = ifp->if_softc;
3473
3474         if (sc->bge_flags & BGE_FLAG_TBI) {
3475                 ifmr->ifm_status = IFM_AVALID;
3476                 ifmr->ifm_active = IFM_ETHER;
3477                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3478                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3479                         ifmr->ifm_status |= IFM_ACTIVE;
3480                 } else {
3481                         ifmr->ifm_active |= IFM_NONE;
3482                         return;
3483                 }
3484
3485                 ifmr->ifm_active |= IFM_1000_SX;
3486                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3487                         ifmr->ifm_active |= IFM_HDX;
3488                 else
3489                         ifmr->ifm_active |= IFM_FDX;
3490         } else {
3491                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3492
3493                 mii_pollstat(mii);
3494                 ifmr->ifm_active = mii->mii_media_active;
3495                 ifmr->ifm_status = mii->mii_media_status;
3496         }
3497 }
3498
3499 static int
3500 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3501 {
3502         struct bge_softc *sc = ifp->if_softc;
3503         struct ifreq *ifr = (struct ifreq *)data;
3504         int mask, error = 0;
3505
3506         ASSERT_SERIALIZED(ifp->if_serializer);
3507
3508         switch (command) {
3509         case SIOCSIFMTU:
3510                 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3511                     (BGE_IS_JUMBO_CAPABLE(sc) &&
3512                      ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3513                         error = EINVAL;
3514                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3515                         ifp->if_mtu = ifr->ifr_mtu;
3516                         if (ifp->if_flags & IFF_RUNNING)
3517                                 bge_init(sc);
3518                 }
3519                 break;
3520         case SIOCSIFFLAGS:
3521                 if (ifp->if_flags & IFF_UP) {
3522                         if (ifp->if_flags & IFF_RUNNING) {
3523                                 mask = ifp->if_flags ^ sc->bge_if_flags;
3524
3525                                 /*
3526                                  * If only the state of the PROMISC flag
3527                                  * changed, then just use the 'set promisc
3528                                  * mode' command instead of reinitializing
3529                                  * the entire NIC. Doing a full re-init
3530                                  * means reloading the firmware and waiting
3531                                  * for it to start up, which may take a
3532                                  * second or two.  Similarly for ALLMULTI.
3533                                  */
3534                                 if (mask & IFF_PROMISC)
3535                                         bge_setpromisc(sc);
3536                                 if (mask & IFF_ALLMULTI)
3537                                         bge_setmulti(sc);
3538                         } else {
3539                                 bge_init(sc);
3540                         }
3541                 } else if (ifp->if_flags & IFF_RUNNING) {
3542                         bge_stop(sc);
3543                 }
3544                 sc->bge_if_flags = ifp->if_flags;
3545                 break;
3546         case SIOCADDMULTI:
3547         case SIOCDELMULTI:
3548                 if (ifp->if_flags & IFF_RUNNING)
3549                         bge_setmulti(sc);
3550                 break;
3551         case SIOCSIFMEDIA:
3552         case SIOCGIFMEDIA:
3553                 if (sc->bge_flags & BGE_FLAG_TBI) {
3554                         error = ifmedia_ioctl(ifp, ifr,
3555                             &sc->bge_ifmedia, command);
3556                 } else {
3557                         struct mii_data *mii;
3558
3559                         mii = device_get_softc(sc->bge_miibus);
3560                         error = ifmedia_ioctl(ifp, ifr,
3561                                               &mii->mii_media, command);
3562                 }
3563                 break;
3564         case SIOCSIFCAP:
3565                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3566                 if (mask & IFCAP_HWCSUM) {
3567                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3568                         if (IFCAP_HWCSUM & ifp->if_capenable)
3569                                 ifp->if_hwassist = BGE_CSUM_FEATURES;
3570                         else
3571                                 ifp->if_hwassist = 0;
3572                 }
3573                 break;
3574         default:
3575                 error = ether_ioctl(ifp, command, data);
3576                 break;
3577         }
3578         return error;
3579 }
3580
3581 static void
3582 bge_watchdog(struct ifnet *ifp)
3583 {
3584         struct bge_softc *sc = ifp->if_softc;
3585
3586         if_printf(ifp, "watchdog timeout -- resetting\n");
3587
3588         bge_init(sc);
3589
3590         ifp->if_oerrors++;
3591
3592         if (!ifq_is_empty(&ifp->if_snd))
3593                 if_devstart(ifp);
3594 }
3595
3596 /*
3597  * Stop the adapter and free any mbufs allocated to the
3598  * RX and TX lists.
3599  */
3600 static void
3601 bge_stop(struct bge_softc *sc)
3602 {
3603         struct ifnet *ifp = &sc->arpcom.ac_if;
3604
3605         ASSERT_SERIALIZED(ifp->if_serializer);
3606
3607         callout_stop(&sc->bge_stat_timer);
3608
3609         /*
3610          * Disable all of the receiver blocks
3611          */
3612         bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3613         bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3614         bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3615         if (BGE_IS_5700_FAMILY(sc))
3616                 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3617         bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3618         bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3619         bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3620
3621         /*
3622          * Disable all of the transmit blocks
3623          */
3624         bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3625         bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3626         bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3627         bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3628         bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3629         if (BGE_IS_5700_FAMILY(sc))
3630                 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3631         bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3632
3633         /*
3634          * Shut down all of the memory managers and related
3635          * state machines.
3636          */
3637         bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3638         bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3639         if (BGE_IS_5700_FAMILY(sc))
3640                 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3641         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3642         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3643         if (!BGE_IS_5705_PLUS(sc)) {
3644                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3645                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3646         }
3647
3648         /* Disable host interrupts. */
3649         bge_disable_intr(sc);
3650
3651         /*
3652          * Tell firmware we're shutting down.
3653          */
3654         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3655
3656         /* Free the RX lists. */
3657         bge_free_rx_ring_std(sc);
3658
3659         /* Free jumbo RX list. */
3660         if (BGE_IS_JUMBO_CAPABLE(sc))
3661                 bge_free_rx_ring_jumbo(sc);
3662
3663         /* Free TX buffers. */
3664         bge_free_tx_ring(sc);
3665
3666         sc->bge_link = 0;
3667         sc->bge_coal_chg = 0;
3668
3669         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3670
3671         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3672         ifp->if_timer = 0;
3673 }
3674
3675 /*
3676  * Stop all chip I/O so that the kernel's probe routines don't
3677  * get confused by errant DMAs when rebooting.
3678  */
3679 static void
3680 bge_shutdown(device_t dev)
3681 {
3682         struct bge_softc *sc = device_get_softc(dev);
3683         struct ifnet *ifp = &sc->arpcom.ac_if;
3684
3685         lwkt_serialize_enter(ifp->if_serializer);
3686         bge_stop(sc);
3687         bge_reset(sc);
3688         lwkt_serialize_exit(ifp->if_serializer);
3689 }
3690
3691 static int
3692 bge_suspend(device_t dev)
3693 {
3694         struct bge_softc *sc = device_get_softc(dev);
3695         struct ifnet *ifp = &sc->arpcom.ac_if;
3696
3697         lwkt_serialize_enter(ifp->if_serializer);
3698         bge_stop(sc);
3699         lwkt_serialize_exit(ifp->if_serializer);
3700
3701         return 0;
3702 }
3703
3704 static int
3705 bge_resume(device_t dev)
3706 {
3707         struct bge_softc *sc = device_get_softc(dev);
3708         struct ifnet *ifp = &sc->arpcom.ac_if;
3709
3710         lwkt_serialize_enter(ifp->if_serializer);
3711
3712         if (ifp->if_flags & IFF_UP) {
3713                 bge_init(sc);
3714
3715                 if (!ifq_is_empty(&ifp->if_snd))
3716                         if_devstart(ifp);
3717         }
3718
3719         lwkt_serialize_exit(ifp->if_serializer);
3720
3721         return 0;
3722 }
3723
3724 static void
3725 bge_setpromisc(struct bge_softc *sc)
3726 {
3727         struct ifnet *ifp = &sc->arpcom.ac_if;
3728
3729         if (ifp->if_flags & IFF_PROMISC)
3730                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3731         else
3732                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3733 }
3734
3735 static void
3736 bge_dma_free(struct bge_softc *sc)
3737 {
3738         int i;
3739
3740         /* Destroy RX mbuf DMA stuffs. */
3741         if (sc->bge_cdata.bge_rx_mtag != NULL) {
3742                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3743                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3744                             sc->bge_cdata.bge_rx_std_dmamap[i]);
3745                 }
3746                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3747                                    sc->bge_cdata.bge_rx_tmpmap);
3748                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3749         }
3750
3751         /* Destroy TX mbuf DMA stuffs. */
3752         if (sc->bge_cdata.bge_tx_mtag != NULL) {
3753                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3754                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3755                             sc->bge_cdata.bge_tx_dmamap[i]);
3756                 }
3757                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3758         }
3759
3760         /* Destroy standard RX ring */
3761         bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3762                            sc->bge_cdata.bge_rx_std_ring_map,
3763                            sc->bge_ldata.bge_rx_std_ring);
3764
3765         if (BGE_IS_JUMBO_CAPABLE(sc))
3766                 bge_free_jumbo_mem(sc);
3767
3768         /* Destroy RX return ring */
3769         bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3770                            sc->bge_cdata.bge_rx_return_ring_map,
3771                            sc->bge_ldata.bge_rx_return_ring);
3772
3773         /* Destroy TX ring */
3774         bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3775                            sc->bge_cdata.bge_tx_ring_map,
3776                            sc->bge_ldata.bge_tx_ring);
3777
3778         /* Destroy status block */
3779         bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3780                            sc->bge_cdata.bge_status_map,
3781                            sc->bge_ldata.bge_status_block);
3782
3783         /* Destroy statistics block */
3784         bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3785                            sc->bge_cdata.bge_stats_map,
3786                            sc->bge_ldata.bge_stats);
3787
3788         /* Destroy the parent tag */
3789         if (sc->bge_cdata.bge_parent_tag != NULL)
3790                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3791 }
3792
3793 static int
3794 bge_dma_alloc(struct bge_softc *sc)
3795 {
3796         struct ifnet *ifp = &sc->arpcom.ac_if;
3797         int i, error;
3798         bus_addr_t lowaddr;
3799
3800         lowaddr = BUS_SPACE_MAXADDR;
3801         if (sc->bge_flags & BGE_FLAG_MAXADDR_40BIT)
3802                 lowaddr = BGE_DMA_MAXADDR_40BIT;
3803
3804         /*
3805          * Allocate the parent bus DMA tag appropriate for PCI.
3806          *
3807          * All of the NetExtreme/NetLink controllers have 4GB boundary
3808          * DMA bug.
3809          * Whenever an address crosses a multiple of the 4GB boundary
3810          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3811          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3812          * state machine will lockup and cause the device to hang.
3813          */
3814         error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
3815                                    lowaddr, BUS_SPACE_MAXADDR,
3816                                    NULL, NULL,
3817                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3818                                    BUS_SPACE_MAXSIZE_32BIT,
3819                                    0, &sc->bge_cdata.bge_parent_tag);
3820         if (error) {
3821                 if_printf(ifp, "could not allocate parent dma tag\n");
3822                 return error;
3823         }
3824
3825         /*
3826          * Create DMA tag and maps for RX mbufs.
3827          */
3828         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3829                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3830                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
3831                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3832                                    &sc->bge_cdata.bge_rx_mtag);
3833         if (error) {
3834                 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
3835                 return error;
3836         }
3837
3838         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3839                                   BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_tmpmap);
3840         if (error) {
3841                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3842                 sc->bge_cdata.bge_rx_mtag = NULL;
3843                 return error;
3844         }
3845
3846         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3847                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3848                                           BUS_DMA_WAITOK,
3849                                           &sc->bge_cdata.bge_rx_std_dmamap[i]);
3850                 if (error) {
3851                         int j;
3852
3853                         for (j = 0; j < i; ++j) {
3854                                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3855                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3856                         }
3857                         bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3858                         sc->bge_cdata.bge_rx_mtag = NULL;
3859
3860                         if_printf(ifp, "could not create DMA map for RX\n");
3861                         return error;
3862                 }
3863         }
3864
3865         /*
3866          * Create DMA tag and maps for TX mbufs.
3867          */
3868         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3869                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3870                                    NULL, NULL,
3871                                    BGE_JUMBO_FRAMELEN, BGE_NSEG_NEW, MCLBYTES,
3872                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
3873                                    BUS_DMA_ONEBPAGE,
3874                                    &sc->bge_cdata.bge_tx_mtag);
3875         if (error) {
3876                 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
3877                 return error;
3878         }
3879
3880         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3881                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag,
3882                                           BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
3883                                           &sc->bge_cdata.bge_tx_dmamap[i]);
3884                 if (error) {
3885                         int j;
3886
3887                         for (j = 0; j < i; ++j) {
3888                                 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3889                                         sc->bge_cdata.bge_tx_dmamap[j]);
3890                         }
3891                         bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3892                         sc->bge_cdata.bge_tx_mtag = NULL;
3893
3894                         if_printf(ifp, "could not create DMA map for TX\n");
3895                         return error;
3896                 }
3897         }
3898
3899         /*
3900          * Create DMA stuffs for standard RX ring.
3901          */
3902         error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3903                                     &sc->bge_cdata.bge_rx_std_ring_tag,
3904                                     &sc->bge_cdata.bge_rx_std_ring_map,
3905                                     (void *)&sc->bge_ldata.bge_rx_std_ring,
3906                                     &sc->bge_ldata.bge_rx_std_ring_paddr);
3907         if (error) {
3908                 if_printf(ifp, "could not create std RX ring\n");
3909                 return error;
3910         }
3911
3912         /*
3913          * Create jumbo buffer pool.
3914          */
3915         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3916                 error = bge_alloc_jumbo_mem(sc);
3917                 if (error) {
3918                         if_printf(ifp, "could not create jumbo buffer pool\n");
3919                         return error;
3920                 }
3921         }
3922
3923         /*
3924          * Create DMA stuffs for RX return ring.
3925          */
3926         error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3927                                     &sc->bge_cdata.bge_rx_return_ring_tag,
3928                                     &sc->bge_cdata.bge_rx_return_ring_map,
3929                                     (void *)&sc->bge_ldata.bge_rx_return_ring,
3930                                     &sc->bge_ldata.bge_rx_return_ring_paddr);
3931         if (error) {
3932                 if_printf(ifp, "could not create RX ret ring\n");
3933                 return error;
3934         }
3935
3936         /*
3937          * Create DMA stuffs for TX ring.
3938          */
3939         error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
3940                                     &sc->bge_cdata.bge_tx_ring_tag,
3941                                     &sc->bge_cdata.bge_tx_ring_map,
3942                                     (void *)&sc->bge_ldata.bge_tx_ring,
3943                                     &sc->bge_ldata.bge_tx_ring_paddr);
3944         if (error) {
3945                 if_printf(ifp, "could not create TX ring\n");
3946                 return error;
3947         }
3948
3949         /*
3950          * Create DMA stuffs for status block.
3951          */
3952         error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3953                                     &sc->bge_cdata.bge_status_tag,
3954                                     &sc->bge_cdata.bge_status_map,
3955                                     (void *)&sc->bge_ldata.bge_status_block,
3956                                     &sc->bge_ldata.bge_status_block_paddr);
3957         if (error) {
3958                 if_printf(ifp, "could not create status block\n");
3959                 return error;
3960         }
3961
3962         /*
3963          * Create DMA stuffs for statistics block.
3964          */
3965         error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
3966                                     &sc->bge_cdata.bge_stats_tag,
3967                                     &sc->bge_cdata.bge_stats_map,
3968                                     (void *)&sc->bge_ldata.bge_stats,
3969                                     &sc->bge_ldata.bge_stats_paddr);
3970         if (error) {
3971                 if_printf(ifp, "could not create stats block\n");
3972                 return error;
3973         }
3974         return 0;
3975 }
3976
3977 static int
3978 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3979                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3980 {
3981         bus_dmamem_t dmem;
3982         int error;
3983
3984         error = bus_dmamem_coherent(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
3985                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3986                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3987         if (error)
3988                 return error;
3989
3990         *tag = dmem.dmem_tag;
3991         *map = dmem.dmem_map;
3992         *addr = dmem.dmem_addr;
3993         *paddr = dmem.dmem_busaddr;
3994
3995         return 0;
3996 }
3997
3998 static void
3999 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
4000 {
4001         if (tag != NULL) {
4002                 bus_dmamap_unload(tag, map);
4003                 bus_dmamem_free(tag, addr, map);
4004                 bus_dma_tag_destroy(tag);
4005         }
4006 }
4007
4008 /*
4009  * Grrr. The link status word in the status block does
4010  * not work correctly on the BCM5700 rev AX and BX chips,
4011  * according to all available information. Hence, we have
4012  * to enable MII interrupts in order to properly obtain
4013  * async link changes. Unfortunately, this also means that
4014  * we have to read the MAC status register to detect link
4015  * changes, thereby adding an additional register access to
4016  * the interrupt handler.
4017  *
4018  * XXX: perhaps link state detection procedure used for
4019  * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
4020  */
4021 static void
4022 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
4023 {
4024         struct ifnet *ifp = &sc->arpcom.ac_if;
4025         struct mii_data *mii = device_get_softc(sc->bge_miibus);
4026
4027         mii_pollstat(mii);
4028
4029         if (!sc->bge_link &&
4030             (mii->mii_media_status & IFM_ACTIVE) &&
4031             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4032                 sc->bge_link++;
4033                 if (bootverbose)
4034                         if_printf(ifp, "link UP\n");
4035         } else if (sc->bge_link &&
4036             (!(mii->mii_media_status & IFM_ACTIVE) ||
4037             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4038                 sc->bge_link = 0;
4039                 if (bootverbose)
4040                         if_printf(ifp, "link DOWN\n");
4041         }
4042
4043         /* Clear the interrupt. */
4044         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
4045         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
4046         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
4047 }
4048
4049 static void
4050 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
4051 {
4052         struct ifnet *ifp = &sc->arpcom.ac_if;
4053
4054 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
4055
4056         /*
4057          * Sometimes PCS encoding errors are detected in
4058          * TBI mode (on fiber NICs), and for some reason
4059          * the chip will signal them as link changes.
4060          * If we get a link change event, but the 'PCS
4061          * encoding error' bit in the MAC status register
4062          * is set, don't bother doing a link check.
4063          * This avoids spurious "gigabit link up" messages
4064          * that sometimes appear on fiber NICs during
4065          * periods of heavy traffic.
4066          */
4067         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4068                 if (!sc->bge_link) {
4069                         sc->bge_link++;
4070                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4071                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
4072                                     BGE_MACMODE_TBI_SEND_CFGS);
4073                         }
4074                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4075
4076                         if (bootverbose)
4077                                 if_printf(ifp, "link UP\n");
4078
4079                         ifp->if_link_state = LINK_STATE_UP;
4080                         if_link_state_change(ifp);
4081                 }
4082         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
4083                 if (sc->bge_link) {
4084                         sc->bge_link = 0;
4085
4086                         if (bootverbose)
4087                                 if_printf(ifp, "link DOWN\n");
4088
4089                         ifp->if_link_state = LINK_STATE_DOWN;
4090                         if_link_state_change(ifp);
4091                 }
4092         }
4093
4094 #undef PCS_ENCODE_ERR
4095
4096         /* Clear the attention. */
4097         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4098             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4099             BGE_MACSTAT_LINK_CHANGED);
4100 }
4101
4102 static void
4103 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
4104 {
4105         struct ifnet *ifp = &sc->arpcom.ac_if;
4106         struct mii_data *mii = device_get_softc(sc->bge_miibus);
4107
4108         mii_pollstat(mii);
4109         bge_miibus_statchg(sc->bge_dev);
4110
4111         if (bootverbose) {
4112                 if (sc->bge_link)
4113                         if_printf(ifp, "link UP\n");
4114                 else
4115                         if_printf(ifp, "link DOWN\n");
4116         }
4117
4118         /* Clear the attention. */
4119         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4120             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4121             BGE_MACSTAT_LINK_CHANGED);
4122 }
4123
4124 static void
4125 bge_autopoll_link_upd(struct bge_softc *sc, uint32_t status __unused)
4126 {
4127         struct ifnet *ifp = &sc->arpcom.ac_if;
4128         struct mii_data *mii = device_get_softc(sc->bge_miibus);
4129
4130         mii_pollstat(mii);
4131
4132         if (!sc->bge_link &&
4133             (mii->mii_media_status & IFM_ACTIVE) &&
4134             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4135                 sc->bge_link++;
4136                 if (bootverbose)
4137                         if_printf(ifp, "link UP\n");
4138         } else if (sc->bge_link &&
4139             (!(mii->mii_media_status & IFM_ACTIVE) ||
4140             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4141                 sc->bge_link = 0;
4142                 if (bootverbose)
4143                         if_printf(ifp, "link DOWN\n");
4144         }
4145
4146         /* Clear the attention. */
4147         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4148             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4149             BGE_MACSTAT_LINK_CHANGED);
4150 }
4151
4152 static int
4153 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
4154 {
4155         struct bge_softc *sc = arg1;
4156
4157         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4158                                    &sc->bge_rx_coal_ticks,
4159                                    BGE_RX_COAL_TICKS_CHG);
4160 }
4161
4162 static int
4163 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
4164 {
4165         struct bge_softc *sc = arg1;
4166
4167         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4168                                    &sc->bge_tx_coal_ticks,
4169                                    BGE_TX_COAL_TICKS_CHG);
4170 }
4171
4172 static int
4173 bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS)
4174 {
4175         struct bge_softc *sc = arg1;
4176
4177         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4178                                    &sc->bge_rx_max_coal_bds,
4179                                    BGE_RX_MAX_COAL_BDS_CHG);
4180 }
4181
4182 static int
4183 bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS)
4184 {
4185         struct bge_softc *sc = arg1;
4186
4187         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4188                                    &sc->bge_tx_max_coal_bds,
4189                                    BGE_TX_MAX_COAL_BDS_CHG);
4190 }
4191
4192 static int
4193 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
4194                     uint32_t coal_chg_mask)
4195 {
4196         struct bge_softc *sc = arg1;
4197         struct ifnet *ifp = &sc->arpcom.ac_if;
4198         int error = 0, v;
4199
4200         lwkt_serialize_enter(ifp->if_serializer);
4201
4202         v = *coal;
4203         error = sysctl_handle_int(oidp, &v, 0, req);
4204         if (!error && req->newptr != NULL) {
4205                 if (v < 0) {
4206                         error = EINVAL;
4207                 } else {
4208                         *coal = v;
4209                         sc->bge_coal_chg |= coal_chg_mask;
4210                 }
4211         }
4212
4213         lwkt_serialize_exit(ifp->if_serializer);
4214         return error;
4215 }
4216
4217 static void
4218 bge_coal_change(struct bge_softc *sc)
4219 {
4220         struct ifnet *ifp = &sc->arpcom.ac_if;
4221         uint32_t val;
4222
4223         ASSERT_SERIALIZED(ifp->if_serializer);
4224
4225         if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
4226                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
4227                             sc->bge_rx_coal_ticks);
4228                 DELAY(10);
4229                 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
4230
4231                 if (bootverbose) {
4232                         if_printf(ifp, "rx_coal_ticks -> %u\n",
4233                                   sc->bge_rx_coal_ticks);
4234                 }
4235         }
4236
4237         if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
4238                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
4239                             sc->bge_tx_coal_ticks);
4240                 DELAY(10);
4241                 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
4242
4243                 if (bootverbose) {
4244                         if_printf(ifp, "tx_coal_ticks -> %u\n",
4245                                   sc->bge_tx_coal_ticks);
4246                 }
4247         }
4248
4249         if (sc->bge_coal_chg & BGE_RX_MAX_COAL_BDS_CHG) {
4250                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
4251                             sc->bge_rx_max_coal_bds);
4252                 DELAY(10);
4253                 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
4254
4255                 if (bootverbose) {
4256                         if_printf(ifp, "rx_max_coal_bds -> %u\n",
4257                                   sc->bge_rx_max_coal_bds);
4258                 }
4259         }
4260
4261         if (sc->bge_coal_chg & BGE_TX_MAX_COAL_BDS_CHG) {
4262                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
4263                             sc->bge_tx_max_coal_bds);
4264                 DELAY(10);
4265                 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
4266
4267                 if (bootverbose) {
4268                         if_printf(ifp, "tx_max_coal_bds -> %u\n",
4269                                   sc->bge_tx_max_coal_bds);
4270                 }
4271         }
4272
4273         sc->bge_coal_chg = 0;
4274 }
4275
4276 static void
4277 bge_enable_intr(struct bge_softc *sc)
4278 {
4279         struct ifnet *ifp = &sc->arpcom.ac_if;
4280
4281         lwkt_serialize_handler_enable(ifp->if_serializer);
4282
4283         /*
4284          * Enable interrupt.
4285          */
4286         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4287
4288         /*
4289          * Unmask the interrupt when we stop polling.
4290          */
4291         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4292
4293         /*
4294          * Trigger another interrupt, since above writing
4295          * to interrupt mailbox0 may acknowledge pending
4296          * interrupt.
4297          */
4298         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4299 }
4300
4301 static void
4302 bge_disable_intr(struct bge_softc *sc)
4303 {
4304         struct ifnet *ifp = &sc->arpcom.ac_if;
4305
4306         /*
4307          * Mask the interrupt when we start polling.
4308          */
4309         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4310
4311         /*
4312          * Acknowledge possible asserted interrupt.
4313          */
4314         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4315
4316         lwkt_serialize_handler_disable(ifp->if_serializer);
4317 }
4318
4319 static int
4320 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
4321 {
4322         uint32_t mac_addr;
4323         int ret = 1;
4324
4325         mac_addr = bge_readmem_ind(sc, 0x0c14);
4326         if ((mac_addr >> 16) == 0x484b) {
4327                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4328                 ether_addr[1] = (uint8_t)mac_addr;
4329                 mac_addr = bge_readmem_ind(sc, 0x0c18);
4330                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4331                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4332                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4333                 ether_addr[5] = (uint8_t)mac_addr;
4334                 ret = 0;
4335         }
4336         return ret;
4337 }
4338
4339 static int
4340 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
4341 {
4342         int mac_offset = BGE_EE_MAC_OFFSET;
4343
4344         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
4345                 mac_offset = BGE_EE_MAC_OFFSET_5906;
4346
4347         return bge_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4348 }
4349
4350 static int
4351 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
4352 {
4353         if (sc->bge_flags & BGE_FLAG_NO_EEPROM)
4354                 return 1;
4355
4356         return bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4357                                ETHER_ADDR_LEN);
4358 }
4359
4360 static int
4361 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
4362 {
4363         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
4364                 /* NOTE: Order is critical */
4365                 bge_get_eaddr_mem,
4366                 bge_get_eaddr_nvram,
4367                 bge_get_eaddr_eeprom,
4368                 NULL
4369         };
4370         const bge_eaddr_fcn_t *func;
4371
4372         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
4373                 if ((*func)(sc, eaddr) == 0)
4374                         break;
4375         }
4376         return (*func == NULL ? ENXIO : 0);
4377 }
4378
4379 /*
4380  * NOTE: 'm' is not freed upon failure
4381  */
4382 struct mbuf *
4383 bge_defrag_shortdma(struct mbuf *m)
4384 {
4385         struct mbuf *n;
4386         int found;
4387
4388         /*
4389          * If device receive two back-to-back send BDs with less than
4390          * or equal to 8 total bytes then the device may hang.  The two
4391          * back-to-back send BDs must in the same frame for this failure
4392          * to occur.  Scan mbuf chains and see whether two back-to-back
4393          * send BDs are there.  If this is the case, allocate new mbuf
4394          * and copy the frame to workaround the silicon bug.
4395          */
4396         for (n = m, found = 0; n != NULL; n = n->m_next) {
4397                 if (n->m_len < 8) {
4398                         found++;
4399                         if (found > 1)
4400                                 break;
4401                         continue;
4402                 }
4403                 found = 0;
4404         }
4405
4406         if (found > 1)
4407                 n = m_defrag(m, MB_DONTWAIT);
4408         else
4409                 n = m;
4410         return n;
4411 }
4412
4413 static void
4414 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
4415 {
4416         int i;
4417
4418         BGE_CLRBIT(sc, reg, bit);
4419         for (i = 0; i < BGE_TIMEOUT; i++) {
4420                 if ((CSR_READ_4(sc, reg) & bit) == 0)
4421                         return;
4422                 DELAY(100);
4423         }
4424 }