2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
23 * Author: Shobhit Kumar <shobhit.kumar@intel.com>
28 #include <drm/drm_crtc.h>
29 #include <drm/drm_edid.h>
30 #include <drm/i915_drm.h>
31 #include <linux/slab.h>
32 #include <video/mipi_display.h>
33 #include <video/mipi_display.h>
35 #include "intel_drv.h"
36 #include "intel_dsi.h"
37 #include "intel_dsi_cmd.h"
39 #define MIPI_TRANSFER_MODE_SHIFT 0
40 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1
41 #define MIPI_PORT_SHIFT 3
43 #define PREPARE_CNT_MAX 0x3F
44 #define EXIT_ZERO_CNT_MAX 0x3F
45 #define CLK_ZERO_CNT_MAX 0xFF
46 #define TRAIL_CNT_MAX 0x1F
48 #define NS_KHZ_RATIO 1000000
50 #define GPI0_NC_0_HV_DDI0_HPD 0x4130
51 #define GPIO_NC_0_HV_DDI0_PAD 0x4138
52 #define GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
53 #define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD 0x4128
54 #define GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
55 #define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD 0x4118
56 #define GPIO_NC_3_PANEL0_VDDEN 0x4140
57 #define GPIO_NC_3_PANEL0_VDDEN_PAD 0x4148
58 #define GPIO_NC_4_PANEL0_BLKEN 0x4150
59 #define GPIO_NC_4_PANEL0_BLKEN_PAD 0x4158
60 #define GPIO_NC_5_PANEL0_BLKCTL 0x4160
61 #define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168
62 #define GPIO_NC_6_PCONF0 0x4180
63 #define GPIO_NC_6_PAD 0x4188
64 #define GPIO_NC_7_PCONF0 0x4190
65 #define GPIO_NC_7_PAD 0x4198
66 #define GPIO_NC_8_PCONF0 0x4170
67 #define GPIO_NC_8_PAD 0x4178
68 #define GPIO_NC_9_PCONF0 0x4100
69 #define GPIO_NC_9_PAD 0x4108
70 #define GPIO_NC_10_PCONF0 0x40E0
71 #define GPIO_NC_10_PAD 0x40E8
72 #define GPIO_NC_11_PCONF0 0x40F0
73 #define GPIO_NC_11_PAD 0x40F8
81 static struct gpio_table gtable[] = {
82 { GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 },
83 { GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 },
84 { GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 },
85 { GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 },
86 { GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 },
87 { GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 },
88 { GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 },
89 { GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 },
90 { GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 },
91 { GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 },
92 { GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0},
93 { GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
96 static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
98 u8 type, byte, mode, vc, port;
102 mode = (byte >> MIPI_TRANSFER_MODE_SHIFT) & 0x1;
103 vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3;
104 port = (byte >> MIPI_PORT_SHIFT) & 0x3;
107 intel_dsi->hs = mode;
109 /* get packet type and increment the pointer */
112 len = *((u16 *) data);
116 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
117 dsi_vc_generic_write_0(intel_dsi, vc);
119 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
120 dsi_vc_generic_write_1(intel_dsi, vc, *data);
122 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
123 dsi_vc_generic_write_2(intel_dsi, vc, *data, *(data + 1));
125 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
126 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
127 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
128 DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
130 case MIPI_DSI_GENERIC_LONG_WRITE:
131 dsi_vc_generic_write(intel_dsi, vc, data, len);
133 case MIPI_DSI_DCS_SHORT_WRITE:
134 dsi_vc_dcs_write_0(intel_dsi, vc, *data);
136 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
137 dsi_vc_dcs_write_1(intel_dsi, vc, *data, *(data + 1));
139 case MIPI_DSI_DCS_READ:
140 DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
142 case MIPI_DSI_DCS_LONG_WRITE:
143 dsi_vc_dcs_write(intel_dsi, vc, data, len);
152 static u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, u8 *data)
154 u32 delay = *((u32 *) data);
156 usleep_range(delay, delay + 10);
162 static u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, u8 *data)
167 struct drm_device *dev = intel_dsi->base.base.dev;
168 struct drm_i915_private *dev_priv = dev->dev_private;
175 function = gtable[gpio].function_reg;
176 pad = gtable[gpio].pad_reg;
178 mutex_lock(&dev_priv->dpio_lock);
179 if (!gtable[gpio].init) {
180 /* program the function */
181 /* FIXME: remove constant below */
182 vlv_gpio_nc_write(dev_priv, function, 0x2000CC00);
183 gtable[gpio].init = 1;
189 vlv_gpio_nc_write(dev_priv, pad, val);
190 mutex_unlock(&dev_priv->dpio_lock);
195 typedef u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, u8 *data);
196 static const fn_mipi_elem_exec exec_elem[] = {
198 mipi_exec_send_packet,
201 NULL, /* status read; later */
205 * MIPI Sequence from VBT #53 parsing logic
206 * We have already separated each seqence during bios parsing
207 * Following is generic execution function for any sequence
210 static const char * const seq_name[] = {
212 "MIPI_SEQ_ASSERT_RESET",
214 "MIPI_SEQ_DISPLAY_ON",
215 "MIPI_SEQ_DISPLAY_OFF",
216 "MIPI_SEQ_DEASSERT_RESET"
219 static void generic_exec_sequence(struct intel_dsi *intel_dsi, char *sequence)
222 fn_mipi_elem_exec mipi_elem_exec;
228 DRM_DEBUG_DRIVER("Starting MIPI sequence - %s\n", seq_name[*data]);
230 /* go to the first element of the sequence */
233 /* parse each byte till we reach end of sequence byte - 0x00 */
236 mipi_elem_exec = exec_elem[index];
237 if (!mipi_elem_exec) {
238 DRM_ERROR("Unsupported MIPI element, skipping sequence execution\n");
242 /* goto element payload */
245 /* execute the element specific rotines */
246 data = mipi_elem_exec(intel_dsi, data);
249 * After processing the element, data should point to
250 * next element or end of sequence
251 * check if have we reached end of sequence
258 static bool generic_init(struct intel_dsi_device *dsi)
260 struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
261 struct drm_device *dev = intel_dsi->base.base.dev;
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
264 struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
265 struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
266 u32 bits_per_pixel = 24;
267 u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
269 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
270 u32 ths_prepare_ns, tclk_trail_ns;
271 u32 tclk_prepare_clkzero, ths_prepare_hszero;
272 u32 lp_to_hs_switch, hs_to_lp_switch;
273 u32 pclk, computed_ddr;
274 u16 burst_mode_ratio;
278 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
279 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
280 intel_dsi->lane_count = mipi_config->lane_cnt + 1;
281 intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
283 if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
285 else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565)
288 intel_dsi->operation_mode = mipi_config->is_cmd_mode;
289 intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
290 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
291 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
292 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
293 intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
294 intel_dsi->init_count = mipi_config->master_init_timer;
295 intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
296 intel_dsi->video_frmt_cfg_bits =
297 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
302 * Target ddr frequency from VBT / non burst ddr freq
303 * multiply by 100 to preserve remainder
305 if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
306 if (mipi_config->target_burst_mode_freq) {
308 (pclk * bits_per_pixel) / intel_dsi->lane_count;
310 if (mipi_config->target_burst_mode_freq <
312 DRM_ERROR("Burst mode freq is less than computed\n");
316 burst_mode_ratio = DIV_ROUND_UP(
317 mipi_config->target_burst_mode_freq * 100,
320 pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100);
322 DRM_ERROR("Burst mode target is not set\n");
326 burst_mode_ratio = 100;
328 intel_dsi->burst_mode_ratio = burst_mode_ratio;
329 intel_dsi->pclk = pclk;
331 bitrate = (pclk * bits_per_pixel) / intel_dsi->lane_count;
333 switch (intel_dsi->escape_clk_div) {
349 switch (intel_dsi->lane_count) {
352 extra_byte_count = 2;
355 extra_byte_count = 4;
359 extra_byte_count = 3;
364 * ui(s) = 1/f [f in hz]
365 * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz)
369 ui_num = NS_KHZ_RATIO;
372 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
373 ths_prepare_hszero = mipi_config->ths_prepare_hszero;
377 * LP byte clock = TLPX/ (8UI)
379 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
381 /* count values in UI = (ns value) * (bitrate / (2 * 10^6))
383 * Since txddrclkhs_i is 2xUI, all the count values programmed in
384 * DPHY param register are divided by 2
388 ths_prepare_ns = max(mipi_config->ths_prepare,
389 mipi_config->tclk_prepare);
390 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
392 /* exit zero count */
393 exit_zero_cnt = DIV_ROUND_UP(
394 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
399 * Exit zero is unified val ths_zero and ths_exit
400 * minimum value for ths_exit = 110ns
401 * min (exit_zero_cnt * 2) = 110/UI
402 * exit_zero_cnt = 55/UI
404 if (exit_zero_cnt < (55 * ui_den / ui_num))
405 if ((55 * ui_den) % ui_num)
409 clk_zero_cnt = DIV_ROUND_UP(
410 (tclk_prepare_clkzero - ths_prepare_ns)
411 * ui_den, 2 * ui_num);
414 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
415 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
417 if (prepare_cnt > PREPARE_CNT_MAX ||
418 exit_zero_cnt > EXIT_ZERO_CNT_MAX ||
419 clk_zero_cnt > CLK_ZERO_CNT_MAX ||
420 trail_cnt > TRAIL_CNT_MAX)
421 DRM_DEBUG_DRIVER("Values crossing maximum limits, restricting to max values\n");
423 if (prepare_cnt > PREPARE_CNT_MAX)
424 prepare_cnt = PREPARE_CNT_MAX;
426 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX)
427 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
429 if (clk_zero_cnt > CLK_ZERO_CNT_MAX)
430 clk_zero_cnt = CLK_ZERO_CNT_MAX;
432 if (trail_cnt > TRAIL_CNT_MAX)
433 trail_cnt = TRAIL_CNT_MAX;
436 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
437 clk_zero_cnt << 8 | prepare_cnt;
440 * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2
441 * + 10UI + Extra Byte Count
443 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
444 * Extra Byte Count is calculated according to number of lanes.
445 * High Low Switch Count is the Max of LP to HS and
446 * HS to LP switch count
449 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
453 * The comment above does not match with the code */
454 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 +
455 exit_zero_cnt * 2 + 10, 8);
457 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
459 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
460 intel_dsi->hs_to_lp_count += extra_byte_count;
463 /* LP -> HS for clock lanes
464 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
466 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
467 * 2(in UI) + extra byte count
468 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
469 * 8 + extra byte count
471 intel_dsi->clk_lp_to_hs_count =
473 4 * tlpx_ui + prepare_cnt * 2 +
477 intel_dsi->clk_lp_to_hs_count += extra_byte_count;
479 /* HS->LP for Clock Lanes
480 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
482 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
483 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
486 intel_dsi->clk_hs_to_lp_count =
487 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
489 intel_dsi->clk_hs_to_lp_count += extra_byte_count;
491 DRM_DEBUG_KMS("Eot %s\n", intel_dsi->eotp_pkt ? "enabled" : "disabled");
492 DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ?
493 "disabled" : "enabled");
494 DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
495 DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
496 DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
497 DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
498 DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val);
499 DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count);
500 DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count);
501 DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
502 DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
503 DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count);
504 DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count);
505 DRM_DEBUG_KMS("BTA %s\n",
506 intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA ?
507 "disabled" : "enabled");
509 /* delays in VBT are in unit of 100us, so need to convert
511 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
512 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
513 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
514 intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
515 intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
516 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
521 static int generic_mode_valid(struct intel_dsi_device *dsi,
522 struct drm_display_mode *mode)
527 static bool generic_mode_fixup(struct intel_dsi_device *dsi,
528 const struct drm_display_mode *mode,
529 struct drm_display_mode *adjusted_mode) {
533 static void generic_panel_reset(struct intel_dsi_device *dsi)
535 struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
536 struct drm_device *dev = intel_dsi->base.base.dev;
537 struct drm_i915_private *dev_priv = dev->dev_private;
539 char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET];
541 generic_exec_sequence(intel_dsi, sequence);
544 static void generic_disable_panel_power(struct intel_dsi_device *dsi)
546 struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
547 struct drm_device *dev = intel_dsi->base.base.dev;
548 struct drm_i915_private *dev_priv = dev->dev_private;
550 char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET];
552 generic_exec_sequence(intel_dsi, sequence);
555 static void generic_send_otp_cmds(struct intel_dsi_device *dsi)
557 struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
558 struct drm_device *dev = intel_dsi->base.base.dev;
559 struct drm_i915_private *dev_priv = dev->dev_private;
561 char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
563 generic_exec_sequence(intel_dsi, sequence);
566 static void generic_enable(struct intel_dsi_device *dsi)
568 struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
569 struct drm_device *dev = intel_dsi->base.base.dev;
570 struct drm_i915_private *dev_priv = dev->dev_private;
572 char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_ON];
574 generic_exec_sequence(intel_dsi, sequence);
577 static void generic_disable(struct intel_dsi_device *dsi)
579 struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
580 struct drm_device *dev = intel_dsi->base.base.dev;
581 struct drm_i915_private *dev_priv = dev->dev_private;
583 char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_OFF];
585 generic_exec_sequence(intel_dsi, sequence);
588 static enum drm_connector_status generic_detect(struct intel_dsi_device *dsi)
590 return connector_status_connected;
593 static bool generic_get_hw_state(struct intel_dsi_device *dev)
598 static struct drm_display_mode *generic_get_modes(struct intel_dsi_device *dsi)
600 struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
601 struct drm_device *dev = intel_dsi->base.base.dev;
602 struct drm_i915_private *dev_priv = dev->dev_private;
604 dev_priv->vbt.lfp_lvds_vbt_mode->type |= DRM_MODE_TYPE_PREFERRED;
605 return dev_priv->vbt.lfp_lvds_vbt_mode;
608 static void generic_destroy(struct intel_dsi_device *dsi) { }
610 /* Callbacks. We might not need them all. */
611 struct intel_dsi_dev_ops vbt_generic_dsi_display_ops = {
612 .init = generic_init,
613 .mode_valid = generic_mode_valid,
614 .mode_fixup = generic_mode_fixup,
615 .panel_reset = generic_panel_reset,
616 .disable_panel_power = generic_disable_panel_power,
617 .send_otp_cmds = generic_send_otp_cmds,
618 .enable = generic_enable,
619 .disable = generic_disable,
620 .detect = generic_detect,
621 .get_hw_state = generic_get_hw_state,
622 .get_modes = generic_get_modes,
623 .destroy = generic_destroy,