2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.53 2008/08/02 01:14:40 dillon Exp $
34 #include "opt_compat_oldpci.h"
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/malloc.h>
39 #include <sys/module.h>
40 #include <sys/fcntl.h>
42 #include <sys/kernel.h>
43 #include <sys/queue.h>
44 #include <sys/types.h>
49 #include <vm/vm_extern.h>
53 #include <machine/smp.h>
54 #include "pci_cfgreg.h"
56 #include <sys/pciio.h>
59 #include "pci_private.h"
63 devclass_t pci_devclass;
64 const char *pcib_owner;
66 static void pci_read_capabilities(device_t dev, pcicfgregs *cfg);
67 static int pcie_slotimpl(const pcicfgregs *);
70 u_int32_t devid; /* Vendor/device of the card */
72 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
77 struct pci_quirk pci_quirks[] = {
79 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
81 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
82 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
83 /* As does the Serverworks OSB4 (the SMBus mapping register) */
84 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
89 /* map register information */
90 #define PCI_MAPMEM 0x01 /* memory map */
91 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
92 #define PCI_MAPPORT 0x04 /* port map */
94 static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
95 u_int32_t pci_numdevs = 0;
96 static u_int32_t pci_generation = 0;
99 pci_find_bsf(u_int8_t bus, u_int8_t slot, u_int8_t func)
101 struct pci_devinfo *dinfo;
103 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
104 if ((dinfo->cfg.bus == bus) &&
105 (dinfo->cfg.slot == slot) &&
106 (dinfo->cfg.func == func)) {
107 return (dinfo->cfg.dev);
115 pci_find_device(u_int16_t vendor, u_int16_t device)
117 struct pci_devinfo *dinfo;
119 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
120 if ((dinfo->cfg.vendor == vendor) &&
121 (dinfo->cfg.device == device)) {
122 return (dinfo->cfg.dev);
130 pcie_slot_implemented(device_t dev)
132 struct pci_devinfo *dinfo = device_get_ivars(dev);
134 return pcie_slotimpl(&dinfo->cfg);
137 /* return base address of memory or port map */
140 pci_mapbase(unsigned mapreg)
143 if ((mapreg & 0x01) == 0)
145 return (mapreg & ~mask);
148 /* return map type of memory or port map */
151 pci_maptype(unsigned mapreg)
153 static u_int8_t maptype[0x10] = {
154 PCI_MAPMEM, PCI_MAPPORT,
156 PCI_MAPMEM, PCI_MAPPORT,
158 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
159 PCI_MAPMEM|PCI_MAPMEMP, 0,
160 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
164 return maptype[mapreg & 0x0f];
167 /* return log2 of map size decoded for memory or port map */
170 pci_mapsize(unsigned testval)
174 testval = pci_mapbase(testval);
177 while ((testval & 1) == 0)
186 /* return log2 of address range supported by map register */
189 pci_maprange(unsigned mapreg)
192 switch (mapreg & 0x07) {
208 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
211 pci_fixancient(pcicfgregs *cfg)
213 if (cfg->hdrtype != 0)
216 /* PCI to PCI bridges use header type 1 */
217 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
221 /* read config data specific to header type 1 device (PCI to PCI bridge) */
224 pci_readppb(device_t pcib, int b, int s, int f)
228 p = kmalloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
230 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2);
231 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2);
233 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1);
235 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f,
237 PCIB_READ_CONFIG(pcib, b, s, f,
239 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f,
241 PCIB_READ_CONFIG(pcib, b, s, f,
242 PCIR_IOLIMITL_1, 1));
244 p->membase = PCI_PPBMEMBASE (0,
245 PCIB_READ_CONFIG(pcib, b, s, f,
247 p->memlimit = PCI_PPBMEMLIMIT (0,
248 PCIB_READ_CONFIG(pcib, b, s, f,
249 PCIR_MEMLIMIT_1, 2));
251 p->pmembase = PCI_PPBMEMBASE (
252 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4),
253 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2));
255 p->pmemlimit = PCI_PPBMEMLIMIT (
256 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,
258 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2));
263 /* read config data specific to header type 2 device (PCI to CardBus bridge) */
266 pci_readpcb(device_t pcib, int b, int s, int f)
270 p = kmalloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
272 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
273 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
275 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
277 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
278 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4);
279 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4);
280 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4);
282 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4);
283 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4);
284 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4);
285 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4);
287 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4);
291 /* extract header type specific config data */
294 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
296 #define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
297 switch (cfg->hdrtype) {
299 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
300 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
301 cfg->nummaps = PCI_MAXMAPS_0;
304 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
305 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
306 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
307 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1);
308 cfg->nummaps = PCI_MAXMAPS_1;
309 cfg->hdrspec = pci_readppb(pcib, b, s, f);
312 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
313 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
314 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
315 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1);
316 cfg->nummaps = PCI_MAXMAPS_2;
317 cfg->hdrspec = pci_readpcb(pcib, b, s, f);
323 /* read configuration header into pcicfgrect structure */
326 pci_read_device(device_t pcib, int b, int s, int f, size_t size)
328 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
330 pcicfgregs *cfg = NULL;
331 struct pci_devinfo *devlist_entry;
332 struct devlist *devlist_head;
334 devlist_head = &pci_devq;
336 devlist_entry = NULL;
338 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) {
340 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
342 cfg = &devlist_entry->cfg;
347 cfg->vendor = REG(PCIR_VENDOR, 2);
348 cfg->device = REG(PCIR_DEVICE, 2);
349 cfg->cmdreg = REG(PCIR_COMMAND, 2);
350 cfg->statreg = REG(PCIR_STATUS, 2);
351 cfg->baseclass = REG(PCIR_CLASS, 1);
352 cfg->subclass = REG(PCIR_SUBCLASS, 1);
353 cfg->progif = REG(PCIR_PROGIF, 1);
354 cfg->revid = REG(PCIR_REVID, 1);
355 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
356 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
357 cfg->lattimer = REG(PCIR_LATTIMER, 1);
358 cfg->intpin = REG(PCIR_INTPIN, 1);
359 cfg->intline = REG(PCIR_INTLINE, 1);
363 * If using the APIC the intpin is probably wrong, since it
364 * is often setup by the BIOS with the PIC in mind.
366 if (cfg->intpin != 0) {
369 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
371 /* PCI specific entry found in MP table */
372 if (airq != cfg->intline) {
373 undirect_pci_irq(cfg->intline);
378 * PCI interrupts might be redirected to the
379 * ISA bus according to some MP tables. Use the
380 * same methods as used by the ISA devices
381 * devices to find the proper IOAPIC int pin.
383 airq = isa_apic_irq(cfg->intline);
384 if ((airq >= 0) && (airq != cfg->intline)) {
385 /* XXX: undirect_pci_irq() ? */
386 undirect_isa_irq(cfg->intline);
393 cfg->mingnt = REG(PCIR_MINGNT, 1);
394 cfg->maxlat = REG(PCIR_MAXLAT, 1);
396 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
397 cfg->hdrtype &= ~PCIM_MFDEV;
400 pci_hdrtypedata(pcib, b, s, f, cfg);
401 pci_read_capabilities(pcib, cfg);
403 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
405 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
406 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
407 devlist_entry->conf.pc_sel.pc_func = cfg->func;
408 devlist_entry->conf.pc_hdr = cfg->hdrtype;
410 devlist_entry->conf.pc_subvendor = cfg->subvendor;
411 devlist_entry->conf.pc_subdevice = cfg->subdevice;
412 devlist_entry->conf.pc_vendor = cfg->vendor;
413 devlist_entry->conf.pc_device = cfg->device;
415 devlist_entry->conf.pc_class = cfg->baseclass;
416 devlist_entry->conf.pc_subclass = cfg->subclass;
417 devlist_entry->conf.pc_progif = cfg->progif;
418 devlist_entry->conf.pc_revid = cfg->revid;
423 return (devlist_entry);
428 pci_fixup_nextptr(int *nextptr0)
430 int nextptr = *nextptr0;
432 /* "Next pointer" is only one byte */
433 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr));
437 * PCI local bus spec 3.0:
439 * "... The bottom two bits of all pointers are reserved
440 * and must be implemented as 00b although software must
441 * mask them to allow for future uses of these bits ..."
444 kprintf("Illegal PCI extended capability "
445 "offset, fixup 0x%02x -> 0x%02x\n",
446 nextptr, nextptr & ~0x3);
452 if (nextptr < 0x40) {
454 kprintf("Illegal PCI extended capability "
455 "offset 0x%02x", nextptr);
463 pci_read_cap_pmgt(device_t pcib, int ptr, pcicfgregs *cfg)
466 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
468 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
473 pmgt->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
474 pmgt->pp_status = ptr + PCIR_POWER_STATUS;
475 pmgt->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
478 * Following way may be used to to test whether
479 * 'data' register exists:
480 * if 'data_select' register of
481 * PCIR_POWER_STATUS(bits[12,9]) is read-only
482 * then 'data' register is _not_ implemented.
490 pcie_slotimpl(const pcicfgregs *cfg)
492 const struct pcicfg_expr *expr = &cfg->expr;
496 * Only version 1 can be parsed currently
498 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
502 * - Slot implemented bit is meaningful iff current port is
503 * root port or down stream port.
504 * - Testing for root port or down stream port is meanningful
505 * iff PCI configure has type 1 header.
508 if (cfg->hdrtype != 1)
511 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
512 if (port_type != PCIE_ROOT_PORT && port_type != PCIE_DOWN_STREAM_PORT)
515 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
522 pci_read_cap_expr(device_t pcib, int ptr, pcicfgregs *cfg)
525 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
527 struct pcicfg_expr *expr = &cfg->expr;
529 expr->expr_ptr = ptr;
530 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2);
533 * Only version 1 can be parsed currently
535 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
539 * Read slot capabilities. Slot capabilities exists iff
540 * current port's slot is implemented
542 if (pcie_slotimpl(cfg))
543 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4);
549 pci_read_capabilities(device_t pcib, pcicfgregs *cfg)
552 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
556 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
557 /* No capabilities */
561 switch (cfg->hdrtype) {
564 ptrptr = PCIR_CAP_PTR;
567 ptrptr = PCIR_CAP_PTR_2;
570 return; /* No capabilities support */
572 nextptr = REG(ptrptr, 1);
575 * Read capability entries.
577 while (pci_fixup_nextptr(&nextptr)) {
580 /* Process this entry */
581 switch (REG(ptr, 1)) {
582 case PCIY_PMG: /* PCI power management */
583 pci_read_cap_pmgt(pcib, ptr, cfg);
585 case PCIY_PCIX: /* PCI-X */
586 cfg->pcixcap_ptr = ptr;
588 case PCIY_EXPRESS: /* PCI Express */
589 pci_read_cap_expr(pcib, ptr, cfg);
595 /* Find the next entry */
596 nextptr = REG(ptr + 1, 1);
602 /* free pcicfgregs structure and all depending data structures */
605 pci_freecfg(struct pci_devinfo *dinfo)
607 struct devlist *devlist_head;
609 devlist_head = &pci_devq;
611 if (dinfo->cfg.hdrspec != NULL)
612 kfree(dinfo->cfg.hdrspec, M_DEVBUF);
613 /* XXX this hasn't been tested */
614 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
615 kfree(dinfo, M_DEVBUF);
617 /* increment the generation count */
620 /* we're losing one device */
627 * PCI power manangement
630 pci_set_powerstate_method(device_t dev, device_t child, int state)
632 struct pci_devinfo *dinfo = device_get_ivars(child);
633 pcicfgregs *cfg = &dinfo->cfg;
634 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
638 if (pmgt->pp_cap != 0) {
639 status = PCI_READ_CONFIG(dev, child, pmgt->pp_status, 2) & ~PCIM_PSTAT_DMASK;
642 case PCI_POWERSTATE_D0:
643 status |= PCIM_PSTAT_D0;
645 case PCI_POWERSTATE_D1:
646 if (pmgt->pp_cap & PCIM_PCAP_D1SUPP) {
647 status |= PCIM_PSTAT_D1;
652 case PCI_POWERSTATE_D2:
653 if (pmgt->pp_cap & PCIM_PCAP_D2SUPP) {
654 status |= PCIM_PSTAT_D2;
659 case PCI_POWERSTATE_D3:
660 status |= PCIM_PSTAT_D3;
666 PCI_WRITE_CONFIG(dev, child, pmgt->pp_status, status, 2);
674 pci_get_powerstate_method(device_t dev, device_t child)
676 struct pci_devinfo *dinfo = device_get_ivars(child);
677 pcicfgregs *cfg = &dinfo->cfg;
678 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
682 if (pmgt->pp_cap != 0) {
683 status = PCI_READ_CONFIG(dev, child, pmgt->pp_status, 2);
684 switch (status & PCIM_PSTAT_DMASK) {
686 result = PCI_POWERSTATE_D0;
689 result = PCI_POWERSTATE_D1;
692 result = PCI_POWERSTATE_D2;
695 result = PCI_POWERSTATE_D3;
698 result = PCI_POWERSTATE_UNKNOWN;
702 /* No support, device is always at D0 */
703 result = PCI_POWERSTATE_D0;
709 * Some convenience functions for PCI device drivers.
713 pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
717 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
719 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
723 pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
727 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
729 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
733 pci_enable_busmaster_method(device_t dev, device_t child)
735 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
740 pci_disable_busmaster_method(device_t dev, device_t child)
742 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
747 pci_enable_io_method(device_t dev, device_t child, int space)
758 bit = PCIM_CMD_PORTEN;
762 bit = PCIM_CMD_MEMEN;
768 pci_set_command_bit(dev, child, bit);
769 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
772 device_printf(child, "failed to enable %s mapping!\n", error);
777 pci_disable_io_method(device_t dev, device_t child, int space)
788 bit = PCIM_CMD_PORTEN;
792 bit = PCIM_CMD_MEMEN;
798 pci_clear_command_bit(dev, child, bit);
799 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
801 device_printf(child, "failed to disable %s mapping!\n", error);
808 * This is the user interface to PCI configuration space.
812 pci_open(struct dev_open_args *ap)
814 if ((ap->a_oflags & FWRITE) && securelevel > 0) {
821 pci_close(struct dev_close_args *ap)
827 * Match a single pci_conf structure against an array of pci_match_conf
828 * structures. The first argument, 'matches', is an array of num_matches
829 * pci_match_conf structures. match_buf is a pointer to the pci_conf
830 * structure that will be compared to every entry in the matches array.
831 * This function returns 1 on failure, 0 on success.
834 pci_conf_match(struct pci_match_conf *matches, int num_matches,
835 struct pci_conf *match_buf)
839 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
842 for (i = 0; i < num_matches; i++) {
844 * I'm not sure why someone would do this...but...
846 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
850 * Look at each of the match flags. If it's set, do the
851 * comparison. If the comparison fails, we don't have a
852 * match, go on to the next item if there is one.
854 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
855 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
858 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
859 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
862 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
863 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
866 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
867 && (match_buf->pc_vendor != matches[i].pc_vendor))
870 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
871 && (match_buf->pc_device != matches[i].pc_device))
874 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
875 && (match_buf->pc_class != matches[i].pc_class))
878 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
879 && (match_buf->pd_unit != matches[i].pd_unit))
882 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
883 && (strncmp(matches[i].pd_name, match_buf->pd_name,
884 sizeof(match_buf->pd_name)) != 0))
894 * Locate the parent of a PCI device by scanning the PCI devlist
895 * and return the entry for the parent.
896 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
897 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
901 pci_devlist_get_parent(pcicfgregs *cfg)
903 struct devlist *devlist_head;
904 struct pci_devinfo *dinfo;
905 pcicfgregs *bridge_cfg;
908 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
910 /* If the device is on PCI bus 0, look for the host */
912 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
913 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
914 bridge_cfg = &dinfo->cfg;
915 if (bridge_cfg->baseclass == PCIC_BRIDGE
916 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
917 && bridge_cfg->bus == cfg->bus) {
923 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
925 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
926 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
927 bridge_cfg = &dinfo->cfg;
928 if (bridge_cfg->baseclass == PCIC_BRIDGE
929 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
930 && bridge_cfg->secondarybus == cfg->bus) {
940 pci_ioctl(struct dev_ioctl_args *ap)
947 if (!(ap->a_fflag & FWRITE))
953 struct pci_devinfo *dinfo;
954 struct pci_conf_io *cio;
955 struct devlist *devlist_head;
956 struct pci_match_conf *pattern_buf;
961 cio = (struct pci_conf_io *)ap->a_data;
967 * Hopefully the user won't pass in a null pointer, but it
968 * can't hurt to check.
976 * If the user specified an offset into the device list,
977 * but the list has changed since they last called this
978 * ioctl, tell them that the list has changed. They will
979 * have to get the list from the beginning.
981 if ((cio->offset != 0)
982 && (cio->generation != pci_generation)){
983 cio->num_matches = 0;
984 cio->status = PCI_GETCONF_LIST_CHANGED;
990 * Check to see whether the user has asked for an offset
991 * past the end of our list.
993 if (cio->offset >= pci_numdevs) {
994 cio->num_matches = 0;
995 cio->status = PCI_GETCONF_LAST_DEVICE;
1000 /* get the head of the device queue */
1001 devlist_head = &pci_devq;
1004 * Determine how much room we have for pci_conf structures.
1005 * Round the user's buffer size down to the nearest
1006 * multiple of sizeof(struct pci_conf) in case the user
1007 * didn't specify a multiple of that size.
1009 iolen = min(cio->match_buf_len -
1010 (cio->match_buf_len % sizeof(struct pci_conf)),
1011 pci_numdevs * sizeof(struct pci_conf));
1014 * Since we know that iolen is a multiple of the size of
1015 * the pciconf union, it's okay to do this.
1017 ionum = iolen / sizeof(struct pci_conf);
1020 * If this test is true, the user wants the pci_conf
1021 * structures returned to match the supplied entries.
1023 if ((cio->num_patterns > 0)
1024 && (cio->pat_buf_len > 0)) {
1026 * pat_buf_len needs to be:
1027 * num_patterns * sizeof(struct pci_match_conf)
1028 * While it is certainly possible the user just
1029 * allocated a large buffer, but set the number of
1030 * matches correctly, it is far more likely that
1031 * their kernel doesn't match the userland utility
1032 * they're using. It's also possible that the user
1033 * forgot to initialize some variables. Yes, this
1034 * may be overly picky, but I hazard to guess that
1035 * it's far more likely to just catch folks that
1036 * updated their kernel but not their userland.
1038 if ((cio->num_patterns *
1039 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
1040 /* The user made a mistake, return an error*/
1041 cio->status = PCI_GETCONF_ERROR;
1042 kprintf("pci_ioctl: pat_buf_len %d != "
1043 "num_patterns (%d) * sizeof(struct "
1044 "pci_match_conf) (%d)\npci_ioctl: "
1045 "pat_buf_len should be = %d\n",
1046 cio->pat_buf_len, cio->num_patterns,
1047 (int)sizeof(struct pci_match_conf),
1048 (int)sizeof(struct pci_match_conf) *
1050 kprintf("pci_ioctl: do your headers match your "
1052 cio->num_matches = 0;
1058 * Check the user's buffer to make sure it's readable.
1060 if (!useracc((caddr_t)cio->patterns,
1061 cio->pat_buf_len, VM_PROT_READ)) {
1062 kprintf("pci_ioctl: pattern buffer %p, "
1063 "length %u isn't user accessible for"
1064 " READ\n", cio->patterns,
1070 * Allocate a buffer to hold the patterns.
1072 pattern_buf = kmalloc(cio->pat_buf_len, M_TEMP,
1074 error = copyin(cio->patterns, pattern_buf,
1078 num_patterns = cio->num_patterns;
1080 } else if ((cio->num_patterns > 0)
1081 || (cio->pat_buf_len > 0)) {
1083 * The user made a mistake, spit out an error.
1085 cio->status = PCI_GETCONF_ERROR;
1086 cio->num_matches = 0;
1087 kprintf("pci_ioctl: invalid GETCONF arguments\n");
1094 * Make sure we can write to the match buffer.
1096 if (!useracc((caddr_t)cio->matches,
1097 cio->match_buf_len, VM_PROT_WRITE)) {
1098 kprintf("pci_ioctl: match buffer %p, length %u "
1099 "isn't user accessible for WRITE\n",
1100 cio->matches, cio->match_buf_len);
1106 * Go through the list of devices and copy out the devices
1107 * that match the user's criteria.
1109 for (cio->num_matches = 0, error = 0, i = 0,
1110 dinfo = STAILQ_FIRST(devlist_head);
1111 (dinfo != NULL) && (cio->num_matches < ionum)
1112 && (error == 0) && (i < pci_numdevs);
1113 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
1115 if (i < cio->offset)
1118 /* Populate pd_name and pd_unit */
1120 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
1121 name = device_get_name(dinfo->cfg.dev);
1123 strncpy(dinfo->conf.pd_name, name,
1124 sizeof(dinfo->conf.pd_name));
1125 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
1126 dinfo->conf.pd_unit =
1127 device_get_unit(dinfo->cfg.dev);
1130 if ((pattern_buf == NULL) ||
1131 (pci_conf_match(pattern_buf, num_patterns,
1132 &dinfo->conf) == 0)) {
1135 * If we've filled up the user's buffer,
1136 * break out at this point. Since we've
1137 * got a match here, we'll pick right back
1138 * up at the matching entry. We can also
1139 * tell the user that there are more matches
1142 if (cio->num_matches >= ionum)
1145 error = copyout(&dinfo->conf,
1146 &cio->matches[cio->num_matches],
1147 sizeof(struct pci_conf));
1153 * Set the pointer into the list, so if the user is getting
1154 * n records at a time, where n < pci_numdevs,
1159 * Set the generation, the user will need this if they make
1160 * another ioctl call with offset != 0.
1162 cio->generation = pci_generation;
1165 * If this is the last device, inform the user so he won't
1166 * bother asking for more devices. If dinfo isn't NULL, we
1167 * know that there are more matches in the list because of
1168 * the way the traversal is done.
1171 cio->status = PCI_GETCONF_LAST_DEVICE;
1173 cio->status = PCI_GETCONF_MORE_DEVS;
1175 if (pattern_buf != NULL)
1176 kfree(pattern_buf, M_TEMP);
1181 io = (struct pci_io *)ap->a_data;
1182 switch(io->pi_width) {
1187 * Assume that the user-level bus number is
1188 * actually the pciN instance number. We map
1189 * from that to the real pcib+bus combination.
1191 pci = devclass_get_device(pci_devclass,
1195 * pci is the pci device and may contain
1196 * several children (for each function code).
1197 * The governing pci bus is the parent to
1202 pcib = device_get_parent(pci);
1203 b = pcib_get_bus(pcib);
1205 PCIB_READ_CONFIG(pcib,
1223 io = (struct pci_io *)ap->a_data;
1224 switch(io->pi_width) {
1229 * Assume that the user-level bus number is
1230 * actually the pciN instance number. We map
1231 * from that to the real pcib+bus combination.
1233 pci = devclass_get_device(pci_devclass,
1237 * pci is the pci device and may contain
1238 * several children (for each function code).
1239 * The governing pci bus is the parent to
1244 pcib = device_get_parent(pci);
1245 b = pcib_get_bus(pcib);
1246 PCIB_WRITE_CONFIG(pcib,
1274 static struct dev_ops pcic_ops = {
1275 { "pci", PCI_CDEV, 0 },
1277 .d_close = pci_close,
1278 .d_ioctl = pci_ioctl,
1284 * New style pci driver. Parent device is either a pci-host-bridge or a
1285 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1288 pci_class_to_string(int baseclass)
1305 case PCIC_MULTIMEDIA:
1306 name = "MULTIMEDIA";
1314 case PCIC_SIMPLECOMM:
1315 name = "SIMPLECOMM";
1317 case PCIC_BASEPERIPH:
1318 name = "BASEPERIPH";
1326 case PCIC_PROCESSOR:
1329 case PCIC_SERIALBUS:
1338 case PCIC_SATELLITE:
1358 pci_print_verbose_expr(const pcicfgregs *cfg)
1360 const struct pcicfg_expr *expr = &cfg->expr;
1361 const char *port_name;
1367 if (expr->expr_ptr == 0) /* No PCI Express capability */
1370 kprintf("\tPCI Express ver.%d cap=0x%04x",
1371 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap);
1372 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
1375 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
1377 switch (port_type) {
1378 case PCIE_END_POINT:
1379 port_name = "DEVICE";
1381 case PCIE_LEG_END_POINT:
1382 port_name = "LEGDEV";
1384 case PCIE_ROOT_PORT:
1387 case PCIE_UP_STREAM_PORT:
1388 port_name = "UPSTREAM";
1390 case PCIE_DOWN_STREAM_PORT:
1391 port_name = "DOWNSTRM";
1393 case PCIE_PCIE2PCI_BRIDGE:
1394 port_name = "PCIE2PCI";
1396 case PCIE_PCI2PCIE_BRIDGE:
1397 port_name = "PCI2PCIE";
1403 if ((port_type == PCIE_ROOT_PORT ||
1404 port_type == PCIE_DOWN_STREAM_PORT) &&
1405 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
1407 if (port_name != NULL)
1408 kprintf("[%s]", port_name);
1410 if (pcie_slotimpl(cfg)) {
1411 kprintf(", slotcap=0x%08x", expr->expr_slotcap);
1412 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP)
1413 kprintf("[HOTPLUG]");
1420 pci_print_verbose(struct pci_devinfo *dinfo)
1423 pcicfgregs *cfg = &dinfo->cfg;
1425 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
1426 cfg->vendor, cfg->device, cfg->revid);
1427 kprintf("\tbus=%d, slot=%d, func=%d\n",
1428 cfg->bus, cfg->slot, cfg->func);
1429 kprintf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
1430 pci_class_to_string(cfg->baseclass),
1431 cfg->baseclass, cfg->subclass, cfg->progif,
1432 cfg->hdrtype, cfg->mfdev);
1433 kprintf("\tsubordinatebus=%x \tsecondarybus=%x\n",
1434 cfg->subordinatebus, cfg->secondarybus);
1436 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
1437 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
1438 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
1439 cfg->lattimer, cfg->lattimer * 30,
1440 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1441 #endif /* PCI_DEBUG */
1442 if (cfg->intpin > 0)
1443 kprintf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
1445 pci_print_verbose_expr(cfg);
1450 pci_porten(device_t pcib, int b, int s, int f)
1452 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1453 & PCIM_CMD_PORTEN) != 0;
1457 pci_memen(device_t pcib, int b, int s, int f)
1459 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1460 & PCIM_CMD_MEMEN) != 0;
1464 * Add a resource based on a pci map register. Return 1 if the map
1465 * register is a 32bit map register or 2 if it is a 64bit register.
1468 pci_add_map(device_t pcib, int b, int s, int f, int reg,
1469 struct resource_list *rl)
1478 #ifdef PCI_ENABLE_IO_MODES
1483 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1485 if (map == 0 || map == 0xffffffff)
1486 return 1; /* skip invalid entry */
1488 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
1489 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1490 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
1492 base = pci_mapbase(map);
1493 if (pci_maptype(map) & PCI_MAPMEM)
1494 type = SYS_RES_MEMORY;
1496 type = SYS_RES_IOPORT;
1497 ln2size = pci_mapsize(testval);
1498 ln2range = pci_maprange(testval);
1499 if (ln2range == 64) {
1500 /* Read the other half of a 64bit map register */
1501 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4);
1505 * This code theoretically does the right thing, but has
1506 * undesirable side effects in some cases where
1507 * peripherals respond oddly to having these bits
1508 * enabled. Leave them alone by default.
1510 #ifdef PCI_ENABLE_IO_MODES
1511 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
1512 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1513 cmd |= PCIM_CMD_PORTEN;
1514 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
1516 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
1517 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1518 cmd |= PCIM_CMD_MEMEN;
1519 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
1522 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
1524 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
1528 resource_list_add(rl, type, reg,
1529 base, base + (1 << ln2size) - 1,
1533 kprintf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
1534 reg, pci_maptype(base), ln2range,
1535 (unsigned int) base, ln2size);
1538 return (ln2range == 64) ? 2 : 1;
1541 #ifdef PCI_MAP_FIXUP
1543 * For ATA devices we need to decide early on what addressing mode to use.
1544 * Legacy demands that the primary and secondary ATA ports sits on the
1545 * same addresses that old ISA hardware did. This dictates that we use
1546 * those addresses and ignore the BARs if we cannot set PCI native
1550 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, int s, int f,
1551 struct resource_list *rl)
1553 int rid, type, progif;
1555 /* if this device supports PCI native addressing use it */
1556 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1557 if ((progif &0x8a) == 0x8a) {
1558 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
1559 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
1560 kprintf("Trying ATA native PCI addressing mode\n");
1561 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
1566 * Because we return any preallocated resources for lazy
1567 * allocation for PCI devices in pci_alloc_resource(), we can
1568 * allocate our legacy resources here.
1570 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1571 type = SYS_RES_IOPORT;
1572 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
1573 pci_add_map(pcib, b, s, f, PCIR_BAR(0), rl);
1574 pci_add_map(pcib, b, s, f, PCIR_BAR(1), rl);
1577 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
1578 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
1581 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
1582 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
1585 if (progif & PCIP_STORAGE_IDE_MODESEC) {
1586 pci_add_map(pcib, b, s, f, PCIR_BAR(2), rl);
1587 pci_add_map(pcib, b, s, f, PCIR_BAR(3), rl);
1590 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
1591 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
1594 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
1595 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
1598 pci_add_map(pcib, b, s, f, PCIR_BAR(4), rl);
1599 pci_add_map(pcib, b, s, f, PCIR_BAR(5), rl);
1601 #endif /* PCI_MAP_FIXUP */
1604 pci_add_resources(device_t pcib, device_t bus, device_t dev)
1606 struct pci_devinfo *dinfo = device_get_ivars(dev);
1607 pcicfgregs *cfg = &dinfo->cfg;
1608 struct resource_list *rl = &dinfo->resources;
1609 struct pci_quirk *q;
1611 #if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */
1618 #ifdef PCI_MAP_FIXUP
1619 /* atapci devices in legacy mode need special map treatment */
1620 if ((pci_get_class(dev) == PCIC_STORAGE) &&
1621 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
1622 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
1623 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
1624 !pci_read_config(dev, PCIR_BAR(2), 4))) )
1625 pci_ata_maps(pcib, bus, dev, b, s, f, rl);
1627 #endif /* PCI_MAP_FIXUP */
1628 for (i = 0; i < cfg->nummaps;) {
1629 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl);
1632 for (q = &pci_quirks[0]; q->devid; q++) {
1633 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1634 && q->type == PCI_QUIRK_MAP_REG)
1635 pci_add_map(pcib, b, s, f, q->arg1, rl);
1638 if (cfg->intpin > 0 && cfg->intline != 255)
1639 resource_list_add(rl, SYS_RES_IRQ, 0,
1640 cfg->intline, cfg->intline, 1);
1644 pci_add_children(device_t dev, int busno, size_t dinfo_size)
1646 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
1647 device_t pcib = device_get_parent(dev);
1648 struct pci_devinfo *dinfo;
1650 int s, f, pcifunchigh;
1653 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo));
1655 maxslots = PCIB_MAXSLOTS(pcib);
1657 for (s = 0; s <= maxslots; s++) {
1660 hdrtype = REG(PCIR_HDRTYPE, 1);
1661 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
1663 if (hdrtype & PCIM_MFDEV)
1664 pcifunchigh = PCI_FUNCMAX;
1665 for (f = 0; f <= pcifunchigh; f++) {
1666 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size);
1667 if (dinfo != NULL) {
1668 pci_add_child(dev, dinfo);
1676 * The actual PCI child that we add has a NULL driver whos parent
1677 * device will be "pci". The child contains the ivars, not the parent.
1680 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
1684 pcib = device_get_parent(bus);
1685 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
1686 device_set_ivars(dinfo->cfg.dev, dinfo);
1687 pci_add_resources(pcib, bus, dinfo->cfg.dev);
1688 pci_print_verbose(dinfo);
1692 * Probe the PCI bus. Note: probe code is not supposed to add children
1696 pci_probe(device_t dev)
1698 device_set_desc(dev, "PCI bus");
1700 /* Allow other subclasses to override this driver */
1705 pci_attach(device_t dev)
1708 int lunit = device_get_unit(dev);
1710 dev_ops_add(&pcic_ops, -1, lunit);
1711 make_dev(&pcic_ops, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit);
1714 * Since there can be multiple independantly numbered PCI
1715 * busses on some large alpha systems, we can't use the unit
1716 * number to decide what bus we are probing. We ask the parent
1717 * pcib what our bus number is.
1719 * pcib_get_bus() must act on the pci bus device, not on the pci
1720 * device, because it uses badly hacked nexus-based ivars to
1721 * store and retrieve the physical bus number. XXX
1723 busno = pcib_get_bus(device_get_parent(dev));
1725 device_printf(dev, "pci_attach() physical bus=%d\n", busno);
1727 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
1729 return (bus_generic_attach(dev));
1733 pci_print_resources(struct resource_list *rl, const char *name, int type,
1736 struct resource_list_entry *rle;
1737 int printed, retval;
1741 /* Yes, this is kinda cheating */
1742 SLIST_FOREACH(rle, rl, link) {
1743 if (rle->type == type) {
1745 retval += kprintf(" %s ", name);
1746 else if (printed > 0)
1747 retval += kprintf(",");
1749 retval += kprintf(format, rle->start);
1750 if (rle->count > 1) {
1751 retval += kprintf("-");
1752 retval += kprintf(format, rle->start +
1761 pci_print_child(device_t dev, device_t child)
1763 struct pci_devinfo *dinfo;
1764 struct resource_list *rl;
1768 dinfo = device_get_ivars(child);
1770 rl = &dinfo->resources;
1772 retval += bus_print_child_header(dev, child);
1774 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1775 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1776 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1777 if (device_get_flags(dev))
1778 retval += kprintf(" flags %#x", device_get_flags(dev));
1780 retval += kprintf(" at device %d.%d", pci_get_slot(child),
1781 pci_get_function(child));
1783 retval += bus_print_child_footer(dev, child);
1789 pci_probe_nomatch(device_t dev, device_t child)
1791 struct pci_devinfo *dinfo;
1797 dinfo = device_get_ivars(child);
1799 desc = pci_ata_match(child);
1800 if (!desc) desc = pci_usb_match(child);
1801 if (!desc) desc = pci_vga_match(child);
1802 if (!desc) desc = pci_chip_match(child);
1804 desc = "unknown card";
1807 device_printf(dev, "<%s>", desc);
1808 if (bootverbose || unknown) {
1809 kprintf(" (vendor=0x%04x, dev=0x%04x)",
1813 kprintf(" at %d.%d",
1814 pci_get_slot(child),
1815 pci_get_function(child));
1816 if (cfg->intpin > 0 && cfg->intline != 255) {
1817 kprintf(" irq %d", cfg->intline);
1825 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1827 struct pci_devinfo *dinfo;
1830 dinfo = device_get_ivars(child);
1834 case PCI_IVAR_SUBVENDOR:
1835 *result = cfg->subvendor;
1837 case PCI_IVAR_SUBDEVICE:
1838 *result = cfg->subdevice;
1840 case PCI_IVAR_VENDOR:
1841 *result = cfg->vendor;
1843 case PCI_IVAR_DEVICE:
1844 *result = cfg->device;
1846 case PCI_IVAR_DEVID:
1847 *result = (cfg->device << 16) | cfg->vendor;
1849 case PCI_IVAR_CLASS:
1850 *result = cfg->baseclass;
1852 case PCI_IVAR_SUBCLASS:
1853 *result = cfg->subclass;
1855 case PCI_IVAR_PROGIF:
1856 *result = cfg->progif;
1858 case PCI_IVAR_REVID:
1859 *result = cfg->revid;
1861 case PCI_IVAR_INTPIN:
1862 *result = cfg->intpin;
1865 *result = cfg->intline;
1871 *result = cfg->slot;
1873 case PCI_IVAR_FUNCTION:
1874 *result = cfg->func;
1876 case PCI_IVAR_SECONDARYBUS:
1877 *result = cfg->secondarybus;
1879 case PCI_IVAR_SUBORDINATEBUS:
1880 *result = cfg->subordinatebus;
1882 case PCI_IVAR_ETHADDR:
1884 * The generic accessor doesn't deal with failure, so
1885 * we set the return value, then return an error.
1889 case PCI_IVAR_PCIXCAP_PTR:
1890 *result = cfg->pcixcap_ptr;
1892 case PCI_IVAR_PCIECAP_PTR:
1893 *result = cfg->expr.expr_ptr;
1902 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1904 struct pci_devinfo *dinfo;
1907 dinfo = device_get_ivars(child);
1911 case PCI_IVAR_SUBVENDOR:
1912 case PCI_IVAR_SUBDEVICE:
1913 case PCI_IVAR_VENDOR:
1914 case PCI_IVAR_DEVICE:
1915 case PCI_IVAR_DEVID:
1916 case PCI_IVAR_CLASS:
1917 case PCI_IVAR_SUBCLASS:
1918 case PCI_IVAR_PROGIF:
1919 case PCI_IVAR_REVID:
1920 case PCI_IVAR_INTPIN:
1924 case PCI_IVAR_FUNCTION:
1925 case PCI_IVAR_ETHADDR:
1926 case PCI_IVAR_PCIXCAP_PTR:
1927 case PCI_IVAR_PCIECAP_PTR:
1928 return EINVAL; /* disallow for now */
1930 case PCI_IVAR_SECONDARYBUS:
1931 cfg->secondarybus = value;
1933 case PCI_IVAR_SUBORDINATEBUS:
1934 cfg->subordinatebus = value;
1942 #ifdef PCI_MAP_FIXUP
1943 static struct resource *
1944 pci_alloc_map(device_t dev, device_t child, int type, int *rid, u_long start,
1945 u_long end, u_long count, u_int flags)
1947 struct pci_devinfo *dinfo = device_get_ivars(child);
1948 struct resource_list *rl = &dinfo->resources;
1949 struct resource_list_entry *rle;
1950 struct resource *res;
1951 uint32_t map, testval;
1955 * Weed out the bogons, and figure out how large the BAR/map
1956 * is. BARs that read back 0 here are bogus and unimplemented.
1958 * Note: atapci in legacy mode are special and handled elsewhere
1959 * in the code. If you have an atapci device in legacy mode and
1960 * it fails here, that other code is broken.
1963 map = pci_read_config(child, *rid, 4);
1964 pci_write_config(child, *rid, 0xffffffff, 4);
1965 testval = pci_read_config(child, *rid, 4);
1966 if (pci_mapbase(testval) == 0)
1968 if (pci_maptype(testval) & PCI_MAPMEM) {
1969 if (type != SYS_RES_MEMORY) {
1971 device_printf(dev, "child %s requested type %d"
1972 " for rid %#x, but the BAR says "
1974 device_get_nameunit(child), type,
1979 if (type != SYS_RES_IOPORT) {
1981 device_printf(dev, "child %s requested type %d"
1982 " for rid %#x, but the BAR says "
1983 "it is an ioport\n",
1984 device_get_nameunit(child), type,
1990 * For real BARs, we need to override the size that
1991 * the driver requests, because that's what the BAR
1992 * actually uses and we would otherwise have a
1993 * situation where we might allocate the excess to
1994 * another driver, which won't work.
1996 mapsize = pci_mapsize(testval);
1997 count = 1 << mapsize;
1998 if (RF_ALIGNMENT(flags) < mapsize)
1999 flags = (flags & ~RF_ALIGNMENT_MASK) |
2000 RF_ALIGNMENT_LOG2(mapsize);
2002 * Allocate enough resource, and then write back the
2003 * appropriate BAR for that resource.
2005 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
2006 start, end, count, flags);
2008 device_printf(child, "%#lx bytes at rid %#x res %d failed "
2009 "(%#lx, %#lx)\n", count, *rid, type, start, end);
2012 resource_list_add(rl, type, *rid, start, end, count);
2013 rle = resource_list_find(rl, type, *rid);
2015 panic("pci_alloc_map: unexpectedly can't find resource.");
2017 rle->start = rman_get_start(res);
2018 rle->end = rman_get_end(res);
2021 device_printf(child, "lazy allocation of %#lx bytes rid %#x "
2022 "type %d at %#lx\n", count, *rid, type,
2023 rman_get_start(res));
2024 map = rman_get_start(res);
2026 pci_write_config(child, *rid, map, 4);
2029 #endif /* PCI_MAP_FIXUP */
2032 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
2033 u_long start, u_long end, u_long count, u_int flags)
2035 struct pci_devinfo *dinfo = device_get_ivars(child);
2036 struct resource_list *rl = &dinfo->resources;
2037 #ifdef PCI_MAP_FIXUP
2038 struct resource_list_entry *rle;
2039 #endif /* PCI_MAP_FIXUP */
2040 pcicfgregs *cfg = &dinfo->cfg;
2043 * Perform lazy resource allocation
2045 if (device_get_parent(child) == dev) {
2050 * If device doesn't have an interrupt routed, and is
2051 * deserving of an interrupt, try to assign it one.
2053 if ((cfg->intline == 255 || cfg->intline == 0) &&
2054 (cfg->intpin != 0) &&
2055 (start == 0) && (end == ~0UL)) {
2056 cfg->intline = PCIB_ROUTE_INTERRUPT(
2057 device_get_parent(dev), child,
2059 if (cfg->intline != 255) {
2060 pci_write_config(child, PCIR_INTLINE,
2062 resource_list_add(rl, SYS_RES_IRQ, 0,
2063 cfg->intline, cfg->intline, 1);
2068 case SYS_RES_IOPORT:
2070 case SYS_RES_MEMORY:
2071 if (*rid < PCIR_BAR(cfg->nummaps)) {
2073 * Enable the I/O mode. We should
2074 * also be assigning resources too
2075 * when none are present. The
2076 * resource_list_alloc kind of sorta does
2079 if (PCI_ENABLE_IO(dev, child, type))
2082 #ifdef PCI_MAP_FIXUP
2083 rle = resource_list_find(rl, type, *rid);
2085 return pci_alloc_map(dev, child, type, rid,
2086 start, end, count, flags);
2087 #endif /* PCI_MAP_FIXUP */
2090 #ifdef PCI_MAP_FIXUP
2092 * If we've already allocated the resource, then
2093 * return it now. But first we may need to activate
2094 * it, since we don't allocate the resource as active
2095 * above. Normally this would be done down in the
2096 * nexus, but since we short-circuit that path we have
2097 * to do its job here. Not sure if we should free the
2098 * resource if it fails to activate.
2100 * Note: this also finds and returns resources for
2101 * atapci devices in legacy mode as allocated in
2104 rle = resource_list_find(rl, type, *rid);
2105 if (rle != NULL && rle->res != NULL) {
2107 device_printf(child, "reserved %#lx bytes for "
2108 "rid %#x type %d at %#lx\n",
2109 rman_get_size(rle->res), *rid,
2110 type, rman_get_start(rle->res));
2111 if ((flags & RF_ACTIVE) &&
2112 bus_generic_activate_resource(dev, child, type,
2113 *rid, rle->res) != 0)
2117 #endif /* PCI_MAP_FIXUP */
2119 return resource_list_alloc(rl, dev, child, type, rid,
2120 start, end, count, flags);
2124 pci_release_resource(device_t dev, device_t child, int type, int rid,
2127 struct pci_devinfo *dinfo = device_get_ivars(child);
2128 struct resource_list *rl = &dinfo->resources;
2130 return resource_list_release(rl, dev, child, type, rid, r);
2134 pci_set_resource(device_t dev, device_t child, int type, int rid,
2135 u_long start, u_long count)
2137 struct pci_devinfo *dinfo = device_get_ivars(child);
2138 struct resource_list *rl = &dinfo->resources;
2140 resource_list_add(rl, type, rid, start, start + count - 1, count);
2145 pci_get_resource(device_t dev, device_t child, int type, int rid,
2146 u_long *startp, u_long *countp)
2148 struct pci_devinfo *dinfo = device_get_ivars(child);
2149 struct resource_list *rl = &dinfo->resources;
2150 struct resource_list_entry *rle;
2152 rle = resource_list_find(rl, type, rid);
2157 *startp = rle->start;
2159 *countp = rle->count;
2165 pci_delete_resource(device_t dev, device_t child, int type, int rid)
2167 kprintf("pci_delete_resource: PCI resources can not be deleted\n");
2170 struct resource_list *
2171 pci_get_resource_list (device_t dev, device_t child)
2173 struct pci_devinfo *dinfo = device_get_ivars(child);
2177 return (&dinfo->resources);
2181 pci_read_config_method(device_t dev, device_t child, int reg, int width)
2183 struct pci_devinfo *dinfo = device_get_ivars(child);
2184 pcicfgregs *cfg = &dinfo->cfg;
2186 return PCIB_READ_CONFIG(device_get_parent(dev),
2187 cfg->bus, cfg->slot, cfg->func,
2192 pci_write_config_method(device_t dev, device_t child, int reg,
2193 u_int32_t val, int width)
2195 struct pci_devinfo *dinfo = device_get_ivars(child);
2196 pcicfgregs *cfg = &dinfo->cfg;
2198 PCIB_WRITE_CONFIG(device_get_parent(dev),
2199 cfg->bus, cfg->slot, cfg->func,
2204 pci_child_location_str_method(device_t cbdev, device_t child, char *buf,
2207 struct pci_devinfo *dinfo;
2209 dinfo = device_get_ivars(child);
2210 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
2211 pci_get_function(child));
2216 pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf,
2219 struct pci_devinfo *dinfo;
2222 dinfo = device_get_ivars(child);
2224 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
2225 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
2226 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
2232 pci_assign_interrupt_method(device_t dev, device_t child)
2234 struct pci_devinfo *dinfo = device_get_ivars(child);
2235 pcicfgregs *cfg = &dinfo->cfg;
2237 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
2242 pci_modevent(module_t mod, int what, void *arg)
2246 STAILQ_INIT(&pci_devq);
2256 pci_resume(device_t dev)
2262 struct pci_devinfo *dinfo;
2265 device_get_children(dev, &children, &numdevs);
2267 for (i = 0; i < numdevs; i++) {
2268 child = children[i];
2270 dinfo = device_get_ivars(child);
2272 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2273 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child);
2274 if (PCI_INTERRUPT_VALID(cfg->intline)) {
2275 pci_write_config(child, PCIR_INTLINE,
2281 kfree(children, M_TEMP);
2283 return (bus_generic_resume(dev));
2286 static device_method_t pci_methods[] = {
2287 /* Device interface */
2288 DEVMETHOD(device_probe, pci_probe),
2289 DEVMETHOD(device_attach, pci_attach),
2290 DEVMETHOD(device_shutdown, bus_generic_shutdown),
2291 DEVMETHOD(device_suspend, bus_generic_suspend),
2292 DEVMETHOD(device_resume, pci_resume),
2295 DEVMETHOD(bus_print_child, pci_print_child),
2296 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
2297 DEVMETHOD(bus_read_ivar, pci_read_ivar),
2298 DEVMETHOD(bus_write_ivar, pci_write_ivar),
2299 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
2300 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
2301 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
2303 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
2304 DEVMETHOD(bus_set_resource, pci_set_resource),
2305 DEVMETHOD(bus_get_resource, pci_get_resource),
2306 DEVMETHOD(bus_delete_resource, pci_delete_resource),
2307 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
2308 DEVMETHOD(bus_release_resource, pci_release_resource),
2309 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
2310 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
2311 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
2312 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
2315 DEVMETHOD(pci_read_config, pci_read_config_method),
2316 DEVMETHOD(pci_write_config, pci_write_config_method),
2317 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
2318 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
2319 DEVMETHOD(pci_enable_io, pci_enable_io_method),
2320 DEVMETHOD(pci_disable_io, pci_disable_io_method),
2321 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
2322 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
2323 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
2328 driver_t pci_driver = {
2334 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
2335 MODULE_VERSION(pci, 1);