2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/bge/if_bgereg.h,v 1.1.2.16 2004/09/23 20:11:18 ps Exp $
40 * Tigon general information block. This resides in host memory
41 * and contains the status counters, ring control blocks and
46 struct bge_stats bge_stats;
47 struct bge_rcb bge_tx_rcb[16];
48 struct bge_rcb bge_std_rx_rcb;
49 struct bge_rcb bge_jumbo_rx_rcb;
50 struct bge_rcb bge_mini_rx_rcb;
51 struct bge_rcb bge_return_rcb;
54 #define BGE_MIN_FRAMELEN 60
55 #define BGE_MAX_FRAMELEN 1536
56 #define BGE_JUMBO_FRAMELEN 9018
57 #define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
59 #define BGE_TIMEOUT 5000
60 #define BGE_FIRMWARE_TIMEOUT 100000
61 #define BGE_TXCONS_UNSET 0xFFFF /* impossible value */
64 * Other utility macros.
66 #define BGE_INC(x, y) (x) = ((x) + 1) % (y)
69 * BAR0 MAC register access macros. The Tigon always uses memory mapped
70 * register accesses and all registers must be accessed with 32 bit
74 #define CSR_WRITE_4(sc, reg, val) \
75 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val)
77 #define CSR_READ_4(sc, reg) \
78 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg)
80 #define BGE_SETBIT(sc, reg, x) \
81 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x))
83 #define BGE_CLRBIT(sc, reg, x) \
84 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))
86 /* BAR2 APE register access macros. */
87 #define APE_WRITE_4(sc, reg, val) \
88 bus_write_4(sc->bge_res2, reg, val)
90 #define APE_READ_4(sc, reg) \
91 bus_read_4(sc->bge_res2, reg)
93 #define APE_SETBIT(sc, reg, x) \
94 APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) | (x)))
95 #define APE_CLRBIT(sc, reg, x) \
96 APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) & ~(x)))
98 #define BGE_MEMWIN_READ(sc, x, val) \
100 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
101 (0xFFFF0000 & x), 4); \
102 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \
105 #define BGE_MEMWIN_WRITE(sc, x, val) \
107 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
108 (0xFFFF0000 & x), 4); \
109 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \
112 #define RCB_WRITE_4(sc, rcb, offset, val) \
113 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \
114 rcb + offsetof(struct bge_rcb, offset), val)
117 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS
118 * values are tuneable. They control the actual amount of buffers
119 * allocated for the standard, mini and jumbo receive rings.
122 #define BGE_SSLOTS 256
123 #define BGE_MSLOTS 256
124 #define BGE_JSLOTS 384
126 #define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN)
127 #define BGE_JLEN (BGE_JRAWLEN + \
128 (sizeof(uint64_t) - BGE_JRAWLEN % sizeof(uint64_t)))
129 #define BGE_JPAGESZ PAGE_SIZE
130 #define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ)
131 #define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID)
136 struct bge_softc *bge_sc;
138 bus_addr_t bge_paddr;
141 SLIST_ENTRY(bge_jslot) jslot_link;
145 * Ring structures. Most of these reside in host memory and we tell
146 * the NIC where they are via the ring control blocks. The exceptions
147 * are the tx and command rings, which live in NIC memory and which
148 * we access via the shared memory window.
150 struct bge_ring_data {
151 struct bge_rx_bd *bge_rx_std_ring;
152 bus_addr_t bge_rx_std_ring_paddr;
153 struct bge_rx_bd *bge_rx_jumbo_ring;
154 bus_addr_t bge_rx_jumbo_ring_paddr;
155 struct bge_rx_bd *bge_rx_return_ring;
156 bus_addr_t bge_rx_return_ring_paddr;
157 struct bge_tx_bd *bge_tx_ring;
158 bus_addr_t bge_tx_ring_paddr;
159 struct bge_status_block *bge_status_block;
160 bus_addr_t bge_status_block_paddr;
161 struct bge_stats *bge_stats;
162 bus_addr_t bge_stats_paddr;
164 struct bge_gib bge_info;
168 struct mbuf *bge_mbuf;
169 bus_addr_t bge_paddr;
173 * Mbuf pointers. We need these to keep track of the virtual addresses
174 * of our mbuf chains since we can only convert from physical to virtual,
175 * not the other way around.
177 struct bge_chain_data {
178 bus_dma_tag_t bge_parent_tag;
179 bus_dma_tag_t bge_rx_std_ring_tag;
180 bus_dma_tag_t bge_rx_jumbo_ring_tag;
181 bus_dma_tag_t bge_rx_return_ring_tag;
182 bus_dma_tag_t bge_tx_ring_tag;
183 bus_dma_tag_t bge_status_tag;
184 bus_dma_tag_t bge_stats_tag;
185 bus_dma_tag_t bge_jumbo_tag;
186 bus_dma_tag_t bge_tx_mtag; /* TX mbuf DMA tag */
187 bus_dma_tag_t bge_rx_mtag; /* RX mbuf DMA tag */
188 bus_dmamap_t bge_rx_tmpmap;
189 bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT];
190 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT];
191 bus_dmamap_t bge_rx_std_ring_map;
192 bus_dmamap_t bge_rx_jumbo_ring_map;
193 bus_dmamap_t bge_tx_ring_map;
194 bus_dmamap_t bge_rx_return_ring_map;
195 bus_dmamap_t bge_status_map;
196 bus_dmamap_t bge_stats_map;
197 bus_dmamap_t bge_jumbo_map;
198 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT];
199 struct bge_rxchain bge_rx_std_chain[BGE_STD_RX_RING_CNT];
200 struct bge_rxchain bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT];
201 /* Stick the jumbo mem management stuff here too. */
202 struct bge_jslot bge_jslots[BGE_JSLOTS];
206 struct arpcom arpcom; /* interface info */
209 bus_space_handle_t bge_bhandle;
210 bus_space_tag_t bge_btag;
212 struct resource *bge_irq;
215 struct resource *bge_res; /* MAC mapped I/O */
216 struct resource *bge_res2; /* APE mapped I/O */
217 struct ifmedia bge_ifmedia; /* TBI media info */
221 uint32_t bge_pci_miscctl;
222 uint32_t bge_status_tag;
223 uint32_t bge_flags; /* BGE_FLAG_ */
224 #define BGE_FLAG_TBI 0x00000001
225 #define BGE_FLAG_JUMBO 0x00000002
226 #define BGE_FLAG_ONESHOT_MSI 0x00000004
227 #define BGE_FLAG_TSO 0x00000008
228 #define BGE_FLAG_MII_SERDES 0x00000010
229 #define BGE_FLAG_CPMU 0x00000020
230 #define BGE_FLAG_APE 0x00000040
231 #define BGE_FLAG_PCIX 0x00000200
232 #define BGE_FLAG_PCIE 0x00000400
233 #define BGE_FLAG_5700_FAMILY 0x00001000
234 #define BGE_FLAG_5705_PLUS 0x00002000
235 #define BGE_FLAG_5714_FAMILY 0x00004000
236 #define BGE_FLAG_575X_PLUS 0x00008000
237 #define BGE_FLAG_5755_PLUS 0x00010000
238 #define BGE_FLAG_MAXADDR_40BIT 0x00020000
239 #define BGE_FLAG_RX_ALIGNBUG 0x00100000
240 #define BGE_FLAG_NO_EEPROM 0x10000000
241 #define BGE_FLAG_5788 0x20000000
242 #define BGE_FLAG_SHORTDMA 0x40000000
243 #define BGE_FLAG_STATUS_TAG 0x80000000
245 uint32_t bge_mfw_flags; /* Management F/W flags */
246 #define BGE_MFW_ON_RXCPU 0x00000001
247 #define BGE_MFW_ON_APE 0x00000002
248 #define BGE_MFW_TYPE_NCSI 0x00000004
249 #define BGE_MFW_TYPE_DASH 0x00000008
250 int bge_phy_ape_lock;
254 uint8_t bge_asf_mode;
255 #define ASF_ENABLE 0x01
256 #define ASF_NEW_HANDSHAKE 0x02
257 #define ASF_STACKUP 0x04
258 uint8_t bge_asf_count;
259 uint32_t bge_asicrev;
260 uint32_t bge_chiprev;
261 struct ifpoll_compat bge_npoll; /* polling */
262 struct bge_ring_data bge_ldata; /* rings */
263 struct bge_chain_data bge_cdata; /* mbufs */
264 uint16_t bge_tx_saved_considx;
265 uint16_t bge_rx_saved_considx;
266 uint16_t bge_ev_saved_considx;
267 uint16_t bge_return_ring_cnt;
268 uint16_t bge_std; /* current std ring head */
269 uint16_t bge_jumbo; /* current jumo ring head */
270 SLIST_HEAD(__bge_jfreehead, bge_jslot) bge_jfree_listhead;
271 struct lwkt_serialize bge_jslot_serializer;
272 uint32_t bge_stat_ticks;
273 uint32_t bge_rx_coal_ticks;
274 uint32_t bge_tx_coal_ticks;
275 uint32_t bge_rx_coal_bds;
276 uint32_t bge_tx_coal_bds;
277 uint32_t bge_rx_coal_ticks_int;
278 uint32_t bge_tx_coal_ticks_int;
279 uint32_t bge_rx_coal_bds_int;
280 uint32_t bge_tx_coal_bds_int;
281 uint32_t bge_tx_prodidx;
284 uint32_t bge_tx_buf_ratio;
285 uint32_t bge_mi_mode;
286 int bge_force_defrag;
287 int bge_mbox_reorder;
294 struct callout bge_stat_timer;
297 uint32_t bge_coal_chg;
298 #define BGE_RX_COAL_TICKS_CHG 0x01
299 #define BGE_TX_COAL_TICKS_CHG 0x02
300 #define BGE_RX_COAL_BDS_CHG 0x04
301 #define BGE_TX_COAL_BDS_CHG 0x08
302 #define BGE_RX_COAL_TICKS_INT_CHG 0x10
303 #define BGE_TX_COAL_TICKS_INT_CHG 0x20
304 #define BGE_RX_COAL_BDS_INT_CHG 0x40
305 #define BGE_TX_COAL_BDS_INT_CHG 0x80
307 void (*bge_link_upd)(struct bge_softc *, uint32_t);
308 uint32_t bge_link_chg;
311 #define BGE_NSEG_NEW 40
312 #define BGE_NSEG_SPARE 5
313 #define BGE_NSEG_SPARE_TSO 33
314 #define BGE_NSEG_RSVD 16
315 #define BGE_NSEG_RSVD_TSO 4
317 /* RX coalesce ticks, unit: us */
318 #define BGE_RX_COAL_TICKS_MIN 0
319 #define BGE_RX_COAL_TICKS_DEF 160
320 #define BGE_RX_COAL_TICKS_MAX 1023
322 /* TX coalesce ticks, unit: us */
323 #define BGE_TX_COAL_TICKS_MIN 0
324 #define BGE_TX_COAL_TICKS_DEF 1023
325 #define BGE_TX_COAL_TICKS_MAX 1023
327 /* RX coalesce BDs */
328 #define BGE_RX_COAL_BDS_MIN 0
329 #define BGE_RX_COAL_BDS_DEF 80
330 #define BGE_RX_COAL_BDS_MAX 255
332 /* TX coalesce BDs */
333 #define BGE_TX_COAL_BDS_MIN 0
334 #define BGE_TX_COAL_BDS_DEF 128
335 #define BGE_TX_COAL_BDS_MAX 255
337 /* Number of segments sent before writing to TX related registers */
338 #define BGE_TX_WREG_NSEGS 16
340 #endif /* !_IF_BGEVAR_H_ */