2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $
32 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
35 #include "opt_ifpoll.h"
37 #include <sys/param.h>
38 #include <sys/systm.h>
40 #include <sys/malloc.h>
41 #include <sys/kernel.h>
42 #include <sys/interrupt.h>
43 #include <sys/socket.h>
44 #include <sys/sysctl.h>
45 #include <sys/thread2.h>
48 #include <net/ifq_var.h>
49 #include <net/if_dl.h>
50 #include <net/if_media.h>
53 #include <sys/sockio.h>
57 #include <net/ethernet.h>
58 #include <net/if_arp.h>
59 #include <net/if_poll.h>
61 #include <vm/vm.h> /* for vtophys */
62 #include <vm/pmap.h> /* for vtophys */
64 #include <net/if_types.h>
65 #include <net/vlan/if_vlan_var.h>
67 #include <bus/pci/pcivar.h>
68 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */
70 #include "../mii_layer/mii.h"
71 #include "../mii_layer/miivar.h"
73 #include "if_fxpreg.h"
74 #include "if_fxpvar.h"
77 #include "miibus_if.h"
80 * NOTE! On the Alpha, we have an alignment constraint. The
81 * card DMAs the packet immediately following the RFA. However,
82 * the first thing in the packet is a 14-byte Ethernet header.
83 * This means that the packet is misaligned. To compensate,
84 * we actually offset the RFA 2 bytes into the cluster. This
85 * alignes the packet after the Ethernet header at a 32-bit
86 * boundary. HOWEVER! This means that the RFA is misaligned!
88 #define RFA_ALIGNMENT_FUDGE 2
91 * Set initial transmit threshold at 64 (512 bytes). This is
92 * increased by 64 (512 bytes) at a time, to maximum of 192
93 * (1536 bytes), if an underrun occurs.
95 static int tx_threshold = 64;
98 * The configuration byte map has several undefined fields which
99 * must be one or must be zero. Set up a template for these bits
100 * only, (assuming a 82557 chip) leaving the actual configuration
103 * See struct fxp_cb_config for the bit definitions.
105 static u_char fxp_cb_config_template[] = {
106 0x0, 0x0, /* cb_status */
107 0x0, 0x0, /* cb_command */
108 0x0, 0x0, 0x0, 0x0, /* link_addr */
135 int16_t revid; /* -1 matches anything */
140 * Claim various Intel PCI device identifiers for this driver. The
141 * sub-vendor and sub-device field are extensively used to identify
142 * particular variants, but we don't currently differentiate between
145 static struct fxp_ident fxp_ident_table[] = {
146 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" },
147 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" },
148 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
149 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
150 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
151 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
152 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
153 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
154 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
155 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
156 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
157 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
158 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
159 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
160 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
161 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
162 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
163 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" },
164 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" },
165 { 0x1064, -1, "Intel 82562ET/EZ/GT/GZ (ICH6/ICH6R) Pro/100 VE Ethernet" },
166 { 0x1065, -1, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" },
167 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" },
168 { 0x1069, -1, "Intel 82562EM/EX/GX Pro/100 Ethernet" },
169 { 0x1091, -1, "Intel 82562GX Pro/100 Ethernet" },
170 { 0x1092, -1, "Intel Pro/100 VE Network Connection" },
171 { 0x1093, -1, "Intel Pro/100 VM Network Connection" },
172 { 0x1094, -1, "Intel Pro/100 946GZ (ICH7) Network Connection" },
173 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" },
174 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" },
175 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" },
176 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" },
177 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" },
178 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" },
179 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" },
180 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" },
181 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" },
182 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" },
183 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" },
184 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" },
185 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" },
186 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" },
187 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" },
188 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" },
189 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
190 { 0x27dc, -1, "Intel 82801GB (ICH7) 10/100 Ethernet" },
194 static int fxp_probe(device_t dev);
195 static int fxp_attach(device_t dev);
196 static int fxp_detach(device_t dev);
197 static int fxp_shutdown(device_t dev);
198 static int fxp_suspend(device_t dev);
199 static int fxp_resume(device_t dev);
201 static void fxp_intr(void *xsc);
202 static void fxp_intr_body(struct fxp_softc *sc,
203 u_int8_t statack, int count);
205 static void fxp_init(void *xsc);
206 static void fxp_tick(void *xsc);
207 static void fxp_powerstate_d0(device_t dev);
208 static void fxp_start(struct ifnet *ifp, struct ifaltq_subque *);
209 static void fxp_stop(struct fxp_softc *sc);
210 static void fxp_release(device_t dev);
211 static int fxp_ioctl(struct ifnet *ifp, u_long command,
212 caddr_t data, struct ucred *);
213 static void fxp_watchdog(struct ifnet *ifp);
214 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm);
215 static int fxp_mc_addrs(struct fxp_softc *sc);
216 static void fxp_mc_setup(struct fxp_softc *sc);
217 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
219 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
221 static void fxp_autosize_eeprom(struct fxp_softc *sc);
222 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
223 int offset, int words);
224 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
225 int offset, int words);
226 static int fxp_ifmedia_upd(struct ifnet *ifp);
227 static void fxp_ifmedia_sts(struct ifnet *ifp,
228 struct ifmediareq *ifmr);
229 static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
230 static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
231 struct ifmediareq *ifmr);
232 static int fxp_miibus_readreg(device_t dev, int phy, int reg);
233 static void fxp_miibus_writereg(device_t dev, int phy, int reg,
235 static void fxp_load_ucode(struct fxp_softc *sc);
236 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
237 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
239 static void fxp_npoll(struct ifnet *, struct ifpoll_info *);
240 static void fxp_npoll_compat(struct ifnet *, void *, int);
243 static void fxp_lwcopy(volatile u_int32_t *src,
244 volatile u_int32_t *dst);
245 static void fxp_scb_wait(struct fxp_softc *sc);
246 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
247 static void fxp_dma_wait(volatile u_int16_t *status,
248 struct fxp_softc *sc);
250 static device_method_t fxp_methods[] = {
251 /* Device interface */
252 DEVMETHOD(device_probe, fxp_probe),
253 DEVMETHOD(device_attach, fxp_attach),
254 DEVMETHOD(device_detach, fxp_detach),
255 DEVMETHOD(device_shutdown, fxp_shutdown),
256 DEVMETHOD(device_suspend, fxp_suspend),
257 DEVMETHOD(device_resume, fxp_resume),
260 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
261 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
266 static driver_t fxp_driver = {
269 sizeof(struct fxp_softc),
272 static devclass_t fxp_devclass;
274 DECLARE_DUMMY_MODULE(if_fxp);
275 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1);
276 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, NULL, NULL);
277 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, NULL, NULL);
278 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, NULL, NULL);
281 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events");
284 * Copy a 16-bit aligned 32-bit quantity.
287 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst)
292 volatile u_int16_t *a = (volatile u_int16_t *)src;
293 volatile u_int16_t *b = (volatile u_int16_t *)dst;
301 * Wait for the previous command to be accepted (but not necessarily
305 fxp_scb_wait(struct fxp_softc *sc)
309 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
312 if_printf(&sc->arpcom.ac_if,
313 "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
314 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
315 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
316 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS),
317 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
322 fxp_scb_cmd(struct fxp_softc *sc, int cmd)
325 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
326 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
329 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
333 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc)
337 while (!(*status & FXP_CB_STATUS_C) && --i)
340 if_printf(&sc->arpcom.ac_if, "DMA timeout\n");
344 * Return identification string if this is device is ours.
347 fxp_probe(device_t dev)
351 struct fxp_ident *ident;
353 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
354 devid = pci_get_device(dev);
355 revid = pci_get_revid(dev);
356 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
357 if (ident->devid == devid &&
358 (ident->revid == revid || ident->revid == -1)) {
359 device_set_desc(dev, ident->name);
368 fxp_powerstate_d0(device_t dev)
370 u_int32_t iobase, membase, irq;
372 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
373 /* Save important PCI config data. */
374 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4);
375 membase = pci_read_config(dev, FXP_PCI_MMBA, 4);
376 irq = pci_read_config(dev, PCIR_INTLINE, 4);
378 /* Reset the power state. */
379 device_printf(dev, "chip is in D%d power mode "
380 "-- setting to D0\n", pci_get_powerstate(dev));
382 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
384 /* Restore PCI config data. */
385 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4);
386 pci_write_config(dev, FXP_PCI_MMBA, membase, 4);
387 pci_write_config(dev, PCIR_INTLINE, irq, 4);
392 fxp_attach(device_t dev)
395 struct fxp_softc *sc = device_get_softc(dev);
397 struct sysctl_ctx_list *ctx;
398 struct sysctl_oid *tree;
401 int i, rid, m1, m2, prefer_iomap;
403 callout_init(&sc->fxp_stat_timer);
406 * Enable bus mastering. Enable memory space too, in case
407 * BIOS/Prom forgot about it.
409 pci_enable_busmaster(dev);
410 pci_enable_io(dev, SYS_RES_MEMORY);
411 val = pci_read_config(dev, PCIR_COMMAND, 2);
413 fxp_powerstate_d0(dev);
416 * Figure out which we should try first - memory mapping or i/o mapping?
417 * We default to memory mapping. Then we accept an override from the
418 * command line. Then we check to see which one is enabled.
421 m2 = PCIM_CMD_PORTEN;
423 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
424 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) {
425 m1 = PCIM_CMD_PORTEN;
431 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
432 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
433 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd,
436 if (sc->mem == NULL && (val & m2)) {
438 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
439 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
440 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd,
445 device_printf(dev, "could not map device registers\n");
450 device_printf(dev, "using %s space register mapping\n",
451 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O");
454 sc->sc_st = rman_get_bustag(sc->mem);
455 sc->sc_sh = rman_get_bushandle(sc->mem);
458 * Allocate our interrupt.
461 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
462 RF_SHAREABLE | RF_ACTIVE);
463 if (sc->irq == NULL) {
464 device_printf(dev, "could not map interrupt\n");
470 * Reset to a stable state.
472 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
475 sc->cbl_base = kmalloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB,
476 M_DEVBUF, M_WAITOK | M_ZERO);
478 sc->fxp_stats = kmalloc(sizeof(struct fxp_stats), M_DEVBUF,
481 sc->mcsp = kmalloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK);
484 * Pre-allocate our receive buffers.
486 for (i = 0; i < FXP_NRFABUFS; i++) {
487 if (fxp_add_rfabuf(sc, NULL) != 0) {
493 * Find out how large of an SEEPROM we have.
495 fxp_autosize_eeprom(sc);
498 * Determine whether we must use the 503 serial interface.
500 fxp_read_eeprom(sc, &data, 6, 1);
501 if ((data & FXP_PHY_DEVICE_MASK) != 0 &&
502 (data & FXP_PHY_SERIAL_ONLY))
503 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
506 * Create the sysctl tree
508 ctx = device_get_sysctl_ctx(dev);
509 tree = device_get_sysctl_tree(dev);
510 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
511 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
512 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I",
513 "FXP driver receive interrupt microcode bundling delay");
514 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
515 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
516 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I",
517 "FXP driver receive interrupt microcode bundle size limit");
520 * Pull in device tunables.
522 sc->tunable_int_delay = TUNABLE_INT_DELAY;
523 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
524 resource_int_value(device_get_name(dev), device_get_unit(dev),
525 "int_delay", &sc->tunable_int_delay);
526 resource_int_value(device_get_name(dev), device_get_unit(dev),
527 "bundle_max", &sc->tunable_bundle_max);
530 * Find out the chip revision; lump all 82557 revs together.
532 fxp_read_eeprom(sc, &data, 5, 1);
533 if ((data >> 8) == 1)
534 sc->revision = FXP_REV_82557;
536 sc->revision = pci_get_revid(dev);
539 * Enable workarounds for certain chip revision deficiencies.
541 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
542 * some systems based a normal 82559 design, have a defect where
543 * the chip can cause a PCI protocol violation if it receives
544 * a CU_RESUME command when it is entering the IDLE state. The
545 * workaround is to disable Dynamic Standby Mode, so the chip never
546 * deasserts CLKRUN#, and always remains in an active state.
548 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
550 i = pci_get_device(dev);
551 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) ||
552 sc->revision >= FXP_REV_82559_A0) {
553 fxp_read_eeprom(sc, &data, 10, 1);
554 if (data & 0x02) { /* STB enable */
559 "Disabling dynamic standby mode in EEPROM\n");
561 fxp_write_eeprom(sc, &data, 10, 1);
562 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
564 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
565 fxp_read_eeprom(sc, &data, i, 1);
568 i = (1 << sc->eeprom_size) - 1;
569 cksum = 0xBABA - cksum;
570 fxp_read_eeprom(sc, &data, i, 1);
571 fxp_write_eeprom(sc, &cksum, i, 1);
573 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
577 * If the user elects to continue, try the software
578 * workaround, as it is better than nothing.
580 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
586 * If we are not a 82557 chip, we can enable extended features.
588 if (sc->revision != FXP_REV_82557) {
590 * If MWI is enabled in the PCI configuration, and there
591 * is a valid cacheline size (8 or 16 dwords), then tell
592 * the board to turn on MWI.
594 if (val & PCIM_CMD_MWRICEN &&
595 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
596 sc->flags |= FXP_FLAG_MWI_ENABLE;
598 /* turn on the extended TxCB feature */
599 sc->flags |= FXP_FLAG_EXT_TXCB;
601 /* enable reception of long frames for VLAN */
602 sc->flags |= FXP_FLAG_LONG_PKT_EN;
608 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3);
609 if (sc->flags & FXP_FLAG_SERIAL_MEDIA)
610 device_printf(dev, "10Mbps\n");
612 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
613 pci_get_vendor(dev), pci_get_device(dev),
614 pci_get_subvendor(dev), pci_get_subdevice(dev),
616 fxp_read_eeprom(sc, &data, 10, 1);
617 device_printf(dev, "Dynamic Standby mode is %s\n",
618 data & 0x02 ? "enabled" : "disabled");
622 * If this is only a 10Mbps device, then there is no MII, and
623 * the PHY will use a serial interface instead.
625 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
626 * doesn't have a programming interface of any sort. The
627 * media is sensed automatically based on how the link partner
628 * is configured. This is, in essence, manual configuration.
630 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
631 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
632 fxp_serial_ifmedia_sts);
633 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
634 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
636 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
638 device_printf(dev, "MII without any PHY!\n");
644 ifp = &sc->arpcom.ac_if;
645 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
646 ifp->if_baudrate = 100000000;
647 ifp->if_init = fxp_init;
649 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
650 ifp->if_ioctl = fxp_ioctl;
651 ifp->if_start = fxp_start;
653 ifp->if_npoll = fxp_npoll;
655 ifp->if_watchdog = fxp_watchdog;
658 * Attach the interface.
660 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
663 ifpoll_compat_setup(&sc->fxp_npoll, ctx, (struct sysctl_oid *)tree,
664 device_get_unit(dev), ifp->if_serializer);
668 * Tell the upper layer(s) we support long frames.
670 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
673 * Let the system queue as many packets as we have available
676 ifq_set_maxlen(&ifp->if_snd, FXP_USABLE_TXCB);
677 ifq_set_ready(&ifp->if_snd);
679 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->irq));
681 error = bus_setup_intr(dev, sc->irq, INTR_MPSAFE,
682 fxp_intr, sc, &sc->ih,
686 if (sc->flags & FXP_FLAG_SERIAL_MEDIA)
687 ifmedia_removeall(&sc->sc_media);
688 device_printf(dev, "could not setup irq\n");
695 device_printf(dev, "Failed to malloc memory\n");
703 * release all resources
706 fxp_release(device_t dev)
708 struct fxp_softc *sc = device_get_softc(dev);
711 device_delete_child(dev, sc->miibus);
712 bus_generic_detach(dev);
715 kfree(sc->cbl_base, M_DEVBUF);
717 kfree(sc->fxp_stats, M_DEVBUF);
719 kfree(sc->mcsp, M_DEVBUF);
721 m_freem(sc->rfa_headm);
724 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
726 bus_release_resource(dev, sc->rtp, sc->rgd, sc->mem);
733 fxp_detach(device_t dev)
735 struct fxp_softc *sc = device_get_softc(dev);
737 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
740 * Stop DMA and drop transmit queue.
745 * Disable interrupts.
747 * NOTE: This should be done after fxp_stop(), because software
748 * resetting in fxp_stop() may leave interrupts turned on.
750 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
753 * Free all media structures.
755 if (sc->flags & FXP_FLAG_SERIAL_MEDIA)
756 ifmedia_removeall(&sc->sc_media);
759 bus_teardown_intr(dev, sc->irq, sc->ih);
761 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
764 * Close down routes etc.
766 ether_ifdetach(&sc->arpcom.ac_if);
768 /* Release our allocated resources. */
775 * Device shutdown routine. Called at system shutdown after sync. The
776 * main purpose of this routine is to shut off receiver DMA so that
777 * kernel memory doesn't get clobbered during warmboot.
780 fxp_shutdown(device_t dev)
782 struct fxp_softc *sc = device_get_softc(dev);
783 struct ifnet *ifp = &sc->arpcom.ac_if;
785 lwkt_serialize_enter(ifp->if_serializer);
787 * Make sure that DMA is disabled prior to reboot. Not doing
788 * do could allow DMA to corrupt kernel memory during the
789 * reboot before the driver initializes.
792 lwkt_serialize_exit(ifp->if_serializer);
797 * Device suspend routine. Stop the interface and save some PCI
798 * settings in case the BIOS doesn't restore them properly on
802 fxp_suspend(device_t dev)
804 struct fxp_softc *sc = device_get_softc(dev);
807 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
811 for (i = 0; i < 5; i++)
812 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4);
813 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
814 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
815 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
816 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
820 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
825 * Device resume routine. Restore some PCI settings in case the BIOS
826 * doesn't, re-enable busmastering, and restart the interface if
830 fxp_resume(device_t dev)
832 struct fxp_softc *sc = device_get_softc(dev);
833 struct ifnet *ifp = &sc->arpcom.ac_if;
836 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
838 fxp_powerstate_d0(dev);
840 /* better way to do this? */
841 for (i = 0; i < 5; i++)
842 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4);
843 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
844 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
845 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
846 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
848 /* reenable busmastering and memory space */
849 pci_enable_busmaster(dev);
850 pci_enable_io(dev, SYS_RES_MEMORY);
852 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
855 /* reinitialize interface if necessary */
856 if (ifp->if_flags & IFF_UP)
861 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
866 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
874 for (x = 1 << (length - 1); x; x >>= 1) {
876 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
878 reg = FXP_EEPROM_EECS;
879 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
881 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
883 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
889 * Read from the serial EEPROM. Basically, you manually shift in
890 * the read opcode (one bit at a time) and then shift in the address,
891 * and then you shift out the data (all of this one bit at a time).
892 * The word size is 16 bits, so you have to provide the address for
893 * every 16 bits of data.
896 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
901 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
903 * Shift in read opcode.
905 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
910 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
912 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
914 reg = FXP_EEPROM_EECS;
915 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
917 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
919 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
921 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
923 if (autosize && reg == 0) {
924 sc->eeprom_size = data;
932 reg = FXP_EEPROM_EECS;
933 for (x = 1 << 15; x; x >>= 1) {
934 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
936 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
938 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
941 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
948 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data)
953 * Erase/write enable.
955 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
956 fxp_eeprom_shiftin(sc, 0x4, 3);
957 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
958 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
961 * Shift in write opcode, address, data.
963 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
964 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
965 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
966 fxp_eeprom_shiftin(sc, data, 16);
967 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
970 * Wait for EEPROM to finish up.
972 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
974 for (i = 0; i < 1000; i++) {
975 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
979 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
982 * Erase/write disable.
984 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
985 fxp_eeprom_shiftin(sc, 0x4, 3);
986 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
987 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
994 * Figure out EEPROM size.
996 * 559's can have either 64-word or 256-word EEPROMs, the 558
997 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
998 * talks about the existance of 16 to 256 word EEPROMs.
1000 * The only known sizes are 64 and 256, where the 256 version is used
1001 * by CardBus cards to store CIS information.
1003 * The address is shifted in msb-to-lsb, and after the last
1004 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1005 * after which follows the actual data. We try to detect this zero, by
1006 * probing the data-out bit in the EEPROM control register just after
1007 * having shifted in a bit. If the bit is zero, we assume we've
1008 * shifted enough address bits. The data-out should be tri-state,
1009 * before this, which should translate to a logical one.
1012 fxp_autosize_eeprom(struct fxp_softc *sc)
1015 /* guess maximum size of 256 words */
1016 sc->eeprom_size = 8;
1019 fxp_eeprom_getword(sc, 0, 1);
1023 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1027 for (i = 0; i < words; i++)
1028 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1032 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1036 for (i = 0; i < words; i++)
1037 fxp_eeprom_putword(sc, offset + i, data[i]);
1041 * Start packet transmission on the interface.
1044 fxp_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1046 struct fxp_softc *sc = ifp->if_softc;
1047 struct fxp_cb_tx *txp;
1049 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1050 ASSERT_SERIALIZED(ifp->if_serializer);
1053 * See if we need to suspend xmit until the multicast filter
1054 * has been reprogrammed (which can only be done at the head
1055 * of the command chain).
1057 if (sc->need_mcsetup) {
1058 ifq_purge(&ifp->if_snd);
1062 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
1068 * We're finished if there is nothing more to add to the list or if
1069 * we're all filled up with buffers to transmit.
1070 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1071 * a NOP command when needed.
1073 while (!ifq_is_empty(&ifp->if_snd) && sc->tx_queued < FXP_USABLE_TXCB) {
1074 struct mbuf *m, *mb_head;
1075 int segment, ntries = 0;
1078 * Grab a packet to transmit.
1080 mb_head = ifq_dequeue(&ifp->if_snd);
1081 if (mb_head == NULL)
1085 * Make sure that the packet fits into one TX desc
1088 for (m = mb_head; m != NULL; m = m->m_next) {
1089 if (m->m_len != 0) {
1091 if (segment >= FXP_NTXSEG)
1095 if (segment >= FXP_NTXSEG) {
1100 * Packet is excessively fragmented,
1101 * and will never fit into one TX
1105 IFNET_STAT_INC(ifp, oerrors, 1);
1109 mn = m_dup(mb_head, MB_DONTWAIT);
1112 IFNET_STAT_INC(ifp, oerrors, 1);
1123 * Get pointer to next available tx desc.
1125 txp = sc->cbl_last->next;
1128 * Go through each of the mbufs in the chain and initialize
1129 * the transmit buffer descriptors with the physical address
1130 * and size of the mbuf.
1132 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) {
1133 if (m->m_len != 0) {
1134 KKASSERT(segment < FXP_NTXSEG);
1136 txp->tbd[segment].tb_addr =
1137 vtophys(mtod(m, vm_offset_t));
1138 txp->tbd[segment].tb_size = m->m_len;
1142 KKASSERT(m == NULL);
1144 txp->tbd_number = segment;
1145 txp->mb_head = mb_head;
1147 if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1149 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1153 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1154 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
1156 txp->tx_threshold = tx_threshold;
1159 * Advance the end of list forward.
1161 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
1165 * Advance the beginning of the list forward if there are
1166 * no other packets queued (when nothing is queued, cbl_first
1167 * sits on the last TxCB that was sent out).
1169 if (sc->tx_queued == 0)
1170 sc->cbl_first = txp;
1174 * Set a 5 second timer just in case we don't hear
1175 * from the card again.
1179 BPF_MTAP(ifp, mb_head);
1182 if (sc->tx_queued >= FXP_USABLE_TXCB)
1183 ifq_set_oactive(&ifp->if_snd);
1186 * We're finished. If we added to the list, issue a RESUME to get DMA
1187 * going again if suspended.
1191 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1195 #ifdef IFPOLL_ENABLE
1198 fxp_npoll_compat(struct ifnet *ifp, void *arg __unused, int count)
1200 struct fxp_softc *sc = ifp->if_softc;
1203 ASSERT_SERIALIZED(ifp->if_serializer);
1205 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1207 if (sc->fxp_npoll.ifpc_stcount-- == 0) {
1210 sc->fxp_npoll.ifpc_stcount = sc->fxp_npoll.ifpc_stfrac;
1212 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1213 if (tmp == 0xff || tmp == 0)
1214 return; /* nothing to do */
1216 /* ack what we can */
1218 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1221 fxp_intr_body(sc, statack, count);
1225 fxp_npoll(struct ifnet *ifp, struct ifpoll_info *info)
1227 struct fxp_softc *sc = ifp->if_softc;
1229 ASSERT_SERIALIZED(ifp->if_serializer);
1232 int cpuid = sc->fxp_npoll.ifpc_cpuid;
1234 info->ifpi_rx[cpuid].poll_func = fxp_npoll_compat;
1235 info->ifpi_rx[cpuid].arg = NULL;
1236 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
1238 if (ifp->if_flags & IFF_RUNNING) {
1239 /* disable interrupts */
1240 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,
1241 FXP_SCB_INTR_DISABLE);
1242 sc->fxp_npoll.ifpc_stcount = 0;
1244 ifq_set_cpuid(&ifp->if_snd, cpuid);
1246 if (ifp->if_flags & IFF_RUNNING) {
1247 /* enable interrupts */
1248 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1250 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->irq));
1254 #endif /* IFPOLL_ENABLE */
1257 * Process interface interrupts.
1262 struct fxp_softc *sc = xsc;
1265 ASSERT_SERIALIZED(sc->arpcom.ac_if.if_serializer);
1267 if (sc->suspended) {
1271 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1273 * It should not be possible to have all bits set; the
1274 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1275 * all bits are set, this may indicate that the card has
1276 * been physically ejected, so ignore it.
1278 if (statack == 0xff)
1282 * First ACK all the interrupts in this pass.
1284 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1285 fxp_intr_body(sc, statack, -1);
1290 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count)
1292 struct ifnet *ifp = &sc->arpcom.ac_if;
1294 struct fxp_rfa *rfa;
1295 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1299 #ifdef IFPOLL_ENABLE
1300 /* Pick up a deferred RNR condition if `count' ran out last time. */
1301 if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1302 sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1308 * Free any finished transmit mbuf chains.
1310 * Handle the CNA event likt a CXTNO event. It used to
1311 * be that this event (control unit not ready) was not
1312 * encountered, but it is now with the SMPng modifications.
1313 * The exact sequence of events that occur when the interface
1314 * is brought up are different now, and if this event
1315 * goes unhandled, the configuration/rxfilter setup sequence
1316 * can stall for several seconds. The result is that no
1317 * packets go out onto the wire for about 5 to 10 seconds
1318 * after the interface is ifconfig'ed for the first time.
1320 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) {
1321 struct fxp_cb_tx *txp;
1323 for (txp = sc->cbl_first; sc->tx_queued &&
1324 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1326 if ((m = txp->mb_head) != NULL) {
1327 txp->mb_head = NULL;
1334 sc->cbl_first = txp;
1336 if (sc->tx_queued < FXP_USABLE_TXCB)
1337 ifq_clr_oactive(&ifp->if_snd);
1339 if (sc->tx_queued == 0) {
1341 if (sc->need_mcsetup)
1346 * Try to start more packets transmitting.
1348 if (!ifq_is_empty(&ifp->if_snd))
1353 * Just return if nothing happened on the receive side.
1355 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1359 * Process receiver interrupts. If a no-resource (RNR)
1360 * condition exists, get whatever packets we can and
1361 * re-start the receiver.
1363 * When using polling, we do not process the list to completion,
1364 * so when we get an RNR interrupt we must defer the restart
1365 * until we hit the last buffer with the C bit set.
1366 * If we run out of cycles and rfa_headm has the C bit set,
1367 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1368 * that the info will be used in the subsequent polling cycle.
1372 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1373 RFA_ALIGNMENT_FUDGE);
1375 #ifdef IFPOLL_ENABLE /* loop at most count times if count >=0 */
1376 if (count >= 0 && count-- == 0) {
1378 /* Defer RNR processing until the next time. */
1379 sc->flags |= FXP_FLAG_DEFERRED_RNR;
1384 #endif /* IFPOLL_ENABLE */
1386 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0)
1390 * Remove first packet from the chain.
1392 sc->rfa_headm = m->m_next;
1393 if (sc->rfa_headm == NULL)
1394 sc->rfa_tailm = NULL;
1398 * Add a new buffer to the receive chain.
1399 * If this fails, the old buffer is recycled
1402 if (fxp_add_rfabuf(sc, m) == 0) {
1406 * Fetch packet length (the top 2 bits of
1407 * actual_size are flags set by the controller
1408 * upon completion), and drop the packet in case
1409 * of bogus length or CRC errors.
1411 total_len = rfa->actual_size & 0x3fff;
1412 if (total_len < sizeof(struct ether_header) ||
1413 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE -
1414 sizeof(struct fxp_rfa) ||
1415 (rfa->rfa_status & FXP_RFA_STATUS_CRC)) {
1419 m->m_pkthdr.len = m->m_len = total_len;
1420 ifp->if_input(ifp, m, NULL, -1);
1426 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1427 vtophys(sc->rfa_headm->m_ext.ext_buf) +
1428 RFA_ALIGNMENT_FUDGE);
1429 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1434 * Update packet in/out/collision statistics. The i82557 doesn't
1435 * allow you to access these counters without doing a fairly
1436 * expensive DMA to get _all_ of the statistics it maintains, so
1437 * we do this operation here only once per second. The statistics
1438 * counters in the kernel are updated from the previous dump-stats
1439 * DMA and then a new dump-stats DMA is started. The on-chip
1440 * counters are zeroed when the DMA completes. If we can't start
1441 * the DMA immediately, we don't wait - we just prepare to read
1442 * them again next time.
1447 struct fxp_softc *sc = xsc;
1448 struct ifnet *ifp = &sc->arpcom.ac_if;
1449 struct fxp_stats *sp = sc->fxp_stats;
1450 struct fxp_cb_tx *txp;
1453 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1455 IFNET_STAT_INC(ifp, opackets, sp->tx_good);
1456 IFNET_STAT_INC(ifp, collisions, sp->tx_total_collisions);
1458 IFNET_STAT_INC(ifp, ipackets, sp->rx_good);
1459 sc->rx_idle_secs = 0;
1462 * Receiver's been idle for another second.
1466 IFNET_STAT_INC(ifp, ierrors,
1468 sp->rx_alignment_errors +
1470 sp->rx_overrun_errors);
1472 * If any transmit underruns occured, bump up the transmit
1473 * threshold by another 512 bytes (64 * 8).
1475 if (sp->tx_underruns) {
1476 IFNET_STAT_INC(ifp, oerrors, sp->tx_underruns);
1477 if (tx_threshold < 192)
1482 * Release any xmit buffers that have completed DMA. This isn't
1483 * strictly necessary to do here, but it's advantagous for mbufs
1484 * with external storage to be released in a timely manner rather
1485 * than being defered for a potentially long time. This limits
1486 * the delay to a maximum of one second.
1488 for (txp = sc->cbl_first; sc->tx_queued &&
1489 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1491 if ((m = txp->mb_head) != NULL) {
1492 txp->mb_head = NULL;
1499 sc->cbl_first = txp;
1501 if (sc->tx_queued < FXP_USABLE_TXCB)
1502 ifq_clr_oactive(&ifp->if_snd);
1503 if (sc->tx_queued == 0)
1507 * Try to start more packets transmitting.
1509 if (!ifq_is_empty(&ifp->if_snd))
1513 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1514 * then assume the receiver has locked up and attempt to clear
1515 * the condition by reprogramming the multicast filter. This is
1516 * a work-around for a bug in the 82557 where the receiver locks
1517 * up if it gets certain types of garbage in the syncronization
1518 * bits prior to the packet header. This bug is supposed to only
1519 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
1520 * mode as well (perhaps due to a 10/100 speed transition).
1522 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1523 sc->rx_idle_secs = 0;
1527 * If there is no pending command, start another stats
1528 * dump. Otherwise punt for now.
1530 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1532 * Start another stats dump.
1534 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1537 * A previous command is still waiting to be accepted.
1538 * Just zero our copy of the stats and wait for the
1539 * next timer event to update them.
1542 sp->tx_underruns = 0;
1543 sp->tx_total_collisions = 0;
1546 sp->rx_crc_errors = 0;
1547 sp->rx_alignment_errors = 0;
1548 sp->rx_rnr_errors = 0;
1549 sp->rx_overrun_errors = 0;
1551 if (sc->miibus != NULL)
1552 mii_tick(device_get_softc(sc->miibus));
1554 * Schedule another timeout one second from now.
1556 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc);
1558 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1562 * Stop the interface. Cancels the statistics updater and resets
1566 fxp_stop(struct fxp_softc *sc)
1568 struct ifnet *ifp = &sc->arpcom.ac_if;
1569 struct fxp_cb_tx *txp;
1572 ASSERT_SERIALIZED(ifp->if_serializer);
1574 ifp->if_flags &= ~IFF_RUNNING;
1575 ifq_clr_oactive(&ifp->if_snd);
1579 * Cancel stats updater.
1581 callout_stop(&sc->fxp_stat_timer);
1584 * Issue software reset, which also unloads the microcode.
1586 sc->flags &= ~FXP_FLAG_UCODE;
1587 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
1591 * Release any xmit buffers.
1595 for (i = 0; i < FXP_NTXCB; i++) {
1596 if (txp[i].mb_head != NULL) {
1597 m_freem(txp[i].mb_head);
1598 txp[i].mb_head = NULL;
1605 * Free all the receive buffers then reallocate/reinitialize
1607 if (sc->rfa_headm != NULL)
1608 m_freem(sc->rfa_headm);
1609 sc->rfa_headm = NULL;
1610 sc->rfa_tailm = NULL;
1611 for (i = 0; i < FXP_NRFABUFS; i++) {
1612 if (fxp_add_rfabuf(sc, NULL) != 0) {
1614 * This "can't happen" - we're at splimp()
1615 * and we just freed all the buffers we need
1618 panic("fxp_stop: no buffers!");
1624 * Watchdog/transmission transmit timeout handler. Called when a
1625 * transmission is started on the interface, but no interrupt is
1626 * received before the timeout. This usually indicates that the
1627 * card has wedged for some reason.
1630 fxp_watchdog(struct ifnet *ifp)
1632 ASSERT_SERIALIZED(ifp->if_serializer);
1634 if_printf(ifp, "device timeout\n");
1635 IFNET_STAT_INC(ifp, oerrors, 1);
1636 fxp_init(ifp->if_softc);
1642 struct fxp_softc *sc = xsc;
1643 struct ifnet *ifp = &sc->arpcom.ac_if;
1644 struct fxp_cb_config *cbp;
1645 struct fxp_cb_ias *cb_ias;
1646 struct fxp_cb_tx *txp;
1647 struct fxp_cb_mcs *mcsp;
1650 ASSERT_SERIALIZED(ifp->if_serializer);
1653 * Cancel any pending I/O
1657 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1660 * Initialize base of CBL and RFA memory. Loading with zero
1661 * sets it up for regular linear addressing.
1663 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1664 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
1667 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
1670 * Initialize base of dump-stats buffer.
1673 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats));
1674 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
1677 * Attempt to load microcode if requested.
1679 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0)
1683 * Initialize the multicast address list.
1685 if (fxp_mc_addrs(sc)) {
1687 mcsp->cb_status = 0;
1688 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL;
1689 mcsp->link_addr = -1;
1691 * Start the multicast setup command.
1694 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
1695 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1696 /* ...and wait for it to complete. */
1697 fxp_dma_wait(&mcsp->cb_status, sc);
1701 * We temporarily use memory that contains the TxCB list to
1702 * construct the config CB. The TxCB list memory is rebuilt
1705 cbp = (struct fxp_cb_config *) sc->cbl_base;
1708 * This bcopy is kind of disgusting, but there are a bunch of must be
1709 * zero and must be one bits in this structure and this is the easiest
1710 * way to initialize them all to proper values.
1712 bcopy(fxp_cb_config_template,
1713 (void *)(uintptr_t)(volatile void *)&cbp->cb_status,
1714 sizeof(fxp_cb_config_template));
1717 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL;
1718 cbp->link_addr = -1; /* (no) next command */
1719 cbp->byte_count = 22; /* (22) bytes to config */
1720 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
1721 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
1722 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
1723 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
1724 cbp->type_enable = 0; /* actually reserved */
1725 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
1726 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
1727 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
1728 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
1729 cbp->dma_mbce = 0; /* (disable) dma max counters */
1730 cbp->late_scb = 0; /* (don't) defer SCB update */
1731 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
1732 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
1733 cbp->ci_int = 1; /* interrupt on CU idle */
1734 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
1735 cbp->ext_stats_dis = 1; /* disable extended counters */
1736 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
1737 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm;
1738 cbp->disc_short_rx = !prm; /* discard short packets */
1739 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
1740 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
1741 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */
1742 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
1743 cbp->csma_dis = 0; /* (don't) disable link */
1744 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */
1745 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
1746 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
1747 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
1748 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
1749 cbp->nsai = 1; /* (don't) disable source addr insert */
1750 cbp->preamble_length = 2; /* (7 byte) preamble */
1751 cbp->loopback = 0; /* (don't) loopback */
1752 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
1753 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
1754 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
1755 cbp->promiscuous = prm; /* promiscuous mode */
1756 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
1757 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
1758 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
1759 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
1760 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
1762 cbp->stripping = !prm; /* truncate rx packet to byte count */
1763 cbp->padding = 1; /* (do) pad short tx packets */
1764 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
1765 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
1766 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
1767 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */
1768 /* must set wake_en in PMCSR also */
1769 cbp->force_fdx = 0; /* (don't) force full duplex */
1770 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
1771 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
1772 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
1774 if (sc->revision == FXP_REV_82557) {
1776 * The 82557 has no hardware flow control, the values
1777 * below are the defaults for the chip.
1779 cbp->fc_delay_lsb = 0;
1780 cbp->fc_delay_msb = 0x40;
1781 cbp->pri_fc_thresh = 3;
1783 cbp->rx_fc_restop = 0;
1784 cbp->rx_fc_restart = 0;
1786 cbp->pri_fc_loc = 1;
1788 cbp->fc_delay_lsb = 0x1f;
1789 cbp->fc_delay_msb = 0x01;
1790 cbp->pri_fc_thresh = 3;
1791 cbp->tx_fc_dis = 0; /* enable transmit FC */
1792 cbp->rx_fc_restop = 1; /* enable FC restop frames */
1793 cbp->rx_fc_restart = 1; /* enable FC restart frames */
1794 cbp->fc_filter = !prm; /* drop FC frames to host */
1795 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
1799 * Start the config command/DMA.
1802 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
1803 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1804 /* ...and wait for it to complete. */
1805 fxp_dma_wait(&cbp->cb_status, sc);
1808 * Now initialize the station address. Temporarily use the TxCB
1809 * memory area like we did above for the config CB.
1811 cb_ias = (struct fxp_cb_ias *) sc->cbl_base;
1812 cb_ias->cb_status = 0;
1813 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL;
1814 cb_ias->link_addr = -1;
1815 bcopy(sc->arpcom.ac_enaddr,
1816 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr,
1817 sizeof(sc->arpcom.ac_enaddr));
1820 * Start the IAS (Individual Address Setup) command/DMA.
1823 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1824 /* ...and wait for it to complete. */
1825 fxp_dma_wait(&cb_ias->cb_status, sc);
1828 * Initialize transmit control block (TxCB) list.
1832 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
1833 for (i = 0; i < FXP_NTXCB; i++) {
1834 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK;
1835 txp[i].cb_command = FXP_CB_COMMAND_NOP;
1837 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status);
1838 if (sc->flags & FXP_FLAG_EXT_TXCB)
1839 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]);
1841 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]);
1842 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK];
1845 * Set the suspend flag on the first TxCB and start the control
1846 * unit. It will execute the NOP and then suspend.
1848 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S;
1849 sc->cbl_first = sc->cbl_last = txp;
1853 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1856 * Initialize receiver buffer area - RFA.
1859 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1860 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE);
1861 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1864 * Set current media.
1866 if (sc->miibus != NULL)
1867 mii_mediachg(device_get_softc(sc->miibus));
1869 ifp->if_flags |= IFF_RUNNING;
1870 ifq_clr_oactive(&ifp->if_snd);
1873 * Enable interrupts.
1875 #ifdef IFPOLL_ENABLE
1877 * ... but only do that if we are not polling. And because (presumably)
1878 * the default is interrupts on, we need to disable them explicitly!
1880 if (ifp->if_flags & IFF_NPOLLING) {
1881 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1882 sc->fxp_npoll.ifpc_stcount = 0;
1884 #endif /* IFPOLL_ENABLE */
1885 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1888 * Start stats updater.
1890 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc);
1894 fxp_serial_ifmedia_upd(struct ifnet *ifp)
1896 ASSERT_SERIALIZED(ifp->if_serializer);
1901 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1903 ASSERT_SERIALIZED(ifp->if_serializer);
1904 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
1908 * Change media according to request.
1911 fxp_ifmedia_upd(struct ifnet *ifp)
1913 struct fxp_softc *sc = ifp->if_softc;
1914 struct mii_data *mii;
1916 ASSERT_SERIALIZED(ifp->if_serializer);
1918 mii = device_get_softc(sc->miibus);
1924 * Notify the world which media we're using.
1927 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1929 struct fxp_softc *sc = ifp->if_softc;
1930 struct mii_data *mii;
1932 ASSERT_SERIALIZED(ifp->if_serializer);
1934 mii = device_get_softc(sc->miibus);
1936 ifmr->ifm_active = mii->mii_media_active;
1937 ifmr->ifm_status = mii->mii_media_status;
1939 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG)
1940 sc->cu_resume_bug = 1;
1942 sc->cu_resume_bug = 0;
1946 * Add a buffer to the end of the RFA buffer list.
1947 * Return 0 if successful, 1 for failure. A failure results in
1948 * adding the 'oldm' (if non-NULL) on to the end of the list -
1949 * tossing out its old contents and recycling it.
1950 * The RFA struct is stuck at the beginning of mbuf cluster and the
1951 * data pointer is fixed up to point just past it.
1954 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm)
1958 struct fxp_rfa *rfa, *p_rfa;
1960 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1961 if (m == NULL) { /* try to recycle the old mbuf instead */
1965 m->m_data = m->m_ext.ext_buf;
1969 * Move the data pointer up so that the incoming data packet
1970 * will be 32-bit aligned.
1972 m->m_data += RFA_ALIGNMENT_FUDGE;
1975 * Get a pointer to the base of the mbuf cluster and move
1976 * data start past it.
1978 rfa = mtod(m, struct fxp_rfa *);
1979 m->m_data += sizeof(struct fxp_rfa);
1980 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) -
1981 RFA_ALIGNMENT_FUDGE);
1984 * Initialize the rest of the RFA. Note that since the RFA
1985 * is misaligned, we cannot store values directly. Instead,
1986 * we use an optimized, inline copy.
1989 rfa->rfa_status = 0;
1990 rfa->rfa_control = FXP_RFA_CONTROL_EL;
1991 rfa->actual_size = 0;
1994 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr);
1995 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr);
1998 * If there are other buffers already on the list, attach this
1999 * one to the end by fixing up the tail to point to this one.
2001 if (sc->rfa_headm != NULL) {
2002 p_rfa = (struct fxp_rfa *)(sc->rfa_tailm->m_ext.ext_buf +
2003 RFA_ALIGNMENT_FUDGE);
2004 sc->rfa_tailm->m_next = m;
2006 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr);
2007 p_rfa->rfa_control = 0;
2017 fxp_miibus_readreg(device_t dev, int phy, int reg)
2019 struct fxp_softc *sc = device_get_softc(dev);
2023 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2024 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2026 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2031 device_printf(dev, "fxp_miibus_readreg: timed out\n");
2033 return (value & 0xffff);
2037 fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2039 struct fxp_softc *sc = device_get_softc(dev);
2042 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2043 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2046 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2051 device_printf(dev, "fxp_miibus_writereg: timed out\n");
2055 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2057 struct fxp_softc *sc = ifp->if_softc;
2058 struct ifreq *ifr = (struct ifreq *)data;
2059 struct mii_data *mii;
2062 ASSERT_SERIALIZED(ifp->if_serializer);
2067 if (ifp->if_flags & IFF_ALLMULTI)
2068 sc->flags |= FXP_FLAG_ALL_MCAST;
2070 sc->flags &= ~FXP_FLAG_ALL_MCAST;
2073 * If interface is marked up and not running, then start it.
2074 * If it is marked down and running, stop it.
2075 * XXX If it's up then re-initialize it. This is so flags
2076 * such as IFF_PROMISC are handled.
2078 if (ifp->if_flags & IFF_UP) {
2081 if (ifp->if_flags & IFF_RUNNING)
2088 if (ifp->if_flags & IFF_ALLMULTI)
2089 sc->flags |= FXP_FLAG_ALL_MCAST;
2091 sc->flags &= ~FXP_FLAG_ALL_MCAST;
2093 * Multicast list has changed; set the hardware filter
2096 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
2099 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
2100 * again rather than else {}.
2102 if (sc->flags & FXP_FLAG_ALL_MCAST)
2109 if (sc->miibus != NULL) {
2110 mii = device_get_softc(sc->miibus);
2111 error = ifmedia_ioctl(ifp, ifr,
2112 &mii->mii_media, command);
2114 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2119 error = ether_ioctl(ifp, command, data);
2126 * Fill in the multicast address list and return number of entries.
2129 fxp_mc_addrs(struct fxp_softc *sc)
2131 struct fxp_cb_mcs *mcsp = sc->mcsp;
2132 struct ifnet *ifp = &sc->arpcom.ac_if;
2133 struct ifmultiaddr *ifma;
2137 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
2138 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2139 if (ifma->ifma_addr->sa_family != AF_LINK)
2141 if (nmcasts >= MAXMCADDR) {
2142 sc->flags |= FXP_FLAG_ALL_MCAST;
2146 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2147 (void *)(uintptr_t)(volatile void *)
2148 &sc->mcsp->mc_addr[nmcasts][0], 6);
2152 mcsp->mc_cnt = nmcasts * 6;
2157 * Program the multicast filter.
2159 * We have an artificial restriction that the multicast setup command
2160 * must be the first command in the chain, so we take steps to ensure
2161 * this. By requiring this, it allows us to keep up the performance of
2162 * the pre-initialized command ring (esp. link pointers) by not actually
2163 * inserting the mcsetup command in the ring - i.e. its link pointer
2164 * points to the TxCB ring, but the mcsetup descriptor itself is not part
2165 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2166 * lead into the regular TxCB ring when it completes.
2168 * This function must be called at splimp.
2171 fxp_mc_setup(struct fxp_softc *sc)
2173 struct fxp_cb_mcs *mcsp = sc->mcsp;
2174 struct ifnet *ifp = &sc->arpcom.ac_if;
2178 * If there are queued commands, we must wait until they are all
2179 * completed. If we are already waiting, then add a NOP command
2180 * with interrupt option so that we're notified when all commands
2181 * have been completed - fxp_start() ensures that no additional
2182 * TX commands will be added when need_mcsetup is true.
2184 if (sc->tx_queued) {
2185 struct fxp_cb_tx *txp;
2188 * need_mcsetup will be true if we are already waiting for the
2189 * NOP command to be completed (see below). In this case, bail.
2191 if (sc->need_mcsetup)
2193 sc->need_mcsetup = 1;
2196 * Add a NOP command with interrupt so that we are notified
2197 * when all TX commands have been processed.
2199 txp = sc->cbl_last->next;
2200 txp->mb_head = NULL;
2202 txp->cb_command = FXP_CB_COMMAND_NOP |
2203 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2205 * Advance the end of list forward.
2207 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
2211 * Issue a resume in case the CU has just suspended.
2214 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2216 * Set a 5 second timer just in case we don't hear from the
2223 sc->need_mcsetup = 0;
2226 * Initialize multicast setup descriptor.
2228 mcsp->next = sc->cbl_base;
2229 mcsp->mb_head = NULL;
2230 mcsp->cb_status = 0;
2231 mcsp->cb_command = FXP_CB_COMMAND_MCAS |
2232 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2233 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status);
2235 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp;
2239 * Wait until command unit is not active. This should never
2240 * be the case when nothing is queued, but make sure anyway.
2243 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2244 FXP_SCB_CUS_ACTIVE && --count)
2247 if_printf(&sc->arpcom.ac_if, "command queue timeout\n");
2252 * Start the multicast setup command.
2255 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
2256 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2262 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
2263 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
2264 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
2265 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
2266 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
2267 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
2269 #define UCODE(x) x, sizeof(x)
2275 u_short int_delay_offset;
2276 u_short bundle_max_offset;
2278 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
2279 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
2280 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
2281 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
2282 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
2283 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
2284 { FXP_REV_82550, UCODE(fxp_ucode_d102),
2285 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
2286 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
2287 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
2288 { 0, NULL, 0, 0, 0 }
2292 fxp_load_ucode(struct fxp_softc *sc)
2295 struct fxp_cb_ucode *cbp;
2297 for (uc = ucode_table; uc->ucode != NULL; uc++)
2298 if (sc->revision == uc->revision)
2300 if (uc->ucode == NULL)
2302 cbp = (struct fxp_cb_ucode *)sc->cbl_base;
2304 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL;
2305 cbp->link_addr = -1; /* (no) next command */
2306 memcpy(cbp->ucode, uc->ucode, uc->length);
2307 if (uc->int_delay_offset)
2308 *(u_short *)&cbp->ucode[uc->int_delay_offset] =
2309 sc->tunable_int_delay + sc->tunable_int_delay / 2;
2310 if (uc->bundle_max_offset)
2311 *(u_short *)&cbp->ucode[uc->bundle_max_offset] =
2312 sc->tunable_bundle_max;
2314 * Download the ucode to the chip.
2317 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
2318 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2319 /* ...and wait for it to complete. */
2320 fxp_dma_wait(&cbp->cb_status, sc);
2321 if_printf(&sc->arpcom.ac_if,
2322 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
2323 sc->tunable_int_delay,
2324 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
2325 sc->flags |= FXP_FLAG_UCODE;
2329 * Interrupt delay is expressed in microseconds, a multiplier is used
2330 * to convert this to the appropriate clock ticks before using.
2333 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
2335 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
2339 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
2341 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));