2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $
30 #include "opt_polling.h"
33 #include <sys/param.h>
34 #include <sys/endian.h>
35 #include <sys/kernel.h>
37 #include <sys/interrupt.h>
38 #include <sys/malloc.h>
41 #include <sys/serialize.h>
42 #include <sys/serialize2.h>
43 #include <sys/socket.h>
44 #include <sys/sockio.h>
45 #include <sys/sysctl.h>
47 #include <net/ethernet.h>
50 #include <net/if_arp.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
53 #include <net/ifq_var.h>
54 #include <net/toeplitz.h>
55 #include <net/toeplitz2.h>
56 #include <net/vlan/if_vlan_var.h>
57 #include <net/vlan/if_vlan_ether.h>
59 #include <netinet/in.h>
61 #include <dev/netif/mii_layer/miivar.h>
62 #include <dev/netif/mii_layer/jmphyreg.h>
64 #include <bus/pci/pcireg.h>
65 #include <bus/pci/pcivar.h>
66 #include <bus/pci/pcidevs.h>
68 #include <dev/netif/jme/if_jmereg.h>
69 #include <dev/netif/jme/if_jmevar.h>
71 #include "miibus_if.h"
73 #define JME_TX_SERIALIZE 1
74 #define JME_RX_SERIALIZE 2
76 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
79 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \
81 if ((sc)->jme_rss_debug >= (lvl)) \
82 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \
84 #else /* !JME_RSS_DEBUG */
85 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
86 #endif /* JME_RSS_DEBUG */
88 static int jme_probe(device_t);
89 static int jme_attach(device_t);
90 static int jme_detach(device_t);
91 static int jme_shutdown(device_t);
92 static int jme_suspend(device_t);
93 static int jme_resume(device_t);
95 static int jme_miibus_readreg(device_t, int, int);
96 static int jme_miibus_writereg(device_t, int, int, int);
97 static void jme_miibus_statchg(device_t);
99 static void jme_init(void *);
100 static int jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
101 static void jme_start(struct ifnet *);
102 static void jme_watchdog(struct ifnet *);
103 static void jme_mediastatus(struct ifnet *, struct ifmediareq *);
104 static int jme_mediachange(struct ifnet *);
105 #ifdef DEVICE_POLLING
106 static void jme_poll(struct ifnet *, enum poll_cmd, int);
108 static void jme_serialize(struct ifnet *, enum ifnet_serialize);
109 static void jme_deserialize(struct ifnet *, enum ifnet_serialize);
110 static int jme_tryserialize(struct ifnet *, enum ifnet_serialize);
112 static void jme_serialize_assert(struct ifnet *, enum ifnet_serialize,
116 static void jme_intr(void *);
117 static void jme_msix_tx(void *);
118 static void jme_msix_rx(void *);
119 static void jme_txeof(struct jme_softc *);
120 static void jme_rxeof(struct jme_rxdata *, int);
121 static void jme_rx_intr(struct jme_softc *, uint32_t);
123 static int jme_msix_setup(device_t);
124 static void jme_msix_teardown(device_t, int);
125 static int jme_intr_setup(device_t);
126 static void jme_intr_teardown(device_t);
127 static void jme_msix_try_alloc(device_t);
128 static void jme_msix_free(device_t);
129 static int jme_intr_alloc(device_t);
130 static void jme_intr_free(device_t);
131 static int jme_dma_alloc(struct jme_softc *);
132 static void jme_dma_free(struct jme_softc *);
133 static int jme_init_rx_ring(struct jme_rxdata *);
134 static void jme_init_tx_ring(struct jme_softc *);
135 static void jme_init_ssb(struct jme_softc *);
136 static int jme_newbuf(struct jme_rxdata *, struct jme_rxdesc *, int);
137 static int jme_encap(struct jme_softc *, struct mbuf **);
138 static void jme_rxpkt(struct jme_rxdata *);
139 static int jme_rxring_dma_alloc(struct jme_rxdata *);
140 static int jme_rxbuf_dma_alloc(struct jme_rxdata *);
141 static int jme_rxbuf_dma_filter(void *, bus_addr_t);
143 static void jme_tick(void *);
144 static void jme_stop(struct jme_softc *);
145 static void jme_reset(struct jme_softc *);
146 static void jme_set_msinum(struct jme_softc *);
147 static void jme_set_vlan(struct jme_softc *);
148 static void jme_set_filter(struct jme_softc *);
149 static void jme_stop_tx(struct jme_softc *);
150 static void jme_stop_rx(struct jme_softc *);
151 static void jme_mac_config(struct jme_softc *);
152 static void jme_reg_macaddr(struct jme_softc *, uint8_t[]);
153 static int jme_eeprom_macaddr(struct jme_softc *, uint8_t[]);
154 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
156 static void jme_setwol(struct jme_softc *);
157 static void jme_setlinkspeed(struct jme_softc *);
159 static void jme_set_tx_coal(struct jme_softc *);
160 static void jme_set_rx_coal(struct jme_softc *);
161 static void jme_enable_rss(struct jme_softc *);
162 static void jme_disable_rss(struct jme_softc *);
163 static void jme_serialize_skipmain(struct jme_softc *);
164 static void jme_deserialize_skipmain(struct jme_softc *);
166 static void jme_sysctl_node(struct jme_softc *);
167 static int jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS);
168 static int jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
169 static int jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS);
170 static int jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
173 * Devices supported by this driver.
175 static const struct jme_dev {
176 uint16_t jme_vendorid;
177 uint16_t jme_deviceid;
179 const char *jme_name;
181 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250,
183 "JMicron Inc, JMC250 Gigabit Ethernet" },
184 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260,
186 "JMicron Inc, JMC260 Fast Ethernet" },
190 static device_method_t jme_methods[] = {
191 /* Device interface. */
192 DEVMETHOD(device_probe, jme_probe),
193 DEVMETHOD(device_attach, jme_attach),
194 DEVMETHOD(device_detach, jme_detach),
195 DEVMETHOD(device_shutdown, jme_shutdown),
196 DEVMETHOD(device_suspend, jme_suspend),
197 DEVMETHOD(device_resume, jme_resume),
200 DEVMETHOD(bus_print_child, bus_generic_print_child),
201 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
204 DEVMETHOD(miibus_readreg, jme_miibus_readreg),
205 DEVMETHOD(miibus_writereg, jme_miibus_writereg),
206 DEVMETHOD(miibus_statchg, jme_miibus_statchg),
211 static driver_t jme_driver = {
214 sizeof(struct jme_softc)
217 static devclass_t jme_devclass;
219 DECLARE_DUMMY_MODULE(if_jme);
220 MODULE_DEPEND(if_jme, miibus, 1, 1, 1);
221 DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, NULL, NULL);
222 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, NULL, NULL);
224 static const struct {
228 } jme_rx_status[JME_NRXRING_MAX] = {
229 { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP,
230 INTR_RXQ0_DESC_EMPTY },
231 { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP,
232 INTR_RXQ1_DESC_EMPTY },
233 { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP,
234 INTR_RXQ2_DESC_EMPTY },
235 { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP,
236 INTR_RXQ3_DESC_EMPTY }
239 static int jme_rx_desc_count = JME_RX_DESC_CNT_DEF;
240 static int jme_tx_desc_count = JME_TX_DESC_CNT_DEF;
241 static int jme_rx_ring_count = 0;
242 static int jme_msi_enable = 1;
243 static int jme_msix_enable = 1;
245 TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count);
246 TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count);
247 TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count);
248 TUNABLE_INT("hw.jme.msi.enable", &jme_msi_enable);
249 TUNABLE_INT("hw.jme.msix.enable", &jme_msix_enable);
252 jme_setup_rxdesc(struct jme_rxdesc *rxd)
254 struct jme_desc *desc;
257 desc->buflen = htole32(MCLBYTES);
258 desc->addr_lo = htole32(JME_ADDR_LO(rxd->rx_paddr));
259 desc->addr_hi = htole32(JME_ADDR_HI(rxd->rx_paddr));
260 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
264 * Read a PHY register on the MII of the JMC250.
267 jme_miibus_readreg(device_t dev, int phy, int reg)
269 struct jme_softc *sc = device_get_softc(dev);
273 /* For FPGA version, PHY address 0 should be ignored. */
274 if (sc->jme_caps & JME_CAP_FPGA) {
278 if (sc->jme_phyaddr != phy)
282 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
283 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
285 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
287 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
291 device_printf(sc->jme_dev, "phy read timeout: "
292 "phy %d, reg %d\n", phy, reg);
296 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
300 * Write a PHY register on the MII of the JMC250.
303 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
305 struct jme_softc *sc = device_get_softc(dev);
308 /* For FPGA version, PHY address 0 should be ignored. */
309 if (sc->jme_caps & JME_CAP_FPGA) {
313 if (sc->jme_phyaddr != phy)
317 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
318 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
319 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
321 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
323 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
327 device_printf(sc->jme_dev, "phy write timeout: "
328 "phy %d, reg %d\n", phy, reg);
335 * Callback from MII layer when media changes.
338 jme_miibus_statchg(device_t dev)
340 struct jme_softc *sc = device_get_softc(dev);
341 struct ifnet *ifp = &sc->arpcom.ac_if;
342 struct mii_data *mii;
343 struct jme_txdesc *txd;
348 jme_serialize_skipmain(sc);
349 ASSERT_IFNET_SERIALIZED_ALL(ifp);
351 if ((ifp->if_flags & IFF_RUNNING) == 0)
354 mii = device_get_softc(sc->jme_miibus);
356 sc->jme_has_link = FALSE;
357 if ((mii->mii_media_status & IFM_AVALID) != 0) {
358 switch (IFM_SUBTYPE(mii->mii_media_active)) {
361 sc->jme_has_link = TRUE;
364 if (sc->jme_caps & JME_CAP_FASTETH)
366 sc->jme_has_link = TRUE;
374 * Disabling Rx/Tx MACs have a side-effect of resetting
375 * JME_TXNDA/JME_RXNDA register to the first address of
376 * Tx/Rx descriptor address. So driver should reset its
377 * internal procucer/consumer pointer and reclaim any
378 * allocated resources. Note, just saving the value of
379 * JME_TXNDA and JME_RXNDA registers before stopping MAC
380 * and restoring JME_TXNDA/JME_RXNDA register is not
381 * sufficient to make sure correct MAC state because
382 * stopping MAC operation can take a while and hardware
383 * might have updated JME_TXNDA/JME_RXNDA registers
384 * during the stop operation.
387 /* Disable interrupts */
388 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
391 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
393 callout_stop(&sc->jme_tick_ch);
395 /* Stop receiver/transmitter. */
399 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
400 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
402 jme_rxeof(rdata, -1);
403 if (rdata->jme_rxhead != NULL)
404 m_freem(rdata->jme_rxhead);
405 JME_RXCHAIN_RESET(rdata);
408 * Reuse configured Rx descriptors and reset
409 * procuder/consumer index.
411 rdata->jme_rx_cons = 0;
413 if (JME_ENABLE_HWRSS(sc))
419 if (sc->jme_cdata.jme_tx_cnt != 0) {
420 /* Remove queued packets for transmit. */
421 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
422 txd = &sc->jme_cdata.jme_txdesc[i];
423 if (txd->tx_m != NULL) {
425 sc->jme_cdata.jme_tx_tag,
434 jme_init_tx_ring(sc);
436 /* Initialize shadow status block. */
439 /* Program MAC with resolved speed/duplex/flow-control. */
440 if (sc->jme_has_link) {
443 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
445 /* Set Tx ring address to the hardware. */
446 paddr = sc->jme_cdata.jme_tx_ring_paddr;
447 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
448 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
450 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
451 CSR_WRITE_4(sc, JME_RXCSR,
452 sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
454 /* Set Rx ring address to the hardware. */
455 paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
456 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
457 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
460 /* Restart receiver/transmitter. */
461 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
463 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
466 ifp->if_flags |= IFF_RUNNING;
467 ifp->if_flags &= ~IFF_OACTIVE;
468 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
470 #ifdef DEVICE_POLLING
471 if (!(ifp->if_flags & IFF_POLLING))
473 /* Reenable interrupts. */
474 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
478 jme_deserialize_skipmain(sc);
482 * Get the current interface media status.
485 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
487 struct jme_softc *sc = ifp->if_softc;
488 struct mii_data *mii = device_get_softc(sc->jme_miibus);
490 ASSERT_IFNET_SERIALIZED_ALL(ifp);
493 ifmr->ifm_status = mii->mii_media_status;
494 ifmr->ifm_active = mii->mii_media_active;
498 * Set hardware to newly-selected media.
501 jme_mediachange(struct ifnet *ifp)
503 struct jme_softc *sc = ifp->if_softc;
504 struct mii_data *mii = device_get_softc(sc->jme_miibus);
507 ASSERT_IFNET_SERIALIZED_ALL(ifp);
509 if (mii->mii_instance != 0) {
510 struct mii_softc *miisc;
512 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
513 mii_phy_reset(miisc);
515 error = mii_mediachg(mii);
521 jme_probe(device_t dev)
523 const struct jme_dev *sp;
526 vid = pci_get_vendor(dev);
527 did = pci_get_device(dev);
528 for (sp = jme_devs; sp->jme_name != NULL; ++sp) {
529 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) {
530 struct jme_softc *sc = device_get_softc(dev);
532 sc->jme_caps = sp->jme_caps;
533 device_set_desc(dev, sp->jme_name);
541 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
547 for (i = JME_TIMEOUT; i > 0; i--) {
548 reg = CSR_READ_4(sc, JME_SMBCSR);
549 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
555 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
559 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
560 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
561 for (i = JME_TIMEOUT; i > 0; i--) {
563 reg = CSR_READ_4(sc, JME_SMBINTF);
564 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
569 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
573 reg = CSR_READ_4(sc, JME_SMBINTF);
574 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
580 jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[])
582 uint8_t fup, reg, val;
587 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
588 fup != JME_EEPROM_SIG0)
590 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
591 fup != JME_EEPROM_SIG1)
595 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
597 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
598 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
599 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0)
601 if (reg >= JME_PAR0 &&
602 reg < JME_PAR0 + ETHER_ADDR_LEN) {
603 if (jme_eeprom_read_byte(sc, offset + 2,
606 eaddr[reg - JME_PAR0] = val;
610 /* Check for the end of EEPROM descriptor. */
611 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
613 /* Try next eeprom descriptor. */
614 offset += JME_EEPROM_DESC_BYTES;
615 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
617 if (match == ETHER_ADDR_LEN)
624 jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[])
628 /* Read station address. */
629 par0 = CSR_READ_4(sc, JME_PAR0);
630 par1 = CSR_READ_4(sc, JME_PAR1);
632 if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) {
633 device_printf(sc->jme_dev,
634 "generating fake ethernet address.\n");
635 par0 = karc4random();
636 /* Set OUI to JMicron. */
640 eaddr[3] = (par0 >> 16) & 0xff;
641 eaddr[4] = (par0 >> 8) & 0xff;
642 eaddr[5] = par0 & 0xff;
644 eaddr[0] = (par0 >> 0) & 0xFF;
645 eaddr[1] = (par0 >> 8) & 0xFF;
646 eaddr[2] = (par0 >> 16) & 0xFF;
647 eaddr[3] = (par0 >> 24) & 0xFF;
648 eaddr[4] = (par1 >> 0) & 0xFF;
649 eaddr[5] = (par1 >> 8) & 0xFF;
654 jme_attach(device_t dev)
656 struct jme_softc *sc = device_get_softc(dev);
657 struct ifnet *ifp = &sc->arpcom.ac_if;
660 uint8_t pcie_ptr, rev;
661 int error = 0, i, j, rx_desc_cnt;
662 uint8_t eaddr[ETHER_ADDR_LEN];
664 device_printf(dev, "rxdata %zu, chain_data %zu\n",
665 sizeof(struct jme_rxdata), sizeof(struct jme_chain_data));
667 lwkt_serialize_init(&sc->jme_serialize);
668 lwkt_serialize_init(&sc->jme_cdata.jme_tx_serialize);
669 for (i = 0; i < JME_NRXRING_MAX; ++i) {
671 &sc->jme_cdata.jme_rx_data[i].jme_rx_serialize);
674 rx_desc_cnt = device_getenv_int(dev, "rx_desc_count",
676 rx_desc_cnt = roundup(rx_desc_cnt, JME_NDESC_ALIGN);
677 if (rx_desc_cnt > JME_NDESC_MAX)
678 rx_desc_cnt = JME_NDESC_MAX;
680 sc->jme_cdata.jme_tx_desc_cnt = device_getenv_int(dev, "tx_desc_count",
682 sc->jme_cdata.jme_tx_desc_cnt = roundup(sc->jme_cdata.jme_tx_desc_cnt,
684 if (sc->jme_cdata.jme_tx_desc_cnt > JME_NDESC_MAX)
685 sc->jme_cdata.jme_tx_desc_cnt = JME_NDESC_MAX;
690 sc->jme_cdata.jme_rx_ring_cnt = device_getenv_int(dev, "rx_ring_count",
692 sc->jme_cdata.jme_rx_ring_cnt =
693 if_ring_count2(sc->jme_cdata.jme_rx_ring_cnt, JME_NRXRING_MAX);
696 sc->jme_serialize_arr[i++] = &sc->jme_serialize;
698 KKASSERT(i == JME_TX_SERIALIZE);
699 sc->jme_serialize_arr[i++] = &sc->jme_cdata.jme_tx_serialize;
701 KKASSERT(i == JME_RX_SERIALIZE);
702 for (j = 0; j < sc->jme_cdata.jme_rx_ring_cnt; ++j) {
703 sc->jme_serialize_arr[i++] =
704 &sc->jme_cdata.jme_rx_data[j].jme_rx_serialize;
706 KKASSERT(i <= JME_NSERIALIZE);
707 sc->jme_serialize_cnt = i;
709 sc->jme_cdata.jme_sc = sc;
710 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
711 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
714 rdata->jme_rx_coal = jme_rx_status[i].jme_coal;
715 rdata->jme_rx_comp = jme_rx_status[i].jme_comp;
716 rdata->jme_rx_empty = jme_rx_status[i].jme_empty;
717 rdata->jme_rx_idx = i;
718 rdata->jme_rx_desc_cnt = rx_desc_cnt;
722 sc->jme_lowaddr = BUS_SPACE_MAXADDR;
724 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
726 callout_init(&sc->jme_tick_ch);
729 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
732 irq = pci_read_config(dev, PCIR_INTLINE, 4);
733 mem = pci_read_config(dev, JME_PCIR_BAR, 4);
735 device_printf(dev, "chip is in D%d power mode "
736 "-- setting to D0\n", pci_get_powerstate(dev));
738 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
740 pci_write_config(dev, PCIR_INTLINE, irq, 4);
741 pci_write_config(dev, JME_PCIR_BAR, mem, 4);
743 #endif /* !BURN_BRIDGE */
745 /* Enable bus mastering */
746 pci_enable_busmaster(dev);
751 * JMC250 supports both memory mapped and I/O register space
752 * access. Because I/O register access should use different
753 * BARs to access registers it's waste of time to use I/O
754 * register spce access. JMC250 uses 16K to map entire memory
757 sc->jme_mem_rid = JME_PCIR_BAR;
758 sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
759 &sc->jme_mem_rid, RF_ACTIVE);
760 if (sc->jme_mem_res == NULL) {
761 device_printf(dev, "can't allocate IO memory\n");
764 sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res);
765 sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res);
770 error = jme_intr_alloc(dev);
777 reg = CSR_READ_4(sc, JME_CHIPMODE);
778 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
780 sc->jme_caps |= JME_CAP_FPGA;
782 device_printf(dev, "FPGA revision: 0x%04x\n",
783 (reg & CHIPMODE_FPGA_REV_MASK) >>
784 CHIPMODE_FPGA_REV_SHIFT);
788 /* NOTE: FM revision is put in the upper 4 bits */
789 rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4;
790 rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT;
792 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev);
794 did = pci_get_device(dev);
796 case PCI_PRODUCT_JMICRON_JMC250:
797 if (rev == JME_REV1_A2)
798 sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX;
801 case PCI_PRODUCT_JMICRON_JMC260:
803 sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT;
807 panic("unknown device id 0x%04x", did);
809 if (rev >= JME_REV2) {
810 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC;
811 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 |
812 GHC_TXMAC_CLKSRC_1000;
815 /* Reset the ethernet controller. */
818 /* Map MSI/MSI-X vectors */
821 /* Get station address. */
822 reg = CSR_READ_4(sc, JME_SMBCSR);
823 if (reg & SMBCSR_EEPROM_PRESENT)
824 error = jme_eeprom_macaddr(sc, eaddr);
825 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
826 if (error != 0 && (bootverbose)) {
827 device_printf(dev, "ethernet hardware address "
828 "not found in EEPROM.\n");
830 jme_reg_macaddr(sc, eaddr);
835 * Integrated JR0211 has fixed PHY address whereas FPGA version
836 * requires PHY probing to get correct PHY address.
838 if ((sc->jme_caps & JME_CAP_FPGA) == 0) {
839 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
840 GPREG0_PHY_ADDR_MASK;
842 device_printf(dev, "PHY is at address %d.\n",
849 /* Set max allowable DMA size. */
850 pcie_ptr = pci_get_pciecap_ptr(dev);
854 sc->jme_caps |= JME_CAP_PCIE;
855 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
857 device_printf(dev, "Read request size : %d bytes.\n",
858 128 << ((ctrl >> 12) & 0x07));
859 device_printf(dev, "TLP payload size : %d bytes.\n",
860 128 << ((ctrl >> 5) & 0x07));
862 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) {
863 case PCIEM_DEVCTL_MAX_READRQ_128:
864 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
866 case PCIEM_DEVCTL_MAX_READRQ_256:
867 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
870 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
873 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
875 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
876 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
880 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
881 sc->jme_caps |= JME_CAP_PMCAP;
889 /* Allocate DMA stuffs */
890 error = jme_dma_alloc(sc);
895 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
896 ifp->if_init = jme_init;
897 ifp->if_ioctl = jme_ioctl;
898 ifp->if_start = jme_start;
899 #ifdef DEVICE_POLLING
900 ifp->if_poll = jme_poll;
902 ifp->if_watchdog = jme_watchdog;
903 ifp->if_serialize = jme_serialize;
904 ifp->if_deserialize = jme_deserialize;
905 ifp->if_tryserialize = jme_tryserialize;
907 ifp->if_serialize_assert = jme_serialize_assert;
909 ifq_set_maxlen(&ifp->if_snd,
910 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
911 ifq_set_ready(&ifp->if_snd);
913 /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */
914 ifp->if_capabilities = IFCAP_HWCSUM |
916 IFCAP_VLAN_HWTAGGING;
917 if (sc->jme_cdata.jme_rx_ring_cnt > JME_NRXRING_MIN)
918 ifp->if_capabilities |= IFCAP_RSS;
919 ifp->if_capenable = ifp->if_capabilities;
922 * Disable TXCSUM by default to improve bulk data
923 * transmit performance (+20Mbps improvement).
925 ifp->if_capenable &= ~IFCAP_TXCSUM;
927 if (ifp->if_capenable & IFCAP_TXCSUM)
928 ifp->if_hwassist = JME_CSUM_FEATURES;
930 /* Set up MII bus. */
931 error = mii_phy_probe(dev, &sc->jme_miibus,
932 jme_mediachange, jme_mediastatus);
934 device_printf(dev, "no PHY found!\n");
939 * Save PHYADDR for FPGA mode PHY.
941 if (sc->jme_caps & JME_CAP_FPGA) {
942 struct mii_data *mii = device_get_softc(sc->jme_miibus);
944 if (mii->mii_instance != 0) {
945 struct mii_softc *miisc;
947 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
948 if (miisc->mii_phy != 0) {
949 sc->jme_phyaddr = miisc->mii_phy;
953 if (sc->jme_phyaddr != 0) {
954 device_printf(sc->jme_dev,
955 "FPGA PHY is at %d\n", sc->jme_phyaddr);
957 jme_miibus_writereg(dev, sc->jme_phyaddr,
958 JMPHY_CONF, JMPHY_CONF_DEFFIFO);
960 /* XXX should we clear JME_WA_EXTFIFO */
965 ether_ifattach(ifp, eaddr, NULL);
967 /* Tell the upper layer(s) we support long frames. */
968 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
970 error = jme_intr_setup(dev);
983 jme_detach(device_t dev)
985 struct jme_softc *sc = device_get_softc(dev);
987 if (device_is_attached(dev)) {
988 struct ifnet *ifp = &sc->arpcom.ac_if;
990 ifnet_serialize_all(ifp);
992 jme_intr_teardown(dev);
993 ifnet_deserialize_all(ifp);
998 if (sc->jme_sysctl_tree != NULL)
999 sysctl_ctx_free(&sc->jme_sysctl_ctx);
1001 if (sc->jme_miibus != NULL)
1002 device_delete_child(dev, sc->jme_miibus);
1003 bus_generic_detach(dev);
1007 if (sc->jme_mem_res != NULL) {
1008 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid,
1018 jme_sysctl_node(struct jme_softc *sc)
1021 #ifdef JME_RSS_DEBUG
1025 sysctl_ctx_init(&sc->jme_sysctl_ctx);
1026 sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx,
1027 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1028 device_get_nameunit(sc->jme_dev),
1030 if (sc->jme_sysctl_tree == NULL) {
1031 device_printf(sc->jme_dev, "can't add sysctl node\n");
1035 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1036 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1037 "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1038 sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout");
1040 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1041 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1042 "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1043 sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet");
1045 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1046 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1047 "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1048 sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout");
1050 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1051 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1052 "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1053 sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet");
1055 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1056 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1057 "rx_desc_count", CTLFLAG_RD,
1058 &sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt,
1059 0, "RX desc count");
1060 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1061 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1062 "tx_desc_count", CTLFLAG_RD,
1063 &sc->jme_cdata.jme_tx_desc_cnt,
1064 0, "TX desc count");
1065 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1066 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1067 "rx_ring_count", CTLFLAG_RD,
1068 &sc->jme_cdata.jme_rx_ring_cnt,
1069 0, "RX ring count");
1070 #ifdef JME_RSS_DEBUG
1071 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1072 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1073 "rss_debug", CTLFLAG_RW, &sc->jme_rss_debug,
1074 0, "RSS debug level");
1075 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1076 char rx_ring_pkt[32];
1078 ksnprintf(rx_ring_pkt, sizeof(rx_ring_pkt), "rx_ring%d_pkt", r);
1079 SYSCTL_ADD_ULONG(&sc->jme_sysctl_ctx,
1080 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1081 rx_ring_pkt, CTLFLAG_RW,
1082 &sc->jme_cdata.jme_rx_data[r].jme_rx_pkt, "RXed packets");
1087 * Set default coalesce valves
1089 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
1090 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
1091 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
1092 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
1095 * Adjust coalesce valves, in case that the number of TX/RX
1096 * descs are set to small values by users.
1098 * NOTE: coal_max will not be zero, since number of descs
1099 * must aligned by JME_NDESC_ALIGN (16 currently)
1101 coal_max = sc->jme_cdata.jme_tx_desc_cnt / 6;
1102 if (coal_max < sc->jme_tx_coal_pkt)
1103 sc->jme_tx_coal_pkt = coal_max;
1105 coal_max = sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt / 4;
1106 if (coal_max < sc->jme_rx_coal_pkt)
1107 sc->jme_rx_coal_pkt = coal_max;
1111 jme_dma_alloc(struct jme_softc *sc)
1113 struct jme_txdesc *txd;
1115 int error, i, asize;
1117 sc->jme_cdata.jme_txdesc =
1118 kmalloc(sc->jme_cdata.jme_tx_desc_cnt * sizeof(struct jme_txdesc),
1119 M_DEVBUF, M_WAITOK | M_ZERO);
1120 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1121 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
1124 kmalloc(rdata->jme_rx_desc_cnt * sizeof(struct jme_rxdesc),
1125 M_DEVBUF, M_WAITOK | M_ZERO);
1128 /* Create parent ring tag. */
1129 error = bus_dma_tag_create(NULL,/* parent */
1130 1, JME_RING_BOUNDARY, /* algnmnt, boundary */
1131 sc->jme_lowaddr, /* lowaddr */
1132 BUS_SPACE_MAXADDR, /* highaddr */
1133 NULL, NULL, /* filter, filterarg */
1134 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1136 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1138 &sc->jme_cdata.jme_ring_tag);
1140 device_printf(sc->jme_dev,
1141 "could not create parent ring DMA tag.\n");
1146 * Create DMA stuffs for TX ring
1148 asize = roundup2(JME_TX_RING_SIZE(sc), JME_TX_RING_ALIGN);
1149 error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
1150 JME_TX_RING_ALIGN, 0,
1151 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1152 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1154 device_printf(sc->jme_dev, "could not allocate Tx ring.\n");
1157 sc->jme_cdata.jme_tx_ring_tag = dmem.dmem_tag;
1158 sc->jme_cdata.jme_tx_ring_map = dmem.dmem_map;
1159 sc->jme_cdata.jme_tx_ring = dmem.dmem_addr;
1160 sc->jme_cdata.jme_tx_ring_paddr = dmem.dmem_busaddr;
1163 * Create DMA stuffs for RX rings
1165 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1166 error = jme_rxring_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
1171 /* Create parent buffer tag. */
1172 error = bus_dma_tag_create(NULL,/* parent */
1173 1, 0, /* algnmnt, boundary */
1174 sc->jme_lowaddr, /* lowaddr */
1175 BUS_SPACE_MAXADDR, /* highaddr */
1176 NULL, NULL, /* filter, filterarg */
1177 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1179 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1181 &sc->jme_cdata.jme_buffer_tag);
1183 device_printf(sc->jme_dev,
1184 "could not create parent buffer DMA tag.\n");
1189 * Create DMA stuffs for shadow status block
1191 asize = roundup2(JME_SSB_SIZE, JME_SSB_ALIGN);
1192 error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag,
1193 JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1194 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1196 device_printf(sc->jme_dev,
1197 "could not create shadow status block.\n");
1200 sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag;
1201 sc->jme_cdata.jme_ssb_map = dmem.dmem_map;
1202 sc->jme_cdata.jme_ssb_block = dmem.dmem_addr;
1203 sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr;
1206 * Create DMA stuffs for TX buffers
1209 /* Create tag for Tx buffers. */
1210 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1211 1, 0, /* algnmnt, boundary */
1212 BUS_SPACE_MAXADDR, /* lowaddr */
1213 BUS_SPACE_MAXADDR, /* highaddr */
1214 NULL, NULL, /* filter, filterarg */
1215 JME_JUMBO_FRAMELEN, /* maxsize */
1216 JME_MAXTXSEGS, /* nsegments */
1217 JME_MAXSEGSIZE, /* maxsegsize */
1218 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */
1219 &sc->jme_cdata.jme_tx_tag);
1221 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1225 /* Create DMA maps for Tx buffers. */
1226 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
1227 txd = &sc->jme_cdata.jme_txdesc[i];
1228 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag,
1229 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1234 device_printf(sc->jme_dev,
1235 "could not create %dth Tx dmamap.\n", i);
1237 for (j = 0; j < i; ++j) {
1238 txd = &sc->jme_cdata.jme_txdesc[j];
1239 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1242 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1243 sc->jme_cdata.jme_tx_tag = NULL;
1249 * Create DMA stuffs for RX buffers
1251 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1252 error = jme_rxbuf_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
1260 jme_dma_free(struct jme_softc *sc)
1262 struct jme_txdesc *txd;
1263 struct jme_rxdesc *rxd;
1264 struct jme_rxdata *rdata;
1268 if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1269 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1270 sc->jme_cdata.jme_tx_ring_map);
1271 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1272 sc->jme_cdata.jme_tx_ring,
1273 sc->jme_cdata.jme_tx_ring_map);
1274 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1275 sc->jme_cdata.jme_tx_ring_tag = NULL;
1279 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1280 rdata = &sc->jme_cdata.jme_rx_data[r];
1281 if (rdata->jme_rx_ring_tag != NULL) {
1282 bus_dmamap_unload(rdata->jme_rx_ring_tag,
1283 rdata->jme_rx_ring_map);
1284 bus_dmamem_free(rdata->jme_rx_ring_tag,
1286 rdata->jme_rx_ring_map);
1287 bus_dma_tag_destroy(rdata->jme_rx_ring_tag);
1288 rdata->jme_rx_ring_tag = NULL;
1293 if (sc->jme_cdata.jme_tx_tag != NULL) {
1294 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
1295 txd = &sc->jme_cdata.jme_txdesc[i];
1296 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1299 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1300 sc->jme_cdata.jme_tx_tag = NULL;
1304 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1305 rdata = &sc->jme_cdata.jme_rx_data[r];
1306 if (rdata->jme_rx_tag != NULL) {
1307 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
1308 rxd = &rdata->jme_rxdesc[i];
1309 bus_dmamap_destroy(rdata->jme_rx_tag,
1312 bus_dmamap_destroy(rdata->jme_rx_tag,
1313 rdata->jme_rx_sparemap);
1314 bus_dma_tag_destroy(rdata->jme_rx_tag);
1315 rdata->jme_rx_tag = NULL;
1319 /* Shadow status block. */
1320 if (sc->jme_cdata.jme_ssb_tag != NULL) {
1321 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1322 sc->jme_cdata.jme_ssb_map);
1323 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1324 sc->jme_cdata.jme_ssb_block,
1325 sc->jme_cdata.jme_ssb_map);
1326 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1327 sc->jme_cdata.jme_ssb_tag = NULL;
1330 if (sc->jme_cdata.jme_buffer_tag != NULL) {
1331 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1332 sc->jme_cdata.jme_buffer_tag = NULL;
1334 if (sc->jme_cdata.jme_ring_tag != NULL) {
1335 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1336 sc->jme_cdata.jme_ring_tag = NULL;
1339 if (sc->jme_cdata.jme_txdesc != NULL) {
1340 kfree(sc->jme_cdata.jme_txdesc, M_DEVBUF);
1341 sc->jme_cdata.jme_txdesc = NULL;
1343 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1344 rdata = &sc->jme_cdata.jme_rx_data[r];
1345 if (rdata->jme_rxdesc != NULL) {
1346 kfree(rdata->jme_rxdesc, M_DEVBUF);
1347 rdata->jme_rxdesc = NULL;
1353 * Make sure the interface is stopped at reboot time.
1356 jme_shutdown(device_t dev)
1358 return jme_suspend(dev);
1363 * Unlike other ethernet controllers, JMC250 requires
1364 * explicit resetting link speed to 10/100Mbps as gigabit
1365 * link will cunsume more power than 375mA.
1366 * Note, we reset the link speed to 10/100Mbps with
1367 * auto-negotiation but we don't know whether that operation
1368 * would succeed or not as we have no control after powering
1369 * off. If the renegotiation fail WOL may not work. Running
1370 * at 1Gbps draws more power than 375mA at 3.3V which is
1371 * specified in PCI specification and that would result in
1372 * complete shutdowning power to ethernet controller.
1375 * Save current negotiated media speed/duplex/flow-control
1376 * to softc and restore the same link again after resuming.
1377 * PHY handling such as power down/resetting to 100Mbps
1378 * may be better handled in suspend method in phy driver.
1381 jme_setlinkspeed(struct jme_softc *sc)
1383 struct mii_data *mii;
1386 JME_LOCK_ASSERT(sc);
1388 mii = device_get_softc(sc->jme_miibus);
1391 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1392 switch IFM_SUBTYPE(mii->mii_media_active) {
1402 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1403 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1404 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1405 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1406 BMCR_AUTOEN | BMCR_STARTNEG);
1409 /* Poll link state until jme(4) get a 10/100 link. */
1410 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1412 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1413 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1423 pause("jmelnk", hz);
1426 if (i == MII_ANEGTICKS_GIGE)
1427 device_printf(sc->jme_dev, "establishing link failed, "
1428 "WOL may not work!");
1431 * No link, force MAC to have 100Mbps, full-duplex link.
1432 * This is the last resort and may/may not work.
1434 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1435 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1440 jme_setwol(struct jme_softc *sc)
1442 struct ifnet *ifp = &sc->arpcom.ac_if;
1447 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1448 /* No PME capability, PHY power down. */
1449 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1450 MII_BMCR, BMCR_PDOWN);
1454 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1455 pmcs = CSR_READ_4(sc, JME_PMCS);
1456 pmcs &= ~PMCS_WOL_ENB_MASK;
1457 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1458 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1459 /* Enable PME message. */
1460 gpr |= GPREG0_PME_ENB;
1461 /* For gigabit controllers, reset link speed to 10/100. */
1462 if ((sc->jme_caps & JME_CAP_FASTETH) == 0)
1463 jme_setlinkspeed(sc);
1466 CSR_WRITE_4(sc, JME_PMCS, pmcs);
1467 CSR_WRITE_4(sc, JME_GPREG0, gpr);
1470 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1471 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1472 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1473 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1474 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1475 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1476 /* No WOL, PHY power down. */
1477 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1478 MII_BMCR, BMCR_PDOWN);
1484 jme_suspend(device_t dev)
1486 struct jme_softc *sc = device_get_softc(dev);
1487 struct ifnet *ifp = &sc->arpcom.ac_if;
1489 ifnet_serialize_all(ifp);
1494 ifnet_deserialize_all(ifp);
1500 jme_resume(device_t dev)
1502 struct jme_softc *sc = device_get_softc(dev);
1503 struct ifnet *ifp = &sc->arpcom.ac_if;
1508 ifnet_serialize_all(ifp);
1511 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1514 pmstat = pci_read_config(sc->jme_dev,
1515 pmc + PCIR_POWER_STATUS, 2);
1516 /* Disable PME clear PME status. */
1517 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1518 pci_write_config(sc->jme_dev,
1519 pmc + PCIR_POWER_STATUS, pmstat, 2);
1523 if (ifp->if_flags & IFF_UP)
1526 ifnet_deserialize_all(ifp);
1532 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1534 struct jme_txdesc *txd;
1535 struct jme_desc *desc;
1537 bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1539 int error, i, prod, symbol_desc;
1540 uint32_t cflags, flag64;
1542 M_ASSERTPKTHDR((*m_head));
1544 prod = sc->jme_cdata.jme_tx_prod;
1545 txd = &sc->jme_cdata.jme_txdesc[prod];
1547 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
1552 maxsegs = (sc->jme_cdata.jme_tx_desc_cnt - sc->jme_cdata.jme_tx_cnt) -
1553 (JME_TXD_RSVD + symbol_desc);
1554 if (maxsegs > JME_MAXTXSEGS)
1555 maxsegs = JME_MAXTXSEGS;
1556 KASSERT(maxsegs >= (sc->jme_txd_spare - symbol_desc),
1557 ("not enough segments %d", maxsegs));
1559 error = bus_dmamap_load_mbuf_defrag(sc->jme_cdata.jme_tx_tag,
1560 txd->tx_dmamap, m_head,
1561 txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1565 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1566 BUS_DMASYNC_PREWRITE);
1571 /* Configure checksum offload. */
1572 if (m->m_pkthdr.csum_flags & CSUM_IP)
1573 cflags |= JME_TD_IPCSUM;
1574 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1575 cflags |= JME_TD_TCPCSUM;
1576 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1577 cflags |= JME_TD_UDPCSUM;
1579 /* Configure VLAN. */
1580 if (m->m_flags & M_VLANTAG) {
1581 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK);
1582 cflags |= JME_TD_VLAN_TAG;
1585 desc = &sc->jme_cdata.jme_tx_ring[prod];
1586 desc->flags = htole32(cflags);
1587 desc->addr_hi = htole32(m->m_pkthdr.len);
1588 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1590 * Use 64bits TX desc chain format.
1592 * The first TX desc of the chain, which is setup here,
1593 * is just a symbol TX desc carrying no payload.
1595 flag64 = JME_TD_64BIT;
1599 /* No effective TX desc is consumed */
1603 * Use 32bits TX desc chain format.
1605 * The first TX desc of the chain, which is setup here,
1606 * is an effective TX desc carrying the first segment of
1610 desc->buflen = htole32(txsegs[0].ds_len);
1611 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr));
1613 /* One effective TX desc is consumed */
1616 sc->jme_cdata.jme_tx_cnt++;
1617 KKASSERT(sc->jme_cdata.jme_tx_cnt - i <
1618 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
1619 JME_DESC_INC(prod, sc->jme_cdata.jme_tx_desc_cnt);
1621 txd->tx_ndesc = 1 - i;
1622 for (; i < nsegs; i++) {
1623 desc = &sc->jme_cdata.jme_tx_ring[prod];
1624 desc->buflen = htole32(txsegs[i].ds_len);
1625 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1626 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1627 desc->flags = htole32(JME_TD_OWN | flag64);
1629 sc->jme_cdata.jme_tx_cnt++;
1630 KKASSERT(sc->jme_cdata.jme_tx_cnt <=
1631 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
1632 JME_DESC_INC(prod, sc->jme_cdata.jme_tx_desc_cnt);
1635 /* Update producer index. */
1636 sc->jme_cdata.jme_tx_prod = prod;
1638 * Finally request interrupt and give the first descriptor
1639 * owenership to hardware.
1641 desc = txd->tx_desc;
1642 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1645 txd->tx_ndesc += nsegs;
1655 jme_start(struct ifnet *ifp)
1657 struct jme_softc *sc = ifp->if_softc;
1658 struct mbuf *m_head;
1661 ASSERT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
1663 if (!sc->jme_has_link) {
1664 ifq_purge(&ifp->if_snd);
1668 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1671 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT(sc))
1674 while (!ifq_is_empty(&ifp->if_snd)) {
1676 * Check number of available TX descs, always
1677 * leave JME_TXD_RSVD free TX descs.
1679 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare >
1680 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD) {
1681 ifp->if_flags |= IFF_OACTIVE;
1685 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1690 * Pack the data into the transmit ring. If we
1691 * don't have room, set the OACTIVE flag and wait
1692 * for the NIC to drain the ring.
1694 if (jme_encap(sc, &m_head)) {
1695 KKASSERT(m_head == NULL);
1697 ifp->if_flags |= IFF_OACTIVE;
1703 * If there's a BPF listener, bounce a copy of this frame
1706 ETHER_BPF_MTAP(ifp, m_head);
1711 * Reading TXCSR takes very long time under heavy load
1712 * so cache TXCSR value and writes the ORed value with
1713 * the kick command to the TXCSR. This saves one register
1716 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1717 TXCSR_TXQ_N_START(TXCSR_TXQ0));
1718 /* Set a timeout in case the chip goes out to lunch. */
1719 ifp->if_timer = JME_TX_TIMEOUT;
1724 jme_watchdog(struct ifnet *ifp)
1726 struct jme_softc *sc = ifp->if_softc;
1728 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1730 if (!sc->jme_has_link) {
1731 if_printf(ifp, "watchdog timeout (missed link)\n");
1738 if (sc->jme_cdata.jme_tx_cnt == 0) {
1739 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
1741 if (!ifq_is_empty(&ifp->if_snd))
1746 if_printf(ifp, "watchdog timeout\n");
1749 if (!ifq_is_empty(&ifp->if_snd))
1754 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1756 struct jme_softc *sc = ifp->if_softc;
1757 struct mii_data *mii = device_get_softc(sc->jme_miibus);
1758 struct ifreq *ifr = (struct ifreq *)data;
1759 int error = 0, mask;
1761 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1765 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1766 (!(sc->jme_caps & JME_CAP_JUMBO) &&
1767 ifr->ifr_mtu > JME_MAX_MTU)) {
1772 if (ifp->if_mtu != ifr->ifr_mtu) {
1774 * No special configuration is required when interface
1775 * MTU is changed but availability of Tx checksum
1776 * offload should be chcked against new MTU size as
1777 * FIFO size is just 2K.
1779 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1780 ifp->if_capenable &= ~IFCAP_TXCSUM;
1781 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1783 ifp->if_mtu = ifr->ifr_mtu;
1784 if (ifp->if_flags & IFF_RUNNING)
1790 if (ifp->if_flags & IFF_UP) {
1791 if (ifp->if_flags & IFF_RUNNING) {
1792 if ((ifp->if_flags ^ sc->jme_if_flags) &
1793 (IFF_PROMISC | IFF_ALLMULTI))
1799 if (ifp->if_flags & IFF_RUNNING)
1802 sc->jme_if_flags = ifp->if_flags;
1807 if (ifp->if_flags & IFF_RUNNING)
1813 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1817 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1819 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1820 ifp->if_capenable ^= IFCAP_TXCSUM;
1821 if (IFCAP_TXCSUM & ifp->if_capenable)
1822 ifp->if_hwassist |= JME_CSUM_FEATURES;
1824 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1826 if (mask & IFCAP_RXCSUM) {
1829 ifp->if_capenable ^= IFCAP_RXCSUM;
1830 reg = CSR_READ_4(sc, JME_RXMAC);
1831 reg &= ~RXMAC_CSUM_ENB;
1832 if (ifp->if_capenable & IFCAP_RXCSUM)
1833 reg |= RXMAC_CSUM_ENB;
1834 CSR_WRITE_4(sc, JME_RXMAC, reg);
1837 if (mask & IFCAP_VLAN_HWTAGGING) {
1838 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1842 if (mask & IFCAP_RSS)
1843 ifp->if_capenable ^= IFCAP_RSS;
1847 error = ether_ioctl(ifp, cmd, data);
1854 jme_mac_config(struct jme_softc *sc)
1856 struct mii_data *mii;
1857 uint32_t ghc, rxmac, txmac, txpause, gp1;
1858 int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0;
1860 mii = device_get_softc(sc->jme_miibus);
1862 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
1864 CSR_WRITE_4(sc, JME_GHC, 0);
1866 rxmac = CSR_READ_4(sc, JME_RXMAC);
1867 rxmac &= ~RXMAC_FC_ENB;
1868 txmac = CSR_READ_4(sc, JME_TXMAC);
1869 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
1870 txpause = CSR_READ_4(sc, JME_TXPFC);
1871 txpause &= ~TXPFC_PAUSE_ENB;
1872 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1873 ghc |= GHC_FULL_DUPLEX;
1874 rxmac &= ~RXMAC_COLL_DET_ENB;
1875 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
1876 TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
1879 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1880 txpause |= TXPFC_PAUSE_ENB;
1881 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1882 rxmac |= RXMAC_FC_ENB;
1884 /* Disable retry transmit timer/retry limit. */
1885 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
1886 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
1888 rxmac |= RXMAC_COLL_DET_ENB;
1889 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
1890 /* Enable retry transmit timer/retry limit. */
1891 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
1892 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
1896 * Reprogram Tx/Rx MACs with resolved speed/duplex.
1898 gp1 = CSR_READ_4(sc, JME_GPREG1);
1899 gp1 &= ~GPREG1_WA_HDX;
1901 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
1904 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1906 ghc |= GHC_SPEED_10 | sc->jme_clksrc;
1908 gp1 |= GPREG1_WA_HDX;
1912 ghc |= GHC_SPEED_100 | sc->jme_clksrc;
1914 gp1 |= GPREG1_WA_HDX;
1917 * Use extended FIFO depth to workaround CRC errors
1918 * emitted by chips before JMC250B
1920 phyconf = JMPHY_CONF_EXTFIFO;
1924 if (sc->jme_caps & JME_CAP_FASTETH)
1927 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000;
1929 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
1935 CSR_WRITE_4(sc, JME_GHC, ghc);
1936 CSR_WRITE_4(sc, JME_RXMAC, rxmac);
1937 CSR_WRITE_4(sc, JME_TXMAC, txmac);
1938 CSR_WRITE_4(sc, JME_TXPFC, txpause);
1940 if (sc->jme_workaround & JME_WA_EXTFIFO) {
1941 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1942 JMPHY_CONF, phyconf);
1944 if (sc->jme_workaround & JME_WA_HDX)
1945 CSR_WRITE_4(sc, JME_GPREG1, gp1);
1951 struct jme_softc *sc = xsc;
1952 struct ifnet *ifp = &sc->arpcom.ac_if;
1956 ASSERT_SERIALIZED(&sc->jme_serialize);
1958 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
1959 if (status == 0 || status == 0xFFFFFFFF)
1962 /* Disable interrupts. */
1963 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
1965 status = CSR_READ_4(sc, JME_INTR_STATUS);
1966 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
1969 /* Reset PCC counter/timer and Ack interrupts. */
1970 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
1972 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO))
1973 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
1975 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1976 if (status & jme_rx_status[r].jme_coal) {
1977 status |= jme_rx_status[r].jme_coal |
1978 jme_rx_status[r].jme_comp;
1982 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
1984 if (ifp->if_flags & IFF_RUNNING) {
1985 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
1986 jme_rx_intr(sc, status);
1988 if (status & INTR_RXQ_DESC_EMPTY) {
1990 * Notify hardware availability of new Rx buffers.
1991 * Reading RXCSR takes very long time under heavy
1992 * load so cache RXCSR value and writes the ORed
1993 * value with the kick command to the RXCSR. This
1994 * saves one register access cycle.
1996 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
1997 RXCSR_RX_ENB | RXCSR_RXQ_START);
2000 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) {
2001 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
2003 if (!ifq_is_empty(&ifp->if_snd))
2005 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
2009 /* Reenable interrupts. */
2010 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2014 jme_txeof(struct jme_softc *sc)
2016 struct ifnet *ifp = &sc->arpcom.ac_if;
2019 cons = sc->jme_cdata.jme_tx_cons;
2020 if (cons == sc->jme_cdata.jme_tx_prod)
2024 * Go through our Tx list and free mbufs for those
2025 * frames which have been transmitted.
2027 while (cons != sc->jme_cdata.jme_tx_prod) {
2028 struct jme_txdesc *txd, *next_txd;
2029 uint32_t status, next_status;
2030 int next_cons, nsegs;
2032 txd = &sc->jme_cdata.jme_txdesc[cons];
2033 KASSERT(txd->tx_m != NULL,
2034 ("%s: freeing NULL mbuf!", __func__));
2036 status = le32toh(txd->tx_desc->flags);
2037 if ((status & JME_TD_OWN) == JME_TD_OWN)
2042 * This chip will always update the TX descriptor's
2043 * buflen field and this updating always happens
2044 * after clearing the OWN bit, so even if the OWN
2045 * bit is cleared by the chip, we still don't sure
2046 * about whether the buflen field has been updated
2047 * by the chip or not. To avoid this race, we wait
2048 * for the next TX descriptor's OWN bit to be cleared
2049 * by the chip before reusing this TX descriptor.
2052 JME_DESC_ADD(next_cons, txd->tx_ndesc,
2053 sc->jme_cdata.jme_tx_desc_cnt);
2054 next_txd = &sc->jme_cdata.jme_txdesc[next_cons];
2055 if (next_txd->tx_m == NULL)
2057 next_status = le32toh(next_txd->tx_desc->flags);
2058 if ((next_status & JME_TD_OWN) == JME_TD_OWN)
2061 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) {
2065 if (status & JME_TD_COLLISION) {
2066 ifp->if_collisions +=
2067 le32toh(txd->tx_desc->buflen) &
2068 JME_TD_BUF_LEN_MASK;
2073 * Only the first descriptor of multi-descriptor
2074 * transmission is updated so driver have to skip entire
2075 * chained buffers for the transmiited frame. In other
2076 * words, JME_TD_OWN bit is valid only at the first
2077 * descriptor of a multi-descriptor transmission.
2079 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
2080 sc->jme_cdata.jme_tx_ring[cons].flags = 0;
2081 JME_DESC_INC(cons, sc->jme_cdata.jme_tx_desc_cnt);
2084 /* Reclaim transferred mbufs. */
2085 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2088 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2089 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
2090 ("%s: Active Tx desc counter was garbled", __func__));
2093 sc->jme_cdata.jme_tx_cons = cons;
2095 if (sc->jme_cdata.jme_tx_cnt < JME_MAXTXSEGS + 1)
2098 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare <=
2099 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD)
2100 ifp->if_flags &= ~IFF_OACTIVE;
2103 static __inline void
2104 jme_discard_rxbufs(struct jme_rxdata *rdata, int cons, int count)
2108 for (i = 0; i < count; ++i) {
2109 jme_setup_rxdesc(&rdata->jme_rxdesc[cons]);
2110 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
2114 static __inline struct pktinfo *
2115 jme_pktinfo(struct pktinfo *pi, uint32_t flags)
2117 if (flags & JME_RD_IPV4)
2118 pi->pi_netisr = NETISR_IP;
2119 else if (flags & JME_RD_IPV6)
2120 pi->pi_netisr = NETISR_IPV6;
2125 pi->pi_l3proto = IPPROTO_UNKNOWN;
2127 if (flags & JME_RD_MORE_FRAG)
2128 pi->pi_flags |= PKTINFO_FLAG_FRAG;
2129 else if (flags & JME_RD_TCP)
2130 pi->pi_l3proto = IPPROTO_TCP;
2131 else if (flags & JME_RD_UDP)
2132 pi->pi_l3proto = IPPROTO_UDP;
2138 /* Receive a frame. */
2140 jme_rxpkt(struct jme_rxdata *rdata)
2142 struct ifnet *ifp = &rdata->jme_sc->arpcom.ac_if;
2143 struct jme_desc *desc;
2144 struct jme_rxdesc *rxd;
2145 struct mbuf *mp, *m;
2146 uint32_t flags, status, hash, hashinfo;
2147 int cons, count, nsegs;
2149 cons = rdata->jme_rx_cons;
2150 desc = &rdata->jme_rx_ring[cons];
2152 flags = le32toh(desc->flags);
2153 status = le32toh(desc->buflen);
2154 hash = le32toh(desc->addr_hi);
2155 hashinfo = le32toh(desc->addr_lo);
2156 nsegs = JME_RX_NSEGS(status);
2159 /* Skip the first descriptor. */
2160 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
2163 * Clear the OWN bit of the following RX descriptors;
2164 * hardware will not clear the OWN bit except the first
2167 * Since the first RX descriptor is setup, i.e. OWN bit
2168 * on, before its followins RX descriptors, leaving the
2169 * OWN bit on the following RX descriptors will trick
2170 * the hardware into thinking that the following RX
2171 * descriptors are ready to be used too.
2173 for (count = 1; count < nsegs; count++,
2174 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt))
2175 rdata->jme_rx_ring[cons].flags = 0;
2177 cons = rdata->jme_rx_cons;
2180 JME_RSS_DPRINTF(rdata->jme_sc, 15, "ring%d, flags 0x%08x, "
2181 "hash 0x%08x, hash info 0x%08x\n",
2182 rdata->jme_rx_idx, flags, hash, hashinfo);
2184 if (status & JME_RX_ERR_STAT) {
2186 jme_discard_rxbufs(rdata, cons, nsegs);
2187 #ifdef JME_SHOW_ERRORS
2188 if_printf(ifp, "%s : receive error = 0x%b\n",
2189 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2191 rdata->jme_rx_cons += nsegs;
2192 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
2196 rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2197 for (count = 0; count < nsegs; count++,
2198 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt)) {
2199 rxd = &rdata->jme_rxdesc[cons];
2202 /* Add a new receive buffer to the ring. */
2203 if (jme_newbuf(rdata, rxd, 0) != 0) {
2206 jme_discard_rxbufs(rdata, cons, nsegs - count);
2207 if (rdata->jme_rxhead != NULL) {
2208 m_freem(rdata->jme_rxhead);
2209 JME_RXCHAIN_RESET(rdata);
2215 * Assume we've received a full sized frame.
2216 * Actual size is fixed when we encounter the end of
2217 * multi-segmented frame.
2219 mp->m_len = MCLBYTES;
2221 /* Chain received mbufs. */
2222 if (rdata->jme_rxhead == NULL) {
2223 rdata->jme_rxhead = mp;
2224 rdata->jme_rxtail = mp;
2227 * Receive processor can receive a maximum frame
2228 * size of 65535 bytes.
2230 rdata->jme_rxtail->m_next = mp;
2231 rdata->jme_rxtail = mp;
2234 if (count == nsegs - 1) {
2235 struct pktinfo pi0, *pi;
2237 /* Last desc. for this frame. */
2238 m = rdata->jme_rxhead;
2239 m->m_pkthdr.len = rdata->jme_rxlen;
2241 /* Set first mbuf size. */
2242 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2243 /* Set last mbuf size. */
2244 mp->m_len = rdata->jme_rxlen -
2245 ((MCLBYTES - JME_RX_PAD_BYTES) +
2246 (MCLBYTES * (nsegs - 2)));
2248 m->m_len = rdata->jme_rxlen;
2250 m->m_pkthdr.rcvif = ifp;
2253 * Account for 10bytes auto padding which is used
2254 * to align IP header on 32bit boundary. Also note,
2255 * CRC bytes is automatically removed by the
2258 m->m_data += JME_RX_PAD_BYTES;
2260 /* Set checksum information. */
2261 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2262 (flags & JME_RD_IPV4)) {
2263 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2264 if (flags & JME_RD_IPCSUM)
2265 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2266 if ((flags & JME_RD_MORE_FRAG) == 0 &&
2267 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2268 (JME_RD_TCP | JME_RD_TCPCSUM) ||
2269 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2270 (JME_RD_UDP | JME_RD_UDPCSUM))) {
2271 m->m_pkthdr.csum_flags |=
2272 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2273 m->m_pkthdr.csum_data = 0xffff;
2277 /* Check for VLAN tagged packets. */
2278 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) &&
2279 (flags & JME_RD_VLAN_TAG)) {
2280 m->m_pkthdr.ether_vlantag =
2281 flags & JME_RD_VLAN_MASK;
2282 m->m_flags |= M_VLANTAG;
2287 if (ifp->if_capenable & IFCAP_RSS)
2288 pi = jme_pktinfo(&pi0, flags);
2293 (hashinfo & JME_RD_HASH_FN_MASK) != 0) {
2294 m->m_flags |= M_HASH;
2295 m->m_pkthdr.hash = toeplitz_hash(hash);
2298 #ifdef JME_RSS_DEBUG
2300 JME_RSS_DPRINTF(rdata->jme_sc, 10,
2301 "isr %d flags %08x, l3 %d %s\n",
2302 pi->pi_netisr, pi->pi_flags,
2304 (m->m_flags & M_HASH) ? "hash" : "");
2309 ether_input_pkt(ifp, m, pi);
2311 /* Reset mbuf chains. */
2312 JME_RXCHAIN_RESET(rdata);
2313 #ifdef JME_RSS_DEBUG
2314 rdata->jme_rx_pkt++;
2319 rdata->jme_rx_cons += nsegs;
2320 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
2324 jme_rxeof(struct jme_rxdata *rdata, int count)
2326 struct jme_desc *desc;
2330 #ifdef DEVICE_POLLING
2331 if (count >= 0 && count-- == 0)
2334 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons];
2335 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2337 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2341 * Check number of segments against received bytes.
2342 * Non-matching value would indicate that hardware
2343 * is still trying to update Rx descriptors. I'm not
2344 * sure whether this check is needed.
2346 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2347 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2348 if (nsegs != howmany(pktlen, MCLBYTES)) {
2349 if_printf(&rdata->jme_sc->arpcom.ac_if,
2350 "RX fragment count(%d) and "
2351 "packet size(%d) mismach\n", nsegs, pktlen);
2357 * RSS hash and hash information may _not_ be set by the
2358 * hardware even if the OWN bit is cleared and VALID bit
2361 * If the RSS information is not delivered by the hardware
2362 * yet, we MUST NOT accept this packet, let alone reusing
2363 * its RX descriptor. If this packet was accepted and its
2364 * RX descriptor was reused before hardware delivering the
2365 * RSS information, the RX buffer's address would be trashed
2366 * by the RSS information delivered by the hardware.
2368 if (JME_ENABLE_HWRSS(rdata->jme_sc)) {
2369 struct jme_rxdesc *rxd;
2372 hashinfo = le32toh(desc->addr_lo);
2373 rxd = &rdata->jme_rxdesc[rdata->jme_rx_cons];
2376 * This test should be enough to detect the pending
2377 * RSS information delivery, given:
2378 * - If RSS hash is not calculated, the hashinfo
2379 * will be 0. Howvever, the lower 32bits of RX
2380 * buffers' physical address will never be 0.
2381 * (see jme_rxbuf_dma_filter)
2382 * - If RSS hash is calculated, the lowest 4 bits
2383 * of hashinfo will be set, while the RX buffers
2384 * are at least 2K aligned.
2386 if (hashinfo == JME_ADDR_LO(rxd->rx_paddr)) {
2387 #ifdef JME_SHOW_RSSWB
2388 if_printf(&rdata->jme_sc->arpcom.ac_if,
2389 "RSS is not written back yet\n");
2395 /* Received a frame. */
2403 struct jme_softc *sc = xsc;
2404 struct mii_data *mii = device_get_softc(sc->jme_miibus);
2406 lwkt_serialize_enter(&sc->jme_serialize);
2408 sc->jme_in_tick = TRUE;
2410 sc->jme_in_tick = FALSE;
2412 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2414 lwkt_serialize_exit(&sc->jme_serialize);
2418 jme_reset(struct jme_softc *sc)
2422 /* Make sure that TX and RX are stopped */
2427 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2431 * Hold reset bit before stop reset
2434 /* Disable TXMAC and TXOFL clock sources */
2435 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2436 /* Disable RXMAC clock source */
2437 val = CSR_READ_4(sc, JME_GPREG1);
2438 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2440 CSR_READ_4(sc, JME_GHC);
2443 CSR_WRITE_4(sc, JME_GHC, 0);
2445 CSR_READ_4(sc, JME_GHC);
2448 * Clear reset bit after stop reset
2451 /* Enable TXMAC and TXOFL clock sources */
2452 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2453 /* Enable RXMAC clock source */
2454 val = CSR_READ_4(sc, JME_GPREG1);
2455 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2457 CSR_READ_4(sc, JME_GHC);
2459 /* Disable TXMAC and TXOFL clock sources */
2460 CSR_WRITE_4(sc, JME_GHC, 0);
2461 /* Disable RXMAC clock source */
2462 val = CSR_READ_4(sc, JME_GPREG1);
2463 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2465 CSR_READ_4(sc, JME_GHC);
2467 /* Enable TX and RX */
2468 val = CSR_READ_4(sc, JME_TXCSR);
2469 CSR_WRITE_4(sc, JME_TXCSR, val | TXCSR_TX_ENB);
2470 val = CSR_READ_4(sc, JME_RXCSR);
2471 CSR_WRITE_4(sc, JME_RXCSR, val | RXCSR_RX_ENB);
2473 CSR_READ_4(sc, JME_TXCSR);
2474 CSR_READ_4(sc, JME_RXCSR);
2476 /* Enable TXMAC and TXOFL clock sources */
2477 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2478 /* Eisable RXMAC clock source */
2479 val = CSR_READ_4(sc, JME_GPREG1);
2480 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2482 CSR_READ_4(sc, JME_GHC);
2484 /* Stop TX and RX */
2492 struct jme_softc *sc = xsc;
2493 struct ifnet *ifp = &sc->arpcom.ac_if;
2494 struct mii_data *mii;
2495 uint8_t eaddr[ETHER_ADDR_LEN];
2500 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2503 * Cancel any pending I/O.
2508 * Reset the chip to a known state.
2513 * Setup MSI/MSI-X vectors to interrupts mapping
2518 howmany(ifp->if_mtu + sizeof(struct ether_vlan_header), MCLBYTES);
2519 KKASSERT(sc->jme_txd_spare >= 1);
2522 * If we use 64bit address mode for transmitting, each Tx request
2523 * needs one more symbol descriptor.
2525 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
2526 sc->jme_txd_spare += 1;
2528 if (JME_ENABLE_HWRSS(sc))
2531 jme_disable_rss(sc);
2533 /* Init RX descriptors */
2534 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2535 error = jme_init_rx_ring(&sc->jme_cdata.jme_rx_data[r]);
2537 if_printf(ifp, "initialization failed: "
2538 "no memory for %dth RX ring.\n", r);
2544 /* Init TX descriptors */
2545 jme_init_tx_ring(sc);
2547 /* Initialize shadow status block. */
2550 /* Reprogram the station address. */
2551 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2552 CSR_WRITE_4(sc, JME_PAR0,
2553 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2554 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2557 * Configure Tx queue.
2558 * Tx priority queue weight value : 0
2559 * Tx FIFO threshold for processing next packet : 16QW
2560 * Maximum Tx DMA length : 512
2561 * Allow Tx DMA burst.
2563 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2564 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2565 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2566 sc->jme_txcsr |= sc->jme_tx_dma_size;
2567 sc->jme_txcsr |= TXCSR_DMA_BURST;
2568 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2570 /* Set Tx descriptor counter. */
2571 CSR_WRITE_4(sc, JME_TXQDC, sc->jme_cdata.jme_tx_desc_cnt);
2573 /* Set Tx ring address to the hardware. */
2574 paddr = sc->jme_cdata.jme_tx_ring_paddr;
2575 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2576 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2578 /* Configure TxMAC parameters. */
2579 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2580 reg |= TXMAC_THRESH_1_PKT;
2581 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2582 CSR_WRITE_4(sc, JME_TXMAC, reg);
2585 * Configure Rx queue.
2586 * FIFO full threshold for transmitting Tx pause packet : 128T
2587 * FIFO threshold for processing next packet : 128QW
2589 * Max Rx DMA length : 128
2590 * Rx descriptor retry : 32
2591 * Rx descriptor retry time gap : 256ns
2592 * Don't receive runt/bad frame.
2594 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2597 * Since Rx FIFO size is 4K bytes, receiving frames larger
2598 * than 4K bytes will suffer from Rx FIFO overruns. So
2599 * decrease FIFO threshold to reduce the FIFO overruns for
2600 * frames larger than 4000 bytes.
2601 * For best performance of standard MTU sized frames use
2602 * maximum allowable FIFO threshold, 128QW.
2604 if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) >
2606 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2608 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2610 /* Improve PCI Express compatibility */
2611 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2613 sc->jme_rxcsr |= sc->jme_rx_dma_size;
2614 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2615 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2616 /* XXX TODO DROP_BAD */
2618 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2619 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
2621 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
2623 /* Set Rx descriptor counter. */
2624 CSR_WRITE_4(sc, JME_RXQDC, rdata->jme_rx_desc_cnt);
2626 /* Set Rx ring address to the hardware. */
2627 paddr = rdata->jme_rx_ring_paddr;
2628 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2629 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2632 /* Clear receive filter. */
2633 CSR_WRITE_4(sc, JME_RXMAC, 0);
2635 /* Set up the receive filter. */
2640 * Disable all WOL bits as WOL can interfere normal Rx
2641 * operation. Also clear WOL detection status bits.
2643 reg = CSR_READ_4(sc, JME_PMCS);
2644 reg &= ~PMCS_WOL_ENB_MASK;
2645 CSR_WRITE_4(sc, JME_PMCS, reg);
2648 * Pad 10bytes right before received frame. This will greatly
2649 * help Rx performance on strict-alignment architectures as
2650 * it does not need to copy the frame to align the payload.
2652 reg = CSR_READ_4(sc, JME_RXMAC);
2653 reg |= RXMAC_PAD_10BYTES;
2655 if (ifp->if_capenable & IFCAP_RXCSUM)
2656 reg |= RXMAC_CSUM_ENB;
2657 CSR_WRITE_4(sc, JME_RXMAC, reg);
2659 /* Configure general purpose reg0 */
2660 reg = CSR_READ_4(sc, JME_GPREG0);
2661 reg &= ~GPREG0_PCC_UNIT_MASK;
2662 /* Set PCC timer resolution to micro-seconds unit. */
2663 reg |= GPREG0_PCC_UNIT_US;
2665 * Disable all shadow register posting as we have to read
2666 * JME_INTR_STATUS register in jme_intr. Also it seems
2667 * that it's hard to synchronize interrupt status between
2668 * hardware and software with shadow posting due to
2669 * requirements of bus_dmamap_sync(9).
2671 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2672 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2673 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2674 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2675 /* Disable posting of DW0. */
2676 reg &= ~GPREG0_POST_DW0_ENB;
2677 /* Clear PME message. */
2678 reg &= ~GPREG0_PME_ENB;
2679 /* Set PHY address. */
2680 reg &= ~GPREG0_PHY_ADDR_MASK;
2681 reg |= sc->jme_phyaddr;
2682 CSR_WRITE_4(sc, JME_GPREG0, reg);
2684 /* Configure Tx queue 0 packet completion coalescing. */
2685 jme_set_tx_coal(sc);
2687 /* Configure Rx queues packet completion coalescing. */
2688 jme_set_rx_coal(sc);
2690 /* Configure shadow status block but don't enable posting. */
2691 paddr = sc->jme_cdata.jme_ssb_block_paddr;
2692 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2693 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2695 /* Disable Timer 1 and Timer 2. */
2696 CSR_WRITE_4(sc, JME_TIMER1, 0);
2697 CSR_WRITE_4(sc, JME_TIMER2, 0);
2699 /* Configure retry transmit period, retry limit value. */
2700 CSR_WRITE_4(sc, JME_TXTRHD,
2701 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2702 TXTRHD_RT_PERIOD_MASK) |
2703 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2704 TXTRHD_RT_LIMIT_SHIFT));
2706 #ifdef DEVICE_POLLING
2707 if (!(ifp->if_flags & IFF_POLLING))
2709 /* Initialize the interrupt mask. */
2710 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2711 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2714 * Enabling Tx/Rx DMA engines and Rx queue processing is
2715 * done after detection of valid link in jme_miibus_statchg.
2717 sc->jme_has_link = FALSE;
2719 /* Set the current media. */
2720 mii = device_get_softc(sc->jme_miibus);
2723 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2725 ifp->if_flags |= IFF_RUNNING;
2726 ifp->if_flags &= ~IFF_OACTIVE;
2730 jme_stop(struct jme_softc *sc)
2732 struct ifnet *ifp = &sc->arpcom.ac_if;
2733 struct jme_txdesc *txd;
2734 struct jme_rxdesc *rxd;
2735 struct jme_rxdata *rdata;
2738 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2741 * Mark the interface down and cancel the watchdog timer.
2743 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2746 callout_stop(&sc->jme_tick_ch);
2747 sc->jme_has_link = FALSE;
2750 * Disable interrupts.
2752 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2753 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2755 /* Disable updating shadow status block. */
2756 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2757 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2759 /* Stop receiver, transmitter. */
2764 * Free partial finished RX segments
2766 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2767 rdata = &sc->jme_cdata.jme_rx_data[r];
2768 if (rdata->jme_rxhead != NULL)
2769 m_freem(rdata->jme_rxhead);
2770 JME_RXCHAIN_RESET(rdata);
2774 * Free RX and TX mbufs still in the queues.
2776 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2777 rdata = &sc->jme_cdata.jme_rx_data[r];
2778 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
2779 rxd = &rdata->jme_rxdesc[i];
2780 if (rxd->rx_m != NULL) {
2781 bus_dmamap_unload(rdata->jme_rx_tag,
2788 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
2789 txd = &sc->jme_cdata.jme_txdesc[i];
2790 if (txd->tx_m != NULL) {
2791 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2801 jme_stop_tx(struct jme_softc *sc)
2806 reg = CSR_READ_4(sc, JME_TXCSR);
2807 if ((reg & TXCSR_TX_ENB) == 0)
2809 reg &= ~TXCSR_TX_ENB;
2810 CSR_WRITE_4(sc, JME_TXCSR, reg);
2811 for (i = JME_TIMEOUT; i > 0; i--) {
2813 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2817 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2821 jme_stop_rx(struct jme_softc *sc)
2826 reg = CSR_READ_4(sc, JME_RXCSR);
2827 if ((reg & RXCSR_RX_ENB) == 0)
2829 reg &= ~RXCSR_RX_ENB;
2830 CSR_WRITE_4(sc, JME_RXCSR, reg);
2831 for (i = JME_TIMEOUT; i > 0; i--) {
2833 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2837 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2841 jme_init_tx_ring(struct jme_softc *sc)
2843 struct jme_chain_data *cd;
2844 struct jme_txdesc *txd;
2847 sc->jme_cdata.jme_tx_prod = 0;
2848 sc->jme_cdata.jme_tx_cons = 0;
2849 sc->jme_cdata.jme_tx_cnt = 0;
2851 cd = &sc->jme_cdata;
2852 bzero(cd->jme_tx_ring, JME_TX_RING_SIZE(sc));
2853 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
2854 txd = &sc->jme_cdata.jme_txdesc[i];
2856 txd->tx_desc = &cd->jme_tx_ring[i];
2862 jme_init_ssb(struct jme_softc *sc)
2864 struct jme_chain_data *cd;
2866 cd = &sc->jme_cdata;
2867 bzero(cd->jme_ssb_block, JME_SSB_SIZE);
2871 jme_init_rx_ring(struct jme_rxdata *rdata)
2873 struct jme_rxdesc *rxd;
2876 KKASSERT(rdata->jme_rxhead == NULL &&
2877 rdata->jme_rxtail == NULL &&
2878 rdata->jme_rxlen == 0);
2879 rdata->jme_rx_cons = 0;
2881 bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(rdata));
2882 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
2885 rxd = &rdata->jme_rxdesc[i];
2887 rxd->rx_desc = &rdata->jme_rx_ring[i];
2888 error = jme_newbuf(rdata, rxd, 1);
2896 jme_newbuf(struct jme_rxdata *rdata, struct jme_rxdesc *rxd, int init)
2899 bus_dma_segment_t segs;
2903 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2907 * JMC250 has 64bit boundary alignment limitation so jme(4)
2908 * takes advantage of 10 bytes padding feature of hardware
2909 * in order not to copy entire frame to align IP header on
2912 m->m_len = m->m_pkthdr.len = MCLBYTES;
2914 error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag,
2915 rdata->jme_rx_sparemap, m, &segs, 1, &nsegs,
2920 if_printf(&rdata->jme_sc->arpcom.ac_if,
2921 "can't load RX mbuf\n");
2926 if (rxd->rx_m != NULL) {
2927 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap,
2928 BUS_DMASYNC_POSTREAD);
2929 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap);
2931 map = rxd->rx_dmamap;
2932 rxd->rx_dmamap = rdata->jme_rx_sparemap;
2933 rdata->jme_rx_sparemap = map;
2935 rxd->rx_paddr = segs.ds_addr;
2937 jme_setup_rxdesc(rxd);
2942 jme_set_vlan(struct jme_softc *sc)
2944 struct ifnet *ifp = &sc->arpcom.ac_if;
2947 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2949 reg = CSR_READ_4(sc, JME_RXMAC);
2950 reg &= ~RXMAC_VLAN_ENB;
2951 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2952 reg |= RXMAC_VLAN_ENB;
2953 CSR_WRITE_4(sc, JME_RXMAC, reg);
2957 jme_set_filter(struct jme_softc *sc)
2959 struct ifnet *ifp = &sc->arpcom.ac_if;
2960 struct ifmultiaddr *ifma;
2965 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2967 rxcfg = CSR_READ_4(sc, JME_RXMAC);
2968 rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
2972 * Always accept frames destined to our station address.
2973 * Always accept broadcast frames.
2975 rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST;
2977 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2978 if (ifp->if_flags & IFF_PROMISC)
2979 rxcfg |= RXMAC_PROMISC;
2980 if (ifp->if_flags & IFF_ALLMULTI)
2981 rxcfg |= RXMAC_ALLMULTI;
2982 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
2983 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
2984 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2989 * Set up the multicast address filter by passing all multicast
2990 * addresses through a CRC generator, and then using the low-order
2991 * 6 bits as an index into the 64 bit multicast hash table. The
2992 * high order bits select the register, while the rest of the bits
2993 * select the bit within the register.
2995 rxcfg |= RXMAC_MULTICAST;
2996 bzero(mchash, sizeof(mchash));
2998 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2999 if (ifma->ifma_addr->sa_family != AF_LINK)
3001 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3002 ifma->ifma_addr), ETHER_ADDR_LEN);
3004 /* Just want the 6 least significant bits. */
3007 /* Set the corresponding bit in the hash table. */
3008 mchash[crc >> 5] |= 1 << (crc & 0x1f);
3011 CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
3012 CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
3013 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3017 jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS)
3019 struct jme_softc *sc = arg1;
3020 struct ifnet *ifp = &sc->arpcom.ac_if;
3023 ifnet_serialize_all(ifp);
3025 v = sc->jme_tx_coal_to;
3026 error = sysctl_handle_int(oidp, &v, 0, req);
3027 if (error || req->newptr == NULL)
3030 if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) {
3035 if (v != sc->jme_tx_coal_to) {
3036 sc->jme_tx_coal_to = v;
3037 if (ifp->if_flags & IFF_RUNNING)
3038 jme_set_tx_coal(sc);
3041 ifnet_deserialize_all(ifp);
3046 jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
3048 struct jme_softc *sc = arg1;
3049 struct ifnet *ifp = &sc->arpcom.ac_if;
3052 ifnet_serialize_all(ifp);
3054 v = sc->jme_tx_coal_pkt;
3055 error = sysctl_handle_int(oidp, &v, 0, req);
3056 if (error || req->newptr == NULL)
3059 if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) {
3064 if (v != sc->jme_tx_coal_pkt) {
3065 sc->jme_tx_coal_pkt = v;
3066 if (ifp->if_flags & IFF_RUNNING)
3067 jme_set_tx_coal(sc);
3070 ifnet_deserialize_all(ifp);
3075 jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS)
3077 struct jme_softc *sc = arg1;
3078 struct ifnet *ifp = &sc->arpcom.ac_if;
3081 ifnet_serialize_all(ifp);
3083 v = sc->jme_rx_coal_to;
3084 error = sysctl_handle_int(oidp, &v, 0, req);
3085 if (error || req->newptr == NULL)
3088 if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) {
3093 if (v != sc->jme_rx_coal_to) {
3094 sc->jme_rx_coal_to = v;
3095 if (ifp->if_flags & IFF_RUNNING)
3096 jme_set_rx_coal(sc);
3099 ifnet_deserialize_all(ifp);
3104 jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
3106 struct jme_softc *sc = arg1;
3107 struct ifnet *ifp = &sc->arpcom.ac_if;
3110 ifnet_serialize_all(ifp);
3112 v = sc->jme_rx_coal_pkt;
3113 error = sysctl_handle_int(oidp, &v, 0, req);
3114 if (error || req->newptr == NULL)
3117 if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) {
3122 if (v != sc->jme_rx_coal_pkt) {
3123 sc->jme_rx_coal_pkt = v;
3124 if (ifp->if_flags & IFF_RUNNING)
3125 jme_set_rx_coal(sc);
3128 ifnet_deserialize_all(ifp);
3133 jme_set_tx_coal(struct jme_softc *sc)
3137 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
3139 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
3140 PCCTX_COAL_PKT_MASK;
3141 reg |= PCCTX_COAL_TXQ0;
3142 CSR_WRITE_4(sc, JME_PCCTX, reg);
3146 jme_set_rx_coal(struct jme_softc *sc)
3151 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
3153 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
3154 PCCRX_COAL_PKT_MASK;
3155 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r)
3156 CSR_WRITE_4(sc, JME_PCCRX(r), reg);
3159 #ifdef DEVICE_POLLING
3162 jme_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3164 struct jme_softc *sc = ifp->if_softc;
3168 ASSERT_SERIALIZED(&sc->jme_serialize);
3172 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
3175 case POLL_DEREGISTER:
3176 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
3179 case POLL_AND_CHECK_STATUS:
3181 status = CSR_READ_4(sc, JME_INTR_STATUS);
3183 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3184 struct jme_rxdata *rdata =
3185 &sc->jme_cdata.jme_rx_data[r];
3187 lwkt_serialize_enter(&rdata->jme_rx_serialize);
3188 jme_rxeof(rdata, count);
3189 lwkt_serialize_exit(&rdata->jme_rx_serialize);
3192 if (status & INTR_RXQ_DESC_EMPTY) {
3193 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3194 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3195 RXCSR_RX_ENB | RXCSR_RXQ_START);
3198 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
3200 if (!ifq_is_empty(&ifp->if_snd))
3202 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
3207 #endif /* DEVICE_POLLING */
3210 jme_rxring_dma_alloc(struct jme_rxdata *rdata)
3215 asize = roundup2(JME_RX_RING_SIZE(rdata), JME_RX_RING_ALIGN);
3216 error = bus_dmamem_coherent(rdata->jme_sc->jme_cdata.jme_ring_tag,
3217 JME_RX_RING_ALIGN, 0,
3218 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3219 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3221 device_printf(rdata->jme_sc->jme_dev,
3222 "could not allocate %dth Rx ring.\n", rdata->jme_rx_idx);
3225 rdata->jme_rx_ring_tag = dmem.dmem_tag;
3226 rdata->jme_rx_ring_map = dmem.dmem_map;
3227 rdata->jme_rx_ring = dmem.dmem_addr;
3228 rdata->jme_rx_ring_paddr = dmem.dmem_busaddr;
3234 jme_rxbuf_dma_filter(void *arg __unused, bus_addr_t paddr)
3236 if ((paddr & 0xffffffff) == 0) {
3238 * Don't allow lower 32bits of the RX buffer's
3239 * physical address to be 0, else it will break
3240 * hardware pending RSS information delivery
3241 * detection on RX path.
3249 jme_rxbuf_dma_alloc(struct jme_rxdata *rdata)
3254 lowaddr = BUS_SPACE_MAXADDR;
3255 if (JME_ENABLE_HWRSS(rdata->jme_sc)) {
3256 /* jme_rxbuf_dma_filter will be called */
3257 lowaddr = BUS_SPACE_MAXADDR_32BIT;
3260 /* Create tag for Rx buffers. */
3261 error = bus_dma_tag_create(
3262 rdata->jme_sc->jme_cdata.jme_buffer_tag,/* parent */
3263 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */
3264 lowaddr, /* lowaddr */
3265 BUS_SPACE_MAXADDR, /* highaddr */
3266 jme_rxbuf_dma_filter, NULL, /* filter, filterarg */
3267 MCLBYTES, /* maxsize */
3269 MCLBYTES, /* maxsegsize */
3270 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */
3271 &rdata->jme_rx_tag);
3273 device_printf(rdata->jme_sc->jme_dev,
3274 "could not create %dth Rx DMA tag.\n", rdata->jme_rx_idx);
3278 /* Create DMA maps for Rx buffers. */
3279 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3280 &rdata->jme_rx_sparemap);
3282 device_printf(rdata->jme_sc->jme_dev,
3283 "could not create %dth spare Rx dmamap.\n",
3285 bus_dma_tag_destroy(rdata->jme_rx_tag);
3286 rdata->jme_rx_tag = NULL;
3289 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
3290 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i];
3292 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3297 device_printf(rdata->jme_sc->jme_dev,
3298 "could not create %dth Rx dmamap "
3299 "for %dth RX ring.\n", i, rdata->jme_rx_idx);
3301 for (j = 0; j < i; ++j) {
3302 rxd = &rdata->jme_rxdesc[j];
3303 bus_dmamap_destroy(rdata->jme_rx_tag,
3306 bus_dmamap_destroy(rdata->jme_rx_tag,
3307 rdata->jme_rx_sparemap);
3308 bus_dma_tag_destroy(rdata->jme_rx_tag);
3309 rdata->jme_rx_tag = NULL;
3317 jme_rx_intr(struct jme_softc *sc, uint32_t status)
3321 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3322 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3324 if (status & rdata->jme_rx_coal) {
3325 lwkt_serialize_enter(&rdata->jme_rx_serialize);
3326 jme_rxeof(rdata, -1);
3327 lwkt_serialize_exit(&rdata->jme_rx_serialize);
3333 jme_enable_rss(struct jme_softc *sc)
3336 uint8_t key[RSSKEY_NREGS * RSSKEY_REGSIZE];
3339 KASSERT(sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_2 ||
3340 sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_4,
3341 ("%s: invalid # of RX rings (%d)",
3342 sc->arpcom.ac_if.if_xname, sc->jme_cdata.jme_rx_ring_cnt));
3344 rssc = RSSC_HASH_64_ENTRY;
3345 rssc |= RSSC_HASH_IPV4 | RSSC_HASH_IPV4_TCP;
3346 rssc |= sc->jme_cdata.jme_rx_ring_cnt >> 1;
3347 JME_RSS_DPRINTF(sc, 1, "rssc 0x%08x\n", rssc);
3348 CSR_WRITE_4(sc, JME_RSSC, rssc);
3350 toeplitz_get_key(key, sizeof(key));
3351 for (i = 0; i < RSSKEY_NREGS; ++i) {
3354 keyreg = RSSKEY_REGVAL(key, i);
3355 JME_RSS_DPRINTF(sc, 5, "keyreg%d 0x%08x\n", i, keyreg);
3357 CSR_WRITE_4(sc, RSSKEY_REG(i), keyreg);
3361 * Create redirect table in following fashion:
3362 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
3365 for (i = 0; i < RSSTBL_REGSIZE; ++i) {
3368 q = i % sc->jme_cdata.jme_rx_ring_cnt;
3369 ind |= q << (i * 8);
3371 JME_RSS_DPRINTF(sc, 1, "ind 0x%08x\n", ind);
3373 for (i = 0; i < RSSTBL_NREGS; ++i)
3374 CSR_WRITE_4(sc, RSSTBL_REG(i), ind);
3378 jme_disable_rss(struct jme_softc *sc)
3380 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
3384 jme_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3386 struct jme_softc *sc = ifp->if_softc;
3388 ifnet_serialize_array_enter(sc->jme_serialize_arr,
3389 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
3393 jme_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3395 struct jme_softc *sc = ifp->if_softc;
3397 ifnet_serialize_array_exit(sc->jme_serialize_arr,
3398 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
3402 jme_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3404 struct jme_softc *sc = ifp->if_softc;
3406 return ifnet_serialize_array_try(sc->jme_serialize_arr,
3407 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
3413 jme_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3414 boolean_t serialized)
3416 struct jme_softc *sc = ifp->if_softc;
3418 ifnet_serialize_array_assert(sc->jme_serialize_arr,
3419 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE,
3423 #endif /* INVARIANTS */
3426 jme_msix_try_alloc(device_t dev)
3428 struct jme_softc *sc = device_get_softc(dev);
3429 struct jme_msix_data *msix;
3430 int error, i, r, msix_enable, msix_count;
3432 msix_count = 1 + sc->jme_cdata.jme_rx_ring_cnt;
3433 KKASSERT(msix_count <= JME_NMSIX);
3435 msix_enable = device_getenv_int(dev, "msix.enable", jme_msix_enable);
3438 * We leave the 1st MSI-X vector unused, so we
3439 * actually need msix_count + 1 MSI-X vectors.
3441 if (!msix_enable || pci_msix_count(dev) < (msix_count + 1))
3444 for (i = 0; i < msix_count; ++i)
3445 sc->jme_msix[i].jme_msix_rid = -1;
3449 msix = &sc->jme_msix[i++];
3450 msix->jme_msix_cpuid = 0; /* XXX Put TX to cpu0 */
3451 msix->jme_msix_arg = &sc->jme_cdata;
3452 msix->jme_msix_func = jme_msix_tx;
3453 msix->jme_msix_intrs = INTR_TXQ_COAL | INTR_TXQ_COAL_TO;
3454 msix->jme_msix_serialize = &sc->jme_cdata.jme_tx_serialize;
3455 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), "%s tx",
3456 device_get_nameunit(dev));
3458 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3459 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3461 msix = &sc->jme_msix[i++];
3462 msix->jme_msix_cpuid = r; /* XXX Put RX to cpuX */
3463 msix->jme_msix_arg = rdata;
3464 msix->jme_msix_func = jme_msix_rx;
3465 msix->jme_msix_intrs = rdata->jme_rx_coal | rdata->jme_rx_empty;
3466 msix->jme_msix_serialize = &rdata->jme_rx_serialize;
3467 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc),
3468 "%s rx%d", device_get_nameunit(dev), r);
3471 KKASSERT(i == msix_count);
3473 error = pci_setup_msix(dev);
3477 /* Setup jme_msix_cnt early, so we could cleanup */
3478 sc->jme_msix_cnt = msix_count;
3480 for (i = 0; i < msix_count; ++i) {
3481 msix = &sc->jme_msix[i];
3483 msix->jme_msix_vector = i + 1;
3484 error = pci_alloc_msix_vector(dev, msix->jme_msix_vector,
3485 &msix->jme_msix_rid, msix->jme_msix_cpuid);
3489 msix->jme_msix_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3490 &msix->jme_msix_rid, RF_ACTIVE);
3491 if (msix->jme_msix_res == NULL) {
3497 for (i = 0; i < JME_INTR_CNT; ++i) {
3498 uint32_t intr_mask = (1 << i);
3501 if ((JME_INTRS & intr_mask) == 0)
3504 for (x = 0; x < msix_count; ++x) {
3505 msix = &sc->jme_msix[x];
3506 if (msix->jme_msix_intrs & intr_mask) {
3509 reg = i / JME_MSINUM_FACTOR;
3510 KKASSERT(reg < JME_MSINUM_CNT);
3512 shift = (i % JME_MSINUM_FACTOR) * 4;
3514 sc->jme_msinum[reg] |=
3515 (msix->jme_msix_vector << shift);
3523 for (i = 0; i < JME_MSINUM_CNT; ++i) {
3524 device_printf(dev, "MSINUM%d: %#x\n", i,
3529 pci_enable_msix(dev);
3530 sc->jme_irq_type = PCI_INTR_TYPE_MSIX;
3538 jme_intr_alloc(device_t dev)
3540 struct jme_softc *sc = device_get_softc(dev);
3543 jme_msix_try_alloc(dev);
3545 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3546 sc->jme_irq_type = pci_alloc_1intr(dev, jme_msi_enable,
3547 &sc->jme_irq_rid, &irq_flags);
3549 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3550 &sc->jme_irq_rid, irq_flags);
3551 if (sc->jme_irq_res == NULL) {
3552 device_printf(dev, "can't allocate irq\n");
3560 jme_msix_free(device_t dev)
3562 struct jme_softc *sc = device_get_softc(dev);
3565 KKASSERT(sc->jme_msix_cnt > 1);
3567 for (i = 0; i < sc->jme_msix_cnt; ++i) {
3568 struct jme_msix_data *msix = &sc->jme_msix[i];
3570 if (msix->jme_msix_res != NULL) {
3571 bus_release_resource(dev, SYS_RES_IRQ,
3572 msix->jme_msix_rid, msix->jme_msix_res);
3573 msix->jme_msix_res = NULL;
3575 if (msix->jme_msix_rid >= 0) {
3576 pci_release_msix_vector(dev, msix->jme_msix_rid);
3577 msix->jme_msix_rid = -1;
3580 pci_teardown_msix(dev);
3584 jme_intr_free(device_t dev)
3586 struct jme_softc *sc = device_get_softc(dev);
3588 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3589 if (sc->jme_irq_res != NULL) {
3590 bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid,
3593 if (sc->jme_irq_type == PCI_INTR_TYPE_MSI)
3594 pci_release_msi(dev);
3601 jme_msix_tx(void *xcd)
3603 struct jme_chain_data *cd = xcd;
3604 struct jme_softc *sc = cd->jme_sc;
3605 struct ifnet *ifp = &sc->arpcom.ac_if;
3607 ASSERT_SERIALIZED(&cd->jme_tx_serialize);
3609 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3611 CSR_WRITE_4(sc, JME_INTR_STATUS,
3612 INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP);
3614 if (ifp->if_flags & IFF_RUNNING) {
3616 if (!ifq_is_empty(&ifp->if_snd))
3620 CSR_WRITE_4(sc, JME_INTR_MASK_SET, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3624 jme_msix_rx(void *xrdata)
3626 struct jme_rxdata *rdata = xrdata;
3627 struct jme_softc *sc = rdata->jme_sc;
3628 struct ifnet *ifp = &sc->arpcom.ac_if;
3631 ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3633 CSR_WRITE_4(sc, JME_INTR_MASK_CLR,
3634 (rdata->jme_rx_coal | rdata->jme_rx_empty));
3636 status = CSR_READ_4(sc, JME_INTR_STATUS);
3637 status &= (rdata->jme_rx_coal | rdata->jme_rx_empty);
3639 if (status & rdata->jme_rx_coal)
3640 status |= (rdata->jme_rx_coal | rdata->jme_rx_comp);
3641 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3643 if (ifp->if_flags & IFF_RUNNING) {
3644 if (status & rdata->jme_rx_coal)
3645 jme_rxeof(rdata, -1);
3647 if (status & rdata->jme_rx_empty) {
3648 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3649 RXCSR_RX_ENB | RXCSR_RXQ_START);
3653 CSR_WRITE_4(sc, JME_INTR_MASK_SET,
3654 (rdata->jme_rx_coal | rdata->jme_rx_empty));
3658 jme_set_msinum(struct jme_softc *sc)
3662 for (i = 0; i < JME_MSINUM_CNT; ++i)
3663 CSR_WRITE_4(sc, JME_MSINUM(i), sc->jme_msinum[i]);
3667 jme_intr_setup(device_t dev)
3669 struct jme_softc *sc = device_get_softc(dev);
3670 struct ifnet *ifp = &sc->arpcom.ac_if;
3673 if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3674 return jme_msix_setup(dev);
3676 error = bus_setup_intr(dev, sc->jme_irq_res, INTR_MPSAFE,
3677 jme_intr, sc, &sc->jme_irq_handle, &sc->jme_serialize);
3679 device_printf(dev, "could not set up interrupt handler.\n");
3683 ifp->if_cpuid = rman_get_cpuid(sc->jme_irq_res);
3684 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3689 jme_intr_teardown(device_t dev)
3691 struct jme_softc *sc = device_get_softc(dev);
3693 if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3694 jme_msix_teardown(dev, sc->jme_msix_cnt);
3696 bus_teardown_intr(dev, sc->jme_irq_res, sc->jme_irq_handle);
3700 jme_msix_setup(device_t dev)
3702 struct jme_softc *sc = device_get_softc(dev);
3703 struct ifnet *ifp = &sc->arpcom.ac_if;
3706 for (x = 0; x < sc->jme_msix_cnt; ++x) {
3707 struct jme_msix_data *msix = &sc->jme_msix[x];
3710 error = bus_setup_intr_descr(dev, msix->jme_msix_res,
3711 INTR_MPSAFE, msix->jme_msix_func, msix->jme_msix_arg,
3712 &msix->jme_msix_handle, msix->jme_msix_serialize,
3713 msix->jme_msix_desc);
3715 device_printf(dev, "could not set up %s "
3716 "interrupt handler.\n", msix->jme_msix_desc);
3717 jme_msix_teardown(dev, x);
3721 ifp->if_cpuid = 0; /* XXX */
3726 jme_msix_teardown(device_t dev, int msix_count)
3728 struct jme_softc *sc = device_get_softc(dev);
3731 for (x = 0; x < msix_count; ++x) {
3732 struct jme_msix_data *msix = &sc->jme_msix[x];
3734 bus_teardown_intr(dev, msix->jme_msix_res,
3735 msix->jme_msix_handle);
3740 jme_serialize_skipmain(struct jme_softc *sc)
3742 lwkt_serialize_array_enter(sc->jme_serialize_arr,
3743 sc->jme_serialize_cnt, 1);
3747 jme_deserialize_skipmain(struct jme_softc *sc)
3749 lwkt_serialize_array_exit(sc->jme_serialize_arr,
3750 sc->jme_serialize_cnt, 1);