sys/dev/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <ddb/ddb.h>
  28 #include <sys/limits.h>
  29
  30 #include <drm/drmP.h>
  31 #include <drm/drm_edid.h>
  32 #include "intel_drv.h"
  33 #include <drm/i915_drm.h>
  34 #include "i915_drv.h"
  35 #include <drm/drm_dp_helper.h>
  36 #include <drm/drm_crtc_helper.h>
  37
  38 #include <linux/err.h>
  39
  40 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  41 static void intel_increase_pllclock(struct drm_crtc *crtc);
  42 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  43
  44 typedef struct {
  45         /* given values */
  46         int n;
  47         int m1, m2;
  48         int p1, p2;
  49         /* derived values */
  50         int     dot;
  51         int     vco;
  52         int     m;
  53         int     p;
  54 } intel_clock_t;
  55
  56 typedef struct {
  57         int     min, max;
  58 } intel_range_t;
  59
  60 typedef struct {
  61         int     dot_limit;
  62         int     p2_slow, p2_fast;
  63 } intel_p2_t;
  64
  65 #define INTEL_P2_NUM                  2
  66 typedef struct intel_limit intel_limit_t;
  67 struct intel_limit {
  68         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  69         intel_p2_t          p2;
  70         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  71                         int, int, intel_clock_t *, intel_clock_t *);
  72 };
  73
  74 /* FDI */
  75 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  76
  77 int
  78 intel_pch_rawclk(struct drm_device *dev)
  79 {
  80         struct drm_i915_private *dev_priv = dev->dev_private;
  81
  82         WARN_ON(!HAS_PCH_SPLIT(dev));
  83
  84         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  85 }
  86
  87 static bool
  88 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  89                     int target, int refclk, intel_clock_t *match_clock,
  90                     intel_clock_t *best_clock);
  91 static bool
  92 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  93                         int target, int refclk, intel_clock_t *match_clock,
  94                         intel_clock_t *best_clock);
  95
  96 static bool
  97 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  98                       int target, int refclk, intel_clock_t *match_clock,
  99                       intel_clock_t *best_clock);
 100 static bool
 101 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 102                            int target, int refclk, intel_clock_t *match_clock,
 103                            intel_clock_t *best_clock);
 104
 105 static bool
 106 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 107                         int target, int refclk, intel_clock_t *match_clock,
 108                         intel_clock_t *best_clock);
 109
 110 static inline u32 /* units of 100MHz */
 111 intel_fdi_link_freq(struct drm_device *dev)
 112 {
 113         if (IS_GEN5(dev)) {
 114                 struct drm_i915_private *dev_priv = dev->dev_private;
 115                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 116         } else
 117                 return 27;
 118 }
 119
 120 static const intel_limit_t intel_limits_i8xx_dvo = {
 121         .dot = { .min = 25000, .max = 350000 },
 122         .vco = { .min = 930000, .max = 1400000 },
 123         .n = { .min = 3, .max = 16 },
 124         .m = { .min = 96, .max = 140 },
 125         .m1 = { .min = 18, .max = 26 },
 126         .m2 = { .min = 6, .max = 16 },
 127         .p = { .min = 4, .max = 128 },
 128         .p1 = { .min = 2, .max = 33 },
 129         .p2 = { .dot_limit = 165000,
 130                 .p2_slow = 4, .p2_fast = 2 },
 131         .find_pll = intel_find_best_PLL,
 132 };
 133
 134 static const intel_limit_t intel_limits_i8xx_lvds = {
 135         .dot = { .min = 25000, .max = 350000 },
 136         .vco = { .min = 930000, .max = 1400000 },
 137         .n = { .min = 3, .max = 16 },
 138         .m = { .min = 96, .max = 140 },
 139         .m1 = { .min = 18, .max = 26 },
 140         .m2 = { .min = 6, .max = 16 },
 141         .p = { .min = 4, .max = 128 },
 142         .p1 = { .min = 1, .max = 6 },
 143         .p2 = { .dot_limit = 165000,
 144                 .p2_slow = 14, .p2_fast = 7 },
 145         .find_pll = intel_find_best_PLL,
 146 };
 147
 148 static const intel_limit_t intel_limits_i9xx_sdvo = {
 149         .dot = { .min = 20000, .max = 400000 },
 150         .vco = { .min = 1400000, .max = 2800000 },
 151         .n = { .min = 1, .max = 6 },
 152         .m = { .min = 70, .max = 120 },
 153         .m1 = { .min = 8, .max = 18 },
 154         .m2 = { .min = 3, .max = 7 },
 155         .p = { .min = 5, .max = 80 },
 156         .p1 = { .min = 1, .max = 8 },
 157         .p2 = { .dot_limit = 200000,
 158                 .p2_slow = 10, .p2_fast = 5 },
 159         .find_pll = intel_find_best_PLL,
 160 };
 161
 162 static const intel_limit_t intel_limits_i9xx_lvds = {
 163         .dot = { .min = 20000, .max = 400000 },
 164         .vco = { .min = 1400000, .max = 2800000 },
 165         .n = { .min = 1, .max = 6 },
 166         .m = { .min = 70, .max = 120 },
 167         .m1 = { .min = 8, .max = 18 },
 168         .m2 = { .min = 3, .max = 7 },
 169         .p = { .min = 7, .max = 98 },
 170         .p1 = { .min = 1, .max = 8 },
 171         .p2 = { .dot_limit = 112000,
 172                 .p2_slow = 14, .p2_fast = 7 },
 173         .find_pll = intel_find_best_PLL,
 174 };
 175
 176
 177 static const intel_limit_t intel_limits_g4x_sdvo = {
 178         .dot = { .min = 25000, .max = 270000 },
 179         .vco = { .min = 1750000, .max = 3500000},
 180         .n = { .min = 1, .max = 4 },
 181         .m = { .min = 104, .max = 138 },
 182         .m1 = { .min = 17, .max = 23 },
 183         .m2 = { .min = 5, .max = 11 },
 184         .p = { .min = 10, .max = 30 },
 185         .p1 = { .min = 1, .max = 3},
 186         .p2 = { .dot_limit = 270000,
 187                 .p2_slow = 10,
 188                 .p2_fast = 10
 189         },
 190         .find_pll = intel_g4x_find_best_PLL,
 191 };
 192
 193 static const intel_limit_t intel_limits_g4x_hdmi = {
 194         .dot = { .min = 22000, .max = 400000 },
 195         .vco = { .min = 1750000, .max = 3500000},
 196         .n = { .min = 1, .max = 4 },
 197         .m = { .min = 104, .max = 138 },
 198         .m1 = { .min = 16, .max = 23 },
 199         .m2 = { .min = 5, .max = 11 },
 200         .p = { .min = 5, .max = 80 },
 201         .p1 = { .min = 1, .max = 8},
 202         .p2 = { .dot_limit = 165000,
 203                 .p2_slow = 10, .p2_fast = 5 },
 204         .find_pll = intel_g4x_find_best_PLL,
 205 };
 206
 207 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 208         .dot = { .min = 20000, .max = 115000 },
 209         .vco = { .min = 1750000, .max = 3500000 },
 210         .n = { .min = 1, .max = 3 },
 211         .m = { .min = 104, .max = 138 },
 212         .m1 = { .min = 17, .max = 23 },
 213         .m2 = { .min = 5, .max = 11 },
 214         .p = { .min = 28, .max = 112 },
 215         .p1 = { .min = 2, .max = 8 },
 216         .p2 = { .dot_limit = 0,
 217                 .p2_slow = 14, .p2_fast = 14
 218         },
 219         .find_pll = intel_g4x_find_best_PLL,
 220 };
 221
 222 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 223         .dot = { .min = 80000, .max = 224000 },
 224         .vco = { .min = 1750000, .max = 3500000 },
 225         .n = { .min = 1, .max = 3 },
 226         .m = { .min = 104, .max = 138 },
 227         .m1 = { .min = 17, .max = 23 },
 228         .m2 = { .min = 5, .max = 11 },
 229         .p = { .min = 14, .max = 42 },
 230         .p1 = { .min = 2, .max = 6 },
 231         .p2 = { .dot_limit = 0,
 232                 .p2_slow = 7, .p2_fast = 7
 233         },
 234         .find_pll = intel_g4x_find_best_PLL,
 235 };
 236
 237 static const intel_limit_t intel_limits_g4x_display_port = {
 238         .dot = { .min = 161670, .max = 227000 },
 239         .vco = { .min = 1750000, .max = 3500000},
 240         .n = { .min = 1, .max = 2 },
 241         .m = { .min = 97, .max = 108 },
 242         .m1 = { .min = 0x10, .max = 0x12 },
 243         .m2 = { .min = 0x05, .max = 0x06 },
 244         .p = { .min = 10, .max = 20 },
 245         .p1 = { .min = 1, .max = 2},
 246         .p2 = { .dot_limit = 0,
 247                 .p2_slow = 10, .p2_fast = 10 },
 248         .find_pll = intel_find_pll_g4x_dp,
 249 };
 250
 251 static const intel_limit_t intel_limits_pineview_sdvo = {
 252         .dot = { .min = 20000, .max = 400000},
 253         .vco = { .min = 1700000, .max = 3500000 },
 254         /* Pineview's Ncounter is a ring counter */
 255         .n = { .min = 3, .max = 6 },
 256         .m = { .min = 2, .max = 256 },
 257         /* Pineview only has one combined m divider, which we treat as m2. */
 258         .m1 = { .min = 0, .max = 0 },
 259         .m2 = { .min = 0, .max = 254 },
 260         .p = { .min = 5, .max = 80 },
 261         .p1 = { .min = 1, .max = 8 },
 262         .p2 = { .dot_limit = 200000,
 263                 .p2_slow = 10, .p2_fast = 5 },
 264         .find_pll = intel_find_best_PLL,
 265 };
 266
 267 static const intel_limit_t intel_limits_pineview_lvds = {
 268         .dot = { .min = 20000, .max = 400000 },
 269         .vco = { .min = 1700000, .max = 3500000 },
 270         .n = { .min = 3, .max = 6 },
 271         .m = { .min = 2, .max = 256 },
 272         .m1 = { .min = 0, .max = 0 },
 273         .m2 = { .min = 0, .max = 254 },
 274         .p = { .min = 7, .max = 112 },
 275         .p1 = { .min = 1, .max = 8 },
 276         .p2 = { .dot_limit = 112000,
 277                 .p2_slow = 14, .p2_fast = 14 },
 278         .find_pll = intel_find_best_PLL,
 279 };
 280
 281 /* Ironlake / Sandybridge
 282  *
 283  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 284  * the range value for them is (actual_value - 2).
 285  */
 286 static const intel_limit_t intel_limits_ironlake_dac = {
 287         .dot = { .min = 25000, .max = 350000 },
 288         .vco = { .min = 1760000, .max = 3510000 },
 289         .n = { .min = 1, .max = 5 },
 290         .m = { .min = 79, .max = 127 },
 291         .m1 = { .min = 12, .max = 22 },
 292         .m2 = { .min = 5, .max = 9 },
 293         .p = { .min = 5, .max = 80 },
 294         .p1 = { .min = 1, .max = 8 },
 295         .p2 = { .dot_limit = 225000,
 296                 .p2_slow = 10, .p2_fast = 5 },
 297         .find_pll = intel_g4x_find_best_PLL,
 298 };
 299
 300 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 301         .dot = { .min = 25000, .max = 350000 },
 302         .vco = { .min = 1760000, .max = 3510000 },
 303         .n = { .min = 1, .max = 3 },
 304         .m = { .min = 79, .max = 118 },
 305         .m1 = { .min = 12, .max = 22 },
 306         .m2 = { .min = 5, .max = 9 },
 307         .p = { .min = 28, .max = 112 },
 308         .p1 = { .min = 2, .max = 8 },
 309         .p2 = { .dot_limit = 225000,
 310                 .p2_slow = 14, .p2_fast = 14 },
 311         .find_pll = intel_g4x_find_best_PLL,
 312 };
 313
 314 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 315         .dot = { .min = 25000, .max = 350000 },
 316         .vco = { .min = 1760000, .max = 3510000 },
 317         .n = { .min = 1, .max = 3 },
 318         .m = { .min = 79, .max = 127 },
 319         .m1 = { .min = 12, .max = 22 },
 320         .m2 = { .min = 5, .max = 9 },
 321         .p = { .min = 14, .max = 56 },
 322         .p1 = { .min = 2, .max = 8 },
 323         .p2 = { .dot_limit = 225000,
 324                 .p2_slow = 7, .p2_fast = 7 },
 325         .find_pll = intel_g4x_find_best_PLL,
 326 };
 327
 328 /* LVDS 100mhz refclk limits. */
 329 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 330         .dot = { .min = 25000, .max = 350000 },
 331         .vco = { .min = 1760000, .max = 3510000 },
 332         .n = { .min = 1, .max = 2 },
 333         .m = { .min = 79, .max = 126 },
 334         .m1 = { .min = 12, .max = 22 },
 335         .m2 = { .min = 5, .max = 9 },
 336         .p = { .min = 28, .max = 112 },
 337         .p1 = { .min = 2, .max = 8 },
 338         .p2 = { .dot_limit = 225000,
 339                 .p2_slow = 14, .p2_fast = 14 },
 340         .find_pll = intel_g4x_find_best_PLL,
 341 };
 342
 343 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 344         .dot = { .min = 25000, .max = 350000 },
 345         .vco = { .min = 1760000, .max = 3510000 },
 346         .n = { .min = 1, .max = 3 },
 347         .m = { .min = 79, .max = 126 },
 348         .m1 = { .min = 12, .max = 22 },
 349         .m2 = { .min = 5, .max = 9 },
 350         .p = { .min = 14, .max = 42 },
 351         .p1 = { .min = 2, .max = 6 },
 352         .p2 = { .dot_limit = 225000,
 353                 .p2_slow = 7, .p2_fast = 7 },
 354         .find_pll = intel_g4x_find_best_PLL,
 355 };
 356
 357 static const intel_limit_t intel_limits_ironlake_display_port = {
 358         .dot = { .min = 25000, .max = 350000 },
 359         .vco = { .min = 1760000, .max = 3510000},
 360         .n = { .min = 1, .max = 2 },
 361         .m = { .min = 81, .max = 90 },
 362         .m1 = { .min = 12, .max = 22 },
 363         .m2 = { .min = 5, .max = 9 },
 364         .p = { .min = 10, .max = 20 },
 365         .p1 = { .min = 1, .max = 2},
 366         .p2 = { .dot_limit = 0,
 367                 .p2_slow = 10, .p2_fast = 10 },
 368         .find_pll = intel_find_pll_ironlake_dp,
 369 };
 370
 371 static const intel_limit_t intel_limits_vlv_dac = {
 372         .dot = { .min = 25000, .max = 270000 },
 373         .vco = { .min = 4000000, .max = 6000000 },
 374         .n = { .min = 1, .max = 7 },
 375         .m = { .min = 22, .max = 450 }, /* guess */
 376         .m1 = { .min = 2, .max = 3 },
 377         .m2 = { .min = 11, .max = 156 },
 378         .p = { .min = 10, .max = 30 },
 379         .p1 = { .min = 2, .max = 3 },
 380         .p2 = { .dot_limit = 270000,
 381                 .p2_slow = 2, .p2_fast = 20 },
 382         .find_pll = intel_vlv_find_best_pll,
 383 };
 384
 385 static const intel_limit_t intel_limits_vlv_hdmi = {
 386         .dot = { .min = 20000, .max = 165000 },
 387         .vco = { .min = 4000000, .max = 5994000},
 388         .n = { .min = 1, .max = 7 },
 389         .m = { .min = 60, .max = 300 }, /* guess */
 390         .m1 = { .min = 2, .max = 3 },
 391         .m2 = { .min = 11, .max = 156 },
 392         .p = { .min = 10, .max = 30 },
 393         .p1 = { .min = 2, .max = 3 },
 394         .p2 = { .dot_limit = 270000,
 395                 .p2_slow = 2, .p2_fast = 20 },
 396         .find_pll = intel_vlv_find_best_pll,
 397 };
 398
 399 static const intel_limit_t intel_limits_vlv_dp = {
 400         .dot = { .min = 25000, .max = 270000 },
 401         .vco = { .min = 4000000, .max = 6000000 },
 402         .n = { .min = 1, .max = 7 },
 403         .m = { .min = 22, .max = 450 },
 404         .m1 = { .min = 2, .max = 3 },
 405         .m2 = { .min = 11, .max = 156 },
 406         .p = { .min = 10, .max = 30 },
 407         .p1 = { .min = 2, .max = 3 },
 408         .p2 = { .dot_limit = 270000,
 409                 .p2_slow = 2, .p2_fast = 20 },
 410         .find_pll = intel_vlv_find_best_pll,
 411 };
 412
 413 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 414 {
 415         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 416
 417         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 418                 DRM_ERROR("DPIO idle wait timed out\n");
 419                 return 0;
 420         }
 421
 422         I915_WRITE(DPIO_REG, reg);
 423         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 424                    DPIO_BYTE);
 425         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 426                 DRM_ERROR("DPIO read wait timed out\n");
 427                 return 0;
 428         }
 429
 430         return I915_READ(DPIO_DATA);
 431 }
 432
 433 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 434                              u32 val)
 435 {
 436         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 437
 438         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 439                 DRM_ERROR("DPIO idle wait timed out\n");
 440                 return;
 441         }
 442
 443         I915_WRITE(DPIO_DATA, val);
 444         I915_WRITE(DPIO_REG, reg);
 445         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 446                    DPIO_BYTE);
 447         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 448                 DRM_ERROR("DPIO write wait timed out\n");
 449 }
 450
 451 static void vlv_init_dpio(struct drm_device *dev)
 452 {
 453         struct drm_i915_private *dev_priv = dev->dev_private;
 454
 455         /* Reset the DPIO config */
 456         I915_WRITE(DPIO_CTL, 0);
 457         POSTING_READ(DPIO_CTL);
 458         I915_WRITE(DPIO_CTL, 1);
 459         POSTING_READ(DPIO_CTL);
 460 }
 461
 462 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 463                                                 int refclk)
 464 {
 465         struct drm_device *dev = crtc->dev;
 466         const intel_limit_t *limit;
 467
 468         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 469                 if (intel_is_dual_link_lvds(dev)) {
 470                         /* LVDS dual channel */
 471                         if (refclk == 100000)
 472                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 473                         else
 474                                 limit = &intel_limits_ironlake_dual_lvds;
 475                 } else {
 476                         if (refclk == 100000)
 477                                 limit = &intel_limits_ironlake_single_lvds_100m;
 478                         else
 479                                 limit = &intel_limits_ironlake_single_lvds;
 480                 }
 481         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 482                    intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
 483                 limit = &intel_limits_ironlake_display_port;
 484         else
 485                 limit = &intel_limits_ironlake_dac;
 486
 487         return limit;
 488 }
 489
 490 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 491 {
 492         struct drm_device *dev = crtc->dev;
 493         const intel_limit_t *limit;
 494
 495         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 496                 if (intel_is_dual_link_lvds(dev))
 497                         /* LVDS with dual channel */
 498                         limit = &intel_limits_g4x_dual_channel_lvds;
 499                 else
 500                         /* LVDS with dual channel */
 501                         limit = &intel_limits_g4x_single_channel_lvds;
 502         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 503                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 504                 limit = &intel_limits_g4x_hdmi;
 505         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 506                 limit = &intel_limits_g4x_sdvo;
 507         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 508                 limit = &intel_limits_g4x_display_port;
 509         } else /* The option is for other outputs */
 510                 limit = &intel_limits_i9xx_sdvo;
 511
 512         return limit;
 513 }
 514
 515 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 516 {
 517         struct drm_device *dev = crtc->dev;
 518         const intel_limit_t *limit;
 519
 520         if (HAS_PCH_SPLIT(dev))
 521                 limit = intel_ironlake_limit(crtc, refclk);
 522         else if (IS_G4X(dev)) {
 523                 limit = intel_g4x_limit(crtc);
 524         } else if (IS_PINEVIEW(dev)) {
 525                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 526                         limit = &intel_limits_pineview_lvds;
 527                 else
 528                         limit = &intel_limits_pineview_sdvo;
 529         } else if (IS_VALLEYVIEW(dev)) {
 530                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 531                         limit = &intel_limits_vlv_dac;
 532                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 533                         limit = &intel_limits_vlv_hdmi;
 534                 else
 535                         limit = &intel_limits_vlv_dp;
 536         } else if (!IS_GEN2(dev)) {
 537                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 538                         limit = &intel_limits_i9xx_lvds;
 539                 else
 540                         limit = &intel_limits_i9xx_sdvo;
 541         } else {
 542                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 543                         limit = &intel_limits_i8xx_lvds;
 544                 else
 545                         limit = &intel_limits_i8xx_dvo;
 546         }
 547         return limit;
 548 }
 549
 550 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 551 static void pineview_clock(int refclk, intel_clock_t *clock)
 552 {
 553         clock->m = clock->m2 + 2;
 554         clock->p = clock->p1 * clock->p2;
 555         clock->vco = refclk * clock->m / clock->n;
 556         clock->dot = clock->vco / clock->p;
 557 }
 558
 559 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 560 {
 561         if (IS_PINEVIEW(dev)) {
 562                 pineview_clock(refclk, clock);
 563                 return;
 564         }
 565         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 566         clock->p = clock->p1 * clock->p2;
 567         clock->vco = refclk * clock->m / (clock->n + 2);
 568         clock->dot = clock->vco / clock->p;
 569 }
 570
 571 /**
 572  * Returns whether any output on the specified pipe is of the specified type
 573  */
 574 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 575 {
 576         struct drm_device *dev = crtc->dev;
 577         struct intel_encoder *encoder;
 578
 579         for_each_encoder_on_crtc(dev, crtc, encoder)
 580                 if (encoder->type == type)
 581                         return true;
 582
 583         return false;
 584 }
 585
 586 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 587 /**
 588  * Returns whether the given set of divisors are valid for a given refclk with
 589  * the given connectors.
 590  */
 591
 592 static bool intel_PLL_is_valid(struct drm_device *dev,
 593                                const intel_limit_t *limit,
 594                                const intel_clock_t *clock)
 595 {
 596         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 597                 INTELPllInvalid("p1 out of range\n");
 598         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 599                 INTELPllInvalid("p out of range\n");
 600         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 601                 INTELPllInvalid("m2 out of range\n");
 602         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 603                 INTELPllInvalid("m1 out of range\n");
 604         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 605                 INTELPllInvalid("m1 <= m2\n");
 606         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 607                 INTELPllInvalid("m out of range\n");
 608         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 609                 INTELPllInvalid("n out of range\n");
 610         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 611                 INTELPllInvalid("vco out of range\n");
 612         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 613          * connector, etc., rather than just a single range.
 614          */
 615         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 616                 INTELPllInvalid("dot out of range\n");
 617
 618         return true;
 619 }
 620
 621 static bool
 622 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 623                     int target, int refclk, intel_clock_t *match_clock,
 624                     intel_clock_t *best_clock)
 625
 626 {
 627         struct drm_device *dev = crtc->dev;
 628         intel_clock_t clock;
 629         int err = target;
 630
 631         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 632                 /*
 633                  * For LVDS just rely on its current settings for dual-channel.
 634                  * We haven't figured out how to reliably set up different
 635                  * single/dual channel state, if we even can.
 636                  */
 637                 if (intel_is_dual_link_lvds(dev))
 638                         clock.p2 = limit->p2.p2_fast;
 639                 else
 640                         clock.p2 = limit->p2.p2_slow;
 641         } else {
 642                 if (target < limit->p2.dot_limit)
 643                         clock.p2 = limit->p2.p2_slow;
 644                 else
 645                         clock.p2 = limit->p2.p2_fast;
 646         }
 647
 648         memset(best_clock, 0, sizeof(*best_clock));
 649
 650         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 651              clock.m1++) {
 652                 for (clock.m2 = limit->m2.min;
 653                      clock.m2 <= limit->m2.max; clock.m2++) {
 654                         /* m1 is always 0 in Pineview */
 655                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 656                                 break;
 657                         for (clock.n = limit->n.min;
 658                              clock.n <= limit->n.max; clock.n++) {
 659                                 for (clock.p1 = limit->p1.min;
 660                                         clock.p1 <= limit->p1.max; clock.p1++) {
 661                                         int this_err;
 662
 663                                         intel_clock(dev, refclk, &clock);
 664                                         if (!intel_PLL_is_valid(dev, limit,
 665                                                                 &clock))
 666                                                 continue;
 667                                         if (match_clock &&
 668                                             clock.p != match_clock->p)
 669                                                 continue;
 670
 671                                         this_err = abs(clock.dot - target);
 672                                         if (this_err < err) {
 673                                                 *best_clock = clock;
 674                                                 err = this_err;
 675                                         }
 676                                 }
 677                         }
 678                 }
 679         }
 680
 681         return (err != target);
 682 }
 683
 684 static bool
 685 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 686                         int target, int refclk, intel_clock_t *match_clock,
 687                         intel_clock_t *best_clock)
 688 {
 689         struct drm_device *dev = crtc->dev;
 690         intel_clock_t clock;
 691         int max_n;
 692         bool found;
 693         /* approximately equals target * 0.00585 */
 694         int err_most = (target >> 8) + (target >> 9);
 695         found = false;
 696
 697         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 698                 int lvds_reg;
 699
 700                 if (HAS_PCH_SPLIT(dev))
 701                         lvds_reg = PCH_LVDS;
 702                 else
 703                         lvds_reg = LVDS;
 704                 if (intel_is_dual_link_lvds(dev))
 705                         clock.p2 = limit->p2.p2_fast;
 706                 else
 707                         clock.p2 = limit->p2.p2_slow;
 708         } else {
 709                 if (target < limit->p2.dot_limit)
 710                         clock.p2 = limit->p2.p2_slow;
 711                 else
 712                         clock.p2 = limit->p2.p2_fast;
 713         }
 714
 715         memset(best_clock, 0, sizeof(*best_clock));
 716         max_n = limit->n.max;
 717         /* based on hardware requirement, prefer smaller n to precision */
 718         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 719                 /* based on hardware requirement, prefere larger m1,m2 */
 720                 for (clock.m1 = limit->m1.max;
 721                      clock.m1 >= limit->m1.min; clock.m1--) {
 722                         for (clock.m2 = limit->m2.max;
 723                              clock.m2 >= limit->m2.min; clock.m2--) {
 724                                 for (clock.p1 = limit->p1.max;
 725                                      clock.p1 >= limit->p1.min; clock.p1--) {
 726                                         int this_err;
 727
 728                                         intel_clock(dev, refclk, &clock);
 729                                         if (!intel_PLL_is_valid(dev, limit,
 730                                                                 &clock))
 731                                                 continue;
 732                                         if (match_clock &&
 733                                             clock.p != match_clock->p)
 734                                                 continue;
 735
 736                                         this_err = abs(clock.dot - target);
 737                                         if (this_err < err_most) {
 738                                                 *best_clock = clock;
 739                                                 err_most = this_err;
 740                                                 max_n = clock.n;
 741                                                 found = true;
 742                                         }
 743                                 }
 744                         }
 745                 }
 746         }
 747         return found;
 748 }
 749
 750 static bool
 751 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 752                            int target, int refclk, intel_clock_t *match_clock,
 753                            intel_clock_t *best_clock)
 754 {
 755         struct drm_device *dev = crtc->dev;
 756         intel_clock_t clock;
 757
 758         if (target < 200000) {
 759                 clock.n = 1;
 760                 clock.p1 = 2;
 761                 clock.p2 = 10;
 762                 clock.m1 = 12;
 763                 clock.m2 = 9;
 764         } else {
 765                 clock.n = 2;
 766                 clock.p1 = 1;
 767                 clock.p2 = 10;
 768                 clock.m1 = 14;
 769                 clock.m2 = 8;
 770         }
 771         intel_clock(dev, refclk, &clock);
 772         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 773         return true;
 774 }
 775
 776 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 777 static bool
 778 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 779                       int target, int refclk, intel_clock_t *match_clock,
 780                       intel_clock_t *best_clock)
 781 {
 782         intel_clock_t clock;
 783         if (target < 200000) {
 784                 clock.p1 = 2;
 785                 clock.p2 = 10;
 786                 clock.n = 2;
 787                 clock.m1 = 23;
 788                 clock.m2 = 8;
 789         } else {
 790                 clock.p1 = 1;
 791                 clock.p2 = 10;
 792                 clock.n = 1;
 793                 clock.m1 = 14;
 794                 clock.m2 = 2;
 795         }
 796         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 797         clock.p = (clock.p1 * clock.p2);
 798         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 799         clock.vco = 0;
 800         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 801         return true;
 802 }
 803
 804 static bool
 805 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 806                         int target, int refclk, intel_clock_t *match_clock,
 807                         intel_clock_t *best_clock)
 808 {
 809         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 810         u32 m, n, fastclk;
 811         u32 updrate, minupdate, fracbits, p;
 812         unsigned long bestppm, ppm, absppm;
 813         int dotclk, flag;
 814
 815         flag = 0;
 816         dotclk = target * 1000;
 817         bestppm = 1000000;
 818         ppm = absppm = 0;
 819         fastclk = dotclk / (2*100);
 820         updrate = 0;
 821         minupdate = 19200;
 822         fracbits = 1;
 823         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 824         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 825
 826         /* based on hardware requirement, prefer smaller n to precision */
 827         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 828                 updrate = refclk / n;
 829                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 830                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 831                                 if (p2 > 10)
 832                                         p2 = p2 - 1;
 833                                 p = p1 * p2;
 834                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 835                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 836                                         m2 = (((2*(fastclk * p * n / m1 )) +
 837                                                refclk) / (2*refclk));
 838                                         m = m1 * m2;
 839                                         vco = updrate * m;
 840                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 841                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 842                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 843                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 844                                                         bestppm = 0;
 845                                                         flag = 1;
 846                                                 }
 847                                                 if (absppm < bestppm - 10) {
 848                                                         bestppm = absppm;
 849                                                         flag = 1;
 850                                                 }
 851                                                 if (flag) {
 852                                                         bestn = n;
 853                                                         bestm1 = m1;
 854                                                         bestm2 = m2;
 855                                                         bestp1 = p1;
 856                                                         bestp2 = p2;
 857                                                         flag = 0;
 858                                                 }
 859                                         }
 860                                 }
 861                         }
 862                 }
 863         }
 864         best_clock->n = bestn;
 865         best_clock->m1 = bestm1;
 866         best_clock->m2 = bestm2;
 867         best_clock->p1 = bestp1;
 868         best_clock->p2 = bestp2;
 869
 870         return true;
 871 }
 872
 873 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 874                                              enum i915_pipe pipe)
 875 {
 876         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 877         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 878
 879         return intel_crtc->cpu_transcoder;
 880 }
 881
 882 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 883 {
 884         struct drm_i915_private *dev_priv = dev->dev_private;
 885         u32 frame, frame_reg = PIPEFRAME(pipe);
 886
 887         frame = I915_READ(frame_reg);
 888
 889         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 890                 DRM_DEBUG_KMS("vblank wait timed out\n");
 891 }
 892
 893 /**
 894  * intel_wait_for_vblank - wait for vblank on a given pipe
 895  * @dev: drm device
 896  * @pipe: pipe to wait for
 897  *
 898  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 899  * mode setting code.
 900  */
 901 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 902 {
 903         struct drm_i915_private *dev_priv = dev->dev_private;
 904         int pipestat_reg = PIPESTAT(pipe);
 905
 906         if (INTEL_INFO(dev)->gen >= 5) {
 907                 ironlake_wait_for_vblank(dev, pipe);
 908                 return;
 909         }
 910
 911         /* Clear existing vblank status. Note this will clear any other
 912          * sticky status fields as well.
 913          *
 914          * This races with i915_driver_irq_handler() with the result
 915          * that either function could miss a vblank event.  Here it is not
 916          * fatal, as we will either wait upon the next vblank interrupt or
 917          * timeout.  Generally speaking intel_wait_for_vblank() is only
 918          * called during modeset at which time the GPU should be idle and
 919          * should *not* be performing page flips and thus not waiting on
 920          * vblanks...
 921          * Currently, the result of us stealing a vblank from the irq
 922          * handler is that a single frame will be skipped during swapbuffers.
 923          */
 924         I915_WRITE(pipestat_reg,
 925                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 926
 927         /* Wait for vblank interrupt bit to set */
 928         if (wait_for(I915_READ(pipestat_reg) &
 929                      PIPE_VBLANK_INTERRUPT_STATUS,
 930                      50))
 931                 DRM_DEBUG_KMS("vblank wait timed out\n");
 932 }
 933
 934 /*
 935  * intel_wait_for_pipe_off - wait for pipe to turn off
 936  * @dev: drm device
 937  * @pipe: pipe to wait for
 938  *
 939  * After disabling a pipe, we can't wait for vblank in the usual way,
 940  * spinning on the vblank interrupt status bit, since we won't actually
 941  * see an interrupt when the pipe is disabled.
 942  *
 943  * On Gen4 and above:
 944  *   wait for the pipe register state bit to turn off
 945  *
 946  * Otherwise:
 947  *   wait for the display line value to settle (it usually
 948  *   ends up stopping at the start of the next frame).
 949  *
 950  */
 951 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 952 {
 953         struct drm_i915_private *dev_priv = dev->dev_private;
 954         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 955                                                                       pipe);
 956
 957         if (INTEL_INFO(dev)->gen >= 4) {
 958                 int reg = PIPECONF(cpu_transcoder);
 959
 960                 /* Wait for the Pipe State to go off */
 961                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 962                              100))
 963                         WARN(1, "pipe_off wait timed out\n");
 964         } else {
 965                 u32 last_line, line_mask;
 966                 int reg = PIPEDSL(pipe);
 967                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 968
 969                 if (IS_GEN2(dev))
 970                         line_mask = DSL_LINEMASK_GEN2;
 971                 else
 972                         line_mask = DSL_LINEMASK_GEN3;
 973
 974                 /* Wait for the display line to settle */
 975                 do {
 976                         last_line = I915_READ(reg) & line_mask;
 977                         mdelay(5);
 978                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 979                          time_after(timeout, jiffies));
 980                 if (time_after(jiffies, timeout))
 981                         WARN(1, "pipe_off wait timed out\n");
 982         }
 983 }
 984
 985 /*
 986  * ibx_digital_port_connected - is the specified port connected?
 987  * @dev_priv: i915 private structure
 988  * @port: the port to test
 989  *
 990  * Returns true if @port is connected, false otherwise.
 991  */
 992 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 993                                 struct intel_digital_port *port)
 994 {
 995         u32 bit;
 996
 997         if (HAS_PCH_IBX(dev_priv->dev)) {
 998                 switch(port->port) {
 999                 case PORT_B:
1000                         bit = SDE_PORTB_HOTPLUG;
1001                         break;
1002                 case PORT_C:
1003                         bit = SDE_PORTC_HOTPLUG;
1004                         break;
1005                 case PORT_D:
1006                         bit = SDE_PORTD_HOTPLUG;
1007                         break;
1008                 default:
1009                         return true;
1010                 }
1011         } else {
1012                 switch(port->port) {
1013                 case PORT_B:
1014                         bit = SDE_PORTB_HOTPLUG_CPT;
1015                         break;
1016                 case PORT_C:
1017                         bit = SDE_PORTC_HOTPLUG_CPT;
1018                         break;
1019                 case PORT_D:
1020                         bit = SDE_PORTD_HOTPLUG_CPT;
1021                         break;
1022                 default:
1023                         return true;
1024                 }
1025         }
1026
1027         return I915_READ(SDEISR) & bit;
1028 }
1029
1030 static const char *state_string(bool enabled)
1031 {
1032         return enabled ? "on" : "off";
1033 }
1034
1035 /* Only for pre-ILK configs */
1036 static void assert_pll(struct drm_i915_private *dev_priv,
1037                        enum i915_pipe pipe, bool state)
1038 {
1039         int reg;
1040         u32 val;
1041         bool cur_state;
1042
1043         reg = DPLL(pipe);
1044         val = I915_READ(reg);
1045         cur_state = !!(val & DPLL_VCO_ENABLE);
1046         WARN(cur_state != state,
1047              "PLL state assertion failure (expected %s, current %s)\n",
1048              state_string(state), state_string(cur_state));
1049 }
1050 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1051 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1052
1053 /* For ILK+ */
1054 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1055                            struct intel_pch_pll *pll,
1056                            struct intel_crtc *crtc,
1057                            bool state)
1058 {
1059         u32 val;
1060         bool cur_state;
1061
1062         if (HAS_PCH_LPT(dev_priv->dev)) {
1063                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1064                 return;
1065         }
1066
1067         if (WARN (!pll,
1068                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1069                 return;
1070
1071         val = I915_READ(pll->pll_reg);
1072         cur_state = !!(val & DPLL_VCO_ENABLE);
1073         WARN(cur_state != state,
1074              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1075              pll->pll_reg, state_string(state), state_string(cur_state), val);
1076
1077         /* Make sure the selected PLL is correctly attached to the transcoder */
1078         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1079                 u32 pch_dpll;
1080
1081                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1082                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1083                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1084                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1085                           cur_state, crtc->pipe, pch_dpll)) {
1086                         cur_state = !!(val >> (4*crtc->pipe + 3));
1087                         WARN(cur_state != state,
1088                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1089                              pll->pll_reg == _PCH_DPLL_B,
1090                              state_string(state),
1091                              crtc->pipe,
1092                              val);
1093                 }
1094         }
1095 }
1096 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1097 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1098
1099 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1100                           enum i915_pipe pipe, bool state)
1101 {
1102         int reg;
1103         u32 val;
1104         bool cur_state;
1105         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1106                                                                       pipe);
1107
1108         if (HAS_DDI(dev_priv->dev)) {
1109                 /* DDI does not have a specific FDI_TX register */
1110                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1111                 val = I915_READ(reg);
1112                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1113         } else {
1114                 reg = FDI_TX_CTL(pipe);
1115                 val = I915_READ(reg);
1116                 cur_state = !!(val & FDI_TX_ENABLE);
1117         }
1118         WARN(cur_state != state,
1119              "FDI TX state assertion failure (expected %s, current %s)\n",
1120              state_string(state), state_string(cur_state));
1121 }
1122 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1123 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1124
1125 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1126                           enum i915_pipe pipe, bool state)
1127 {
1128         int reg;
1129         u32 val;
1130         bool cur_state;
1131
1132         reg = FDI_RX_CTL(pipe);
1133         val = I915_READ(reg);
1134         cur_state = !!(val & FDI_RX_ENABLE);
1135         WARN(cur_state != state,
1136              "FDI RX state assertion failure (expected %s, current %s)\n",
1137              state_string(state), state_string(cur_state));
1138 }
1139 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1140 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1141
1142 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1143                                       enum i915_pipe pipe)
1144 {
1145         int reg;
1146         u32 val;
1147
1148         /* ILK FDI PLL is always enabled */
1149         if (dev_priv->info->gen == 5)
1150                 return;
1151
1152         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1153         if (HAS_DDI(dev_priv->dev))
1154                 return;
1155
1156         reg = FDI_TX_CTL(pipe);
1157         val = I915_READ(reg);
1158         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1159 }
1160
1161 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1162                                       enum i915_pipe pipe)
1163 {
1164         int reg;
1165         u32 val;
1166
1167         reg = FDI_RX_CTL(pipe);
1168         val = I915_READ(reg);
1169         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1170 }
1171
1172 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1173                                   enum i915_pipe pipe)
1174 {
1175         int pp_reg, lvds_reg;
1176         u32 val;
1177         enum i915_pipe panel_pipe = PIPE_A;
1178         bool locked = true;
1179
1180         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1181                 pp_reg = PCH_PP_CONTROL;
1182                 lvds_reg = PCH_LVDS;
1183         } else {
1184                 pp_reg = PP_CONTROL;
1185                 lvds_reg = LVDS;
1186         }
1187
1188         val = I915_READ(pp_reg);
1189         if (!(val & PANEL_POWER_ON) ||
1190             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1191                 locked = false;
1192
1193         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1194                 panel_pipe = PIPE_B;
1195
1196         WARN(panel_pipe == pipe && locked,
1197              "panel assertion failure, pipe %c regs locked\n",
1198              pipe_name(pipe));
1199 }
1200
1201 void assert_pipe(struct drm_i915_private *dev_priv,
1202                  enum i915_pipe pipe, bool state)
1203 {
1204         int reg;
1205         u32 val;
1206         bool cur_state;
1207         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1208                                                                       pipe);
1209
1210         /* if we need the pipe A quirk it must be always on */
1211         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1212                 state = true;
1213
1214         if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1215             !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1216                 cur_state = false;
1217         } else {
1218                 reg = PIPECONF(cpu_transcoder);
1219                 val = I915_READ(reg);
1220                 cur_state = !!(val & PIPECONF_ENABLE);
1221         }
1222
1223         WARN(cur_state != state,
1224              "pipe %c assertion failure (expected %s, current %s)\n",
1225              pipe_name(pipe), state_string(state), state_string(cur_state));
1226 }
1227
1228 static void assert_plane(struct drm_i915_private *dev_priv,
1229                          enum plane plane, bool state)
1230 {
1231         int reg;
1232         u32 val;
1233         bool cur_state;
1234
1235         reg = DSPCNTR(plane);
1236         val = I915_READ(reg);
1237         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238         WARN(cur_state != state,
1239              "plane %c assertion failure (expected %s, current %s)\n",
1240              plane_name(plane), state_string(state), state_string(cur_state));
1241 }
1242
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
1246 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247                                    enum i915_pipe pipe)
1248 {
1249         int reg, i;
1250         u32 val;
1251         int cur_pipe;
1252
1253         /* Planes are fixed to pipes on ILK+ */
1254         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255                 reg = DSPCNTR(pipe);
1256                 val = I915_READ(reg);
1257                 WARN((val & DISPLAY_PLANE_ENABLE),
1258                      "plane %c assertion failure, should be disabled but not\n",
1259                      plane_name(pipe));
1260                 return;
1261         }
1262
1263         /* Need to check both planes against the pipe */
1264         for (i = 0; i < 2; i++) {
1265                 reg = DSPCNTR(i);
1266                 val = I915_READ(reg);
1267                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268                         DISPPLANE_SEL_PIPE_SHIFT;
1269                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1270                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271                      plane_name(i), pipe_name(pipe));
1272         }
1273 }
1274
1275 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276 {
1277         u32 val;
1278         bool enabled;
1279
1280         if (HAS_PCH_LPT(dev_priv->dev)) {
1281                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282                 return;
1283         }
1284
1285         val = I915_READ(PCH_DREF_CONTROL);
1286         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287                             DREF_SUPERSPREAD_SOURCE_MASK));
1288         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289 }
1290
1291 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292                                        enum i915_pipe pipe)
1293 {
1294         int reg;
1295         u32 val;
1296         bool enabled;
1297
1298         reg = TRANSCONF(pipe);
1299         val = I915_READ(reg);
1300         enabled = !!(val & TRANS_ENABLE);
1301         WARN(enabled,
1302              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303              pipe_name(pipe));
1304 }
1305
1306 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307                             enum i915_pipe pipe, u32 port_sel, u32 val)
1308 {
1309         if ((val & DP_PORT_EN) == 0)
1310                 return false;
1311
1312         if (HAS_PCH_CPT(dev_priv->dev)) {
1313                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316                         return false;
1317         } else {
1318                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319                         return false;
1320         }
1321         return true;
1322 }
1323
1324 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325                               enum i915_pipe pipe, u32 val)
1326 {
1327         if ((val & PORT_ENABLE) == 0)
1328                 return false;
1329
1330         if (HAS_PCH_CPT(dev_priv->dev)) {
1331                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332                         return false;
1333         } else {
1334                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335                         return false;
1336         }
1337         return true;
1338 }
1339
1340 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341                               enum i915_pipe pipe, u32 val)
1342 {
1343         if ((val & LVDS_PORT_EN) == 0)
1344                 return false;
1345
1346         if (HAS_PCH_CPT(dev_priv->dev)) {
1347                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348                         return false;
1349         } else {
1350                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351                         return false;
1352         }
1353         return true;
1354 }
1355
1356 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357                               enum i915_pipe pipe, u32 val)
1358 {
1359         if ((val & ADPA_DAC_ENABLE) == 0)
1360                 return false;
1361         if (HAS_PCH_CPT(dev_priv->dev)) {
1362                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363                         return false;
1364         } else {
1365                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366                         return false;
1367         }
1368         return true;
1369 }
1370
1371 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1372                                    enum i915_pipe pipe, int reg, u32 port_sel)
1373 {
1374         u32 val = I915_READ(reg);
1375         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1376              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377              reg, pipe_name(pipe));
1378
1379         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1380              && (val & DP_PIPEB_SELECT),
1381              "IBX PCH dp port still using transcoder B\n");
1382 }
1383
1384 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1385                                      enum i915_pipe pipe, int reg)
1386 {
1387         u32 val = I915_READ(reg);
1388         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1389              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1390              reg, pipe_name(pipe));
1391
1392         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1393              && (val & SDVO_PIPE_B_SELECT),
1394              "IBX PCH hdmi port still using transcoder B\n");
1395 }
1396
1397 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1398                                       enum i915_pipe pipe)
1399 {
1400         int reg;
1401         u32 val;
1402
1403         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1404         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1405         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1406
1407         reg = PCH_ADPA;
1408         val = I915_READ(reg);
1409         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1410              "PCH VGA enabled on transcoder %c, should be disabled\n",
1411              pipe_name(pipe));
1412
1413         reg = PCH_LVDS;
1414         val = I915_READ(reg);
1415         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1416              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1417              pipe_name(pipe));
1418
1419         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1420         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1421         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1422 }
1423
1424 /**
1425  * intel_enable_pll - enable a PLL
1426  * @dev_priv: i915 private structure
1427  * @pipe: pipe PLL to enable
1428  *
1429  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1430  * make sure the PLL reg is writable first though, since the panel write
1431  * protect mechanism may be enabled.
1432  *
1433  * Note!  This is for pre-ILK only.
1434  *
1435  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1436  */
1437 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe)
1438 {
1439         int reg;
1440         u32 val;
1441
1442         /* No really, not for ILK+ */
1443         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1444
1445         /* PLL is protected by panel, make sure we can write it */
1446         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1447                 assert_panel_unlocked(dev_priv, pipe);
1448
1449         reg = DPLL(pipe);
1450         val = I915_READ(reg);
1451         val |= DPLL_VCO_ENABLE;
1452
1453         /* We do this three times for luck */
1454         I915_WRITE(reg, val);
1455         POSTING_READ(reg);
1456         udelay(150); /* wait for warmup */
1457         I915_WRITE(reg, val);
1458         POSTING_READ(reg);
1459         udelay(150); /* wait for warmup */
1460         I915_WRITE(reg, val);
1461         POSTING_READ(reg);
1462         udelay(150); /* wait for warmup */
1463 }
1464
1465 /**
1466  * intel_disable_pll - disable a PLL
1467  * @dev_priv: i915 private structure
1468  * @pipe: pipe PLL to disable
1469  *
1470  * Disable the PLL for @pipe, making sure the pipe is off first.
1471  *
1472  * Note!  This is for pre-ILK only.
1473  */
1474 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe)
1475 {
1476         int reg;
1477         u32 val;
1478
1479         /* Don't disable pipe A or pipe A PLLs if needed */
1480         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1481                 return;
1482
1483         /* Make sure the pipe isn't still relying on us */
1484         assert_pipe_disabled(dev_priv, pipe);
1485
1486         reg = DPLL(pipe);
1487         val = I915_READ(reg);
1488         val &= ~DPLL_VCO_ENABLE;
1489         I915_WRITE(reg, val);
1490         POSTING_READ(reg);
1491 }
1492
1493 /* SBI access */
1494 static void
1495 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1496                 enum intel_sbi_destination destination)
1497 {
1498         u32 tmp;
1499
1500         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1501
1502         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, 100)) {
1503                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1504                 return;
1505         }
1506
1507         I915_WRITE(SBI_ADDR, (reg << 16));
1508         I915_WRITE(SBI_DATA, value);
1509
1510         if (destination == SBI_ICLK)
1511                 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1512         else
1513                 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1514         I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1515
1516         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1517                                 100)) {
1518                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1519                 return;
1520         }
1521 }
1522
1523 static u32
1524 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1525                enum intel_sbi_destination destination)
1526 {
1527         u32 value = 0;
1528
1529         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1530
1531         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, 100)) {
1532                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1533                 return 0;
1534         }
1535
1536         I915_WRITE(SBI_ADDR, (reg << 16));
1537
1538         if (destination == SBI_ICLK)
1539                 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1540         else
1541                 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1542         I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1543
1544         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1545                                 100)) {
1546                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1547                 return 0;
1548         }
1549
1550         return I915_READ(SBI_DATA);
1551 }
1552
1553 /**
1554  * ironlake_enable_pch_pll - enable PCH PLL
1555  * @dev_priv: i915 private structure
1556  * @pipe: pipe PLL to enable
1557  *
1558  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1559  * drives the transcoder clock.
1560  */
1561 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1562 {
1563         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1564         struct intel_pch_pll *pll;
1565         int reg;
1566         u32 val;
1567
1568         /* PCH PLLs only available on ILK, SNB and IVB */
1569         BUG_ON(dev_priv->info->gen < 5);
1570         pll = intel_crtc->pch_pll;
1571         if (pll == NULL)
1572                 return;
1573
1574         if (WARN_ON(pll->refcount == 0))
1575                 return;
1576
1577         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1578                       pll->pll_reg, pll->active, pll->on,
1579                       intel_crtc->base.base.id);
1580
1581         /* PCH refclock must be enabled first */
1582         assert_pch_refclk_enabled(dev_priv);
1583
1584         if (pll->active++ && pll->on) {
1585                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1586                 return;
1587         }
1588
1589         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1590
1591         reg = pll->pll_reg;
1592         val = I915_READ(reg);
1593         val |= DPLL_VCO_ENABLE;
1594         I915_WRITE(reg, val);
1595         POSTING_READ(reg);
1596         udelay(200);
1597
1598         pll->on = true;
1599 }
1600
1601 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1602 {
1603         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1604         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1605         int reg;
1606         u32 val;
1607
1608         /* PCH only available on ILK+ */
1609         BUG_ON(dev_priv->info->gen < 5);
1610         if (pll == NULL)
1611                return;
1612
1613         if (WARN_ON(pll->refcount == 0))
1614                 return;
1615
1616         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1617                       pll->pll_reg, pll->active, pll->on,
1618                       intel_crtc->base.base.id);
1619
1620         if (WARN_ON(pll->active == 0)) {
1621                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1622                 return;
1623         }
1624
1625         if (--pll->active) {
1626                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1627                 return;
1628         }
1629
1630         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1631
1632         /* Make sure transcoder isn't still depending on us */
1633         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1634
1635         reg = pll->pll_reg;
1636         val = I915_READ(reg);
1637         val &= ~DPLL_VCO_ENABLE;
1638         I915_WRITE(reg, val);
1639         POSTING_READ(reg);
1640         udelay(200);
1641
1642         pll->on = false;
1643 }
1644
1645 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1646                                            enum i915_pipe pipe)
1647 {
1648         struct drm_device *dev = dev_priv->dev;
1649         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1650         uint32_t reg, val, pipeconf_val;
1651
1652         /* PCH only available on ILK+ */
1653         BUG_ON(dev_priv->info->gen < 5);
1654
1655         /* Make sure PCH DPLL is enabled */
1656         assert_pch_pll_enabled(dev_priv,
1657                                to_intel_crtc(crtc)->pch_pll,
1658                                to_intel_crtc(crtc));
1659
1660         /* FDI must be feeding us bits for PCH ports */
1661         assert_fdi_tx_enabled(dev_priv, pipe);
1662         assert_fdi_rx_enabled(dev_priv, pipe);
1663
1664         if (HAS_PCH_CPT(dev)) {
1665                 /* Workaround: Set the timing override bit before enabling the
1666                  * pch transcoder. */
1667                 reg = TRANS_CHICKEN2(pipe);
1668                 val = I915_READ(reg);
1669                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1670                 I915_WRITE(reg, val);
1671         }
1672
1673         reg = TRANSCONF(pipe);
1674         val = I915_READ(reg);
1675         pipeconf_val = I915_READ(PIPECONF(pipe));
1676
1677         if (HAS_PCH_IBX(dev_priv->dev)) {
1678                 /*
1679                  * make the BPC in transcoder be consistent with
1680                  * that in pipeconf reg.
1681                  */
1682                 val &= ~PIPECONF_BPC_MASK;
1683                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1684         }
1685
1686         val &= ~TRANS_INTERLACE_MASK;
1687         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1688                 if (HAS_PCH_IBX(dev_priv->dev) &&
1689                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1690                         val |= TRANS_LEGACY_INTERLACED_ILK;
1691                 else
1692                         val |= TRANS_INTERLACED;
1693         else
1694                 val |= TRANS_PROGRESSIVE;
1695
1696         I915_WRITE(reg, val | TRANS_ENABLE);
1697         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1698                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1699 }
1700
1701 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1702                                       enum transcoder cpu_transcoder)
1703 {
1704         u32 val, pipeconf_val;
1705
1706         /* PCH only available on ILK+ */
1707         BUG_ON(dev_priv->info->gen < 5);
1708
1709         /* FDI must be feeding us bits for PCH ports */
1710         assert_fdi_tx_enabled(dev_priv, (enum i915_pipe) cpu_transcoder);
1711         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1712
1713         /* Workaround: set timing override bit. */
1714         val = I915_READ(_TRANSA_CHICKEN2);
1715         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1716         I915_WRITE(_TRANSA_CHICKEN2, val);
1717
1718         val = TRANS_ENABLE;
1719         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1720
1721         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1722             PIPECONF_INTERLACED_ILK)
1723                 val |= TRANS_INTERLACED;
1724         else
1725                 val |= TRANS_PROGRESSIVE;
1726
1727         I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1728         if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1729                 DRM_ERROR("Failed to enable PCH transcoder\n");
1730 }
1731
1732 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1733                                             enum i915_pipe pipe)
1734 {
1735         struct drm_device *dev = dev_priv->dev;
1736         uint32_t reg, val;
1737
1738         /* FDI relies on the transcoder */
1739         assert_fdi_tx_disabled(dev_priv, pipe);
1740         assert_fdi_rx_disabled(dev_priv, pipe);
1741
1742         /* Ports must be off as well */
1743         assert_pch_ports_disabled(dev_priv, pipe);
1744
1745         reg = TRANSCONF(pipe);
1746         val = I915_READ(reg);
1747         val &= ~TRANS_ENABLE;
1748         I915_WRITE(reg, val);
1749         /* wait for PCH transcoder off, transcoder state */
1750         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1751                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1752
1753         if (!HAS_PCH_IBX(dev)) {
1754                 /* Workaround: Clear the timing override chicken bit again. */
1755                 reg = TRANS_CHICKEN2(pipe);
1756                 val = I915_READ(reg);
1757                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1758                 I915_WRITE(reg, val);
1759         }
1760 }
1761
1762 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1763 {
1764         u32 val;
1765
1766         val = I915_READ(_TRANSACONF);
1767         val &= ~TRANS_ENABLE;
1768         I915_WRITE(_TRANSACONF, val);
1769         /* wait for PCH transcoder off, transcoder state */
1770         if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1771                 DRM_ERROR("Failed to disable PCH transcoder\n");
1772
1773         /* Workaround: clear timing override bit. */
1774         val = I915_READ(_TRANSA_CHICKEN2);
1775         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1776         I915_WRITE(_TRANSA_CHICKEN2, val);
1777 }
1778
1779 /**
1780  * intel_enable_pipe - enable a pipe, asserting requirements
1781  * @dev_priv: i915 private structure
1782  * @pipe: pipe to enable
1783  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1784  *
1785  * Enable @pipe, making sure that various hardware specific requirements
1786  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1787  *
1788  * @pipe should be %PIPE_A or %PIPE_B.
1789  *
1790  * Will wait until the pipe is actually running (i.e. first vblank) before
1791  * returning.
1792  */
1793 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe,
1794                               bool pch_port)
1795 {
1796         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1797                                                                       pipe);
1798         enum i915_pipe pch_transcoder;
1799         int reg;
1800         u32 val;
1801
1802         if (HAS_PCH_LPT(dev_priv->dev))
1803                 pch_transcoder = TRANSCODER_A;
1804         else
1805                 pch_transcoder = pipe;
1806
1807         /*
1808          * A pipe without a PLL won't actually be able to drive bits from
1809          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1810          * need the check.
1811          */
1812         if (!HAS_PCH_SPLIT(dev_priv->dev))
1813                 assert_pll_enabled(dev_priv, pipe);
1814         else {
1815                 if (pch_port) {
1816                         /* if driving the PCH, we need FDI enabled */
1817                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1818                         assert_fdi_tx_pll_enabled(dev_priv,
1819                                                   (enum i915_pipe) cpu_transcoder);
1820                 }
1821                 /* FIXME: assert CPU port conditions for SNB+ */
1822         }
1823
1824         reg = PIPECONF(cpu_transcoder);
1825         val = I915_READ(reg);
1826         if (val & PIPECONF_ENABLE)
1827                 return;
1828
1829         I915_WRITE(reg, val | PIPECONF_ENABLE);
1830         intel_wait_for_vblank(dev_priv->dev, pipe);
1831 }
1832
1833 /**
1834  * intel_disable_pipe - disable a pipe, asserting requirements
1835  * @dev_priv: i915 private structure
1836  * @pipe: pipe to disable
1837  *
1838  * Disable @pipe, making sure that various hardware specific requirements
1839  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1840  *
1841  * @pipe should be %PIPE_A or %PIPE_B.
1842  *
1843  * Will wait until the pipe has shut down before returning.
1844  */
1845 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1846                                enum i915_pipe pipe)
1847 {
1848         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1849                                                                       pipe);
1850         int reg;
1851         u32 val;
1852
1853         /*
1854          * Make sure planes won't keep trying to pump pixels to us,
1855          * or we might hang the display.
1856          */
1857         assert_planes_disabled(dev_priv, pipe);
1858
1859         /* Don't disable pipe A or pipe A PLLs if needed */
1860         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1861                 return;
1862
1863         reg = PIPECONF(cpu_transcoder);
1864         val = I915_READ(reg);
1865         if ((val & PIPECONF_ENABLE) == 0)
1866                 return;
1867
1868         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1869         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1870 }
1871
1872 /*
1873  * Plane regs are double buffered, going from enabled->disabled needs a
1874  * trigger in order to latch.  The display address reg provides this.
1875  */
1876 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1877                                       enum plane plane)
1878 {
1879         if (dev_priv->info->gen >= 4)
1880                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1881         else
1882                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1883 }
1884
1885 /**
1886  * intel_enable_plane - enable a display plane on a given pipe
1887  * @dev_priv: i915 private structure
1888  * @plane: plane to enable
1889  * @pipe: pipe being fed
1890  *
1891  * Enable @plane on @pipe, making sure that @pipe is running first.
1892  */
1893 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1894                                enum plane plane, enum i915_pipe pipe)
1895 {
1896         int reg;
1897         u32 val;
1898
1899         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1900         assert_pipe_enabled(dev_priv, pipe);
1901
1902         reg = DSPCNTR(plane);
1903         val = I915_READ(reg);
1904         if (val & DISPLAY_PLANE_ENABLE)
1905                 return;
1906
1907         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1908         intel_flush_display_plane(dev_priv, plane);
1909         intel_wait_for_vblank(dev_priv->dev, pipe);
1910 }
1911
1912 /**
1913  * intel_disable_plane - disable a display plane
1914  * @dev_priv: i915 private structure
1915  * @plane: plane to disable
1916  * @pipe: pipe consuming the data
1917  *
1918  * Disable @plane; should be an independent operation.
1919  */
1920 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1921                                 enum plane plane, enum i915_pipe pipe)
1922 {
1923         int reg;
1924         u32 val;
1925
1926         reg = DSPCNTR(plane);
1927         val = I915_READ(reg);
1928         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1929                 return;
1930
1931         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1932         intel_flush_display_plane(dev_priv, plane);
1933         intel_wait_for_vblank(dev_priv->dev, pipe);
1934 }
1935
1936 int
1937 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1938                            struct drm_i915_gem_object *obj,
1939                            struct intel_ring_buffer *pipelined)
1940 {
1941         struct drm_i915_private *dev_priv = dev->dev_private;
1942         u32 alignment;
1943         int ret;
1944
1945         switch (obj->tiling_mode) {
1946         case I915_TILING_NONE:
1947                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1948                         alignment = 128 * 1024;
1949                 else if (INTEL_INFO(dev)->gen >= 4)
1950                         alignment = 4 * 1024;
1951                 else
1952                         alignment = 64 * 1024;
1953                 break;
1954         case I915_TILING_X:
1955                 /* pin() will align the object as required by fence */
1956                 alignment = 0;
1957                 break;
1958         case I915_TILING_Y:
1959                 /* FIXME: Is this true? */
1960                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1961                 return -EINVAL;
1962         default:
1963                 BUG();
1964         }
1965
1966         dev_priv->mm.interruptible = false;
1967         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1968         if (ret)
1969                 goto err_interruptible;
1970
1971         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1972          * fence, whereas 965+ only requires a fence if using
1973          * framebuffer compression.  For simplicity, we always install
1974          * a fence as the cost is not that onerous.
1975          */
1976         ret = i915_gem_object_get_fence(obj);
1977         if (ret)
1978                 goto err_unpin;
1979
1980         i915_gem_object_pin_fence(obj);
1981
1982         dev_priv->mm.interruptible = true;
1983         return 0;
1984
1985 err_unpin:
1986         i915_gem_object_unpin(obj);
1987 err_interruptible:
1988         dev_priv->mm.interruptible = true;
1989         return ret;
1990 }
1991
1992 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1993 {
1994         i915_gem_object_unpin_fence(obj);
1995         i915_gem_object_unpin(obj);
1996 }
1997
1998 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1999  * is assumed to be a power-of-two. */
2000 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2001                                              unsigned int tiling_mode,
2002                                              unsigned int cpp,
2003                                              unsigned int pitch)
2004 {
2005         if (tiling_mode != I915_TILING_NONE) {
2006                 unsigned int tile_rows, tiles;
2007
2008                 tile_rows = *y / 8;
2009                 *y %= 8;
2010
2011                 tiles = *x / (512/cpp);
2012                 *x %= 512/cpp;
2013
2014                 return tile_rows * pitch * 8 + tiles * 4096;
2015         } else {
2016                 unsigned int offset;
2017
2018                 offset = *y * pitch + *x * cpp;
2019                 *y = 0;
2020                 *x = (offset & 4095) / cpp;
2021                 return offset & -4096;
2022         }
2023 }
2024
2025 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2026                              int x, int y)
2027 {
2028         struct drm_device *dev = crtc->dev;
2029         struct drm_i915_private *dev_priv = dev->dev_private;
2030         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2031         struct intel_framebuffer *intel_fb;
2032         struct drm_i915_gem_object *obj;
2033         int plane = intel_crtc->plane;
2034         unsigned long linear_offset;
2035         u32 dspcntr;
2036         u32 reg;
2037
2038         switch (plane) {
2039         case 0:
2040         case 1:
2041                 break;
2042         default:
2043                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2044                 return -EINVAL;
2045         }
2046
2047         intel_fb = to_intel_framebuffer(fb);
2048         obj = intel_fb->obj;
2049
2050         reg = DSPCNTR(plane);
2051         dspcntr = I915_READ(reg);
2052         /* Mask out pixel format bits in case we change it */
2053         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2054         switch (fb->pixel_format) {
2055         case DRM_FORMAT_C8:
2056                 dspcntr |= DISPPLANE_8BPP;
2057                 break;
2058         case DRM_FORMAT_XRGB1555:
2059         case DRM_FORMAT_ARGB1555:
2060                 dspcntr |= DISPPLANE_BGRX555;
2061                 break;
2062         case DRM_FORMAT_RGB565:
2063                 dspcntr |= DISPPLANE_BGRX565;
2064                 break;
2065         case DRM_FORMAT_XRGB8888:
2066         case DRM_FORMAT_ARGB8888:
2067                 dspcntr |= DISPPLANE_BGRX888;
2068                 break;
2069         case DRM_FORMAT_XBGR8888:
2070         case DRM_FORMAT_ABGR8888:
2071                 dspcntr |= DISPPLANE_RGBX888;
2072                 break;
2073         case DRM_FORMAT_XRGB2101010:
2074         case DRM_FORMAT_ARGB2101010:
2075                 dspcntr |= DISPPLANE_BGRX101010;
2076                 break;
2077         case DRM_FORMAT_XBGR2101010:
2078         case DRM_FORMAT_ABGR2101010:
2079                 dspcntr |= DISPPLANE_RGBX101010;
2080                 break;
2081         default:
2082                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2083                 return -EINVAL;
2084         }
2085
2086         if (INTEL_INFO(dev)->gen >= 4) {
2087                 if (obj->tiling_mode != I915_TILING_NONE)
2088                         dspcntr |= DISPPLANE_TILED;
2089                 else
2090                         dspcntr &= ~DISPPLANE_TILED;
2091         }
2092
2093         I915_WRITE(reg, dspcntr);
2094
2095         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2096
2097         if (INTEL_INFO(dev)->gen >= 4) {
2098                 intel_crtc->dspaddr_offset =
2099                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2100                                                        fb->bits_per_pixel / 8,
2101                                                        fb->pitches[0]);
2102                 linear_offset -= intel_crtc->dspaddr_offset;
2103         } else {
2104                 intel_crtc->dspaddr_offset = linear_offset;
2105         }
2106
2107         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2108                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2109         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2110         if (INTEL_INFO(dev)->gen >= 4) {
2111                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2112                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2113                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2114                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2115         } else
2116                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2117         POSTING_READ(reg);
2118
2119         return 0;
2120 }
2121
2122 static int ironlake_update_plane(struct drm_crtc *crtc,
2123                                  struct drm_framebuffer *fb, int x, int y)
2124 {
2125         struct drm_device *dev = crtc->dev;
2126         struct drm_i915_private *dev_priv = dev->dev_private;
2127         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2128         struct intel_framebuffer *intel_fb;
2129         struct drm_i915_gem_object *obj;
2130         int plane = intel_crtc->plane;
2131         unsigned long linear_offset;
2132         u32 dspcntr;
2133         u32 reg;
2134
2135         switch (plane) {
2136         case 0:
2137         case 1:
2138         case 2:
2139                 break;
2140         default:
2141                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2142                 return -EINVAL;
2143         }
2144
2145         intel_fb = to_intel_framebuffer(fb);
2146         obj = intel_fb->obj;
2147
2148         reg = DSPCNTR(plane);
2149         dspcntr = I915_READ(reg);
2150         /* Mask out pixel format bits in case we change it */
2151         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2152         switch (fb->pixel_format) {
2153         case DRM_FORMAT_C8:
2154                 dspcntr |= DISPPLANE_8BPP;
2155                 break;
2156         case DRM_FORMAT_RGB565:
2157                 dspcntr |= DISPPLANE_BGRX565;
2158                 break;
2159         case DRM_FORMAT_XRGB8888:
2160         case DRM_FORMAT_ARGB8888:
2161                 dspcntr |= DISPPLANE_BGRX888;
2162                 break;
2163         case DRM_FORMAT_XBGR8888:
2164         case DRM_FORMAT_ABGR8888:
2165                 dspcntr |= DISPPLANE_RGBX888;
2166                 break;
2167         case DRM_FORMAT_XRGB2101010:
2168         case DRM_FORMAT_ARGB2101010:
2169                 dspcntr |= DISPPLANE_BGRX101010;
2170                 break;
2171         case DRM_FORMAT_XBGR2101010:
2172         case DRM_FORMAT_ABGR2101010:
2173                 dspcntr |= DISPPLANE_RGBX101010;
2174                 break;
2175         default:
2176                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2177                 return -EINVAL;
2178         }
2179
2180         if (obj->tiling_mode != I915_TILING_NONE)
2181                 dspcntr |= DISPPLANE_TILED;
2182         else
2183                 dspcntr &= ~DISPPLANE_TILED;
2184
2185         /* must disable */
2186         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2187
2188         I915_WRITE(reg, dspcntr);
2189
2190         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2191         intel_crtc->dspaddr_offset =
2192                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2193                                                fb->bits_per_pixel / 8,
2194                                                fb->pitches[0]);
2195         linear_offset -= intel_crtc->dspaddr_offset;
2196
2197         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2198                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2199         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2200         I915_MODIFY_DISPBASE(DSPSURF(plane),
2201                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2202         if (IS_HASWELL(dev)) {
2203                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2204         } else {
2205                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2206                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2207         }
2208         POSTING_READ(reg);
2209
2210         return 0;
2211 }
2212
2213 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2214 static int
2215 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2216                            int x, int y, enum mode_set_atomic state)
2217 {
2218         struct drm_device *dev = crtc->dev;
2219         struct drm_i915_private *dev_priv = dev->dev_private;
2220
2221         if (dev_priv->display.disable_fbc)
2222                 dev_priv->display.disable_fbc(dev);
2223         intel_increase_pllclock(crtc);
2224
2225         return dev_priv->display.update_plane(crtc, fb, x, y);
2226 }
2227
2228 static int
2229 intel_finish_fb(struct drm_framebuffer *old_fb)
2230 {
2231         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2232         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2233         bool was_interruptible = dev_priv->mm.interruptible;
2234         int ret;
2235
2236         /* Big Hammer, we also need to ensure that any pending
2237          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2238          * current scanout is retired before unpinning the old
2239          * framebuffer.
2240          *
2241          * This should only fail upon a hung GPU, in which case we
2242          * can safely continue.
2243          */
2244         dev_priv->mm.interruptible = false;
2245         ret = i915_gem_object_finish_gpu(obj);
2246         dev_priv->mm.interruptible = was_interruptible;
2247
2248         return ret;
2249 }
2250
2251 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2252 {
2253         struct drm_device *dev = crtc->dev;
2254         struct drm_i915_master_private *master_priv;
2255         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2256
2257         if (!dev->primary->master)
2258                 return;
2259
2260         master_priv = dev->primary->master->driver_priv;
2261         if (!master_priv->sarea_priv)
2262                 return;
2263
2264         switch (intel_crtc->pipe) {
2265         case 0:
2266                 master_priv->sarea_priv->pipeA_x = x;
2267                 master_priv->sarea_priv->pipeA_y = y;
2268                 break;
2269         case 1:
2270                 master_priv->sarea_priv->pipeB_x = x;
2271                 master_priv->sarea_priv->pipeB_y = y;
2272                 break;
2273         default:
2274                 break;
2275         }
2276 }
2277
2278 static int
2279 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2280                     struct drm_framebuffer *fb)
2281 {
2282         struct drm_device *dev = crtc->dev;
2283         struct drm_i915_private *dev_priv = dev->dev_private;
2284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2285         struct drm_framebuffer *old_fb;
2286         int ret;
2287
2288         /* no fb bound */
2289         if (!fb) {
2290                 DRM_ERROR("No FB bound\n");
2291                 return 0;
2292         }
2293
2294         if(intel_crtc->plane > dev_priv->num_pipe) {
2295                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2296                                 intel_crtc->plane,
2297                                 dev_priv->num_pipe);
2298                 return -EINVAL;
2299         }
2300
2301         mutex_lock(&dev->struct_mutex);
2302         ret = intel_pin_and_fence_fb_obj(dev,
2303                                          to_intel_framebuffer(fb)->obj,
2304                                          NULL);
2305         if (ret != 0) {
2306                 mutex_unlock(&dev->struct_mutex);
2307                 DRM_ERROR("pin & fence failed\n");
2308                 return ret;
2309         }
2310
2311         if (crtc->fb)
2312                 intel_finish_fb(crtc->fb);
2313
2314         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2315         if (ret) {
2316                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2317                 mutex_unlock(&dev->struct_mutex);
2318                 DRM_ERROR("failed to update base address\n");
2319                 return ret;
2320         }
2321
2322         old_fb = crtc->fb;
2323         crtc->fb = fb;
2324         crtc->x = x;
2325         crtc->y = y;
2326
2327         if (old_fb) {
2328                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2329                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2330         }
2331
2332         intel_update_fbc(dev);
2333         mutex_unlock(&dev->struct_mutex);
2334
2335         intel_crtc_update_sarea_pos(crtc, x, y);
2336
2337         return 0;
2338 }
2339
2340 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2341 {
2342         struct drm_device *dev = crtc->dev;
2343         struct drm_i915_private *dev_priv = dev->dev_private;
2344         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2345         int pipe = intel_crtc->pipe;
2346         u32 reg, temp;
2347
2348         /* enable normal train */
2349         reg = FDI_TX_CTL(pipe);
2350         temp = I915_READ(reg);
2351         if (IS_IVYBRIDGE(dev)) {
2352                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2353                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2354         } else {
2355                 temp &= ~FDI_LINK_TRAIN_NONE;
2356                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2357         }
2358         I915_WRITE(reg, temp);
2359
2360         reg = FDI_RX_CTL(pipe);
2361         temp = I915_READ(reg);
2362         if (HAS_PCH_CPT(dev)) {
2363                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2364                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2365         } else {
2366                 temp &= ~FDI_LINK_TRAIN_NONE;
2367                 temp |= FDI_LINK_TRAIN_NONE;
2368         }
2369         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2370
2371         /* wait one idle pattern time */
2372         POSTING_READ(reg);
2373         udelay(1000);
2374
2375         /* IVB wants error correction enabled */
2376         if (IS_IVYBRIDGE(dev))
2377                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2378                            FDI_FE_ERRC_ENABLE);
2379 }
2380
2381 static void ivb_modeset_global_resources(struct drm_device *dev)
2382 {
2383         struct drm_i915_private *dev_priv = dev->dev_private;
2384         struct intel_crtc *pipe_B_crtc =
2385                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2386         struct intel_crtc *pipe_C_crtc =
2387                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2388         uint32_t temp;
2389
2390         /* When everything is off disable fdi C so that we could enable fdi B
2391          * with all lanes. XXX: This misses the case where a pipe is not using
2392          * any pch resources and so doesn't need any fdi lanes. */
2393         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2394                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2395                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2396
2397                 temp = I915_READ(SOUTH_CHICKEN1);
2398                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2399                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2400                 I915_WRITE(SOUTH_CHICKEN1, temp);
2401         }
2402 }
2403
2404 /* The FDI link training functions for ILK/Ibexpeak. */
2405 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2406 {
2407         struct drm_device *dev = crtc->dev;
2408         struct drm_i915_private *dev_priv = dev->dev_private;
2409         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2410         int pipe = intel_crtc->pipe;
2411         int plane = intel_crtc->plane;
2412         u32 reg, temp, tries;
2413
2414         /* FDI needs bits from pipe & plane first */
2415         assert_pipe_enabled(dev_priv, pipe);
2416         assert_plane_enabled(dev_priv, plane);
2417
2418         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2419            for train result */
2420         reg = FDI_RX_IMR(pipe);
2421         temp = I915_READ(reg);
2422         temp &= ~FDI_RX_SYMBOL_LOCK;
2423         temp &= ~FDI_RX_BIT_LOCK;
2424         I915_WRITE(reg, temp);
2425         I915_READ(reg);
2426         udelay(150);
2427
2428         /* enable CPU FDI TX and PCH FDI RX */
2429         reg = FDI_TX_CTL(pipe);
2430         temp = I915_READ(reg);
2431         temp &= ~(7 << 19);
2432         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2433         temp &= ~FDI_LINK_TRAIN_NONE;
2434         temp |= FDI_LINK_TRAIN_PATTERN_1;
2435         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2436
2437         reg = FDI_RX_CTL(pipe);
2438         temp = I915_READ(reg);
2439         temp &= ~FDI_LINK_TRAIN_NONE;
2440         temp |= FDI_LINK_TRAIN_PATTERN_1;
2441         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2442
2443         POSTING_READ(reg);
2444         udelay(150);
2445
2446         /* Ironlake workaround, enable clock pointer after FDI enable*/
2447         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2448         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2449                    FDI_RX_PHASE_SYNC_POINTER_EN);
2450
2451         reg = FDI_RX_IIR(pipe);
2452         for (tries = 0; tries < 5; tries++) {
2453                 temp = I915_READ(reg);
2454                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2455
2456                 if ((temp & FDI_RX_BIT_LOCK)) {
2457                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2458                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2459                         break;
2460                 }
2461         }
2462         if (tries == 5)
2463                 DRM_ERROR("FDI train 1 fail!\n");
2464
2465         /* Train 2 */
2466         reg = FDI_TX_CTL(pipe);
2467         temp = I915_READ(reg);
2468         temp &= ~FDI_LINK_TRAIN_NONE;
2469         temp |= FDI_LINK_TRAIN_PATTERN_2;
2470         I915_WRITE(reg, temp);
2471
2472         reg = FDI_RX_CTL(pipe);
2473         temp = I915_READ(reg);
2474         temp &= ~FDI_LINK_TRAIN_NONE;
2475         temp |= FDI_LINK_TRAIN_PATTERN_2;
2476         I915_WRITE(reg, temp);
2477
2478         POSTING_READ(reg);
2479         udelay(150);
2480
2481         reg = FDI_RX_IIR(pipe);
2482         for (tries = 0; tries < 5; tries++) {
2483                 temp = I915_READ(reg);
2484                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2485
2486                 if (temp & FDI_RX_SYMBOL_LOCK) {
2487                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2488                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2489                         break;
2490                 }
2491         }
2492         if (tries == 5)
2493                 DRM_ERROR("FDI train 2 fail!\n");
2494
2495         DRM_DEBUG_KMS("FDI train done\n");
2496
2497 }
2498
2499 static const int snb_b_fdi_train_param[] = {
2500         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2501         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2502         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2503         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2504 };
2505
2506 /* The FDI link training functions for SNB/Cougarpoint. */
2507 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2508 {
2509         struct drm_device *dev = crtc->dev;
2510         struct drm_i915_private *dev_priv = dev->dev_private;
2511         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2512         int pipe = intel_crtc->pipe;
2513         u32 reg, temp, i, retry;
2514
2515         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2516            for train result */
2517         reg = FDI_RX_IMR(pipe);
2518         temp = I915_READ(reg);
2519         temp &= ~FDI_RX_SYMBOL_LOCK;
2520         temp &= ~FDI_RX_BIT_LOCK;
2521         I915_WRITE(reg, temp);
2522
2523         POSTING_READ(reg);
2524         udelay(150);
2525
2526         /* enable CPU FDI TX and PCH FDI RX */
2527         reg = FDI_TX_CTL(pipe);
2528         temp = I915_READ(reg);
2529         temp &= ~(7 << 19);
2530         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2531         temp &= ~FDI_LINK_TRAIN_NONE;
2532         temp |= FDI_LINK_TRAIN_PATTERN_1;
2533         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2534         /* SNB-B */
2535         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2536         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2537
2538         I915_WRITE(FDI_RX_MISC(pipe),
2539                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2540
2541         reg = FDI_RX_CTL(pipe);
2542         temp = I915_READ(reg);
2543         if (HAS_PCH_CPT(dev)) {
2544                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2545                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2546         } else {
2547                 temp &= ~FDI_LINK_TRAIN_NONE;
2548                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2549         }
2550         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2551
2552         POSTING_READ(reg);
2553         udelay(150);
2554
2555         for (i = 0; i < 4; i++) {
2556                 reg = FDI_TX_CTL(pipe);
2557                 temp = I915_READ(reg);
2558                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2559                 temp |= snb_b_fdi_train_param[i];
2560                 I915_WRITE(reg, temp);
2561
2562                 POSTING_READ(reg);
2563                 udelay(500);
2564
2565                 for (retry = 0; retry < 5; retry++) {
2566                         reg = FDI_RX_IIR(pipe);
2567                         temp = I915_READ(reg);
2568                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2569                         if (temp & FDI_RX_BIT_LOCK) {
2570                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2571                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2572                                 break;
2573                         }
2574                         udelay(50);
2575                 }
2576                 if (retry < 5)
2577                         break;
2578         }
2579         if (i == 4)
2580                 DRM_ERROR("FDI train 1 fail!\n");
2581
2582         /* Train 2 */
2583         reg = FDI_TX_CTL(pipe);
2584         temp = I915_READ(reg);
2585         temp &= ~FDI_LINK_TRAIN_NONE;
2586         temp |= FDI_LINK_TRAIN_PATTERN_2;
2587         if (IS_GEN6(dev)) {
2588                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2589                 /* SNB-B */
2590                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2591         }
2592         I915_WRITE(reg, temp);
2593
2594         reg = FDI_RX_CTL(pipe);
2595         temp = I915_READ(reg);
2596         if (HAS_PCH_CPT(dev)) {
2597                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2598                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2599         } else {
2600                 temp &= ~FDI_LINK_TRAIN_NONE;
2601                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2602         }
2603         I915_WRITE(reg, temp);
2604
2605         POSTING_READ(reg);
2606         udelay(150);
2607
2608         for (i = 0; i < 4; i++) {
2609                 reg = FDI_TX_CTL(pipe);
2610                 temp = I915_READ(reg);
2611                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2612                 temp |= snb_b_fdi_train_param[i];
2613                 I915_WRITE(reg, temp);
2614
2615                 POSTING_READ(reg);
2616                 udelay(500);
2617
2618                 for (retry = 0; retry < 5; retry++) {
2619                         reg = FDI_RX_IIR(pipe);
2620                         temp = I915_READ(reg);
2621                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2622                         if (temp & FDI_RX_SYMBOL_LOCK) {
2623                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2624                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2625                                 break;
2626                         }
2627                         udelay(50);
2628                 }
2629                 if (retry < 5)
2630                         break;
2631         }
2632         if (i == 4)
2633                 DRM_ERROR("FDI train 2 fail!\n");
2634
2635         DRM_DEBUG_KMS("FDI train done.\n");
2636 }
2637
2638 /* Manual link training for Ivy Bridge A0 parts */
2639 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2640 {
2641         struct drm_device *dev = crtc->dev;
2642         struct drm_i915_private *dev_priv = dev->dev_private;
2643         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2644         int pipe = intel_crtc->pipe;
2645         u32 reg, temp, i;
2646
2647         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2648            for train result */
2649         reg = FDI_RX_IMR(pipe);
2650         temp = I915_READ(reg);
2651         temp &= ~FDI_RX_SYMBOL_LOCK;
2652         temp &= ~FDI_RX_BIT_LOCK;
2653         I915_WRITE(reg, temp);
2654
2655         POSTING_READ(reg);
2656         udelay(150);
2657
2658         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2659                       I915_READ(FDI_RX_IIR(pipe)));
2660
2661         /* enable CPU FDI TX and PCH FDI RX */
2662         reg = FDI_TX_CTL(pipe);
2663         temp = I915_READ(reg);
2664         temp &= ~(7 << 19);
2665         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2666         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2667         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2668         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2669         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2670         temp |= FDI_COMPOSITE_SYNC;
2671         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2672
2673         I915_WRITE(FDI_RX_MISC(pipe),
2674                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2675
2676         reg = FDI_RX_CTL(pipe);
2677         temp = I915_READ(reg);
2678         temp &= ~FDI_LINK_TRAIN_AUTO;
2679         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2680         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2681         temp |= FDI_COMPOSITE_SYNC;
2682         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2683
2684         POSTING_READ(reg);
2685         udelay(150);
2686
2687         for (i = 0; i < 4; i++) {
2688                 reg = FDI_TX_CTL(pipe);
2689                 temp = I915_READ(reg);
2690                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2691                 temp |= snb_b_fdi_train_param[i];
2692                 I915_WRITE(reg, temp);
2693
2694                 POSTING_READ(reg);
2695                 udelay(500);
2696
2697                 reg = FDI_RX_IIR(pipe);
2698                 temp = I915_READ(reg);
2699                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2700
2701                 if (temp & FDI_RX_BIT_LOCK ||
2702                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2703                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2704                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2705                         break;
2706                 }
2707         }
2708         if (i == 4)
2709                 DRM_ERROR("FDI train 1 fail!\n");
2710
2711         /* Train 2 */
2712         reg = FDI_TX_CTL(pipe);
2713         temp = I915_READ(reg);
2714         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2715         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2716         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2717         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2718         I915_WRITE(reg, temp);
2719
2720         reg = FDI_RX_CTL(pipe);
2721         temp = I915_READ(reg);
2722         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2723         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2724         I915_WRITE(reg, temp);
2725
2726         POSTING_READ(reg);
2727         udelay(150);
2728
2729         for (i = 0; i < 4; i++) {
2730                 reg = FDI_TX_CTL(pipe);
2731                 temp = I915_READ(reg);
2732                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2733                 temp |= snb_b_fdi_train_param[i];
2734                 I915_WRITE(reg, temp);
2735
2736                 POSTING_READ(reg);
2737                 udelay(500);
2738
2739                 reg = FDI_RX_IIR(pipe);
2740                 temp = I915_READ(reg);
2741                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2742
2743                 if (temp & FDI_RX_SYMBOL_LOCK) {
2744                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2745                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2746                         break;
2747                 }
2748         }
2749         if (i == 4)
2750                 DRM_ERROR("FDI train 2 fail!\n");
2751
2752         DRM_DEBUG_KMS("FDI train done.\n");
2753 }
2754
2755 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2756 {
2757         struct drm_device *dev = intel_crtc->base.dev;
2758         struct drm_i915_private *dev_priv = dev->dev_private;
2759         int pipe = intel_crtc->pipe;
2760         u32 reg, temp;
2761
2762
2763         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2764         reg = FDI_RX_CTL(pipe);
2765         temp = I915_READ(reg);
2766         temp &= ~((0x7 << 19) | (0x7 << 16));
2767         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2768         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2769         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2770
2771         POSTING_READ(reg);
2772         udelay(200);
2773
2774         /* Switch from Rawclk to PCDclk */
2775         temp = I915_READ(reg);
2776         I915_WRITE(reg, temp | FDI_PCDCLK);
2777
2778         POSTING_READ(reg);
2779         udelay(200);
2780
2781         /* Enable CPU FDI TX PLL, always on for Ironlake */
2782         reg = FDI_TX_CTL(pipe);
2783         temp = I915_READ(reg);
2784         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2785                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2786
2787                 POSTING_READ(reg);
2788                 udelay(100);
2789         }
2790 }
2791
2792 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2793 {
2794         struct drm_device *dev = intel_crtc->base.dev;
2795         struct drm_i915_private *dev_priv = dev->dev_private;
2796         int pipe = intel_crtc->pipe;
2797         u32 reg, temp;
2798
2799         /* Switch from PCDclk to Rawclk */
2800         reg = FDI_RX_CTL(pipe);
2801         temp = I915_READ(reg);
2802         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2803
2804         /* Disable CPU FDI TX PLL */
2805         reg = FDI_TX_CTL(pipe);
2806         temp = I915_READ(reg);
2807         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2808
2809         POSTING_READ(reg);
2810         udelay(100);
2811
2812         reg = FDI_RX_CTL(pipe);
2813         temp = I915_READ(reg);
2814         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2815
2816         /* Wait for the clocks to turn off. */
2817         POSTING_READ(reg);
2818         udelay(100);
2819 }
2820
2821 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2822 {
2823         struct drm_device *dev = crtc->dev;
2824         struct drm_i915_private *dev_priv = dev->dev_private;
2825         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2826         int pipe = intel_crtc->pipe;
2827         u32 reg, temp;
2828
2829         /* disable CPU FDI tx and PCH FDI rx */
2830         reg = FDI_TX_CTL(pipe);
2831         temp = I915_READ(reg);
2832         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2833         POSTING_READ(reg);
2834
2835         reg = FDI_RX_CTL(pipe);
2836         temp = I915_READ(reg);
2837         temp &= ~(0x7 << 16);
2838         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2839         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2840
2841         POSTING_READ(reg);
2842         udelay(100);
2843
2844         /* Ironlake workaround, disable clock pointer after downing FDI */
2845         if (HAS_PCH_IBX(dev)) {
2846                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2847         }
2848
2849         /* still set train pattern 1 */
2850         reg = FDI_TX_CTL(pipe);
2851         temp = I915_READ(reg);
2852         temp &= ~FDI_LINK_TRAIN_NONE;
2853         temp |= FDI_LINK_TRAIN_PATTERN_1;
2854         I915_WRITE(reg, temp);
2855
2856         reg = FDI_RX_CTL(pipe);
2857         temp = I915_READ(reg);
2858         if (HAS_PCH_CPT(dev)) {
2859                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2860                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2861         } else {
2862                 temp &= ~FDI_LINK_TRAIN_NONE;
2863                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2864         }
2865         /* BPC in FDI rx is consistent with that in PIPECONF */
2866         temp &= ~(0x07 << 16);
2867         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2868         I915_WRITE(reg, temp);
2869
2870         POSTING_READ(reg);
2871         udelay(100);
2872 }
2873
2874 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2875 {
2876         struct drm_device *dev = crtc->dev;
2877         struct drm_i915_private *dev_priv = dev->dev_private;
2878         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2879         bool pending;
2880
2881         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2882             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2883                 return false;
2884
2885         lockmgr(&dev->event_lock, LK_EXCLUSIVE);
2886         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2887         lockmgr(&dev->event_lock, LK_RELEASE);
2888
2889         return pending;
2890 }
2891
2892 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2893 {
2894         struct drm_device *dev = crtc->dev;
2895         struct drm_i915_private *dev_priv = dev->dev_private;
2896
2897         if (crtc->fb == NULL)
2898                 return;
2899
2900         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2901
2902         wait_event(dev_priv->pending_flip_queue,
2903                    !intel_crtc_has_pending_flip(crtc));
2904
2905         mutex_lock(&dev->struct_mutex);
2906         intel_finish_fb(crtc->fb);
2907         mutex_unlock(&dev->struct_mutex);
2908 }
2909
2910 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2911 {
2912         struct drm_device *dev = crtc->dev;
2913         struct intel_encoder *intel_encoder;
2914
2915         /*
2916          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2917          * must be driven by its own crtc; no sharing is possible.
2918          */
2919         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2920                 switch (intel_encoder->type) {
2921                 case INTEL_OUTPUT_EDP:
2922                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2923                                 return false;
2924                         continue;
2925                 }
2926         }
2927
2928         return true;
2929 }
2930
2931 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2932 {
2933         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2934 }
2935
2936 /* Program iCLKIP clock to the desired frequency */
2937 static void lpt_program_iclkip(struct drm_crtc *crtc)
2938 {
2939         struct drm_device *dev = crtc->dev;
2940         struct drm_i915_private *dev_priv = dev->dev_private;
2941         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2942         u32 temp;
2943
2944         mutex_lock(&dev_priv->dpio_lock);
2945
2946         /* It is necessary to ungate the pixclk gate prior to programming
2947          * the divisors, and gate it back when it is done.
2948          */
2949         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2950
2951         /* Disable SSCCTL */
2952         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2953                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2954                                 SBI_SSCCTL_DISABLE,
2955                         SBI_ICLK);
2956
2957         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2958         if (crtc->mode.clock == 20000) {
2959                 auxdiv = 1;
2960                 divsel = 0x41;
2961                 phaseinc = 0x20;
2962         } else {
2963                 /* The iCLK virtual clock root frequency is in MHz,
2964                  * but the crtc->mode.clock in in KHz. To get the divisors,
2965                  * it is necessary to divide one by another, so we
2966                  * convert the virtual clock precision to KHz here for higher
2967                  * precision.
2968                  */
2969                 u32 iclk_virtual_root_freq = 172800 * 1000;
2970                 u32 iclk_pi_range = 64;
2971                 u32 desired_divisor, msb_divisor_value, pi_value;
2972
2973                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2974                 msb_divisor_value = desired_divisor / iclk_pi_range;
2975                 pi_value = desired_divisor % iclk_pi_range;
2976
2977                 auxdiv = 0;
2978                 divsel = msb_divisor_value - 2;
2979                 phaseinc = pi_value;
2980         }
2981
2982         /* This should not happen with any sane values */
2983         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2984                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2985         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2986                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2987
2988         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2989                         crtc->mode.clock,
2990                         auxdiv,
2991                         divsel,
2992                         phasedir,
2993                         phaseinc);
2994
2995         /* Program SSCDIVINTPHASE6 */
2996         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2997         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2998         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2999         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3000         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3001         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3002         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3003         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3004
3005         /* Program SSCAUXDIV */
3006         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3007         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3008         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3009         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3010
3011         /* Enable modulator and associated divider */
3012         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3013         temp &= ~SBI_SSCCTL_DISABLE;
3014         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3015
3016         /* Wait for initialization time */
3017         udelay(24);
3018
3019         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3020
3021         mutex_unlock(&dev_priv->dpio_lock);
3022 }
3023
3024 /*
3025  * Enable PCH resources required for PCH ports:
3026  *   - PCH PLLs
3027  *   - FDI training & RX/TX
3028  *   - update transcoder timings
3029  *   - DP transcoding bits
3030  *   - transcoder
3031  */
3032 static void ironlake_pch_enable(struct drm_crtc *crtc)
3033 {
3034         struct drm_device *dev = crtc->dev;
3035         struct drm_i915_private *dev_priv = dev->dev_private;
3036         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3037         int pipe = intel_crtc->pipe;
3038         u32 reg, temp;
3039
3040         assert_transcoder_disabled(dev_priv, pipe);
3041
3042         /* Write the TU size bits before fdi link training, so that error
3043          * detection works. */
3044         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3045                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3046
3047         /* For PCH output, training FDI link */
3048         dev_priv->display.fdi_link_train(crtc);
3049
3050         /* XXX: pch pll's can be enabled any time before we enable the PCH
3051          * transcoder, and we actually should do this to not upset any PCH
3052          * transcoder that already use the clock when we share it.
3053          *
3054          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3055          * unconditionally resets the pll - we need that to have the right LVDS
3056          * enable sequence. */
3057         ironlake_enable_pch_pll(intel_crtc);
3058
3059         if (HAS_PCH_CPT(dev)) {
3060                 u32 sel;
3061
3062                 temp = I915_READ(PCH_DPLL_SEL);
3063                 switch (pipe) {
3064                 default:
3065                 case 0:
3066                         temp |= TRANSA_DPLL_ENABLE;
3067                         sel = TRANSA_DPLLB_SEL;
3068                         break;
3069                 case 1:
3070                         temp |= TRANSB_DPLL_ENABLE;
3071                         sel = TRANSB_DPLLB_SEL;
3072                         break;
3073                 case 2:
3074                         temp |= TRANSC_DPLL_ENABLE;
3075                         sel = TRANSC_DPLLB_SEL;
3076                         break;
3077                 }
3078                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3079                         temp |= sel;
3080                 else
3081                         temp &= ~sel;
3082                 I915_WRITE(PCH_DPLL_SEL, temp);
3083         }
3084
3085         /* set transcoder timing, panel must allow it */
3086         assert_panel_unlocked(dev_priv, pipe);
3087         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3088         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3089         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3090
3091         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3092         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3093         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3094         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3095
3096         intel_fdi_normal_train(crtc);
3097
3098         /* For PCH DP, enable TRANS_DP_CTL */
3099         if (HAS_PCH_CPT(dev) &&
3100             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3101              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3102                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3103                 reg = TRANS_DP_CTL(pipe);
3104                 temp = I915_READ(reg);
3105                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3106                           TRANS_DP_SYNC_MASK |
3107                           TRANS_DP_BPC_MASK);
3108                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3109                          TRANS_DP_ENH_FRAMING);
3110                 temp |= bpc << 9; /* same format but at 11:9 */
3111
3112                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3113                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3114                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3115                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3116
3117                 switch (intel_trans_dp_port_sel(crtc)) {
3118                 case PCH_DP_B:
3119                         temp |= TRANS_DP_PORT_SEL_B;
3120                         break;
3121                 case PCH_DP_C:
3122                         temp |= TRANS_DP_PORT_SEL_C;
3123                         break;
3124                 case PCH_DP_D:
3125                         temp |= TRANS_DP_PORT_SEL_D;
3126                         break;
3127                 default:
3128                         BUG();
3129                 }
3130
3131                 I915_WRITE(reg, temp);
3132         }
3133
3134         ironlake_enable_pch_transcoder(dev_priv, pipe);
3135 }
3136
3137 static void lpt_pch_enable(struct drm_crtc *crtc)
3138 {
3139         struct drm_device *dev = crtc->dev;
3140         struct drm_i915_private *dev_priv = dev->dev_private;
3141         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3142         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3143
3144         assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3145
3146         lpt_program_iclkip(crtc);
3147
3148         /* Set transcoder timing. */
3149         I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3150         I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3151         I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));
3152
3153         I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3154         I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3155         I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
3156         I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3157
3158         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3159 }
3160
3161 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3162 {
3163         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3164
3165         if (pll == NULL)
3166                 return;
3167
3168         if (pll->refcount == 0) {
3169                 WARN(1, "bad PCH PLL refcount\n");
3170                 return;
3171         }
3172
3173         --pll->refcount;
3174         intel_crtc->pch_pll = NULL;
3175 }
3176
3177 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3178 {
3179         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3180         struct intel_pch_pll *pll;
3181         int i;
3182
3183         pll = intel_crtc->pch_pll;
3184         if (pll) {
3185                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3186                               intel_crtc->base.base.id, pll->pll_reg);
3187                 goto prepare;
3188         }
3189
3190         if (HAS_PCH_IBX(dev_priv->dev)) {
3191                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3192                 i = intel_crtc->pipe;
3193                 pll = &dev_priv->pch_plls[i];
3194
3195                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3196                               intel_crtc->base.base.id, pll->pll_reg);
3197
3198                 goto found;
3199         }
3200
3201         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3202                 pll = &dev_priv->pch_plls[i];
3203
3204                 /* Only want to check enabled timings first */
3205                 if (pll->refcount == 0)
3206                         continue;
3207
3208                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3209                     fp == I915_READ(pll->fp0_reg)) {
3210                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3211                                       intel_crtc->base.base.id,
3212                                       pll->pll_reg, pll->refcount, pll->active);
3213
3214                         goto found;
3215                 }
3216         }
3217
3218         /* Ok no matching timings, maybe there's a free one? */
3219         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3220                 pll = &dev_priv->pch_plls[i];
3221                 if (pll->refcount == 0) {
3222                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3223                                       intel_crtc->base.base.id, pll->pll_reg);
3224                         goto found;
3225                 }
3226         }
3227
3228         return NULL;
3229
3230 found:
3231         intel_crtc->pch_pll = pll;
3232         pll->refcount++;
3233         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3234 prepare: /* separate function? */
3235         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3236
3237         /* Wait for the clocks to stabilize before rewriting the regs */
3238         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3239         POSTING_READ(pll->pll_reg);
3240         udelay(150);
3241
3242         I915_WRITE(pll->fp0_reg, fp);
3243         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3244         pll->on = false;
3245         return pll;
3246 }
3247
3248 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3249 {
3250         struct drm_i915_private *dev_priv = dev->dev_private;
3251         int dslreg = PIPEDSL(pipe);
3252         u32 temp;
3253
3254         temp = I915_READ(dslreg);
3255         udelay(500);
3256         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3257                 if (wait_for(I915_READ(dslreg) != temp, 5))
3258                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3259         }
3260 }
3261
3262 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3263 {
3264         struct drm_device *dev = crtc->dev;
3265         struct drm_i915_private *dev_priv = dev->dev_private;
3266         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3267         struct intel_encoder *encoder;
3268         int pipe = intel_crtc->pipe;
3269         int plane = intel_crtc->plane;
3270         u32 temp;
3271         bool is_pch_port;
3272
3273         WARN_ON(!crtc->enabled);
3274
3275         if (intel_crtc->active)
3276                 return;
3277
3278         intel_crtc->active = true;
3279         intel_update_watermarks(dev);
3280
3281         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3282                 temp = I915_READ(PCH_LVDS);
3283                 if ((temp & LVDS_PORT_EN) == 0)
3284                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3285         }
3286
3287         is_pch_port = ironlake_crtc_driving_pch(crtc);
3288
3289         if (is_pch_port) {
3290                 /* Note: FDI PLL enabling _must_ be done before we enable the
3291                  * cpu pipes, hence this is separate from all the other fdi/pch
3292                  * enabling. */
3293                 ironlake_fdi_pll_enable(intel_crtc);
3294         } else {
3295                 assert_fdi_tx_disabled(dev_priv, pipe);
3296                 assert_fdi_rx_disabled(dev_priv, pipe);
3297         }
3298
3299         for_each_encoder_on_crtc(dev, crtc, encoder)
3300                 if (encoder->pre_enable)
3301                         encoder->pre_enable(encoder);
3302
3303         /* Enable panel fitting for LVDS */
3304         if (dev_priv->pch_pf_size &&
3305             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3306              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3307                 /* Force use of hard-coded filter coefficients
3308                  * as some pre-programmed values are broken,
3309                  * e.g. x201.
3310                  */
3311                 if (IS_IVYBRIDGE(dev))
3312                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3313                                                  PF_PIPE_SEL_IVB(pipe));
3314                 else
3315                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3316                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3317                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3318         }
3319
3320         /*
3321          * On ILK+ LUT must be loaded before the pipe is running but with
3322          * clocks enabled
3323          */
3324         intel_crtc_load_lut(crtc);
3325
3326         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3327         intel_enable_plane(dev_priv, plane, pipe);
3328
3329         if (is_pch_port)
3330                 ironlake_pch_enable(crtc);
3331
3332         mutex_lock(&dev->struct_mutex);
3333         intel_update_fbc(dev);
3334         mutex_unlock(&dev->struct_mutex);
3335
3336         intel_crtc_update_cursor(crtc, true);
3337
3338         for_each_encoder_on_crtc(dev, crtc, encoder)
3339                 encoder->enable(encoder);
3340
3341         if (HAS_PCH_CPT(dev))
3342                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3343
3344         /*
3345          * There seems to be a race in PCH platform hw (at least on some
3346          * outputs) where an enabled pipe still completes any pageflip right
3347          * away (as if the pipe is off) instead of waiting for vblank. As soon
3348          * as the first vblank happend, everything works as expected. Hence just
3349          * wait for one vblank before returning to avoid strange things
3350          * happening.
3351          */
3352         intel_wait_for_vblank(dev, intel_crtc->pipe);
3353 }
3354
3355 static void haswell_crtc_enable(struct drm_crtc *crtc)
3356 {
3357         struct drm_device *dev = crtc->dev;
3358         struct drm_i915_private *dev_priv = dev->dev_private;
3359         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3360         struct intel_encoder *encoder;
3361         int pipe = intel_crtc->pipe;
3362         int plane = intel_crtc->plane;
3363         bool is_pch_port;
3364
3365         WARN_ON(!crtc->enabled);
3366
3367         if (intel_crtc->active)
3368                 return;
3369
3370         intel_crtc->active = true;
3371         intel_update_watermarks(dev);
3372
3373         is_pch_port = haswell_crtc_driving_pch(crtc);
3374
3375         if (is_pch_port)
3376                 dev_priv->display.fdi_link_train(crtc);
3377
3378         for_each_encoder_on_crtc(dev, crtc, encoder)
3379                 if (encoder->pre_enable)
3380                         encoder->pre_enable(encoder);
3381
3382         intel_ddi_enable_pipe_clock(intel_crtc);
3383
3384         /* Enable panel fitting for eDP */
3385         if (dev_priv->pch_pf_size &&
3386             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3387                 /* Force use of hard-coded filter coefficients
3388                  * as some pre-programmed values are broken,
3389                  * e.g. x201.
3390                  */
3391                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3392                                          PF_PIPE_SEL_IVB(pipe));
3393                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3394                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3395         }
3396
3397         /*
3398          * On ILK+ LUT must be loaded before the pipe is running but with
3399          * clocks enabled
3400          */
3401         intel_crtc_load_lut(crtc);
3402
3403         intel_ddi_set_pipe_settings(crtc);
3404         intel_ddi_enable_pipe_func(crtc);
3405
3406         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3407         intel_enable_plane(dev_priv, plane, pipe);
3408
3409         if (is_pch_port)
3410                 lpt_pch_enable(crtc);
3411
3412         mutex_lock(&dev->struct_mutex);
3413         intel_update_fbc(dev);
3414         mutex_unlock(&dev->struct_mutex);
3415
3416         intel_crtc_update_cursor(crtc, true);
3417
3418         for_each_encoder_on_crtc(dev, crtc, encoder)
3419                 encoder->enable(encoder);
3420
3421         /*
3422          * There seems to be a race in PCH platform hw (at least on some
3423          * outputs) where an enabled pipe still completes any pageflip right
3424          * away (as if the pipe is off) instead of waiting for vblank. As soon
3425          * as the first vblank happend, everything works as expected. Hence just
3426          * wait for one vblank before returning to avoid strange things
3427          * happening.
3428          */
3429         intel_wait_for_vblank(dev, intel_crtc->pipe);
3430 }
3431
3432 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3433 {
3434         struct drm_device *dev = crtc->dev;
3435         struct drm_i915_private *dev_priv = dev->dev_private;
3436         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3437         struct intel_encoder *encoder;
3438         int pipe = intel_crtc->pipe;
3439         int plane = intel_crtc->plane;
3440         u32 reg, temp;
3441
3442
3443         if (!intel_crtc->active)
3444                 return;
3445
3446         for_each_encoder_on_crtc(dev, crtc, encoder)
3447                 encoder->disable(encoder);
3448
3449         intel_crtc_wait_for_pending_flips(crtc);
3450         drm_vblank_off(dev, pipe);
3451         intel_crtc_update_cursor(crtc, false);
3452
3453         intel_disable_plane(dev_priv, plane, pipe);
3454
3455         if (dev_priv->cfb_plane == plane)
3456                 intel_disable_fbc(dev);
3457
3458         intel_disable_pipe(dev_priv, pipe);
3459
3460         /* Disable PF */
3461         I915_WRITE(PF_CTL(pipe), 0);
3462         I915_WRITE(PF_WIN_SZ(pipe), 0);
3463
3464         for_each_encoder_on_crtc(dev, crtc, encoder)
3465                 if (encoder->post_disable)
3466                         encoder->post_disable(encoder);
3467
3468         ironlake_fdi_disable(crtc);
3469
3470         ironlake_disable_pch_transcoder(dev_priv, pipe);
3471
3472         if (HAS_PCH_CPT(dev)) {
3473                 /* disable TRANS_DP_CTL */
3474                 reg = TRANS_DP_CTL(pipe);
3475                 temp = I915_READ(reg);
3476                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3477                 temp |= TRANS_DP_PORT_SEL_NONE;
3478                 I915_WRITE(reg, temp);
3479
3480                 /* disable DPLL_SEL */
3481                 temp = I915_READ(PCH_DPLL_SEL);
3482                 switch (pipe) {
3483                 case 0:
3484                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3485                         break;
3486                 case 1:
3487                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3488                         break;
3489                 case 2:
3490                         /* C shares PLL A or B */
3491                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3492                         break;
3493                 default:
3494                         BUG(); /* wtf */
3495                 }
3496                 I915_WRITE(PCH_DPLL_SEL, temp);
3497         }
3498
3499         /* disable PCH DPLL */
3500         intel_disable_pch_pll(intel_crtc);
3501
3502         ironlake_fdi_pll_disable(intel_crtc);
3503
3504         intel_crtc->active = false;
3505         intel_update_watermarks(dev);
3506
3507         mutex_lock(&dev->struct_mutex);
3508         intel_update_fbc(dev);
3509         mutex_unlock(&dev->struct_mutex);
3510 }
3511
3512 static void haswell_crtc_disable(struct drm_crtc *crtc)
3513 {
3514         struct drm_device *dev = crtc->dev;
3515         struct drm_i915_private *dev_priv = dev->dev_private;
3516         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3517         struct intel_encoder *encoder;
3518         int pipe = intel_crtc->pipe;
3519         int plane = intel_crtc->plane;
3520         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3521         bool is_pch_port;
3522
3523         if (!intel_crtc->active)
3524                 return;
3525
3526         is_pch_port = haswell_crtc_driving_pch(crtc);
3527
3528         for_each_encoder_on_crtc(dev, crtc, encoder)
3529                 encoder->disable(encoder);
3530
3531         intel_crtc_wait_for_pending_flips(crtc);
3532         drm_vblank_off(dev, pipe);
3533         intel_crtc_update_cursor(crtc, false);
3534
3535         intel_disable_plane(dev_priv, plane, pipe);
3536
3537         if (dev_priv->cfb_plane == plane)
3538                 intel_disable_fbc(dev);
3539
3540         intel_disable_pipe(dev_priv, pipe);
3541
3542         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3543
3544         /* Disable PF */
3545         I915_WRITE(PF_CTL(pipe), 0);
3546         I915_WRITE(PF_WIN_SZ(pipe), 0);
3547
3548         intel_ddi_disable_pipe_clock(intel_crtc);
3549
3550         for_each_encoder_on_crtc(dev, crtc, encoder)
3551                 if (encoder->post_disable)
3552                         encoder->post_disable(encoder);
3553
3554         if (is_pch_port) {
3555                 lpt_disable_pch_transcoder(dev_priv);
3556                 intel_ddi_fdi_disable(crtc);
3557         }
3558
3559         intel_crtc->active = false;
3560         intel_update_watermarks(dev);
3561
3562         mutex_lock(&dev->struct_mutex);
3563         intel_update_fbc(dev);
3564         mutex_unlock(&dev->struct_mutex);
3565 }
3566
3567 static void ironlake_crtc_off(struct drm_crtc *crtc)
3568 {
3569         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3570         intel_put_pch_pll(intel_crtc);
3571 }
3572
3573 static void haswell_crtc_off(struct drm_crtc *crtc)
3574 {
3575         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3576
3577         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3578          * start using it. */
3579         intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3580
3581         intel_ddi_put_crtc_pll(crtc);
3582 }
3583
3584 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3585 {
3586         if (!enable && intel_crtc->overlay) {
3587                 struct drm_device *dev = intel_crtc->base.dev;
3588                 struct drm_i915_private *dev_priv = dev->dev_private;
3589
3590                 mutex_lock(&dev->struct_mutex);
3591                 dev_priv->mm.interruptible = false;
3592                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3593                 dev_priv->mm.interruptible = true;
3594                 mutex_unlock(&dev->struct_mutex);
3595         }
3596
3597         /* Let userspace switch the overlay on again. In most cases userspace
3598          * has to recompute where to put it anyway.
3599          */
3600 }
3601
3602 /**
3603  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3604  * cursor plane briefly if not already running after enabling the display
3605  * plane.
3606  * This workaround avoids occasional blank screens when self refresh is
3607  * enabled.
3608  */
3609 static void
3610 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum i915_pipe pipe)
3611 {
3612         u32 cntl = I915_READ(CURCNTR(pipe));
3613
3614         if ((cntl & CURSOR_MODE) == 0) {
3615                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3616
3617                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3618                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3619                 intel_wait_for_vblank(dev_priv->dev, pipe);
3620                 I915_WRITE(CURCNTR(pipe), cntl);
3621                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3622                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3623         }
3624 }
3625
3626 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3627 {
3628         struct drm_device *dev = crtc->dev;
3629         struct drm_i915_private *dev_priv = dev->dev_private;
3630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3631         struct intel_encoder *encoder;
3632         int pipe = intel_crtc->pipe;
3633         int plane = intel_crtc->plane;
3634
3635         WARN_ON(!crtc->enabled);
3636
3637         if (intel_crtc->active)
3638                 return;
3639
3640         intel_crtc->active = true;
3641         intel_update_watermarks(dev);
3642
3643         intel_enable_pll(dev_priv, pipe);
3644
3645         for_each_encoder_on_crtc(dev, crtc, encoder)
3646                 if (encoder->pre_enable)
3647                         encoder->pre_enable(encoder);
3648
3649         intel_enable_pipe(dev_priv, pipe, false);
3650         intel_enable_plane(dev_priv, plane, pipe);
3651         if (IS_G4X(dev))
3652                 g4x_fixup_plane(dev_priv, pipe);
3653
3654         intel_crtc_load_lut(crtc);
3655         intel_update_fbc(dev);
3656
3657         /* Give the overlay scaler a chance to enable if it's on this pipe */
3658         intel_crtc_dpms_overlay(intel_crtc, true);
3659         intel_crtc_update_cursor(crtc, true);
3660
3661         for_each_encoder_on_crtc(dev, crtc, encoder)
3662                 encoder->enable(encoder);
3663 }
3664
3665 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3666 {
3667         struct drm_device *dev = crtc->dev;
3668         struct drm_i915_private *dev_priv = dev->dev_private;
3669         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3670         struct intel_encoder *encoder;
3671         int pipe = intel_crtc->pipe;
3672         int plane = intel_crtc->plane;
3673         u32 pctl;
3674
3675
3676         if (!intel_crtc->active)
3677                 return;
3678
3679         for_each_encoder_on_crtc(dev, crtc, encoder)
3680                 encoder->disable(encoder);
3681
3682         /* Give the overlay scaler a chance to disable if it's on this pipe */
3683         intel_crtc_wait_for_pending_flips(crtc);
3684         drm_vblank_off(dev, pipe);
3685         intel_crtc_dpms_overlay(intel_crtc, false);
3686         intel_crtc_update_cursor(crtc, false);
3687
3688         if (dev_priv->cfb_plane == plane)
3689                 intel_disable_fbc(dev);
3690
3691         intel_disable_plane(dev_priv, plane, pipe);
3692         intel_disable_pipe(dev_priv, pipe);
3693
3694         /* Disable pannel fitter if it is on this pipe. */
3695         pctl = I915_READ(PFIT_CONTROL);
3696         if ((pctl & PFIT_ENABLE) &&
3697             ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3698                 I915_WRITE(PFIT_CONTROL, 0);
3699
3700         intel_disable_pll(dev_priv, pipe);
3701
3702         intel_crtc->active = false;
3703         intel_update_fbc(dev);
3704         intel_update_watermarks(dev);
3705 }
3706
3707 static void i9xx_crtc_off(struct drm_crtc *crtc)
3708 {
3709 }
3710
3711 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3712                                     bool enabled)
3713 {
3714         struct drm_device *dev = crtc->dev;
3715         struct drm_i915_master_private *master_priv;
3716         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3717         int pipe = intel_crtc->pipe;
3718
3719         if (!dev->primary->master)
3720                 return;
3721
3722         master_priv = dev->primary->master->driver_priv;
3723         if (!master_priv->sarea_priv)
3724                 return;
3725
3726         switch (pipe) {
3727         case 0:
3728                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3729                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3730                 break;
3731         case 1:
3732                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3733                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3734                 break;
3735         default:
3736                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3737                 break;
3738         }
3739 }
3740
3741 /**
3742  * Sets the power management mode of the pipe and plane.
3743  */
3744 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3745 {
3746         struct drm_device *dev = crtc->dev;
3747         struct drm_i915_private *dev_priv = dev->dev_private;
3748         struct intel_encoder *intel_encoder;
3749         bool enable = false;
3750
3751         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3752                 enable |= intel_encoder->connectors_active;
3753
3754         if (enable)
3755                 dev_priv->display.crtc_enable(crtc);
3756         else
3757                 dev_priv->display.crtc_disable(crtc);
3758
3759         intel_crtc_update_sarea(crtc, enable);
3760 }
3761
3762 static void intel_crtc_noop(struct drm_crtc *crtc)
3763 {
3764 }
3765
3766 static void intel_crtc_disable(struct drm_crtc *crtc)
3767 {
3768         struct drm_device *dev = crtc->dev;
3769         struct drm_connector *connector;
3770         struct drm_i915_private *dev_priv = dev->dev_private;
3771         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3772
3773         /* crtc should still be enabled when we disable it. */
3774         WARN_ON(!crtc->enabled);
3775
3776         intel_crtc->eld_vld = false;
3777         dev_priv->display.crtc_disable(crtc);
3778         intel_crtc_update_sarea(crtc, false);
3779         dev_priv->display.off(crtc);
3780
3781         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3782         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3783
3784         if (crtc->fb) {
3785                 mutex_lock(&dev->struct_mutex);
3786                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3787                 mutex_unlock(&dev->struct_mutex);
3788                 crtc->fb = NULL;
3789         }
3790
3791         /* Update computed state. */
3792         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3793                 if (!connector->encoder || !connector->encoder->crtc)
3794                         continue;
3795
3796                 if (connector->encoder->crtc != crtc)
3797                         continue;
3798
3799                 connector->dpms = DRM_MODE_DPMS_OFF;
3800                 to_intel_encoder(connector->encoder)->connectors_active = false;
3801         }
3802 }
3803
3804 void intel_modeset_disable(struct drm_device *dev)
3805 {
3806         struct drm_crtc *crtc;
3807
3808         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3809                 if (crtc->enabled)
3810                         intel_crtc_disable(crtc);
3811         }
3812 }
3813
3814 void intel_encoder_noop(struct drm_encoder *encoder)
3815 {
3816 }
3817
3818 void intel_encoder_destroy(struct drm_encoder *encoder)
3819 {
3820         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3821
3822         drm_encoder_cleanup(encoder);
3823         drm_free(intel_encoder, M_DRM);
3824 }
3825
3826 /* Simple dpms helper for encodres with just one connector, no cloning and only
3827  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3828  * state of the entire output pipe. */
3829 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3830 {
3831         if (mode == DRM_MODE_DPMS_ON) {
3832                 encoder->connectors_active = true;
3833
3834                 intel_crtc_update_dpms(encoder->base.crtc);
3835         } else {
3836                 encoder->connectors_active = false;
3837
3838                 intel_crtc_update_dpms(encoder->base.crtc);
3839         }
3840 }
3841
3842 /* Cross check the actual hw state with our own modeset state tracking (and it's
3843  * internal consistency). */
3844 static void intel_connector_check_state(struct intel_connector *connector)
3845 {
3846         if (connector->get_hw_state(connector)) {
3847                 struct intel_encoder *encoder = connector->encoder;
3848                 struct drm_crtc *crtc;
3849                 bool encoder_enabled;
3850                 enum i915_pipe pipe;
3851
3852                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3853                               connector->base.base.id,
3854                               drm_get_connector_name(&connector->base));
3855
3856                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3857                      "wrong connector dpms state\n");
3858                 WARN(connector->base.encoder != &encoder->base,
3859                      "active connector not linked to encoder\n");
3860                 WARN(!encoder->connectors_active,
3861                      "encoder->connectors_active not set\n");
3862
3863                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3864                 WARN(!encoder_enabled, "encoder not enabled\n");
3865                 if (WARN_ON(!encoder->base.crtc))
3866                         return;
3867
3868                 crtc = encoder->base.crtc;
3869
3870                 WARN(!crtc->enabled, "crtc not enabled\n");
3871                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3872                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3873                      "encoder active on the wrong pipe\n");
3874         }
3875 }
3876
3877 /* Even simpler default implementation, if there's really no special case to
3878  * consider. */
3879 void intel_connector_dpms(struct drm_connector *connector, int mode)
3880 {
3881         struct intel_encoder *encoder = intel_attached_encoder(connector);
3882
3883         /* All the simple cases only support two dpms states. */
3884         if (mode != DRM_MODE_DPMS_ON)
3885                 mode = DRM_MODE_DPMS_OFF;
3886
3887         if (mode == connector->dpms)
3888                 return;
3889
3890         connector->dpms = mode;
3891
3892         /* Only need to change hw state when actually enabled */
3893         if (encoder->base.crtc)
3894                 intel_encoder_dpms(encoder, mode);
3895         else
3896                 WARN_ON(encoder->connectors_active != false);
3897
3898         intel_modeset_check_state(connector->dev);
3899 }
3900
3901 /* Simple connector->get_hw_state implementation for encoders that support only
3902  * one connector and no cloning and hence the encoder state determines the state
3903  * of the connector. */
3904 bool intel_connector_get_hw_state(struct intel_connector *connector)
3905 {
3906         enum i915_pipe pipe = 0;
3907         struct intel_encoder *encoder = connector->encoder;
3908
3909         return encoder->get_hw_state(encoder, &pipe);
3910 }
3911
3912 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3913                                   const struct drm_display_mode *mode,
3914                                   struct drm_display_mode *adjusted_mode)
3915 {
3916         struct drm_device *dev = crtc->dev;
3917
3918         if (HAS_PCH_SPLIT(dev)) {
3919                 /* FDI link clock is fixed at 2.7G */
3920                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3921                         return false;
3922         }
3923
3924         /* All interlaced capable intel hw wants timings in frames. Note though
3925          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3926          * timings, so we need to be careful not to clobber these.*/
3927         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3928                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3929
3930         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3931          * with a hsync front porch of 0.
3932          */
3933         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3934                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3935                 return false;
3936
3937         return true;
3938 }
3939
3940 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3941 {
3942         return 400000; /* FIXME */
3943 }
3944
3945 static int i945_get_display_clock_speed(struct drm_device *dev)
3946 {
3947         return 400000;
3948 }
3949
3950 static int i915_get_display_clock_speed(struct drm_device *dev)
3951 {
3952         return 333000;
3953 }
3954
3955 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3956 {
3957         return 200000;
3958 }
3959
3960 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3961 {
3962         u16 gcfgc = 0;
3963
3964         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3965
3966         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3967                 return 133000;
3968         else {
3969                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3970                 case GC_DISPLAY_CLOCK_333_MHZ:
3971                         return 333000;
3972                 default:
3973                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3974                         return 190000;
3975                 }
3976         }
3977 }
3978
3979 static int i865_get_display_clock_speed(struct drm_device *dev)
3980 {
3981         return 266000;
3982 }
3983
3984 static int i855_get_display_clock_speed(struct drm_device *dev)
3985 {
3986         u16 hpllcc = 0;
3987         /* Assume that the hardware is in the high speed state.  This
3988          * should be the default.
3989          */
3990         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3991         case GC_CLOCK_133_200:
3992         case GC_CLOCK_100_200:
3993                 return 200000;
3994         case GC_CLOCK_166_250:
3995                 return 250000;
3996         case GC_CLOCK_100_133:
3997                 return 133000;
3998         }
3999
4000         /* Shouldn't happen */
4001         return 0;
4002 }
4003
4004 static int i830_get_display_clock_speed(struct drm_device *dev)
4005 {
4006         return 133000;
4007 }
4008
4009 static void
4010 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4011 {
4012         while (*num > 0xffffff || *den > 0xffffff) {
4013                 *num >>= 1;
4014                 *den >>= 1;
4015         }
4016 }
4017
4018 void
4019 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4020                        int pixel_clock, int link_clock,
4021                        struct intel_link_m_n *m_n)
4022 {
4023         m_n->tu = 64;
4024         m_n->gmch_m = bits_per_pixel * pixel_clock;
4025         m_n->gmch_n = link_clock * nlanes * 8;
4026         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4027         m_n->link_m = pixel_clock;
4028         m_n->link_n = link_clock;
4029         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4030 }
4031
4032 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4033 {
4034         if (i915_panel_use_ssc >= 0)
4035                 return i915_panel_use_ssc != 0;
4036         return dev_priv->lvds_use_ssc
4037                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4038 }
4039
4040 /**
4041  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4042  * @crtc: CRTC structure
4043  * @mode: requested mode
4044  *
4045  * A pipe may be connected to one or more outputs.  Based on the depth of the
4046  * attached framebuffer, choose a good color depth to use on the pipe.
4047  *
4048  * If possible, match the pipe depth to the fb depth.  In some cases, this
4049  * isn't ideal, because the connected output supports a lesser or restricted
4050  * set of depths.  Resolve that here:
4051  *    LVDS typically supports only 6bpc, so clamp down in that case
4052  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4053  *    Displays may support a restricted set as well, check EDID and clamp as
4054  *      appropriate.
4055  *    DP may want to dither down to 6bpc to fit larger modes
4056  *
4057  * RETURNS:
4058  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4059  * true if they don't match).
4060  */
4061 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4062                                          struct drm_framebuffer *fb,
4063                                          unsigned int *pipe_bpp,
4064                                          struct drm_display_mode *mode)
4065 {
4066         struct drm_device *dev = crtc->dev;
4067         struct drm_i915_private *dev_priv = dev->dev_private;
4068         struct drm_connector *connector;
4069         struct intel_encoder *intel_encoder;
4070         unsigned int display_bpc = UINT_MAX, bpc;
4071
4072         /* Walk the encoders & connectors on this crtc, get min bpc */
4073         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4074
4075                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4076                         unsigned int lvds_bpc;
4077
4078                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4079                             LVDS_A3_POWER_UP)
4080                                 lvds_bpc = 8;
4081                         else
4082                                 lvds_bpc = 6;
4083
4084                         if (lvds_bpc < display_bpc) {
4085                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4086                                 display_bpc = lvds_bpc;
4087                         }
4088                         continue;
4089                 }
4090
4091                 /* Not one of the known troublemakers, check the EDID */
4092                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4093                                     head) {
4094                         if (connector->encoder != &intel_encoder->base)
4095                                 continue;
4096
4097                         /* Don't use an invalid EDID bpc value */
4098                         if (connector->display_info.bpc &&
4099                             connector->display_info.bpc < display_bpc) {
4100                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4101                                 display_bpc = connector->display_info.bpc;
4102                         }
4103                 }
4104
4105                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4106                         /* Use VBT settings if we have an eDP panel */
4107                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4108
4109                         if (edp_bpc && edp_bpc < display_bpc) {
4110                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4111                                 display_bpc = edp_bpc;
4112                         }
4113                         continue;
4114                 }
4115
4116                 /*
4117                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4118                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4119                  */
4120                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4121                         if (display_bpc > 8 && display_bpc < 12) {
4122                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4123                                 display_bpc = 12;
4124                         } else {
4125                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4126                                 display_bpc = 8;
4127                         }
4128                 }
4129         }
4130
4131         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4132                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4133                 display_bpc = 6;
4134         }
4135
4136         /*
4137          * We could just drive the pipe at the highest bpc all the time and
4138          * enable dithering as needed, but that costs bandwidth.  So choose
4139          * the minimum value that expresses the full color range of the fb but
4140          * also stays within the max display bpc discovered above.
4141          */
4142
4143         switch (fb->depth) {
4144         case 8:
4145                 bpc = 8; /* since we go through a colormap */
4146                 break;
4147         case 15:
4148         case 16:
4149                 bpc = 6; /* min is 18bpp */
4150                 break;
4151         case 24:
4152                 bpc = 8;
4153                 break;
4154         case 30:
4155                 bpc = 10;
4156                 break;
4157         case 48:
4158                 bpc = 12;
4159                 break;
4160         default:
4161                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4162                 bpc = min((unsigned int)8, display_bpc);
4163                 break;
4164         }
4165
4166         display_bpc = min(display_bpc, bpc);
4167
4168         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4169                       bpc, display_bpc);
4170
4171         *pipe_bpp = display_bpc * 3;
4172
4173         return display_bpc != bpc;
4174 }
4175
4176 static int vlv_get_refclk(struct drm_crtc *crtc)
4177 {
4178         struct drm_device *dev = crtc->dev;
4179         struct drm_i915_private *dev_priv = dev->dev_private;
4180         int refclk = 27000; /* for DP & HDMI */
4181
4182         return 100000; /* only one validated so far */
4183
4184         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4185                 refclk = 96000;
4186         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4187                 if (intel_panel_use_ssc(dev_priv))
4188                         refclk = 100000;
4189                 else
4190                         refclk = 96000;
4191         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4192                 refclk = 100000;
4193         }
4194
4195         return refclk;
4196 }
4197
4198 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4199 {
4200         struct drm_device *dev = crtc->dev;
4201         struct drm_i915_private *dev_priv = dev->dev_private;
4202         int refclk;
4203
4204         if (IS_VALLEYVIEW(dev)) {
4205                 refclk = vlv_get_refclk(crtc);
4206         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4207             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4208                 refclk = dev_priv->lvds_ssc_freq * 1000;
4209                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4210                               refclk / 1000);
4211         } else if (!IS_GEN2(dev)) {
4212                 refclk = 96000;
4213         } else {
4214                 refclk = 48000;
4215         }
4216
4217         return refclk;
4218 }
4219
4220 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4221                                       intel_clock_t *clock)
4222 {
4223         /* SDVO TV has fixed PLL values depend on its clock range,
4224            this mirrors vbios setting. */
4225         if (adjusted_mode->clock >= 100000
4226             && adjusted_mode->clock < 140500) {
4227                 clock->p1 = 2;
4228                 clock->p2 = 10;
4229                 clock->n = 3;
4230                 clock->m1 = 16;
4231                 clock->m2 = 8;
4232         } else if (adjusted_mode->clock >= 140500
4233                    && adjusted_mode->clock <= 200000) {
4234                 clock->p1 = 1;
4235                 clock->p2 = 10;
4236                 clock->n = 6;
4237                 clock->m1 = 12;
4238                 clock->m2 = 8;
4239         }
4240 }
4241
4242 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4243                                      intel_clock_t *clock,
4244                                      intel_clock_t *reduced_clock)
4245 {
4246         struct drm_device *dev = crtc->dev;
4247         struct drm_i915_private *dev_priv = dev->dev_private;
4248         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4249         int pipe = intel_crtc->pipe;
4250         u32 fp, fp2 = 0;
4251
4252         if (IS_PINEVIEW(dev)) {
4253                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4254                 if (reduced_clock)
4255                         fp2 = (1 << reduced_clock->n) << 16 |
4256                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4257         } else {
4258                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4259                 if (reduced_clock)
4260                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4261                                 reduced_clock->m2;
4262         }
4263
4264         I915_WRITE(FP0(pipe), fp);
4265
4266         intel_crtc->lowfreq_avail = false;
4267         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4268             reduced_clock && i915_powersave) {
4269                 I915_WRITE(FP1(pipe), fp2);
4270                 intel_crtc->lowfreq_avail = true;
4271         } else {
4272                 I915_WRITE(FP1(pipe), fp);
4273         }
4274 }
4275
4276 static void vlv_update_pll(struct drm_crtc *crtc,
4277                            struct drm_display_mode *mode,
4278                            struct drm_display_mode *adjusted_mode,
4279                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4280                            int num_connectors)
4281 {
4282         struct drm_device *dev = crtc->dev;
4283         struct drm_i915_private *dev_priv = dev->dev_private;
4284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4285         int pipe = intel_crtc->pipe;
4286         u32 dpll, mdiv, pdiv;
4287         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4288         bool is_sdvo;
4289         u32 temp;
4290
4291         lockmgr(&dev_priv->dpio_lock, LK_EXCLUSIVE);
4292
4293         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4294                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4295
4296         dpll = DPLL_VGA_MODE_DIS;
4297         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4298         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4299         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4300
4301         I915_WRITE(DPLL(pipe), dpll);
4302         POSTING_READ(DPLL(pipe));
4303
4304         bestn = clock->n;
4305         bestm1 = clock->m1;
4306         bestm2 = clock->m2;
4307         bestp1 = clock->p1;
4308         bestp2 = clock->p2;
4309
4310         /*
4311          * In Valleyview PLL and program lane counter registers are exposed
4312          * through DPIO interface
4313          */
4314         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4315         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4316         mdiv |= ((bestn << DPIO_N_SHIFT));
4317         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4318         mdiv |= (1 << DPIO_K_SHIFT);
4319         mdiv |= DPIO_ENABLE_CALIBRATION;
4320         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4321
4322         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4323
4324         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4325                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4326                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4327                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4328         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4329
4330         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4331
4332         dpll |= DPLL_VCO_ENABLE;
4333         I915_WRITE(DPLL(pipe), dpll);
4334         POSTING_READ(DPLL(pipe));
4335         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4336                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4337
4338         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4339
4340         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4341                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4342
4343         I915_WRITE(DPLL(pipe), dpll);
4344
4345         /* Wait for the clocks to stabilize. */
4346         POSTING_READ(DPLL(pipe));
4347         udelay(150);
4348
4349         temp = 0;
4350         if (is_sdvo) {
4351                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4352                 if (temp > 1)
4353                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4354                 else
4355                         temp = 0;
4356         }
4357         I915_WRITE(DPLL_MD(pipe), temp);
4358         POSTING_READ(DPLL_MD(pipe));
4359
4360         /* Now program lane control registers */
4361         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4362                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4363         {
4364                 temp = 0x1000C4;
4365                 if(pipe == 1)
4366                         temp |= (1 << 21);
4367                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4368         }
4369         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4370         {
4371                 temp = 0x1000C4;
4372                 if(pipe == 1)
4373                         temp |= (1 << 21);
4374                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4375         }
4376
4377         lockmgr(&dev_priv->dpio_lock, LK_RELEASE);
4378 }
4379
4380 static void i9xx_update_pll(struct drm_crtc *crtc,
4381                             struct drm_display_mode *mode,
4382                             struct drm_display_mode *adjusted_mode,
4383                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4384                             int num_connectors)
4385 {
4386         struct drm_device *dev = crtc->dev;
4387         struct drm_i915_private *dev_priv = dev->dev_private;
4388         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4389         struct intel_encoder *encoder;
4390         int pipe = intel_crtc->pipe;
4391         u32 dpll;
4392         bool is_sdvo;
4393
4394         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4395
4396         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4397                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4398
4399         dpll = DPLL_VGA_MODE_DIS;
4400
4401         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4402                 dpll |= DPLLB_MODE_LVDS;
4403         else
4404                 dpll |= DPLLB_MODE_DAC_SERIAL;
4405         if (is_sdvo) {
4406                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4407                 if (pixel_multiplier > 1) {
4408                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4409                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4410                 }
4411                 dpll |= DPLL_DVO_HIGH_SPEED;
4412         }
4413         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4414                 dpll |= DPLL_DVO_HIGH_SPEED;
4415
4416         /* compute bitmask from p1 value */
4417         if (IS_PINEVIEW(dev))
4418                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4419         else {
4420                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4421                 if (IS_G4X(dev) && reduced_clock)
4422                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4423         }
4424         switch (clock->p2) {
4425         case 5:
4426                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4427                 break;
4428         case 7:
4429                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4430                 break;
4431         case 10:
4432                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4433                 break;
4434         case 14:
4435                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4436                 break;
4437         }
4438         if (INTEL_INFO(dev)->gen >= 4)
4439                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4440
4441         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4442                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4443         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4444                 /* XXX: just matching BIOS for now */
4445                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4446                 dpll |= 3;
4447         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4448                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4449                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4450         else
4451                 dpll |= PLL_REF_INPUT_DREFCLK;
4452
4453         dpll |= DPLL_VCO_ENABLE;
4454         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4455         POSTING_READ(DPLL(pipe));
4456         udelay(150);
4457
4458         for_each_encoder_on_crtc(dev, crtc, encoder)
4459                 if (encoder->pre_pll_enable)
4460                         encoder->pre_pll_enable(encoder);
4461
4462         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4463                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4464
4465         I915_WRITE(DPLL(pipe), dpll);
4466
4467         /* Wait for the clocks to stabilize. */
4468         POSTING_READ(DPLL(pipe));
4469         udelay(150);
4470
4471         if (INTEL_INFO(dev)->gen >= 4) {
4472                 u32 temp = 0;
4473                 if (is_sdvo) {
4474                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4475                         if (temp > 1)
4476                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4477                         else
4478                                 temp = 0;
4479                 }
4480                 I915_WRITE(DPLL_MD(pipe), temp);
4481         } else {
4482                 /* The pixel multiplier can only be updated once the
4483                  * DPLL is enabled and the clocks are stable.
4484                  *
4485                  * So write it again.
4486                  */
4487                 I915_WRITE(DPLL(pipe), dpll);
4488         }
4489 }
4490
4491 static void i8xx_update_pll(struct drm_crtc *crtc,
4492                             struct drm_display_mode *adjusted_mode,
4493                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4494                             int num_connectors)
4495 {
4496         struct drm_device *dev = crtc->dev;
4497         struct drm_i915_private *dev_priv = dev->dev_private;
4498         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4499         struct intel_encoder *encoder;
4500         int pipe = intel_crtc->pipe;
4501         u32 dpll;
4502
4503         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4504
4505         dpll = DPLL_VGA_MODE_DIS;
4506
4507         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4508                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4509         } else {
4510                 if (clock->p1 == 2)
4511                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4512                 else
4513                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4514                 if (clock->p2 == 4)
4515                         dpll |= PLL_P2_DIVIDE_BY_4;
4516         }
4517
4518         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4519                 /* XXX: just matching BIOS for now */
4520                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4521                 dpll |= 3;
4522         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4523                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4524                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4525         else
4526                 dpll |= PLL_REF_INPUT_DREFCLK;
4527
4528         dpll |= DPLL_VCO_ENABLE;
4529         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4530         POSTING_READ(DPLL(pipe));
4531         udelay(150);
4532
4533         for_each_encoder_on_crtc(dev, crtc, encoder)
4534                 if (encoder->pre_pll_enable)
4535                         encoder->pre_pll_enable(encoder);
4536
4537         I915_WRITE(DPLL(pipe), dpll);
4538
4539         /* Wait for the clocks to stabilize. */
4540         POSTING_READ(DPLL(pipe));
4541         udelay(150);
4542
4543         /* The pixel multiplier can only be updated once the
4544          * DPLL is enabled and the clocks are stable.
4545          *
4546          * So write it again.
4547          */
4548         I915_WRITE(DPLL(pipe), dpll);
4549 }
4550
4551 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4552                                    struct drm_display_mode *mode,
4553                                    struct drm_display_mode *adjusted_mode)
4554 {
4555         struct drm_device *dev = intel_crtc->base.dev;
4556         struct drm_i915_private *dev_priv = dev->dev_private;
4557         enum i915_pipe pipe = intel_crtc->pipe;
4558         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4559         uint32_t vsyncshift;
4560
4561         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4562                 /* the chip adds 2 halflines automatically */
4563                 adjusted_mode->crtc_vtotal -= 1;
4564                 adjusted_mode->crtc_vblank_end -= 1;
4565                 vsyncshift = adjusted_mode->crtc_hsync_start
4566                              - adjusted_mode->crtc_htotal / 2;
4567         } else {
4568                 vsyncshift = 0;
4569         }
4570
4571         if (INTEL_INFO(dev)->gen > 3)
4572                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4573
4574         I915_WRITE(HTOTAL(cpu_transcoder),
4575                    (adjusted_mode->crtc_hdisplay - 1) |
4576                    ((adjusted_mode->crtc_htotal - 1) << 16));
4577         I915_WRITE(HBLANK(cpu_transcoder),
4578                    (adjusted_mode->crtc_hblank_start - 1) |
4579                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4580         I915_WRITE(HSYNC(cpu_transcoder),
4581                    (adjusted_mode->crtc_hsync_start - 1) |
4582                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4583
4584         I915_WRITE(VTOTAL(cpu_transcoder),
4585                    (adjusted_mode->crtc_vdisplay - 1) |
4586                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4587         I915_WRITE(VBLANK(cpu_transcoder),
4588                    (adjusted_mode->crtc_vblank_start - 1) |
4589                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4590         I915_WRITE(VSYNC(cpu_transcoder),
4591                    (adjusted_mode->crtc_vsync_start - 1) |
4592                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4593
4594         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4595          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4596          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4597          * bits. */
4598         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4599             (pipe == PIPE_B || pipe == PIPE_C))
4600                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4601
4602         /* pipesrc controls the size that is scaled from, which should
4603          * always be the user's requested size.
4604          */
4605         I915_WRITE(PIPESRC(pipe),
4606                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4607 }
4608
4609 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4610                               struct drm_display_mode *mode,
4611                               struct drm_display_mode *adjusted_mode,
4612                               int x, int y,
4613                               struct drm_framebuffer *fb)
4614 {
4615         struct drm_device *dev = crtc->dev;
4616         struct drm_i915_private *dev_priv = dev->dev_private;
4617         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4618         int pipe = intel_crtc->pipe;
4619         int plane = intel_crtc->plane;
4620         int refclk, num_connectors = 0;
4621         intel_clock_t clock, reduced_clock;
4622         u32 dspcntr, pipeconf;
4623         bool ok, has_reduced_clock = false, is_sdvo = false;
4624         bool is_lvds = false, is_tv = false, is_dp = false;
4625         struct intel_encoder *encoder;
4626         const intel_limit_t *limit;
4627         int ret;
4628
4629         for_each_encoder_on_crtc(dev, crtc, encoder) {
4630                 switch (encoder->type) {
4631                 case INTEL_OUTPUT_LVDS:
4632                         is_lvds = true;
4633                         break;
4634                 case INTEL_OUTPUT_SDVO:
4635                 case INTEL_OUTPUT_HDMI:
4636                         is_sdvo = true;
4637                         if (encoder->needs_tv_clock)
4638                                 is_tv = true;
4639                         break;
4640                 case INTEL_OUTPUT_TVOUT:
4641                         is_tv = true;
4642                         break;
4643                 case INTEL_OUTPUT_DISPLAYPORT:
4644                         is_dp = true;
4645                         break;
4646                 }
4647
4648                 num_connectors++;
4649         }
4650
4651         refclk = i9xx_get_refclk(crtc, num_connectors);
4652
4653         /*
4654          * Returns a set of divisors for the desired target clock with the given
4655          * refclk, or FALSE.  The returned values represent the clock equation:
4656          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4657          */
4658         limit = intel_limit(crtc, refclk);
4659         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4660                              &clock);
4661         if (!ok) {
4662                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4663                 return -EINVAL;
4664         }
4665
4666         /* Ensure that the cursor is valid for the new mode before changing... */
4667         intel_crtc_update_cursor(crtc, true);
4668
4669         if (is_lvds && dev_priv->lvds_downclock_avail) {
4670                 /*
4671                  * Ensure we match the reduced clock's P to the target clock.
4672                  * If the clocks don't match, we can't switch the display clock
4673                  * by using the FP0/FP1. In such case we will disable the LVDS
4674                  * downclock feature.
4675                 */
4676                 has_reduced_clock = limit->find_pll(limit, crtc,
4677                                                     dev_priv->lvds_downclock,
4678                                                     refclk,
4679                                                     &clock,
4680                                                     &reduced_clock);
4681         }
4682
4683         if (is_sdvo && is_tv)
4684                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4685
4686         if (IS_GEN2(dev))
4687                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4688                                 has_reduced_clock ? &reduced_clock : NULL,
4689                                 num_connectors);
4690         else if (IS_VALLEYVIEW(dev))
4691                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4692                                 has_reduced_clock ? &reduced_clock : NULL,
4693                                 num_connectors);
4694         else
4695                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4696                                 has_reduced_clock ? &reduced_clock : NULL,
4697                                 num_connectors);
4698
4699         /* setup pipeconf */
4700         pipeconf = I915_READ(PIPECONF(pipe));
4701
4702         /* Set up the display plane register */
4703         dspcntr = DISPPLANE_GAMMA_ENABLE;
4704
4705         if (pipe == 0)
4706                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4707         else
4708                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4709
4710         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4711                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4712                  * core speed.
4713                  *
4714                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4715                  * pipe == 0 check?
4716                  */
4717                 if (mode->clock >
4718                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4719                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4720                 else
4721                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4722         }
4723
4724         /* default to 8bpc */
4725         pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4726         if (is_dp) {
4727                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4728                         pipeconf |= PIPECONF_6BPC |
4729                                     PIPECONF_DITHER_EN |
4730                                     PIPECONF_DITHER_TYPE_SP;
4731                 }
4732         }
4733
4734         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4735                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4736                         pipeconf |= PIPECONF_6BPC |
4737                                         PIPECONF_ENABLE |
4738                                         I965_PIPECONF_ACTIVE;
4739                 }
4740         }
4741
4742         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4743         drm_mode_debug_printmodeline(mode);
4744
4745         if (HAS_PIPE_CXSR(dev)) {
4746                 if (intel_crtc->lowfreq_avail) {
4747                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4748                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4749                 } else {
4750                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4751                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4752                 }
4753         }
4754
4755         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4756         if (!IS_GEN2(dev) &&
4757             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4758                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4759         else
4760                 pipeconf |= PIPECONF_PROGRESSIVE;
4761
4762         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4763
4764         /* pipesrc and dspsize control the size that is scaled from,
4765          * which should always be the user's requested size.
4766          */
4767         I915_WRITE(DSPSIZE(plane),
4768                    ((mode->vdisplay - 1) << 16) |
4769                    (mode->hdisplay - 1));
4770         I915_WRITE(DSPPOS(plane), 0);
4771
4772         I915_WRITE(PIPECONF(pipe), pipeconf);
4773         POSTING_READ(PIPECONF(pipe));
4774         intel_enable_pipe(dev_priv, pipe, false);
4775
4776         intel_wait_for_vblank(dev, pipe);
4777
4778         I915_WRITE(DSPCNTR(plane), dspcntr);
4779         POSTING_READ(DSPCNTR(plane));
4780
4781         ret = intel_pipe_set_base(crtc, x, y, fb);
4782
4783         intel_update_watermarks(dev);
4784
4785         return ret;
4786 }
4787
4788 static void ironlake_init_pch_refclk(struct drm_device *dev)
4789 {
4790         struct drm_i915_private *dev_priv = dev->dev_private;
4791         struct drm_mode_config *mode_config = &dev->mode_config;
4792         struct intel_encoder *encoder;
4793         u32 temp;
4794         bool has_lvds = false;
4795         bool has_cpu_edp = false;
4796         bool has_pch_edp = false;
4797         bool has_panel = false;
4798         bool has_ck505 = false;
4799         bool can_ssc = false;
4800
4801         /* We need to take the global config into account */
4802         list_for_each_entry(encoder, &mode_config->encoder_list,
4803                             base.head) {
4804                 switch (encoder->type) {
4805                 case INTEL_OUTPUT_LVDS:
4806                         has_panel = true;
4807                         has_lvds = true;
4808                         break;
4809                 case INTEL_OUTPUT_EDP:
4810                         has_panel = true;
4811                         if (intel_encoder_is_pch_edp(&encoder->base))
4812                                 has_pch_edp = true;
4813                         else
4814                                 has_cpu_edp = true;
4815                         break;
4816                 }
4817         }
4818
4819         if (HAS_PCH_IBX(dev)) {
4820                 has_ck505 = dev_priv->display_clock_mode;
4821                 can_ssc = has_ck505;
4822         } else {
4823                 has_ck505 = false;
4824                 can_ssc = true;
4825         }
4826
4827         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4828                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4829                       has_ck505);
4830
4831         /* Ironlake: try to setup display ref clock before DPLL
4832          * enabling. This is only under driver's control after
4833          * PCH B stepping, previous chipset stepping should be
4834          * ignoring this setting.
4835          */
4836         temp = I915_READ(PCH_DREF_CONTROL);
4837         /* Always enable nonspread source */
4838         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4839
4840         if (has_ck505)
4841                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4842         else
4843                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4844
4845         if (has_panel) {
4846                 temp &= ~DREF_SSC_SOURCE_MASK;
4847                 temp |= DREF_SSC_SOURCE_ENABLE;
4848
4849                 /* SSC must be turned on before enabling the CPU output  */
4850                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4851                         DRM_DEBUG_KMS("Using SSC on panel\n");
4852                         temp |= DREF_SSC1_ENABLE;
4853                 } else
4854                         temp &= ~DREF_SSC1_ENABLE;
4855
4856                 /* Get SSC going before enabling the outputs */
4857                 I915_WRITE(PCH_DREF_CONTROL, temp);
4858                 POSTING_READ(PCH_DREF_CONTROL);
4859                 udelay(200);
4860
4861                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4862
4863                 /* Enable CPU source on CPU attached eDP */
4864                 if (has_cpu_edp) {
4865                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4866                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4867                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4868                         }
4869                         else
4870                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4871                 } else
4872                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4873
4874                 I915_WRITE(PCH_DREF_CONTROL, temp);
4875                 POSTING_READ(PCH_DREF_CONTROL);
4876                 udelay(200);
4877         } else {
4878                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4879
4880                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4881
4882                 /* Turn off CPU output */
4883                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4884
4885                 I915_WRITE(PCH_DREF_CONTROL, temp);
4886                 POSTING_READ(PCH_DREF_CONTROL);
4887                 udelay(200);
4888
4889                 /* Turn off the SSC source */
4890                 temp &= ~DREF_SSC_SOURCE_MASK;
4891                 temp |= DREF_SSC_SOURCE_DISABLE;
4892
4893                 /* Turn off SSC1 */
4894                 temp &= ~ DREF_SSC1_ENABLE;
4895
4896                 I915_WRITE(PCH_DREF_CONTROL, temp);
4897                 POSTING_READ(PCH_DREF_CONTROL);
4898                 udelay(200);
4899         }
4900 }
4901
4902 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4903 static void lpt_init_pch_refclk(struct drm_device *dev)
4904 {
4905         struct drm_i915_private *dev_priv = dev->dev_private;
4906         struct drm_mode_config *mode_config = &dev->mode_config;
4907         struct intel_encoder *encoder;
4908         bool has_vga = false;
4909         bool is_sdv = false;
4910         u32 tmp;
4911
4912         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4913                 switch (encoder->type) {
4914                 case INTEL_OUTPUT_ANALOG:
4915                         has_vga = true;
4916                         break;
4917                 }
4918         }
4919
4920         if (!has_vga)
4921                 return;
4922
4923         mutex_lock(&dev_priv->dpio_lock);
4924
4925         /* XXX: Rip out SDV support once Haswell ships for real. */
4926         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4927                 is_sdv = true;
4928
4929         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4930         tmp &= ~SBI_SSCCTL_DISABLE;
4931         tmp |= SBI_SSCCTL_PATHALT;
4932         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4933
4934         udelay(24);
4935
4936         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4937         tmp &= ~SBI_SSCCTL_PATHALT;
4938         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4939
4940         if (!is_sdv) {
4941                 tmp = I915_READ(SOUTH_CHICKEN2);
4942                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4943                 I915_WRITE(SOUTH_CHICKEN2, tmp);
4944
4945                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4946                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4947                         DRM_ERROR("FDI mPHY reset assert timeout\n");
4948
4949                 tmp = I915_READ(SOUTH_CHICKEN2);
4950                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4951                 I915_WRITE(SOUTH_CHICKEN2, tmp);
4952
4953                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4954                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4955                                        100))
4956                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4957         }
4958
4959         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4960         tmp &= ~(0xFF << 24);
4961         tmp |= (0x12 << 24);
4962         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4963
4964         if (!is_sdv) {
4965                 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4966                 tmp &= ~(0x3 << 6);
4967                 tmp |= (1 << 6) | (1 << 0);
4968                 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4969         }
4970
4971         if (is_sdv) {
4972                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4973                 tmp |= 0x7FFF;
4974                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4975         }
4976
4977         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4978         tmp |= (1 << 11);
4979         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4980
4981         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4982         tmp |= (1 << 11);
4983         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4984
4985         if (is_sdv) {
4986                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4987                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4988                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4989
4990                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4991                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4992                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4993
4994                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4995                 tmp |= (0x3F << 8);
4996                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4997
4998                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4999                 tmp |= (0x3F << 8);
5000                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5001         }
5002
5003         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5004         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5005         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5006
5007         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5008         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5009         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5010
5011         if (!is_sdv) {
5012                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5013                 tmp &= ~(7 << 13);
5014                 tmp |= (5 << 13);
5015                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5016
5017                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5018                 tmp &= ~(7 << 13);
5019                 tmp |= (5 << 13);
5020                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5021         }
5022
5023         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5024         tmp &= ~0xFF;
5025         tmp |= 0x1C;
5026         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5027
5028         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5029         tmp &= ~0xFF;
5030         tmp |= 0x1C;
5031         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5032
5033         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5034         tmp &= ~(0xFF << 16);
5035         tmp |= (0x1C << 16);
5036         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5037
5038         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5039         tmp &= ~(0xFF << 16);
5040         tmp |= (0x1C << 16);
5041         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5042
5043         if (!is_sdv) {
5044                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5045                 tmp |= (1 << 27);
5046                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5047
5048                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5049                 tmp |= (1 << 27);
5050                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5051
5052                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5053                 tmp &= ~(0xF << 28);
5054                 tmp |= (4 << 28);
5055                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5056
5057                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5058                 tmp &= ~(0xF << 28);
5059                 tmp |= (4 << 28);
5060                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5061         }
5062
5063         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5064         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5065         tmp |= SBI_DBUFF0_ENABLE;
5066         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5067
5068         mutex_unlock(&dev_priv->dpio_lock);
5069 }
5070
5071 /*
5072  * Initialize reference clocks when the driver loads
5073  */
5074 void intel_init_pch_refclk(struct drm_device *dev)
5075 {
5076         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5077                 ironlake_init_pch_refclk(dev);
5078         else if (HAS_PCH_LPT(dev))
5079                 lpt_init_pch_refclk(dev);
5080 }
5081
5082 static int ironlake_get_refclk(struct drm_crtc *crtc)
5083 {
5084         struct drm_device *dev = crtc->dev;
5085         struct drm_i915_private *dev_priv = dev->dev_private;
5086         struct intel_encoder *encoder;
5087         struct intel_encoder *edp_encoder = NULL;
5088         int num_connectors = 0;
5089         bool is_lvds = false;
5090
5091         for_each_encoder_on_crtc(dev, crtc, encoder) {
5092                 switch (encoder->type) {
5093                 case INTEL_OUTPUT_LVDS:
5094                         is_lvds = true;
5095                         break;
5096                 case INTEL_OUTPUT_EDP:
5097                         edp_encoder = encoder;
5098                         break;
5099                 }
5100                 num_connectors++;
5101         }
5102
5103         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5104                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5105                               dev_priv->lvds_ssc_freq);
5106                 return dev_priv->lvds_ssc_freq * 1000;
5107         }
5108
5109         return 120000;
5110 }
5111
5112 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5113                                   struct drm_display_mode *adjusted_mode,
5114                                   bool dither)
5115 {
5116         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5117         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5118         int pipe = intel_crtc->pipe;
5119         uint32_t val;
5120
5121         val = I915_READ(PIPECONF(pipe));
5122
5123         val &= ~PIPECONF_BPC_MASK;
5124         switch (intel_crtc->bpp) {
5125         case 18:
5126                 val |= PIPECONF_6BPC;
5127                 break;
5128         case 24:
5129                 val |= PIPECONF_8BPC;
5130                 break;
5131         case 30:
5132                 val |= PIPECONF_10BPC;
5133                 break;
5134         case 36:
5135                 val |= PIPECONF_12BPC;
5136                 break;
5137         default:
5138                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5139                 BUG();
5140         }
5141
5142         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5143         if (dither)
5144                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5145
5146         val &= ~PIPECONF_INTERLACE_MASK;
5147         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5148                 val |= PIPECONF_INTERLACED_ILK;
5149         else
5150                 val |= PIPECONF_PROGRESSIVE;
5151
5152         if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5153                 val |= PIPECONF_COLOR_RANGE_SELECT;
5154         else
5155                 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5156
5157         I915_WRITE(PIPECONF(pipe), val);
5158         POSTING_READ(PIPECONF(pipe));
5159 }
5160
5161 /*
5162  * Set up the pipe CSC unit.
5163  *
5164  * Currently only full range RGB to limited range RGB conversion
5165  * is supported, but eventually this should handle various
5166  * RGB<->YCbCr scenarios as well.
5167  */
5168 static void intel_set_pipe_csc(struct drm_crtc *crtc,
5169                                const struct drm_display_mode *adjusted_mode)
5170 {
5171         struct drm_device *dev = crtc->dev;
5172         struct drm_i915_private *dev_priv = dev->dev_private;
5173         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5174         int pipe = intel_crtc->pipe;
5175         uint16_t coeff = 0x7800; /* 1.0 */
5176
5177         /*
5178          * TODO: Check what kind of values actually come out of the pipe
5179          * with these coeff/postoff values and adjust to get the best
5180          * accuracy. Perhaps we even need to take the bpc value into
5181          * consideration.
5182          */
5183
5184         if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5185                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5186
5187         /*
5188          * GY/GU and RY/RU should be the other way around according
5189          * to BSpec, but reality doesn't agree. Just set them up in
5190          * a way that results in the correct picture.
5191          */
5192         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5193         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5194
5195         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5196         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5197
5198         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5199         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5200
5201         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5202         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5203         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5204
5205         if (INTEL_INFO(dev)->gen > 6) {
5206                 uint16_t postoff = 0;
5207
5208                 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5209                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5210
5211                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5212                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5213                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5214
5215                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5216         } else {
5217                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5218
5219                 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5220                         mode |= CSC_BLACK_SCREEN_OFFSET;
5221
5222                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5223         }
5224 }
5225
5226 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5227                                  struct drm_display_mode *adjusted_mode,
5228                                  bool dither)
5229 {
5230         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5231         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5232         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5233         uint32_t val;
5234
5235         val = I915_READ(PIPECONF(cpu_transcoder));
5236
5237         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5238         if (dither)
5239                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5240
5241         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5242         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5243                 val |= PIPECONF_INTERLACED_ILK;
5244         else
5245                 val |= PIPECONF_PROGRESSIVE;
5246
5247         I915_WRITE(PIPECONF(cpu_transcoder), val);
5248         POSTING_READ(PIPECONF(cpu_transcoder));
5249 }
5250
5251 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5252                                     struct drm_display_mode *adjusted_mode,
5253                                     intel_clock_t *clock,
5254                                     bool *has_reduced_clock,
5255                                     intel_clock_t *reduced_clock)
5256 {
5257         struct drm_device *dev = crtc->dev;
5258         struct drm_i915_private *dev_priv = dev->dev_private;
5259         struct intel_encoder *intel_encoder;
5260         int refclk;
5261         const intel_limit_t *limit;
5262         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5263
5264         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5265                 switch (intel_encoder->type) {
5266                 case INTEL_OUTPUT_LVDS:
5267                         is_lvds = true;
5268                         break;
5269                 case INTEL_OUTPUT_SDVO:
5270                 case INTEL_OUTPUT_HDMI:
5271                         is_sdvo = true;
5272                         if (intel_encoder->needs_tv_clock)
5273                                 is_tv = true;
5274                         break;
5275                 case INTEL_OUTPUT_TVOUT:
5276                         is_tv = true;
5277                         break;
5278                 }
5279         }
5280
5281         refclk = ironlake_get_refclk(crtc);
5282
5283         /*
5284          * Returns a set of divisors for the desired target clock with the given
5285          * refclk, or FALSE.  The returned values represent the clock equation:
5286          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5287          */
5288         limit = intel_limit(crtc, refclk);
5289         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5290                               clock);
5291         if (!ret)
5292                 return false;
5293
5294         if (is_lvds && dev_priv->lvds_downclock_avail) {
5295                 /*
5296                  * Ensure we match the reduced clock's P to the target clock.
5297                  * If the clocks don't match, we can't switch the display clock
5298                  * by using the FP0/FP1. In such case we will disable the LVDS
5299                  * downclock feature.
5300                 */
5301                 *has_reduced_clock = limit->find_pll(limit, crtc,
5302                                                      dev_priv->lvds_downclock,
5303                                                      refclk,
5304                                                      clock,
5305                                                      reduced_clock);
5306         }
5307
5308         if (is_sdvo && is_tv)
5309                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5310
5311         return true;
5312 }
5313
5314 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5315 {
5316         struct drm_i915_private *dev_priv = dev->dev_private;
5317         uint32_t temp;
5318
5319         temp = I915_READ(SOUTH_CHICKEN1);
5320         if (temp & FDI_BC_BIFURCATION_SELECT)
5321                 return;
5322
5323         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5324         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5325
5326         temp |= FDI_BC_BIFURCATION_SELECT;
5327         DRM_DEBUG_KMS("enabling fdi C rx\n");
5328         I915_WRITE(SOUTH_CHICKEN1, temp);
5329         POSTING_READ(SOUTH_CHICKEN1);
5330 }
5331
5332 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5333 {
5334         struct drm_device *dev = intel_crtc->base.dev;
5335         struct drm_i915_private *dev_priv = dev->dev_private;
5336         struct intel_crtc *pipe_B_crtc =
5337                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5338
5339         DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5340                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5341         if (intel_crtc->fdi_lanes > 4) {
5342                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5343                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5344                 /* Clamp lanes to avoid programming the hw with bogus values. */
5345                 intel_crtc->fdi_lanes = 4;
5346
5347                 return false;
5348         }
5349
5350         if (dev_priv->num_pipe == 2)
5351                 return true;
5352
5353         switch (intel_crtc->pipe) {
5354         case PIPE_A:
5355                 return true;
5356         case PIPE_B:
5357                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5358                     intel_crtc->fdi_lanes > 2) {
5359                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5360                                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5361                         /* Clamp lanes to avoid programming the hw with bogus values. */
5362                         intel_crtc->fdi_lanes = 2;
5363
5364                         return false;
5365                 }
5366
5367                 if (intel_crtc->fdi_lanes > 2)
5368                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5369                 else
5370                         cpt_enable_fdi_bc_bifurcation(dev);
5371
5372                 return true;
5373         case PIPE_C:
5374                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5375                         if (intel_crtc->fdi_lanes > 2) {
5376                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5377                                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5378                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5379                                 intel_crtc->fdi_lanes = 2;
5380
5381                                 return false;
5382                         }
5383                 } else {
5384                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5385                         return false;
5386                 }
5387
5388                 cpt_enable_fdi_bc_bifurcation(dev);
5389
5390                 return true;
5391         default:
5392                 BUG();
5393         }
5394 }
5395
5396 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5397 {
5398         /*
5399          * Account for spread spectrum to avoid
5400          * oversubscribing the link. Max center spread
5401          * is 2.5%; use 5% for safety's sake.
5402          */
5403         u32 bps = target_clock * bpp * 21 / 20;
5404         return bps / (link_bw * 8) + 1;
5405 }
5406
5407 static void ironlake_set_m_n(struct drm_crtc *crtc,
5408                              struct drm_display_mode *mode,
5409                              struct drm_display_mode *adjusted_mode)
5410 {
5411         struct drm_device *dev = crtc->dev;
5412         struct drm_i915_private *dev_priv = dev->dev_private;
5413         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5414         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5415         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5416         struct intel_link_m_n m_n = {0};
5417         int target_clock, pixel_multiplier, lane, link_bw;
5418         bool is_dp = false, is_cpu_edp = false;
5419
5420         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5421                 switch (intel_encoder->type) {
5422                 case INTEL_OUTPUT_DISPLAYPORT:
5423                         is_dp = true;
5424                         break;
5425                 case INTEL_OUTPUT_EDP:
5426                         is_dp = true;
5427                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5428                                 is_cpu_edp = true;
5429                         edp_encoder = intel_encoder;
5430                         break;
5431                 }
5432         }
5433
5434         /* FDI link */
5435         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5436         lane = 0;
5437         /* CPU eDP doesn't require FDI link, so just set DP M/N
5438            according to current link config */
5439         if (is_cpu_edp) {
5440                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5441         } else {
5442                 /* FDI is a binary signal running at ~2.7GHz, encoding
5443                  * each output octet as 10 bits. The actual frequency
5444                  * is stored as a divider into a 100MHz clock, and the
5445                  * mode pixel clock is stored in units of 1KHz.
5446                  * Hence the bw of each lane in terms of the mode signal
5447                  * is:
5448                  */
5449                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5450         }
5451
5452         /* [e]DP over FDI requires target mode clock instead of link clock. */
5453         if (edp_encoder)
5454                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5455         else if (is_dp)
5456                 target_clock = mode->clock;
5457         else
5458                 target_clock = adjusted_mode->clock;
5459
5460         if (!lane)
5461                 lane = ironlake_get_lanes_required(target_clock, link_bw,
5462                                                    intel_crtc->bpp);
5463
5464         intel_crtc->fdi_lanes = lane;
5465
5466         if (pixel_multiplier > 1)
5467                 link_bw *= pixel_multiplier;
5468         intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
5469
5470         I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5471         I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5472         I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5473         I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5474 }
5475
5476 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5477                                       struct drm_display_mode *adjusted_mode,
5478                                       intel_clock_t *clock, u32 fp)
5479 {
5480         struct drm_crtc *crtc = &intel_crtc->base;
5481         struct drm_device *dev = crtc->dev;
5482         struct drm_i915_private *dev_priv = dev->dev_private;
5483         struct intel_encoder *intel_encoder;
5484         uint32_t dpll;
5485         int factor, pixel_multiplier, num_connectors = 0;
5486         bool is_lvds = false, is_sdvo = false, is_tv = false;
5487         bool is_dp = false, is_cpu_edp = false;
5488
5489         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5490                 switch (intel_encoder->type) {
5491                 case INTEL_OUTPUT_LVDS:
5492                         is_lvds = true;
5493                         break;
5494                 case INTEL_OUTPUT_SDVO:
5495                 case INTEL_OUTPUT_HDMI:
5496                         is_sdvo = true;
5497                         if (intel_encoder->needs_tv_clock)
5498                                 is_tv = true;
5499                         break;
5500                 case INTEL_OUTPUT_TVOUT:
5501                         is_tv = true;
5502                         break;
5503                 case INTEL_OUTPUT_DISPLAYPORT:
5504                         is_dp = true;
5505                         break;
5506                 case INTEL_OUTPUT_EDP:
5507                         is_dp = true;
5508                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5509                                 is_cpu_edp = true;
5510                         break;
5511                 }
5512
5513                 num_connectors++;
5514         }
5515
5516         /* Enable autotuning of the PLL clock (if permissible) */
5517         factor = 21;
5518         if (is_lvds) {
5519                 if ((intel_panel_use_ssc(dev_priv) &&
5520                      dev_priv->lvds_ssc_freq == 100) ||
5521                     intel_is_dual_link_lvds(dev))
5522                         factor = 25;
5523         } else if (is_sdvo && is_tv)
5524                 factor = 20;
5525
5526         if (clock->m < factor * clock->n)
5527                 fp |= FP_CB_TUNE;
5528
5529         dpll = 0;
5530
5531         if (is_lvds)
5532                 dpll |= DPLLB_MODE_LVDS;
5533         else
5534                 dpll |= DPLLB_MODE_DAC_SERIAL;
5535         if (is_sdvo) {
5536                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5537                 if (pixel_multiplier > 1) {
5538                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5539                 }
5540                 dpll |= DPLL_DVO_HIGH_SPEED;
5541         }
5542         if (is_dp && !is_cpu_edp)
5543                 dpll |= DPLL_DVO_HIGH_SPEED;
5544
5545         /* compute bitmask from p1 value */
5546         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5547         /* also FPA1 */
5548         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5549
5550         switch (clock->p2) {
5551         case 5:
5552                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5553                 break;
5554         case 7:
5555                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5556                 break;
5557         case 10:
5558                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5559                 break;
5560         case 14:
5561                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5562                 break;
5563         }
5564
5565         if (is_sdvo && is_tv)
5566                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5567         else if (is_tv)
5568                 /* XXX: just matching BIOS for now */
5569                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5570                 dpll |= 3;
5571         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5572                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5573         else
5574                 dpll |= PLL_REF_INPUT_DREFCLK;
5575
5576         return dpll;
5577 }
5578
5579 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5580                                   struct drm_display_mode *mode,
5581                                   struct drm_display_mode *adjusted_mode,
5582                                   int x, int y,
5583                                   struct drm_framebuffer *fb)
5584 {
5585         struct drm_device *dev = crtc->dev;
5586         struct drm_i915_private *dev_priv = dev->dev_private;
5587         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5588         int pipe = intel_crtc->pipe;
5589         int plane = intel_crtc->plane;
5590         int num_connectors = 0;
5591         intel_clock_t clock, reduced_clock;
5592         u32 dpll, fp = 0, fp2 = 0;
5593         bool ok, has_reduced_clock = false;
5594         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5595         struct intel_encoder *encoder;
5596         int ret;
5597         bool dither, fdi_config_ok;
5598
5599         for_each_encoder_on_crtc(dev, crtc, encoder) {
5600                 switch (encoder->type) {
5601                 case INTEL_OUTPUT_LVDS:
5602                         is_lvds = true;
5603                         break;
5604                 case INTEL_OUTPUT_DISPLAYPORT:
5605                         is_dp = true;
5606                         break;
5607                 case INTEL_OUTPUT_EDP:
5608                         is_dp = true;
5609                         if (!intel_encoder_is_pch_edp(&encoder->base))
5610                                 is_cpu_edp = true;
5611                         break;
5612                 }
5613
5614                 num_connectors++;
5615         }
5616
5617         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5618              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5619
5620         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5621                                      &has_reduced_clock, &reduced_clock);
5622         if (!ok) {
5623                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5624                 return -EINVAL;
5625         }
5626
5627         /* Ensure that the cursor is valid for the new mode before changing... */
5628         intel_crtc_update_cursor(crtc, true);
5629
5630         /* determine panel color depth */
5631         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5632                                               adjusted_mode);
5633         if (is_lvds && dev_priv->lvds_dither)
5634                 dither = true;
5635
5636         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5637         if (has_reduced_clock)
5638                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5639                         reduced_clock.m2;
5640
5641         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5642
5643         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5644         drm_mode_debug_printmodeline(mode);
5645
5646         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5647         if (!is_cpu_edp) {
5648                 struct intel_pch_pll *pll;
5649
5650                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5651                 if (pll == NULL) {
5652                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5653                                          pipe);
5654                         return -EINVAL;
5655                 }
5656         } else
5657                 intel_put_pch_pll(intel_crtc);
5658
5659         if (is_dp && !is_cpu_edp)
5660                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5661
5662         for_each_encoder_on_crtc(dev, crtc, encoder)
5663                 if (encoder->pre_pll_enable)
5664                         encoder->pre_pll_enable(encoder);
5665
5666         if (intel_crtc->pch_pll) {
5667                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5668
5669                 /* Wait for the clocks to stabilize. */
5670                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5671                 udelay(150);
5672
5673                 /* The pixel multiplier can only be updated once the
5674                  * DPLL is enabled and the clocks are stable.
5675                  *
5676                  * So write it again.
5677                  */
5678                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5679         }
5680
5681         intel_crtc->lowfreq_avail = false;
5682         if (intel_crtc->pch_pll) {
5683                 if (is_lvds && has_reduced_clock && i915_powersave) {
5684                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5685                         intel_crtc->lowfreq_avail = true;
5686                 } else {
5687                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5688                 }
5689         }
5690
5691         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5692
5693         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5694          * ironlake_check_fdi_lanes. */
5695
5696         ironlake_set_m_n(crtc, mode, adjusted_mode);
5697
5698         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5699
5700         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5701
5702         intel_wait_for_vblank(dev, pipe);
5703
5704         /* Set up the display plane register */
5705         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5706         POSTING_READ(DSPCNTR(plane));
5707
5708         ret = intel_pipe_set_base(crtc, x, y, fb);
5709
5710         intel_update_watermarks(dev);
5711
5712         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5713
5714         return fdi_config_ok ? ret : -EINVAL;
5715 }
5716
5717 static void haswell_modeset_global_resources(struct drm_device *dev)
5718 {
5719         struct drm_i915_private *dev_priv = dev->dev_private;
5720         bool enable = false;
5721         struct intel_crtc *crtc;
5722         struct intel_encoder *encoder;
5723
5724         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5725                 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5726                         enable = true;
5727                 /* XXX: Should check for edp transcoder here, but thanks to init
5728                  * sequence that's not yet available. Just in case desktop eDP
5729                  * on PORT D is possible on haswell, too. */
5730         }
5731
5732         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5733                             base.head) {
5734                 if (encoder->type != INTEL_OUTPUT_EDP &&
5735                     encoder->connectors_active)
5736                         enable = true;
5737         }
5738
5739         /* Even the eDP panel fitter is outside the always-on well. */
5740         if (dev_priv->pch_pf_size)
5741                 enable = true;
5742
5743         intel_set_power_well(dev, enable);
5744 }
5745
5746 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5747                                  struct drm_display_mode *mode,
5748                                  struct drm_display_mode *adjusted_mode,
5749                                  int x, int y,
5750                                  struct drm_framebuffer *fb)
5751 {
5752         struct drm_device *dev = crtc->dev;
5753         struct drm_i915_private *dev_priv = dev->dev_private;
5754         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5755         int pipe = intel_crtc->pipe;
5756         int plane = intel_crtc->plane;
5757         int num_connectors = 0;
5758         bool is_dp = false, is_cpu_edp = false;
5759         struct intel_encoder *encoder;
5760         int ret;
5761         bool dither;
5762
5763         for_each_encoder_on_crtc(dev, crtc, encoder) {
5764                 switch (encoder->type) {
5765                 case INTEL_OUTPUT_DISPLAYPORT:
5766                         is_dp = true;
5767                         break;
5768                 case INTEL_OUTPUT_EDP:
5769                         is_dp = true;
5770                         if (!intel_encoder_is_pch_edp(&encoder->base))
5771                                 is_cpu_edp = true;
5772                         break;
5773                 }
5774
5775                 num_connectors++;
5776         }
5777
5778         if (is_cpu_edp)
5779                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5780         else
5781                 intel_crtc->cpu_transcoder = pipe;
5782
5783         /* We are not sure yet this won't happen. */
5784         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5785              INTEL_PCH_TYPE(dev));
5786
5787         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5788              num_connectors, pipe_name(pipe));
5789
5790         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5791                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5792
5793         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5794
5795         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5796                 return -EINVAL;
5797
5798         /* Ensure that the cursor is valid for the new mode before changing... */
5799         intel_crtc_update_cursor(crtc, true);
5800
5801         /* determine panel color depth */
5802         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5803                                               adjusted_mode);
5804
5805         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5806         drm_mode_debug_printmodeline(mode);
5807
5808         if (is_dp && !is_cpu_edp)
5809                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5810
5811         intel_crtc->lowfreq_avail = false;
5812
5813         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5814
5815         if (!is_dp || is_cpu_edp)
5816                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5817
5818         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5819
5820         intel_set_pipe_csc(crtc, adjusted_mode);
5821
5822         /* Set up the display plane register */
5823         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5824         POSTING_READ(DSPCNTR(plane));
5825
5826         ret = intel_pipe_set_base(crtc, x, y, fb);
5827
5828         intel_update_watermarks(dev);
5829
5830         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5831
5832         return ret;
5833 }
5834
5835 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5836                                struct drm_display_mode *mode,
5837                                struct drm_display_mode *adjusted_mode,
5838                                int x, int y,
5839                                struct drm_framebuffer *fb)
5840 {
5841         struct drm_device *dev = crtc->dev;
5842         struct drm_i915_private *dev_priv = dev->dev_private;
5843         struct drm_encoder_helper_funcs *encoder_funcs;
5844         struct intel_encoder *encoder;
5845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5846         int pipe = intel_crtc->pipe;
5847         int ret;
5848
5849         drm_vblank_pre_modeset(dev, pipe);
5850
5851         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5852                                               x, y, fb);
5853         drm_vblank_post_modeset(dev, pipe);
5854
5855         if (ret != 0)
5856                 return ret;
5857
5858         for_each_encoder_on_crtc(dev, crtc, encoder) {
5859                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5860                         encoder->base.base.id,
5861                         drm_get_encoder_name(&encoder->base),
5862                         mode->base.id, mode->name);
5863                 encoder_funcs = encoder->base.helper_private;
5864                 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5865         }
5866
5867         return 0;
5868 }
5869
5870 static bool intel_eld_uptodate(struct drm_connector *connector,
5871                                int reg_eldv, uint32_t bits_eldv,
5872                                int reg_elda, uint32_t bits_elda,
5873                                int reg_edid)
5874 {
5875         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5876         uint8_t *eld = connector->eld;
5877         uint32_t i;
5878
5879         i = I915_READ(reg_eldv);
5880         i &= bits_eldv;
5881
5882         if (!eld[0])
5883                 return !i;
5884
5885         if (!i)
5886                 return false;
5887
5888         i = I915_READ(reg_elda);
5889         i &= ~bits_elda;
5890         I915_WRITE(reg_elda, i);
5891
5892         for (i = 0; i < eld[2]; i++)
5893                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5894                         return false;
5895
5896         return true;
5897 }
5898
5899 static void g4x_write_eld(struct drm_connector *connector,
5900                           struct drm_crtc *crtc)
5901 {
5902         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5903         uint8_t *eld = connector->eld;
5904         uint32_t eldv;
5905         uint32_t len;
5906         uint32_t i;
5907
5908         i = I915_READ(G4X_AUD_VID_DID);
5909
5910         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5911                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5912         else
5913                 eldv = G4X_ELDV_DEVCTG;
5914
5915         if (intel_eld_uptodate(connector,
5916                                G4X_AUD_CNTL_ST, eldv,
5917                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5918                                G4X_HDMIW_HDMIEDID))
5919                 return;
5920
5921         i = I915_READ(G4X_AUD_CNTL_ST);
5922         i &= ~(eldv | G4X_ELD_ADDR);
5923         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5924         I915_WRITE(G4X_AUD_CNTL_ST, i);
5925
5926         if (!eld[0])
5927                 return;
5928
5929         len = min_t(uint8_t, eld[2], len);
5930         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5931         for (i = 0; i < len; i++)
5932                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5933
5934         i = I915_READ(G4X_AUD_CNTL_ST);
5935         i |= eldv;
5936         I915_WRITE(G4X_AUD_CNTL_ST, i);
5937 }
5938
5939 static void haswell_write_eld(struct drm_connector *connector,
5940                                      struct drm_crtc *crtc)
5941 {
5942         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5943         uint8_t *eld = connector->eld;
5944         struct drm_device *dev = crtc->dev;
5945         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5946         uint32_t eldv;
5947         uint32_t i;
5948         int len;
5949         int pipe = to_intel_crtc(crtc)->pipe;
5950         int tmp;
5951
5952         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5953         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5954         int aud_config = HSW_AUD_CFG(pipe);
5955         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5956
5957
5958         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5959
5960         /* Audio output enable */
5961         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5962         tmp = I915_READ(aud_cntrl_st2);
5963         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5964         I915_WRITE(aud_cntrl_st2, tmp);
5965
5966         /* Wait for 1 vertical blank */
5967         intel_wait_for_vblank(dev, pipe);
5968
5969         /* Set ELD valid state */
5970         tmp = I915_READ(aud_cntrl_st2);
5971         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5972         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5973         I915_WRITE(aud_cntrl_st2, tmp);
5974         tmp = I915_READ(aud_cntrl_st2);
5975         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5976
5977         /* Enable HDMI mode */
5978         tmp = I915_READ(aud_config);
5979         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5980         /* clear N_programing_enable and N_value_index */
5981         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5982         I915_WRITE(aud_config, tmp);
5983
5984         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5985
5986         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5987         intel_crtc->eld_vld = true;
5988
5989         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5990                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5991                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5992                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5993         } else
5994                 I915_WRITE(aud_config, 0);
5995
5996         if (intel_eld_uptodate(connector,
5997                                aud_cntrl_st2, eldv,
5998                                aud_cntl_st, IBX_ELD_ADDRESS,
5999                                hdmiw_hdmiedid))
6000                 return;
6001
6002         i = I915_READ(aud_cntrl_st2);
6003         i &= ~eldv;
6004         I915_WRITE(aud_cntrl_st2, i);
6005
6006         if (!eld[0])
6007                 return;
6008
6009         i = I915_READ(aud_cntl_st);
6010         i &= ~IBX_ELD_ADDRESS;
6011         I915_WRITE(aud_cntl_st, i);
6012         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6013         DRM_DEBUG_DRIVER("port num:%d\n", i);
6014
6015         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6016         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6017         for (i = 0; i < len; i++)
6018                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6019
6020         i = I915_READ(aud_cntrl_st2);
6021         i |= eldv;
6022         I915_WRITE(aud_cntrl_st2, i);
6023
6024 }
6025
6026 static void ironlake_write_eld(struct drm_connector *connector,
6027                                      struct drm_crtc *crtc)
6028 {
6029         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6030         uint8_t *eld = connector->eld;
6031         uint32_t eldv;
6032         uint32_t i;
6033         int len;
6034         int hdmiw_hdmiedid;
6035         int aud_config;
6036         int aud_cntl_st;
6037         int aud_cntrl_st2;
6038         int pipe = to_intel_crtc(crtc)->pipe;
6039
6040         if (HAS_PCH_IBX(connector->dev)) {
6041                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6042                 aud_config = IBX_AUD_CFG(pipe);
6043                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6044                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6045         } else {
6046                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6047                 aud_config = CPT_AUD_CFG(pipe);
6048                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6049                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6050         }
6051
6052         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6053
6054         i = I915_READ(aud_cntl_st);
6055         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6056         if (!i) {
6057                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6058                 /* operate blindly on all ports */
6059                 eldv = IBX_ELD_VALIDB;
6060                 eldv |= IBX_ELD_VALIDB << 4;
6061                 eldv |= IBX_ELD_VALIDB << 8;
6062         } else {
6063                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6064                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6065         }
6066
6067         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6068                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6069                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6070                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6071         } else
6072                 I915_WRITE(aud_config, 0);
6073
6074         if (intel_eld_uptodate(connector,
6075                                aud_cntrl_st2, eldv,
6076                                aud_cntl_st, IBX_ELD_ADDRESS,
6077                                hdmiw_hdmiedid))
6078                 return;
6079
6080         i = I915_READ(aud_cntrl_st2);
6081         i &= ~eldv;
6082         I915_WRITE(aud_cntrl_st2, i);
6083
6084         if (!eld[0])
6085                 return;
6086
6087         i = I915_READ(aud_cntl_st);
6088         i &= ~IBX_ELD_ADDRESS;
6089         I915_WRITE(aud_cntl_st, i);
6090
6091         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6092         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6093         for (i = 0; i < len; i++)
6094                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6095
6096         i = I915_READ(aud_cntrl_st2);
6097         i |= eldv;
6098         I915_WRITE(aud_cntrl_st2, i);
6099 }
6100
6101 void intel_write_eld(struct drm_encoder *encoder,
6102                      struct drm_display_mode *mode)
6103 {
6104         struct drm_crtc *crtc = encoder->crtc;
6105         struct drm_connector *connector;
6106         struct drm_device *dev = encoder->dev;
6107         struct drm_i915_private *dev_priv = dev->dev_private;
6108
6109         connector = drm_select_eld(encoder, mode);
6110         if (!connector)
6111                 return;
6112
6113         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6114                          connector->base.id,
6115                          drm_get_connector_name(connector),
6116                          connector->encoder->base.id,
6117                          drm_get_encoder_name(connector->encoder));
6118
6119         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6120
6121         if (dev_priv->display.write_eld)
6122                 dev_priv->display.write_eld(connector, crtc);
6123 }
6124
6125 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6126 void intel_crtc_load_lut(struct drm_crtc *crtc)
6127 {
6128         struct drm_device *dev = crtc->dev;
6129         struct drm_i915_private *dev_priv = dev->dev_private;
6130         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6131         int palreg = PALETTE(intel_crtc->pipe);
6132         int i;
6133
6134         /* The clocks have to be on to load the palette. */
6135         if (!crtc->enabled || !intel_crtc->active)
6136                 return;
6137
6138         /* use legacy palette for Ironlake */
6139         if (HAS_PCH_SPLIT(dev))
6140                 palreg = LGC_PALETTE(intel_crtc->pipe);
6141
6142         for (i = 0; i < 256; i++) {
6143                 I915_WRITE(palreg + 4 * i,
6144                            (intel_crtc->lut_r[i] << 16) |
6145                            (intel_crtc->lut_g[i] << 8) |
6146                            intel_crtc->lut_b[i]);
6147         }
6148 }
6149
6150 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6151 {
6152         struct drm_device *dev = crtc->dev;
6153         struct drm_i915_private *dev_priv = dev->dev_private;
6154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6155         bool visible = base != 0;
6156         u32 cntl;
6157
6158         if (intel_crtc->cursor_visible == visible)
6159                 return;
6160
6161         cntl = I915_READ(_CURACNTR);
6162         if (visible) {
6163                 /* On these chipsets we can only modify the base whilst
6164                  * the cursor is disabled.
6165                  */
6166                 I915_WRITE(_CURABASE, base);
6167
6168                 cntl &= ~(CURSOR_FORMAT_MASK);
6169                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6170                 cntl |= CURSOR_ENABLE |
6171                         CURSOR_GAMMA_ENABLE |
6172                         CURSOR_FORMAT_ARGB;
6173         } else
6174                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6175         I915_WRITE(_CURACNTR, cntl);
6176
6177         intel_crtc->cursor_visible = visible;
6178 }
6179
6180 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6181 {
6182         struct drm_device *dev = crtc->dev;
6183         struct drm_i915_private *dev_priv = dev->dev_private;
6184         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6185         int pipe = intel_crtc->pipe;
6186         bool visible = base != 0;
6187
6188         if (intel_crtc->cursor_visible != visible) {
6189                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6190                 if (base) {
6191                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6192                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6193                         cntl |= pipe << 28; /* Connect to correct pipe */
6194                 } else {
6195                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6196                         cntl |= CURSOR_MODE_DISABLE;
6197                 }
6198                 I915_WRITE(CURCNTR(pipe), cntl);
6199
6200                 intel_crtc->cursor_visible = visible;
6201         }
6202         /* and commit changes on next vblank */
6203         I915_WRITE(CURBASE(pipe), base);
6204 }
6205
6206 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6207 {
6208         struct drm_device *dev = crtc->dev;
6209         struct drm_i915_private *dev_priv = dev->dev_private;
6210         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6211         int pipe = intel_crtc->pipe;
6212         bool visible = base != 0;
6213
6214         if (intel_crtc->cursor_visible != visible) {
6215                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6216                 if (base) {
6217                         cntl &= ~CURSOR_MODE;
6218                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6219                 } else {
6220                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6221                         cntl |= CURSOR_MODE_DISABLE;
6222                 }
6223                 if (IS_HASWELL(dev))
6224                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6225                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6226
6227                 intel_crtc->cursor_visible = visible;
6228         }
6229         /* and commit changes on next vblank */
6230         I915_WRITE(CURBASE_IVB(pipe), base);
6231 }
6232
6233 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6234 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6235                                      bool on)
6236 {
6237         struct drm_device *dev = crtc->dev;
6238         struct drm_i915_private *dev_priv = dev->dev_private;
6239         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6240         int pipe = intel_crtc->pipe;
6241         int x = intel_crtc->cursor_x;
6242         int y = intel_crtc->cursor_y;
6243         u32 base, pos;
6244         bool visible;
6245
6246         pos = 0;
6247
6248         if (on && crtc->enabled && crtc->fb) {
6249                 base = intel_crtc->cursor_addr;
6250                 if (x > (int) crtc->fb->width)
6251                         base = 0;
6252
6253                 if (y > (int) crtc->fb->height)
6254                         base = 0;
6255         } else
6256                 base = 0;
6257
6258         if (x < 0) {
6259                 if (x + intel_crtc->cursor_width < 0)
6260                         base = 0;
6261
6262                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6263                 x = -x;
6264         }
6265         pos |= x << CURSOR_X_SHIFT;
6266
6267         if (y < 0) {
6268                 if (y + intel_crtc->cursor_height < 0)
6269                         base = 0;
6270
6271                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6272                 y = -y;
6273         }
6274         pos |= y << CURSOR_Y_SHIFT;
6275
6276         visible = base != 0;
6277         if (!visible && !intel_crtc->cursor_visible)
6278                 return;
6279
6280         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6281                 I915_WRITE(CURPOS_IVB(pipe), pos);
6282                 ivb_update_cursor(crtc, base);
6283         } else {
6284                 I915_WRITE(CURPOS(pipe), pos);
6285                 if (IS_845G(dev) || IS_I865G(dev))
6286                         i845_update_cursor(crtc, base);
6287                 else
6288                         i9xx_update_cursor(crtc, base);
6289         }
6290 }
6291
6292 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6293                                  struct drm_file *file,
6294                                  uint32_t handle,
6295                                  uint32_t width, uint32_t height)
6296 {
6297         struct drm_device *dev = crtc->dev;
6298         struct drm_i915_private *dev_priv = dev->dev_private;
6299         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6300         struct drm_i915_gem_object *obj;
6301         uint32_t addr;
6302         int ret;
6303
6304         /* if we want to turn off the cursor ignore width and height */
6305         if (!handle) {
6306                 DRM_DEBUG_KMS("cursor off\n");
6307                 addr = 0;
6308                 obj = NULL;
6309                 mutex_lock(&dev->struct_mutex);
6310                 goto finish;
6311         }
6312
6313         /* Currently we only support 64x64 cursors */
6314         if (width != 64 || height != 64) {
6315                 DRM_ERROR("we currently only support 64x64 cursors\n");
6316                 return -EINVAL;
6317         }
6318
6319         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6320         if (&obj->base == NULL)
6321                 return -ENOENT;
6322
6323         if (obj->base.size < width * height * 4) {
6324                 DRM_ERROR("buffer is to small\n");
6325                 ret = -ENOMEM;
6326                 goto fail;
6327         }
6328
6329         /* we only need to pin inside GTT if cursor is non-phy */
6330         mutex_lock(&dev->struct_mutex);
6331         if (!dev_priv->info->cursor_needs_physical) {
6332                 if (obj->tiling_mode) {
6333                         DRM_ERROR("cursor cannot be tiled\n");
6334                         ret = -EINVAL;
6335                         goto fail_locked;
6336                 }
6337
6338                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6339                 if (ret) {
6340                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6341                         goto fail_locked;
6342                 }
6343
6344                 ret = i915_gem_object_put_fence(obj);
6345                 if (ret) {
6346                         DRM_ERROR("failed to release fence for cursor");
6347                         goto fail_unpin;
6348                 }
6349
6350                 addr = obj->gtt_offset;
6351         } else {
6352                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6353                 ret = i915_gem_attach_phys_object(dev, obj,
6354                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6355                                                   align);
6356                 if (ret) {
6357                         DRM_ERROR("failed to attach phys object\n");
6358                         goto fail_locked;
6359                 }
6360                 addr = obj->phys_obj->handle->busaddr;
6361         }
6362
6363         if (IS_GEN2(dev))
6364                 I915_WRITE(CURSIZE, (height << 12) | width);
6365
6366  finish:
6367         if (intel_crtc->cursor_bo) {
6368                 if (dev_priv->info->cursor_needs_physical) {
6369                         if (intel_crtc->cursor_bo != obj)
6370                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6371                 } else
6372                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6373                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6374         }
6375
6376         mutex_unlock(&dev->struct_mutex);
6377
6378         intel_crtc->cursor_addr = addr;
6379         intel_crtc->cursor_bo = obj;
6380         intel_crtc->cursor_width = width;
6381         intel_crtc->cursor_height = height;
6382
6383         intel_crtc_update_cursor(crtc, true);
6384
6385         return 0;
6386 fail_unpin:
6387         i915_gem_object_unpin(obj);
6388 fail_locked:
6389         mutex_unlock(&dev->struct_mutex);
6390 fail:
6391         drm_gem_object_unreference_unlocked(&obj->base);
6392         return ret;
6393 }
6394
6395 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6396 {
6397         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6398
6399         intel_crtc->cursor_x = x;
6400         intel_crtc->cursor_y = y;
6401
6402         intel_crtc_update_cursor(crtc, true);
6403
6404         return 0;
6405 }
6406
6407 /** Sets the color ramps on behalf of RandR */
6408 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6409                                  u16 blue, int regno)
6410 {
6411         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6412
6413         intel_crtc->lut_r[regno] = red >> 8;
6414         intel_crtc->lut_g[regno] = green >> 8;
6415         intel_crtc->lut_b[regno] = blue >> 8;
6416 }
6417
6418 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6419                              u16 *blue, int regno)
6420 {
6421         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6422
6423         *red = intel_crtc->lut_r[regno] << 8;
6424         *green = intel_crtc->lut_g[regno] << 8;
6425         *blue = intel_crtc->lut_b[regno] << 8;
6426 }
6427
6428 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6429                                  u16 *blue, uint32_t start, uint32_t size)
6430 {
6431         int end = (start + size > 256) ? 256 : start + size, i;
6432         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6433
6434         for (i = start; i < end; i++) {
6435                 intel_crtc->lut_r[i] = red[i] >> 8;
6436                 intel_crtc->lut_g[i] = green[i] >> 8;
6437                 intel_crtc->lut_b[i] = blue[i] >> 8;
6438         }
6439
6440         intel_crtc_load_lut(crtc);
6441 }
6442
6443 /**
6444  * Get a pipe with a simple mode set on it for doing load-based monitor
6445  * detection.
6446  *
6447  * It will be up to the load-detect code to adjust the pipe as appropriate for
6448  * its requirements.  The pipe will be connected to no other encoders.
6449  *
6450  * Currently this code will only succeed if there is a pipe with no encoders
6451  * configured for it.  In the future, it could choose to temporarily disable
6452  * some outputs to free up a pipe for its use.
6453  *
6454  * \return crtc, or NULL if no pipes are available.
6455  */
6456
6457 /* VESA 640x480x72Hz mode to set on the pipe */
6458 static struct drm_display_mode load_detect_mode = {
6459         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6460                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6461 };
6462
6463 static struct drm_framebuffer *
6464 intel_framebuffer_create(struct drm_device *dev,
6465                          struct drm_mode_fb_cmd2 *mode_cmd,
6466                          struct drm_i915_gem_object *obj)
6467 {
6468         struct intel_framebuffer *intel_fb;
6469         int ret;
6470
6471         intel_fb = kmalloc(sizeof(*intel_fb), M_DRM, M_WAITOK | M_ZERO);
6472         if (!intel_fb) {
6473                 drm_gem_object_unreference_unlocked(&obj->base);
6474                 return ERR_PTR(-ENOMEM);
6475         }
6476
6477         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6478         if (ret) {
6479                 drm_gem_object_unreference_unlocked(&obj->base);
6480                 kfree(intel_fb, M_DRM);
6481                 return ERR_PTR(ret);
6482         }
6483
6484         return &intel_fb->base;
6485 }
6486
6487 static u32
6488 intel_framebuffer_pitch_for_width(int width, int bpp)
6489 {
6490         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6491         return ALIGN(pitch, 64);
6492 }
6493
6494 static u32
6495 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6496 {
6497         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6498         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6499 }
6500
6501 static struct drm_framebuffer *
6502 intel_framebuffer_create_for_mode(struct drm_device *dev,
6503                                   struct drm_display_mode *mode,
6504                                   int depth, int bpp)
6505 {
6506         struct drm_i915_gem_object *obj;
6507         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6508
6509         obj = i915_gem_alloc_object(dev,
6510                                     intel_framebuffer_size_for_mode(mode, bpp));
6511         if (obj == NULL)
6512                 return ERR_PTR(-ENOMEM);
6513
6514         mode_cmd.width = mode->hdisplay;
6515         mode_cmd.height = mode->vdisplay;
6516         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6517                                                                 bpp);
6518         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6519
6520         return intel_framebuffer_create(dev, &mode_cmd, obj);
6521 }
6522
6523 static struct drm_framebuffer *
6524 mode_fits_in_fbdev(struct drm_device *dev,
6525                    struct drm_display_mode *mode)
6526 {
6527         struct drm_i915_private *dev_priv = dev->dev_private;
6528         struct drm_i915_gem_object *obj;
6529         struct drm_framebuffer *fb;
6530
6531         if (dev_priv->fbdev == NULL)
6532                 return NULL;
6533
6534         obj = dev_priv->fbdev->ifb.obj;
6535         if (obj == NULL)
6536                 return NULL;
6537
6538         fb = &dev_priv->fbdev->ifb.base;
6539         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6540                                                                fb->bits_per_pixel))
6541                 return NULL;
6542
6543         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6544                 return NULL;
6545
6546         return fb;
6547 }
6548
6549 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6550                                 struct drm_display_mode *mode,
6551                                 struct intel_load_detect_pipe *old)
6552 {
6553         struct intel_crtc *intel_crtc;
6554         struct intel_encoder *intel_encoder =
6555                 intel_attached_encoder(connector);
6556         struct drm_crtc *possible_crtc;
6557         struct drm_encoder *encoder = &intel_encoder->base;
6558         struct drm_crtc *crtc = NULL;
6559         struct drm_device *dev = encoder->dev;
6560         struct drm_framebuffer *fb;
6561         int i = -1;
6562
6563         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6564                       connector->base.id, drm_get_connector_name(connector),
6565                       encoder->base.id, drm_get_encoder_name(encoder));
6566
6567         /*
6568          * Algorithm gets a little messy:
6569          *
6570          *   - if the connector already has an assigned crtc, use it (but make
6571          *     sure it's on first)
6572          *
6573          *   - try to find the first unused crtc that can drive this connector,
6574          *     and use that if we find one
6575          */
6576
6577         /* See if we already have a CRTC for this connector */
6578         if (encoder->crtc) {
6579                 crtc = encoder->crtc;
6580
6581                 mutex_lock(&crtc->mutex);
6582
6583                 old->dpms_mode = connector->dpms;
6584                 old->load_detect_temp = false;
6585
6586                 /* Make sure the crtc and connector are running */
6587                 if (connector->dpms != DRM_MODE_DPMS_ON)
6588                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6589
6590                 return true;
6591         }
6592
6593         /* Find an unused one (if possible) */
6594         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6595                 i++;
6596                 if (!(encoder->possible_crtcs & (1 << i)))
6597                         continue;
6598                 if (!possible_crtc->enabled) {
6599                         crtc = possible_crtc;
6600                         break;
6601                 }
6602         }
6603
6604         /*
6605          * If we didn't find an unused CRTC, don't use any.
6606          */
6607         if (!crtc) {
6608                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6609                 return false;
6610         }
6611
6612         mutex_lock(&crtc->mutex);
6613         intel_encoder->new_crtc = to_intel_crtc(crtc);
6614         to_intel_connector(connector)->new_encoder = intel_encoder;
6615
6616         intel_crtc = to_intel_crtc(crtc);
6617         old->dpms_mode = connector->dpms;
6618         old->load_detect_temp = true;
6619         old->release_fb = NULL;
6620
6621         if (!mode)
6622                 mode = &load_detect_mode;
6623
6624         /* We need a framebuffer large enough to accommodate all accesses
6625          * that the plane may generate whilst we perform load detection.
6626          * We can not rely on the fbcon either being present (we get called
6627          * during its initialisation to detect all boot displays, or it may
6628          * not even exist) or that it is large enough to satisfy the
6629          * requested mode.
6630          */
6631         fb = mode_fits_in_fbdev(dev, mode);
6632         if (fb == NULL) {
6633                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6634                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6635                 old->release_fb = fb;
6636         } else
6637                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6638         if (IS_ERR(fb)) {
6639                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6640                 mutex_unlock(&crtc->mutex);
6641                 return false;
6642         }
6643
6644         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6645                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6646                 if (old->release_fb)
6647                         old->release_fb->funcs->destroy(old->release_fb);
6648                 mutex_unlock(&crtc->mutex);
6649                 return false;
6650         }
6651
6652         /* let the connector get through one full cycle before testing */
6653         intel_wait_for_vblank(dev, intel_crtc->pipe);
6654         return true;
6655 }
6656
6657 void intel_release_load_detect_pipe(struct drm_connector *connector,
6658                                     struct intel_load_detect_pipe *old)
6659 {
6660         struct intel_encoder *intel_encoder =
6661                 intel_attached_encoder(connector);
6662         struct drm_encoder *encoder = &intel_encoder->base;
6663         struct drm_crtc *crtc = encoder->crtc;
6664
6665         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6666                       connector->base.id, drm_get_connector_name(connector),
6667                       encoder->base.id, drm_get_encoder_name(encoder));
6668
6669         if (old->load_detect_temp) {
6670                 to_intel_connector(connector)->new_encoder = NULL;
6671                 intel_encoder->new_crtc = NULL;
6672                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6673
6674                 if (old->release_fb) {
6675                         drm_framebuffer_unregister_private(old->release_fb);
6676                         drm_framebuffer_unreference(old->release_fb);
6677                 }
6678
6679                 mutex_unlock(&crtc->mutex);
6680                 return;
6681         }
6682
6683         /* Switch crtc and encoder back off if necessary */
6684         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6685                 connector->funcs->dpms(connector, old->dpms_mode);
6686
6687         mutex_unlock(&crtc->mutex);
6688 }
6689
6690 /* Returns the clock of the currently programmed mode of the given pipe. */
6691 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6692 {
6693         struct drm_i915_private *dev_priv = dev->dev_private;
6694         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6695         int pipe = intel_crtc->pipe;
6696         u32 dpll = I915_READ(DPLL(pipe));
6697         u32 fp;
6698         intel_clock_t clock;
6699
6700         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6701                 fp = I915_READ(FP0(pipe));
6702         else
6703                 fp = I915_READ(FP1(pipe));
6704
6705         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6706         if (IS_PINEVIEW(dev)) {
6707                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6708                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6709         } else {
6710                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6711                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6712         }
6713
6714         if (!IS_GEN2(dev)) {
6715                 if (IS_PINEVIEW(dev))
6716                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6717                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6718                 else
6719                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6720                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6721
6722                 switch (dpll & DPLL_MODE_MASK) {
6723                 case DPLLB_MODE_DAC_SERIAL:
6724                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6725                                 5 : 10;
6726                         break;
6727                 case DPLLB_MODE_LVDS:
6728                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6729                                 7 : 14;
6730                         break;
6731                 default:
6732                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6733                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6734                         return 0;
6735                 }
6736
6737                 /* XXX: Handle the 100Mhz refclk */
6738                 intel_clock(dev, 96000, &clock);
6739         } else {
6740                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6741
6742                 if (is_lvds) {
6743                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6744                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6745                         clock.p2 = 14;
6746
6747                         if ((dpll & PLL_REF_INPUT_MASK) ==
6748                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6749                                 /* XXX: might not be 66MHz */
6750                                 intel_clock(dev, 66000, &clock);
6751                         } else
6752                                 intel_clock(dev, 48000, &clock);
6753                 } else {
6754                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6755                                 clock.p1 = 2;
6756                         else {
6757                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6758                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6759                         }
6760                         if (dpll & PLL_P2_DIVIDE_BY_4)
6761                                 clock.p2 = 4;
6762                         else
6763                                 clock.p2 = 2;
6764
6765                         intel_clock(dev, 48000, &clock);
6766                 }
6767         }
6768
6769         /* XXX: It would be nice to validate the clocks, but we can't reuse
6770          * i830PllIsValid() because it relies on the xf86_config connector
6771          * configuration being accurate, which it isn't necessarily.
6772          */
6773
6774         return clock.dot;
6775 }
6776
6777 /** Returns the currently programmed mode of the given pipe. */
6778 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6779                                              struct drm_crtc *crtc)
6780 {
6781         struct drm_i915_private *dev_priv = dev->dev_private;
6782         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6783         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6784         struct drm_display_mode *mode;
6785         int htot = I915_READ(HTOTAL(cpu_transcoder));
6786         int hsync = I915_READ(HSYNC(cpu_transcoder));
6787         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6788         int vsync = I915_READ(VSYNC(cpu_transcoder));
6789
6790         mode = kmalloc(sizeof(*mode), M_DRM, M_WAITOK | M_ZERO);
6791         if (!mode)
6792                 return NULL;
6793
6794         mode->clock = intel_crtc_clock_get(dev, crtc);
6795         mode->hdisplay = (htot & 0xffff) + 1;
6796         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6797         mode->hsync_start = (hsync & 0xffff) + 1;
6798         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6799         mode->vdisplay = (vtot & 0xffff) + 1;
6800         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6801         mode->vsync_start = (vsync & 0xffff) + 1;
6802         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6803
6804         drm_mode_set_name(mode);
6805
6806         return mode;
6807 }
6808
6809 static void intel_increase_pllclock(struct drm_crtc *crtc)
6810 {
6811         struct drm_device *dev = crtc->dev;
6812         drm_i915_private_t *dev_priv = dev->dev_private;
6813         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6814         int pipe = intel_crtc->pipe;
6815         int dpll_reg = DPLL(pipe);
6816         int dpll;
6817
6818         if (HAS_PCH_SPLIT(dev))
6819                 return;
6820
6821         if (!dev_priv->lvds_downclock_avail)
6822                 return;
6823
6824         dpll = I915_READ(dpll_reg);
6825         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6826                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6827
6828                 assert_panel_unlocked(dev_priv, pipe);
6829
6830                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6831                 I915_WRITE(dpll_reg, dpll);
6832                 intel_wait_for_vblank(dev, pipe);
6833
6834                 dpll = I915_READ(dpll_reg);
6835                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6836                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6837         }
6838 }
6839
6840 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6841 {
6842         struct drm_device *dev = crtc->dev;
6843         drm_i915_private_t *dev_priv = dev->dev_private;
6844         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6845
6846         if (HAS_PCH_SPLIT(dev))
6847                 return;
6848
6849         if (!dev_priv->lvds_downclock_avail)
6850                 return;
6851
6852         /*
6853          * Since this is called by a timer, we should never get here in
6854          * the manual case.
6855          */
6856         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6857                 int pipe = intel_crtc->pipe;
6858                 int dpll_reg = DPLL(pipe);
6859                 int dpll;
6860
6861                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6862
6863                 assert_panel_unlocked(dev_priv, pipe);
6864
6865                 dpll = I915_READ(dpll_reg);
6866                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6867                 I915_WRITE(dpll_reg, dpll);
6868                 intel_wait_for_vblank(dev, pipe);
6869                 dpll = I915_READ(dpll_reg);
6870                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6871                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6872         }
6873 }
6874
6875 void intel_mark_busy(struct drm_device *dev)
6876 {
6877         i915_update_gfx_val(dev->dev_private);
6878 }
6879
6880 void intel_mark_idle(struct drm_device *dev)
6881 {
6882         struct drm_crtc *crtc;
6883
6884         if (!i915_powersave)
6885                 return;
6886
6887         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6888                 if (!crtc->fb)
6889                         continue;
6890
6891                 intel_decrease_pllclock(crtc);
6892         }
6893 }
6894
6895 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6896 {
6897         struct drm_device *dev = obj->base.dev;
6898         struct drm_crtc *crtc;
6899
6900         if (!i915_powersave)
6901                 return;
6902
6903         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6904                 if (!crtc->fb)
6905                         continue;
6906
6907                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6908                         intel_increase_pllclock(crtc);
6909         }
6910 }
6911
6912 static void intel_crtc_destroy(struct drm_crtc *crtc)
6913 {
6914         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6915         struct drm_device *dev = crtc->dev;
6916         struct intel_unpin_work *work;
6917
6918         lockmgr(&dev->event_lock, LK_EXCLUSIVE);
6919         work = intel_crtc->unpin_work;
6920         intel_crtc->unpin_work = NULL;
6921         lockmgr(&dev->event_lock, LK_RELEASE);
6922
6923         if (work) {
6924                 cancel_work_sync(&work->work);
6925                 kfree(work, M_DRM);
6926         }
6927
6928         drm_crtc_cleanup(crtc);
6929
6930         drm_free(intel_crtc, M_DRM);
6931 }
6932
6933 static void intel_unpin_work_fn(struct work_struct *__work)
6934 {
6935         struct intel_unpin_work *work =
6936                 container_of(__work, struct intel_unpin_work, work);
6937         struct drm_device *dev = work->crtc->dev;
6938
6939         mutex_lock(&dev->struct_mutex);
6940         intel_unpin_fb_obj(work->old_fb_obj);
6941         drm_gem_object_unreference(&work->pending_flip_obj->base);
6942         drm_gem_object_unreference(&work->old_fb_obj->base);
6943
6944         intel_update_fbc(dev);
6945         mutex_unlock(&dev->struct_mutex);
6946
6947         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6948         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6949
6950         drm_free(work, M_DRM);
6951 }
6952
6953 static void do_intel_finish_page_flip(struct drm_device *dev,
6954                                       struct drm_crtc *crtc)
6955 {
6956         drm_i915_private_t *dev_priv = dev->dev_private;
6957         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6958         struct intel_unpin_work *work;
6959         struct drm_i915_gem_object *obj;
6960
6961         /* Ignore early vblank irqs */
6962         if (intel_crtc == NULL)
6963                 return;
6964
6965         lockmgr(&dev->event_lock, LK_EXCLUSIVE);
6966         work = intel_crtc->unpin_work;
6967
6968         /* Ensure we don't miss a work->pending update ... */
6969         cpu_lfence();
6970
6971         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6972                 lockmgr(&dev->event_lock, LK_RELEASE);
6973                 return;
6974         }
6975
6976         /* and that the unpin work is consistent wrt ->pending. */
6977         cpu_lfence();
6978
6979         intel_crtc->unpin_work = NULL;
6980
6981         if (work->event)
6982                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6983
6984         drm_vblank_put(dev, intel_crtc->pipe);
6985
6986         lockmgr(&dev->event_lock, LK_RELEASE);
6987
6988         obj = work->old_fb_obj;
6989
6990         wake_up_all(&dev_priv->pending_flip_queue);
6991
6992         queue_work(dev_priv->wq, &work->work);
6993 }
6994
6995 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6996 {
6997         drm_i915_private_t *dev_priv = dev->dev_private;
6998         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6999
7000         do_intel_finish_page_flip(dev, crtc);
7001 }
7002
7003 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7004 {
7005         drm_i915_private_t *dev_priv = dev->dev_private;
7006         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7007
7008         do_intel_finish_page_flip(dev, crtc);
7009 }
7010
7011 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7012 {
7013         drm_i915_private_t *dev_priv = dev->dev_private;
7014         struct intel_crtc *intel_crtc =
7015                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7016
7017         /* NB: An MMIO update of the plane base pointer will also
7018          * generate a page-flip completion irq, i.e. every modeset
7019          * is also accompanied by a spurious intel_prepare_page_flip().
7020          */
7021         lockmgr(&dev->event_lock, LK_EXCLUSIVE);
7022         if (intel_crtc->unpin_work)
7023                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7024         lockmgr(&dev->event_lock, LK_RELEASE);
7025 }
7026
7027 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7028 {
7029         /* Ensure that the work item is consistent when activating it ... */
7030         cpu_sfence();
7031         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7032         /* and that it is marked active as soon as the irq could fire. */
7033         cpu_sfence();
7034 }
7035
7036 static int intel_gen2_queue_flip(struct drm_device *dev,
7037                                  struct drm_crtc *crtc,
7038                                  struct drm_framebuffer *fb,
7039                                  struct drm_i915_gem_object *obj)
7040 {
7041         struct drm_i915_private *dev_priv = dev->dev_private;
7042         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7043         u32 flip_mask;
7044         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7045         int ret;
7046
7047         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7048         if (ret)
7049                 goto err;
7050
7051         ret = intel_ring_begin(ring, 6);
7052         if (ret)
7053                 goto err_unpin;
7054
7055         /* Can't queue multiple flips, so wait for the previous
7056          * one to finish before executing the next.
7057          */
7058         if (intel_crtc->plane)
7059                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7060         else
7061                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7062         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7063         intel_ring_emit(ring, MI_NOOP);
7064         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7065                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7066         intel_ring_emit(ring, fb->pitches[0]);
7067         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7068         intel_ring_emit(ring, 0); /* aux display base address, unused */
7069
7070         intel_mark_page_flip_active(intel_crtc);
7071         intel_ring_advance(ring);
7072         return 0;
7073
7074 err_unpin:
7075         intel_unpin_fb_obj(obj);
7076 err:
7077         return ret;
7078 }
7079
7080 static int intel_gen3_queue_flip(struct drm_device *dev,
7081                                  struct drm_crtc *crtc,
7082                                  struct drm_framebuffer *fb,
7083                                  struct drm_i915_gem_object *obj)
7084 {
7085         struct drm_i915_private *dev_priv = dev->dev_private;
7086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7087         u32 flip_mask;
7088         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7089         int ret;
7090
7091         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7092         if (ret)
7093                 goto err;
7094
7095         ret = intel_ring_begin(ring, 6);
7096         if (ret)
7097                 goto err_unpin;
7098
7099         if (intel_crtc->plane)
7100                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7101         else
7102                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7103         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7104         intel_ring_emit(ring, MI_NOOP);
7105         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7106                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7107         intel_ring_emit(ring, fb->pitches[0]);
7108         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7109         intel_ring_emit(ring, MI_NOOP);
7110
7111         intel_mark_page_flip_active(intel_crtc);
7112         intel_ring_advance(ring);
7113         return 0;
7114
7115 err_unpin:
7116         intel_unpin_fb_obj(obj);
7117 err:
7118         return ret;
7119 }
7120
7121 static int intel_gen4_queue_flip(struct drm_device *dev,
7122                                  struct drm_crtc *crtc,
7123                                  struct drm_framebuffer *fb,
7124                                  struct drm_i915_gem_object *obj)
7125 {
7126         struct drm_i915_private *dev_priv = dev->dev_private;
7127         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7128         uint32_t pf, pipesrc;
7129         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7130         int ret;
7131
7132         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7133         if (ret)
7134                 goto err;
7135
7136         ret = intel_ring_begin(ring, 4);
7137         if (ret)
7138                 goto err_unpin;
7139
7140         /* i965+ uses the linear or tiled offsets from the
7141          * Display Registers (which do not change across a page-flip)
7142          * so we need only reprogram the base address.
7143          */
7144         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7145                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7146         intel_ring_emit(ring, fb->pitches[0]);
7147         intel_ring_emit(ring,
7148                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7149                         obj->tiling_mode);
7150
7151         /* XXX Enabling the panel-fitter across page-flip is so far
7152          * untested on non-native modes, so ignore it for now.
7153          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7154          */
7155         pf = 0;
7156         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7157         intel_ring_emit(ring, pf | pipesrc);
7158
7159         intel_mark_page_flip_active(intel_crtc);
7160         intel_ring_advance(ring);
7161         return 0;
7162
7163 err_unpin:
7164         intel_unpin_fb_obj(obj);
7165 err:
7166         return ret;
7167 }
7168
7169 static int intel_gen6_queue_flip(struct drm_device *dev,
7170                                  struct drm_crtc *crtc,
7171                                  struct drm_framebuffer *fb,
7172                                  struct drm_i915_gem_object *obj)
7173 {
7174         struct drm_i915_private *dev_priv = dev->dev_private;
7175         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7176         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7177         uint32_t pf, pipesrc;
7178         int ret;
7179
7180         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7181         if (ret)
7182                 goto err;
7183
7184         ret = intel_ring_begin(ring, 4);
7185         if (ret)
7186                 goto err_unpin;
7187
7188         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7189                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7190         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7191         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7192
7193         /* Contrary to the suggestions in the documentation,
7194          * "Enable Panel Fitter" does not seem to be required when page
7195          * flipping with a non-native mode, and worse causes a normal
7196          * modeset to fail.
7197          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7198          */
7199         pf = 0;
7200         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7201         intel_ring_emit(ring, pf | pipesrc);
7202
7203         intel_mark_page_flip_active(intel_crtc);
7204         intel_ring_advance(ring);
7205         return 0;
7206
7207 err_unpin:
7208         intel_unpin_fb_obj(obj);
7209 err:
7210         return ret;
7211 }
7212
7213 /*
7214  * On gen7 we currently use the blit ring because (in early silicon at least)
7215  * the render ring doesn't give us interrpts for page flip completion, which
7216  * means clients will hang after the first flip is queued.  Fortunately the
7217  * blit ring generates interrupts properly, so use it instead.
7218  */
7219 static int intel_gen7_queue_flip(struct drm_device *dev,
7220                                  struct drm_crtc *crtc,
7221                                  struct drm_framebuffer *fb,
7222                                  struct drm_i915_gem_object *obj)
7223 {
7224         struct drm_i915_private *dev_priv = dev->dev_private;
7225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7226         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7227         uint32_t plane_bit = 0;
7228         int ret;
7229
7230         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7231         if (ret)
7232                 goto err;
7233
7234         switch(intel_crtc->plane) {
7235         case PLANE_A:
7236                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7237                 break;
7238         case PLANE_B:
7239                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7240                 break;
7241         case PLANE_C:
7242                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7243                 break;
7244         default:
7245                 WARN_ONCE(1, "unknown plane in flip command\n");
7246                 ret = -ENODEV;
7247                 goto err_unpin;
7248         }
7249
7250         ret = intel_ring_begin(ring, 4);
7251         if (ret)
7252                 goto err_unpin;
7253
7254         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7255         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7256         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7257         intel_ring_emit(ring, (MI_NOOP));
7258
7259         intel_mark_page_flip_active(intel_crtc);
7260         intel_ring_advance(ring);
7261         return 0;
7262
7263 err_unpin:
7264         intel_unpin_fb_obj(obj);
7265 err:
7266         return ret;
7267 }
7268
7269 static int intel_default_queue_flip(struct drm_device *dev,
7270                                     struct drm_crtc *crtc,
7271                                     struct drm_framebuffer *fb,
7272                                     struct drm_i915_gem_object *obj)
7273 {
7274         return -ENODEV;
7275 }
7276
7277 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7278                                 struct drm_framebuffer *fb,
7279                                 struct drm_pending_vblank_event *event)
7280 {
7281         struct drm_device *dev = crtc->dev;
7282         struct drm_i915_private *dev_priv = dev->dev_private;
7283         struct drm_framebuffer *old_fb = crtc->fb;
7284         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7285         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7286         struct intel_unpin_work *work;
7287         int ret;
7288
7289         /* Can't change pixel format via MI display flips. */
7290         if (fb->pixel_format != crtc->fb->pixel_format)
7291                 return -EINVAL;
7292
7293         /*
7294          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7295          * Note that pitch changes could also affect these register.
7296          */
7297         if (INTEL_INFO(dev)->gen > 3 &&
7298             (fb->offsets[0] != crtc->fb->offsets[0] ||
7299              fb->pitches[0] != crtc->fb->pitches[0]))
7300                 return -EINVAL;
7301
7302         work = kmalloc(sizeof *work, M_DRM, M_WAITOK | M_ZERO);
7303         if (work == NULL)
7304                 return -ENOMEM;
7305
7306         work->event = event;
7307         work->crtc = crtc;
7308         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7309         INIT_WORK(&work->work, intel_unpin_work_fn);
7310
7311         ret = drm_vblank_get(dev, intel_crtc->pipe);
7312         if (ret)
7313                 goto free_work;
7314
7315         /* We borrow the event spin lock for protecting unpin_work */
7316         lockmgr(&dev->event_lock, LK_EXCLUSIVE);
7317         if (intel_crtc->unpin_work) {
7318                 lockmgr(&dev->event_lock, LK_RELEASE);
7319                 drm_free(work, M_DRM);
7320                 drm_vblank_put(dev, intel_crtc->pipe);
7321
7322                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7323                 return -EBUSY;
7324         }
7325         intel_crtc->unpin_work = work;
7326         lockmgr(&dev->event_lock, LK_RELEASE);
7327
7328         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7329                 flush_workqueue(dev_priv->wq);
7330
7331         ret = i915_mutex_lock_interruptible(dev);
7332         if (ret)
7333                 goto cleanup;
7334
7335         /* Reference the objects for the scheduled work. */
7336         drm_gem_object_reference(&work->old_fb_obj->base);
7337         drm_gem_object_reference(&obj->base);
7338
7339         crtc->fb = fb;
7340
7341         work->pending_flip_obj = obj;
7342
7343         work->enable_stall_check = true;
7344
7345         atomic_inc(&intel_crtc->unpin_work_count);
7346         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7347
7348         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7349         if (ret)
7350                 goto cleanup_pending;
7351
7352         intel_disable_fbc(dev);
7353         intel_mark_fb_busy(obj);
7354         mutex_unlock(&dev->struct_mutex);
7355
7356         return 0;
7357
7358 cleanup_pending:
7359         atomic_dec(&intel_crtc->unpin_work_count);
7360         crtc->fb = old_fb;
7361         drm_gem_object_unreference(&work->old_fb_obj->base);
7362         drm_gem_object_unreference(&obj->base);
7363         mutex_unlock(&dev->struct_mutex);
7364
7365 cleanup:
7366         lockmgr(&dev->event_lock, LK_EXCLUSIVE);
7367         intel_crtc->unpin_work = NULL;
7368         lockmgr(&dev->event_lock, LK_RELEASE);
7369
7370         drm_vblank_put(dev, intel_crtc->pipe);
7371 free_work:
7372         drm_free(work, M_DRM);
7373
7374         return ret;
7375 }
7376
7377 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7378         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7379         .load_lut = intel_crtc_load_lut,
7380         .disable = intel_crtc_noop,
7381 };
7382
7383 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7384 {
7385         struct intel_encoder *other_encoder;
7386         struct drm_crtc *crtc = &encoder->new_crtc->base;
7387
7388         if (WARN_ON(!crtc))
7389                 return false;
7390
7391         list_for_each_entry(other_encoder,
7392                             &crtc->dev->mode_config.encoder_list,
7393                             base.head) {
7394
7395                 if (&other_encoder->new_crtc->base != crtc ||
7396                     encoder == other_encoder)
7397                         continue;
7398                 else
7399                         return true;
7400         }
7401
7402         return false;
7403 }
7404
7405 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7406                                   struct drm_crtc *crtc)
7407 {
7408         struct drm_device *dev;
7409         struct drm_crtc *tmp;
7410         int crtc_mask = 1;
7411
7412         WARN(!crtc, "checking null crtc?\n");
7413         /* profmakx: this is to prevent the kernel from panicing */
7414         if(!crtc) {
7415                 return false;
7416         }
7417
7418         dev = crtc->dev;
7419
7420         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7421                 if (tmp == crtc)
7422                         break;
7423                 crtc_mask <<= 1;
7424         }
7425
7426         if (encoder->possible_crtcs & crtc_mask)
7427                 return true;
7428         return false;
7429 }
7430
7431 /**
7432  * intel_modeset_update_staged_output_state
7433  *
7434  * Updates the staged output configuration state, e.g. after we've read out the
7435  * current hw state.
7436  */
7437 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7438 {
7439         struct intel_encoder *encoder;
7440         struct intel_connector *connector;
7441
7442         list_for_each_entry(connector, &dev->mode_config.connector_list,
7443                             base.head) {
7444                 connector->new_encoder =
7445                         to_intel_encoder(connector->base.encoder);
7446         }
7447
7448         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7449                             base.head) {
7450                 encoder->new_crtc =
7451                         to_intel_crtc(encoder->base.crtc);
7452         }
7453 }
7454
7455 /**
7456  * intel_modeset_commit_output_state
7457  *
7458  * This function copies the stage display pipe configuration to the real one.
7459  */
7460 static void intel_modeset_commit_output_state(struct drm_device *dev)
7461 {
7462         struct intel_encoder *encoder;
7463         struct intel_connector *connector;
7464
7465         list_for_each_entry(connector, &dev->mode_config.connector_list,
7466                             base.head) {
7467                 connector->base.encoder = &connector->new_encoder->base;
7468         }
7469
7470         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7471                             base.head) {
7472                 encoder->base.crtc = &encoder->new_crtc->base;
7473         }
7474 }
7475
7476 static struct drm_display_mode *
7477 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7478                             struct drm_display_mode *mode)
7479 {
7480         struct drm_device *dev = crtc->dev;
7481         struct drm_display_mode *adjusted_mode;
7482         struct drm_encoder_helper_funcs *encoder_funcs;
7483         struct intel_encoder *encoder;
7484
7485         adjusted_mode = drm_mode_duplicate(dev, mode);
7486         if (!adjusted_mode)
7487                 return ERR_PTR(-ENOMEM);
7488
7489         /* Pass our mode to the connectors and the CRTC to give them a chance to
7490          * adjust it according to limitations or connector properties, and also
7491          * a chance to reject the mode entirely.
7492          */
7493         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7494                             base.head) {
7495
7496                 if (&encoder->new_crtc->base != crtc)
7497                         continue;
7498                 encoder_funcs = encoder->base.helper_private;
7499                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7500                                                 adjusted_mode))) {
7501                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7502                         goto fail;
7503                 }
7504         }
7505
7506         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7507                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7508                 goto fail;
7509         }
7510         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7511
7512         return adjusted_mode;
7513 fail:
7514         drm_mode_destroy(dev, adjusted_mode);
7515         return ERR_PTR(-EINVAL);
7516 }
7517
7518 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7519  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7520 static void
7521 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7522                              unsigned *prepare_pipes, unsigned *disable_pipes)
7523 {
7524         struct intel_crtc *intel_crtc;
7525         struct drm_device *dev = crtc->dev;
7526         struct intel_encoder *encoder;
7527         struct intel_connector *connector;
7528         struct drm_crtc *tmp_crtc;
7529
7530         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7531
7532         /* Check which crtcs have changed outputs connected to them, these need
7533          * to be part of the prepare_pipes mask. We don't (yet) support global
7534          * modeset across multiple crtcs, so modeset_pipes will only have one
7535          * bit set at most. */
7536         list_for_each_entry(connector, &dev->mode_config.connector_list,
7537                             base.head) {
7538                 if (connector->base.encoder == &connector->new_encoder->base)
7539                         continue;
7540
7541                 if (connector->base.encoder) {
7542                         tmp_crtc = connector->base.encoder->crtc;
7543
7544                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7545                 }
7546
7547                 if (connector->new_encoder)
7548                         *prepare_pipes |=
7549                                 1 << connector->new_encoder->new_crtc->pipe;
7550         }
7551
7552         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7553                             base.head) {
7554                 if (encoder->base.crtc == &encoder->new_crtc->base)
7555                         continue;
7556
7557                 if (encoder->base.crtc) {
7558                         tmp_crtc = encoder->base.crtc;
7559
7560                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7561                 }
7562
7563                 if (encoder->new_crtc)
7564                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7565         }
7566
7567         /* Check for any pipes that will be fully disabled ... */
7568         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7569                             base.head) {
7570                 bool used = false;
7571
7572                 /* Don't try to disable disabled crtcs. */
7573                 if (!intel_crtc->base.enabled)
7574                         continue;
7575
7576                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7577                                     base.head) {
7578                         if (encoder->new_crtc == intel_crtc)
7579                                 used = true;
7580                 }
7581
7582                 if (!used)
7583                         *disable_pipes |= 1 << intel_crtc->pipe;
7584         }
7585
7586
7587         /* set_mode is also used to update properties on life display pipes. */
7588         intel_crtc = to_intel_crtc(crtc);
7589         if (crtc->enabled)
7590                 *prepare_pipes |= 1 << intel_crtc->pipe;
7591
7592         /*
7593          * For simplicity do a full modeset on any pipe where the output routing
7594          * changed. We could be more clever, but that would require us to be
7595          * more careful with calling the relevant encoder->mode_set functions.
7596          */
7597         if (*prepare_pipes)
7598                 *modeset_pipes = *prepare_pipes;
7599
7600         /* ... and mask these out. */
7601         *modeset_pipes &= ~(*disable_pipes);
7602         *prepare_pipes &= ~(*disable_pipes);
7603
7604         /*
7605          * HACK: We don't (yet) fully support global modesets. intel_set_config
7606          * obies this rule, but the modeset restore mode of
7607          * intel_modeset_setup_hw_state does not.
7608          */
7609         *modeset_pipes &= 1 << intel_crtc->pipe;
7610         *prepare_pipes &= 1 << intel_crtc->pipe;
7611 }
7612
7613 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7614 {
7615         struct drm_encoder *encoder;
7616         struct drm_device *dev = crtc->dev;
7617
7618         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7619                 if (encoder->crtc == crtc)
7620                         return true;
7621
7622         return false;
7623 }
7624
7625 static void
7626 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7627 {
7628         struct intel_encoder *intel_encoder;
7629         struct intel_crtc *intel_crtc;
7630         struct drm_connector *connector;
7631
7632         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7633                             base.head) {
7634                 if (!intel_encoder->base.crtc)
7635                         continue;
7636
7637                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7638
7639                 if (prepare_pipes & (1 << intel_crtc->pipe))
7640                         intel_encoder->connectors_active = false;
7641         }
7642
7643         intel_modeset_commit_output_state(dev);
7644
7645         /* Update computed state. */
7646         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7647                             base.head) {
7648                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7649         }
7650
7651         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7652                 if (!connector->encoder || !connector->encoder->crtc)
7653                         continue;
7654
7655                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7656
7657                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7658                         struct drm_property *dpms_property =
7659                                 dev->mode_config.dpms_property;
7660
7661                         connector->dpms = DRM_MODE_DPMS_ON;
7662                         drm_object_property_set_value(&connector->base,
7663                                                          dpms_property,
7664                                                          DRM_MODE_DPMS_ON);
7665
7666                         intel_encoder = to_intel_encoder(connector->encoder);
7667                         intel_encoder->connectors_active = true;
7668                 }
7669         }
7670
7671 }
7672
7673 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7674         list_for_each_entry((intel_crtc), \
7675                             &(dev)->mode_config.crtc_list, \
7676                             base.head) \
7677                 if (mask & (1 <<(intel_crtc)->pipe)) \
7678
7679 void
7680 intel_modeset_check_state(struct drm_device *dev)
7681 {
7682         struct intel_crtc *crtc;
7683         struct intel_encoder *encoder;
7684         struct intel_connector *connector;
7685
7686         list_for_each_entry(connector, &dev->mode_config.connector_list,
7687                             base.head) {
7688                 /* This also checks the encoder/connector hw state with the
7689                  * ->get_hw_state callbacks. */
7690                 intel_connector_check_state(connector);
7691
7692                 WARN(&connector->new_encoder->base != connector->base.encoder,
7693                      "connector's staged encoder doesn't match current encoder\n");
7694         }
7695
7696         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7697                             base.head) {
7698                 bool enabled = false;
7699                 bool active = false;
7700                 enum i915_pipe pipe, tracked_pipe;
7701
7702                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7703                               encoder->base.base.id,
7704                               drm_get_encoder_name(&encoder->base));
7705
7706                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7707                      "encoder's stage crtc doesn't match current crtc\n");
7708                 WARN(encoder->connectors_active && !encoder->base.crtc,
7709                      "encoder's active_connectors set, but no crtc\n");
7710
7711                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7712                                     base.head) {
7713                         if (connector->base.encoder != &encoder->base)
7714                                 continue;
7715                         enabled = true;
7716                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7717                                 active = true;
7718                 }
7719                 WARN(!!encoder->base.crtc != enabled,
7720                      "encoder's enabled state mismatch "
7721                      "(expected %i, found %i)\n",
7722                      !!encoder->base.crtc, enabled);
7723                 WARN(active && !encoder->base.crtc,
7724                      "active encoder with no crtc\n");
7725
7726                 WARN(encoder->connectors_active != active,
7727                      "encoder's computed active state doesn't match tracked active state "
7728                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7729
7730                 active = encoder->get_hw_state(encoder, &pipe);
7731                 WARN(active != encoder->connectors_active,
7732                      "encoder's hw state doesn't match sw tracking "
7733                      "(expected %i, found %i)\n",
7734                      encoder->connectors_active, active);
7735
7736                 if (!encoder->base.crtc)
7737                         continue;
7738
7739                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7740                 WARN(active && pipe != tracked_pipe,
7741                      "active encoder's pipe doesn't match"
7742                      "(expected %i, found %i)\n",
7743                      tracked_pipe, pipe);
7744
7745         }
7746
7747         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7748                             base.head) {
7749                 bool enabled = false;
7750                 bool active = false;
7751
7752                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7753                               crtc->base.base.id);
7754
7755                 WARN(crtc->active && !crtc->base.enabled,
7756                      "active crtc, but not enabled in sw tracking\n");
7757
7758                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7759                                     base.head) {
7760                         if (encoder->base.crtc != &crtc->base)
7761                                 continue;
7762                         enabled = true;
7763                         if (encoder->connectors_active)
7764                                 active = true;
7765                 }
7766                 WARN(active != crtc->active,
7767                      "crtc's computed active state doesn't match tracked active state "
7768                      "(expected %i, found %i)\n", active, crtc->active);
7769                 WARN(enabled != crtc->base.enabled,
7770                      "crtc's computed enabled state doesn't match tracked enabled state "
7771                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7772
7773                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7774         }
7775 }
7776
7777 static int __intel_set_mode(struct drm_crtc *crtc,
7778                             struct drm_display_mode *mode,
7779                             int x, int y, struct drm_framebuffer *fb)
7780 {
7781         struct drm_device *dev = crtc->dev;
7782         drm_i915_private_t *dev_priv = dev->dev_private;
7783         struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode;
7784         struct intel_crtc *intel_crtc;
7785         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7786         int ret = 0;
7787
7788         saved_mode = kmalloc(2 * sizeof(*saved_mode), M_DRM, M_WAITOK);
7789         if (!saved_mode)
7790                 return -ENOMEM;
7791         saved_hwmode = saved_mode + 1;
7792
7793         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7794                                      &prepare_pipes, &disable_pipes);
7795
7796         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7797                       modeset_pipes, prepare_pipes, disable_pipes);
7798
7799         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7800                 intel_crtc_disable(&intel_crtc->base);
7801
7802         *saved_hwmode = crtc->hwmode;
7803         *saved_mode = crtc->mode;
7804
7805         /* Hack: Because we don't (yet) support global modeset on multiple
7806          * crtcs, we don't keep track of the new mode for more than one crtc.
7807          * Hence simply check whether any bit is set in modeset_pipes in all the
7808          * pieces of code that are not yet converted to deal with mutliple crtcs
7809          * changing their mode at the same time. */
7810         adjusted_mode = NULL;
7811         if (modeset_pipes) {
7812                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7813                 if (IS_ERR(adjusted_mode)) {
7814                         ret = PTR_ERR(adjusted_mode);
7815                         goto out;
7816                 }
7817         }
7818
7819         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7820                 if (intel_crtc->base.enabled)
7821                         dev_priv->display.crtc_disable(&intel_crtc->base);
7822         }
7823
7824         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7825          * to set it here already despite that we pass it down the callchain.
7826          */
7827         if (modeset_pipes)
7828                 crtc->mode = *mode;
7829
7830         /* Only after disabling all output pipelines that will be changed can we
7831          * update the the output configuration. */
7832         intel_modeset_update_state(dev, prepare_pipes);
7833
7834         if (dev_priv->display.modeset_global_resources)
7835                 dev_priv->display.modeset_global_resources(dev);
7836
7837         /* Set up the DPLL and any encoders state that needs to adjust or depend
7838          * on the DPLL.
7839          */
7840         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7841                 ret = intel_crtc_mode_set(&intel_crtc->base,
7842                                           mode, adjusted_mode,
7843                                           x, y, fb);
7844                 if (ret)
7845                         goto done;
7846         }
7847
7848         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7849         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7850                 dev_priv->display.crtc_enable(&intel_crtc->base);
7851
7852         if (modeset_pipes) {
7853                 /* Store real post-adjustment hardware mode. */
7854                 crtc->hwmode = *adjusted_mode;
7855
7856                 /* Calculate and store various constants which
7857                  * are later needed by vblank and swap-completion
7858                  * timestamping. They are derived from true hwmode.
7859                  */
7860                 drm_calc_timestamping_constants(crtc);
7861         }
7862
7863         /* FIXME: add subpixel order */
7864 done:
7865         drm_mode_destroy(dev, adjusted_mode);
7866         if (ret && crtc->enabled) {
7867                 crtc->hwmode = *saved_hwmode;
7868                 crtc->mode = *saved_mode;
7869         }
7870
7871 out:
7872         kfree(saved_mode, M_DRM);
7873         return ret;
7874 }
7875
7876 int intel_set_mode(struct drm_crtc *crtc,
7877                      struct drm_display_mode *mode,
7878                      int x, int y, struct drm_framebuffer *fb)
7879 {
7880         int ret;
7881
7882         ret = __intel_set_mode(crtc, mode, x, y, fb);
7883
7884         if (ret == 0)
7885                 intel_modeset_check_state(crtc->dev);
7886
7887         return ret;
7888 }
7889
7890 void intel_crtc_restore_mode(struct drm_crtc *crtc)
7891 {
7892         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7893 }
7894
7895 #undef for_each_intel_crtc_masked
7896
7897 static void intel_set_config_free(struct intel_set_config *config)
7898 {
7899         if (!config)
7900                 return;
7901
7902         drm_free(config->save_connector_encoders, M_DRM);
7903         drm_free(config->save_encoder_crtcs, M_DRM);
7904         drm_free(config, M_DRM);
7905 }
7906
7907 static int intel_set_config_save_state(struct drm_device *dev,
7908                                        struct intel_set_config *config)
7909 {
7910         struct drm_encoder *encoder;
7911         struct drm_connector *connector;
7912         int count;
7913
7914         config->save_encoder_crtcs =
7915                 kmalloc(dev->mode_config.num_encoder *
7916                         sizeof(struct drm_crtc *), M_DRM, M_WAITOK | M_ZERO );
7917         if (!config->save_encoder_crtcs)
7918                 return -ENOMEM;
7919
7920         config->save_connector_encoders =
7921                 kmalloc(dev->mode_config.num_connector *
7922                         sizeof(struct drm_encoder *), M_DRM, M_WAITOK | M_ZERO );
7923         if (!config->save_connector_encoders)
7924                 return -ENOMEM;
7925
7926         /* Copy data. Note that driver private data is not affected.
7927          * Should anything bad happen only the expected state is
7928          * restored, not the drivers personal bookkeeping.
7929          */
7930         count = 0;
7931         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7932                 config->save_encoder_crtcs[count++] = encoder->crtc;
7933         }
7934
7935         count = 0;
7936         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7937                 config->save_connector_encoders[count++] = connector->encoder;
7938         }
7939
7940         return 0;
7941 }
7942
7943 static void intel_set_config_restore_state(struct drm_device *dev,
7944                                            struct intel_set_config *config)
7945 {
7946         struct intel_encoder *encoder;
7947         struct intel_connector *connector;
7948         int count;
7949
7950         count = 0;
7951         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7952                 encoder->new_crtc =
7953                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7954         }
7955
7956         count = 0;
7957         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7958                 connector->new_encoder =
7959                         to_intel_encoder(config->save_connector_encoders[count++]);
7960         }
7961 }
7962
7963 static bool
7964 is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
7965                       int num_connectors)
7966 {
7967         int i;
7968
7969         for (i = 0; i < num_connectors; i++)
7970                 if (connectors[i].encoder &&
7971                     connectors[i].encoder->crtc == crtc &&
7972                     connectors[i].dpms != DRM_MODE_DPMS_ON)
7973                         return true;
7974
7975         return false;
7976 }
7977
7978 static void
7979 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7980                                       struct intel_set_config *config)
7981 {
7982
7983         /* We should be able to check here if the fb has the same properties
7984          * and then just flip_or_move it */
7985         if (set->connectors != NULL &&
7986             is_crtc_connector_off(set->crtc, *set->connectors,
7987                                   set->num_connectors)) {
7988                         config->mode_changed = true;
7989         } else if (set->crtc->fb != set->fb) {
7990                 /* If we have no fb then treat it as a full mode set */
7991                 if (set->crtc->fb == NULL) {
7992                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7993                         config->mode_changed = true;
7994                 } else if (set->fb == NULL) {
7995                         config->mode_changed = true;
7996                 } else if (set->fb->depth != set->crtc->fb->depth) {
7997                         config->mode_changed = true;
7998                 } else if (set->fb->bits_per_pixel !=
7999                            set->crtc->fb->bits_per_pixel) {
8000                         config->mode_changed = true;
8001                 } else {
8002                         config->fb_changed = true;
8003                 }
8004         }
8005
8006         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8007                 config->fb_changed = true;
8008
8009         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8010                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8011                 drm_mode_debug_printmodeline(&set->crtc->mode);
8012                 drm_mode_debug_printmodeline(set->mode);
8013                 config->mode_changed = true;
8014         }
8015 }
8016
8017 static int
8018 intel_modeset_stage_output_state(struct drm_device *dev,
8019                                  struct drm_mode_set *set,
8020                                  struct intel_set_config *config)
8021 {
8022         struct drm_crtc *new_crtc;
8023         struct intel_connector *connector;
8024         struct intel_encoder *encoder;
8025         int count, ro;
8026
8027         /* The upper layers ensure that we either disable a crtc or have a list
8028          * of connectors. For paranoia, double-check this. */
8029         WARN_ON(!set->fb && (set->num_connectors != 0));
8030         WARN_ON(set->fb && (set->num_connectors == 0));
8031
8032         count = 0;
8033         list_for_each_entry(connector, &dev->mode_config.connector_list,
8034                             base.head) {
8035                 /* Otherwise traverse passed in connector list and get encoders
8036                  * for them. */
8037                 for (ro = 0; ro < set->num_connectors; ro++) {
8038                         if (set->connectors[ro] == &connector->base) {
8039                                 connector->new_encoder = connector->encoder;
8040                                 break;
8041                         }
8042                 }
8043
8044                 /* If we disable the crtc, disable all its connectors. Also, if
8045                  * the connector is on the changing crtc but not on the new
8046                  * connector list, disable it. */
8047                 if ((!set->fb || ro == set->num_connectors) &&
8048                     connector->base.encoder &&
8049                     connector->base.encoder->crtc == set->crtc) {
8050                         connector->new_encoder = NULL;
8051
8052                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8053                                 connector->base.base.id,
8054                                 drm_get_connector_name(&connector->base));
8055                 }
8056
8057
8058                 if (&connector->new_encoder->base != connector->base.encoder) {
8059                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8060                         config->mode_changed = true;
8061                 }
8062         }
8063         /* connector->new_encoder is now updated for all connectors. */
8064
8065         /* Update crtc of enabled connectors. */
8066         count = 0;
8067         list_for_each_entry(connector, &dev->mode_config.connector_list,
8068                             base.head) {
8069                 if (!connector->new_encoder)
8070                         continue;
8071
8072                 new_crtc = connector->new_encoder->base.crtc;
8073
8074                 for (ro = 0; ro < set->num_connectors; ro++) {
8075                         if (set->connectors[ro] == &connector->base)
8076                                 new_crtc = set->crtc;
8077                 }
8078
8079                 /* Make sure the new CRTC will work with the encoder */
8080                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8081                                            new_crtc)) {
8082                         return -EINVAL;
8083                 }
8084                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8085
8086                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8087                         connector->base.base.id,
8088                         drm_get_connector_name(&connector->base),
8089                         new_crtc->base.id);
8090         }
8091
8092         /* Check for any encoders that needs to be disabled. */
8093         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8094                             base.head) {
8095                 list_for_each_entry(connector,
8096                                     &dev->mode_config.connector_list,
8097                                     base.head) {
8098                         if (connector->new_encoder == encoder) {
8099                                 WARN_ON(!connector->new_encoder->new_crtc);
8100
8101                                 goto next_encoder;
8102                         }
8103                 }
8104                 encoder->new_crtc = NULL;
8105 next_encoder:
8106                 /* Only now check for crtc changes so we don't miss encoders
8107                  * that will be disabled. */
8108                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8109                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8110                         config->mode_changed = true;
8111                 }
8112         }
8113         /* Now we've also updated encoder->new_crtc for all encoders. */
8114
8115         return 0;
8116 }
8117
8118 static int intel_crtc_set_config(struct drm_mode_set *set)
8119 {
8120         struct drm_device *dev;
8121         struct drm_mode_set save_set;
8122         struct intel_set_config *config;
8123         int ret;
8124
8125         BUG_ON(!set);
8126         BUG_ON(!set->crtc);
8127         BUG_ON(!set->crtc->helper_private);
8128
8129         /* Enforce sane interface api - has been abused by the fb helper. */
8130         BUG_ON(!set->mode && set->fb);
8131         BUG_ON(set->fb && set->num_connectors == 0);
8132
8133         if (set->fb) {
8134                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8135                                 set->crtc->base.id, set->fb->base.id,
8136                                 (int)set->num_connectors, set->x, set->y);
8137         } else {
8138                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8139         }
8140
8141         dev = set->crtc->dev;
8142
8143         ret = -ENOMEM;
8144         config = kmalloc(sizeof(*config), M_DRM, M_WAITOK | M_ZERO);
8145         if (!config)
8146                 goto out_config;
8147
8148         ret = intel_set_config_save_state(dev, config);
8149         if (ret)
8150                 goto out_config;
8151
8152         save_set.crtc = set->crtc;
8153         save_set.mode = &set->crtc->mode;
8154         save_set.x = set->crtc->x;
8155         save_set.y = set->crtc->y;
8156         save_set.fb = set->crtc->fb;
8157
8158         /* Compute whether we need a full modeset, only an fb base update or no
8159          * change at all. In the future we might also check whether only the
8160          * mode changed, e.g. for LVDS where we only change the panel fitter in
8161          * such cases. */
8162         intel_set_config_compute_mode_changes(set, config);
8163
8164         ret = intel_modeset_stage_output_state(dev, set, config);
8165         if (ret)
8166                 goto fail;
8167
8168         if (config->mode_changed) {
8169                 if (set->mode) {
8170                         DRM_DEBUG_KMS("attempting to set mode from"
8171                                         " userspace\n");
8172                         drm_mode_debug_printmodeline(set->mode);
8173                 }
8174
8175                 ret = intel_set_mode(set->crtc, set->mode,
8176                                      set->x, set->y, set->fb);
8177                 if (ret) {
8178                         DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8179                                   set->crtc->base.id, ret);
8180                         goto fail;
8181                 }
8182         } else if (config->fb_changed) {
8183                 ret = intel_pipe_set_base(set->crtc,
8184                                           set->x, set->y, set->fb);
8185         }
8186
8187         intel_set_config_free(config);
8188
8189         return 0;
8190
8191 fail:
8192         intel_set_config_restore_state(dev, config);
8193
8194         /* Try to restore the config */
8195         if (config->mode_changed &&
8196             intel_set_mode(save_set.crtc, save_set.mode,
8197                            save_set.x, save_set.y, save_set.fb))
8198                 DRM_ERROR("failed to restore config after modeset failure\n");
8199
8200 out_config:
8201         intel_set_config_free(config);
8202         return ret;
8203 }
8204
8205 static const struct drm_crtc_funcs intel_crtc_funcs = {
8206         .cursor_set = intel_crtc_cursor_set,
8207         .cursor_move = intel_crtc_cursor_move,
8208         .gamma_set = intel_crtc_gamma_set,
8209         .set_config = intel_crtc_set_config,
8210         .destroy = intel_crtc_destroy,
8211         .page_flip = intel_crtc_page_flip,
8212 };
8213
8214 static void intel_cpu_pll_init(struct drm_device *dev)
8215 {
8216         if (HAS_DDI(dev))
8217                 intel_ddi_pll_init(dev);
8218 }
8219
8220 static void intel_pch_pll_init(struct drm_device *dev)
8221 {
8222         drm_i915_private_t *dev_priv = dev->dev_private;
8223         int i;
8224
8225         if (dev_priv->num_pch_pll == 0) {
8226                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8227                 return;
8228         }
8229
8230         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8231                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8232                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8233                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8234         }
8235 }
8236
8237 static void intel_crtc_init(struct drm_device *dev, int pipe)
8238 {
8239         drm_i915_private_t *dev_priv = dev->dev_private;
8240         struct intel_crtc *intel_crtc;
8241         int i;
8242
8243         intel_crtc = kmalloc(sizeof(struct intel_crtc) +
8244             (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)),
8245             M_DRM, M_WAITOK | M_ZERO);
8246         if (intel_crtc == NULL)
8247                 return;
8248
8249         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8250
8251         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8252         for (i = 0; i < 256; i++) {
8253                 intel_crtc->lut_r[i] = i;
8254                 intel_crtc->lut_g[i] = i;
8255                 intel_crtc->lut_b[i] = i;
8256         }
8257
8258         /* Swap pipes & planes for FBC on pre-965 */
8259         intel_crtc->pipe = pipe;
8260         intel_crtc->plane = pipe;
8261         intel_crtc->cpu_transcoder = pipe;
8262         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8263                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8264                 intel_crtc->plane = !pipe;
8265         }
8266
8267         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8268                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8269         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8270         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8271
8272         intel_crtc->bpp = 24; /* default for pre-Ironlake */
8273
8274         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8275 }
8276
8277 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8278                                 struct drm_file *file)
8279 {
8280         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8281         struct drm_mode_object *drmmode_obj;
8282         struct intel_crtc *crtc;
8283
8284         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8285                 return -ENODEV;
8286
8287         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8288                         DRM_MODE_OBJECT_CRTC);
8289
8290         if (!drmmode_obj) {
8291                 DRM_ERROR("no such CRTC id\n");
8292                 return -EINVAL;
8293         }
8294
8295         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8296         pipe_from_crtc_id->pipe = crtc->pipe;
8297
8298         return 0;
8299 }
8300
8301 static int intel_encoder_clones(struct intel_encoder *encoder)
8302 {
8303         struct drm_device *dev = encoder->base.dev;
8304         struct intel_encoder *source_encoder;
8305         int index_mask = 0;
8306         int entry = 0;
8307
8308         list_for_each_entry(source_encoder,
8309                             &dev->mode_config.encoder_list, base.head) {
8310
8311                 if (encoder == source_encoder)
8312                         index_mask |= (1 << entry);
8313
8314                 /* Intel hw has only one MUX where enocoders could be cloned. */
8315                 if (encoder->cloneable && source_encoder->cloneable)
8316                         index_mask |= (1 << entry);
8317
8318                 entry++;
8319         }
8320
8321         return index_mask;
8322 }
8323
8324 static bool has_edp_a(struct drm_device *dev)
8325 {
8326         struct drm_i915_private *dev_priv = dev->dev_private;
8327
8328         if (!IS_MOBILE(dev))
8329                 return false;
8330
8331         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8332                 return false;
8333
8334         if (IS_GEN5(dev) &&
8335             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8336                 return false;
8337
8338         return true;
8339 }
8340
8341 static void intel_setup_outputs(struct drm_device *dev)
8342 {
8343         struct drm_i915_private *dev_priv = dev->dev_private;
8344         struct intel_encoder *encoder;
8345         bool dpd_is_edp = false;
8346         bool has_lvds;
8347
8348         has_lvds = intel_lvds_init(dev);
8349         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8350                 /* disable the panel fitter on everything but LVDS */
8351                 I915_WRITE(PFIT_CONTROL, 0);
8352         }
8353
8354         if (!IS_ULT(dev))
8355                 intel_crt_init(dev);
8356
8357         if (HAS_DDI(dev)) {
8358                 int found;
8359
8360                 /* Haswell uses DDI functions to detect digital outputs */
8361                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8362                 /* DDI A only supports eDP */
8363                 if (found)
8364                         intel_ddi_init(dev, PORT_A);
8365
8366                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8367                  * register */
8368                 found = I915_READ(SFUSE_STRAP);
8369
8370                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8371                         intel_ddi_init(dev, PORT_B);
8372                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8373                         intel_ddi_init(dev, PORT_C);
8374                 if (found & SFUSE_STRAP_DDID_DETECTED)
8375                         intel_ddi_init(dev, PORT_D);
8376         } else if (HAS_PCH_SPLIT(dev)) {
8377                 int found;
8378                 dpd_is_edp = intel_dpd_is_edp(dev);
8379
8380                 if (has_edp_a(dev))
8381                         intel_dp_init(dev, DP_A, PORT_A);
8382
8383                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8384                         /* PCH SDVOB multiplex with HDMIB */
8385                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8386                         if (!found)
8387                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8388                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8389                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8390                 }
8391
8392                 if (I915_READ(HDMIC) & PORT_DETECTED)
8393                         intel_hdmi_init(dev, HDMIC, PORT_C);
8394
8395                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8396                         intel_hdmi_init(dev, HDMID, PORT_D);
8397
8398                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8399                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8400
8401                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8402                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8403         } else if (IS_VALLEYVIEW(dev)) {
8404                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8405                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8406                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8407
8408                 if (I915_READ(VLV_DISPLAY_BASE + SDVOB) & PORT_DETECTED) {
8409                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOB, PORT_B);
8410                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8411                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8412                 }
8413
8414                 if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED)
8415                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C);
8416
8417         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8418                 bool found = false;
8419
8420                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8421                         DRM_DEBUG_KMS("probing SDVOB\n");
8422                         found = intel_sdvo_init(dev, SDVOB, true);
8423                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8424                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8425                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8426                         }
8427
8428                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8429                                 DRM_DEBUG_KMS("probing DP_B\n");
8430                                 intel_dp_init(dev, DP_B, PORT_B);
8431                         }
8432                 }
8433
8434                 /* Before G4X SDVOC doesn't have its own detect register */
8435
8436                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8437                         DRM_DEBUG_KMS("probing SDVOC\n");
8438                         found = intel_sdvo_init(dev, SDVOC, false);
8439                 }
8440
8441                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8442
8443                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8444                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8445                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8446                         }
8447                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8448                                 DRM_DEBUG_KMS("probing DP_C\n");
8449                                 intel_dp_init(dev, DP_C, PORT_C);
8450                         }
8451                 }
8452
8453                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8454                     (I915_READ(DP_D) & DP_DETECTED)) {
8455                         DRM_DEBUG_KMS("probing DP_D\n");
8456                         intel_dp_init(dev, DP_D, PORT_D);
8457                 }
8458         } else if (IS_GEN2(dev)) {
8459 #if 0
8460                 intel_dvo_init(dev);
8461 #endif
8462         }
8463
8464         if (SUPPORTS_TV(dev))
8465                 intel_tv_init(dev);
8466
8467         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8468                 encoder->base.possible_crtcs = encoder->crtc_mask;
8469                 encoder->base.possible_clones =
8470                         intel_encoder_clones(encoder);
8471         }
8472
8473         intel_init_pch_refclk(dev);
8474
8475         drm_helper_move_panel_connectors_to_head(dev);
8476 }
8477
8478 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8479 {
8480         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8481
8482         drm_framebuffer_cleanup(fb);
8483         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8484
8485         drm_free(intel_fb, M_DRM);
8486 }
8487
8488 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8489                                                 struct drm_file *file,
8490                                                 unsigned int *handle)
8491 {
8492         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8493         struct drm_i915_gem_object *obj = intel_fb->obj;
8494
8495         return drm_gem_handle_create(file, &obj->base, handle);
8496 }
8497
8498 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8499         .destroy = intel_user_framebuffer_destroy,
8500         .create_handle = intel_user_framebuffer_create_handle,
8501 };
8502
8503 int intel_framebuffer_init(struct drm_device *dev,
8504                            struct intel_framebuffer *intel_fb,
8505                            struct drm_mode_fb_cmd2 *mode_cmd,
8506                            struct drm_i915_gem_object *obj)
8507 {
8508         int ret;
8509
8510         if (obj->tiling_mode == I915_TILING_Y) {
8511                 DRM_DEBUG("hardware does not support tiling Y\n");
8512                 return -EINVAL;
8513         }
8514
8515         if (mode_cmd->pitches[0] & 63) {
8516                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8517                           mode_cmd->pitches[0]);
8518                 return -EINVAL;
8519         }
8520
8521         /* FIXME <= Gen4 stride limits are bit unclear */
8522         if (mode_cmd->pitches[0] > 32768) {
8523                 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8524                           mode_cmd->pitches[0]);
8525                 return -EINVAL;
8526         }
8527
8528         if (obj->tiling_mode != I915_TILING_NONE &&
8529             mode_cmd->pitches[0] != obj->stride) {
8530                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8531                           mode_cmd->pitches[0], obj->stride);
8532                 return -EINVAL;
8533         }
8534
8535         /* Reject formats not supported by any plane early. */
8536         switch (mode_cmd->pixel_format) {
8537         case DRM_FORMAT_C8:
8538         case DRM_FORMAT_RGB565:
8539         case DRM_FORMAT_XRGB8888:
8540         case DRM_FORMAT_ARGB8888:
8541                 break;
8542         case DRM_FORMAT_XRGB1555:
8543         case DRM_FORMAT_ARGB1555:
8544                 if (INTEL_INFO(dev)->gen > 3) {
8545                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8546                         return -EINVAL;
8547                 }
8548                 break;
8549         case DRM_FORMAT_XBGR8888:
8550         case DRM_FORMAT_ABGR8888:
8551         case DRM_FORMAT_XRGB2101010:
8552         case DRM_FORMAT_ARGB2101010:
8553         case DRM_FORMAT_XBGR2101010:
8554         case DRM_FORMAT_ABGR2101010:
8555                 if (INTEL_INFO(dev)->gen < 4) {
8556                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8557                         return -EINVAL;
8558                 }
8559                 break;
8560         case DRM_FORMAT_YUYV:
8561         case DRM_FORMAT_UYVY:
8562         case DRM_FORMAT_YVYU:
8563         case DRM_FORMAT_VYUY:
8564                 if (INTEL_INFO(dev)->gen < 5) {
8565                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8566                         return -EINVAL;
8567                 }
8568                 break;
8569         default:
8570                 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8571                 return -EINVAL;
8572         }
8573
8574         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8575         if (mode_cmd->offsets[0] != 0)
8576                 return -EINVAL;
8577
8578         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8579         intel_fb->obj = obj;
8580
8581         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8582         if (ret) {
8583                 DRM_ERROR("framebuffer init failed %d\n", ret);
8584                 return ret;
8585         }
8586
8587         return 0;
8588 }
8589
8590 static struct drm_framebuffer *
8591 intel_user_framebuffer_create(struct drm_device *dev,
8592                               struct drm_file *filp,
8593                               struct drm_mode_fb_cmd2 *mode_cmd)
8594 {
8595         struct drm_i915_gem_object *obj;
8596
8597         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8598                                                 mode_cmd->handles[0]));
8599         if (&obj->base == NULL)
8600                 return ERR_PTR(-ENOENT);
8601
8602         return intel_framebuffer_create(dev, mode_cmd, obj);
8603 }
8604
8605 static const struct drm_mode_config_funcs intel_mode_funcs = {
8606         .fb_create = intel_user_framebuffer_create,
8607         .output_poll_changed = intel_fb_output_poll_changed,
8608 };
8609
8610 /* Set up chip specific display functions */
8611 static void intel_init_display(struct drm_device *dev)
8612 {
8613         struct drm_i915_private *dev_priv = dev->dev_private;
8614
8615         /* We always want a DPMS function */
8616         if (HAS_DDI(dev)) {
8617                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8618                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8619                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8620                 dev_priv->display.off = haswell_crtc_off;
8621                 dev_priv->display.update_plane = ironlake_update_plane;
8622         } else if (HAS_PCH_SPLIT(dev)) {
8623                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8624                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8625                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8626                 dev_priv->display.off = ironlake_crtc_off;
8627                 dev_priv->display.update_plane = ironlake_update_plane;
8628         } else {
8629                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8630                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8631                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8632                 dev_priv->display.off = i9xx_crtc_off;
8633                 dev_priv->display.update_plane = i9xx_update_plane;
8634         }
8635
8636         /* Returns the core display clock speed */
8637         if (IS_VALLEYVIEW(dev))
8638                 dev_priv->display.get_display_clock_speed =
8639                         valleyview_get_display_clock_speed;
8640         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8641                 dev_priv->display.get_display_clock_speed =
8642                         i945_get_display_clock_speed;
8643         else if (IS_I915G(dev))
8644                 dev_priv->display.get_display_clock_speed =
8645                         i915_get_display_clock_speed;
8646         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8647                 dev_priv->display.get_display_clock_speed =
8648                         i9xx_misc_get_display_clock_speed;
8649         else if (IS_I915GM(dev))
8650                 dev_priv->display.get_display_clock_speed =
8651                         i915gm_get_display_clock_speed;
8652         else if (IS_I865G(dev))
8653                 dev_priv->display.get_display_clock_speed =
8654                         i865_get_display_clock_speed;
8655         else if (IS_I85X(dev))
8656                 dev_priv->display.get_display_clock_speed =
8657                         i855_get_display_clock_speed;
8658         else /* 852, 830 */
8659                 dev_priv->display.get_display_clock_speed =
8660                         i830_get_display_clock_speed;
8661
8662         if (HAS_PCH_SPLIT(dev)) {
8663                 if (IS_GEN5(dev)) {
8664                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8665                         dev_priv->display.write_eld = ironlake_write_eld;
8666                 } else if (IS_GEN6(dev)) {
8667                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8668                         dev_priv->display.write_eld = ironlake_write_eld;
8669                 } else if (IS_IVYBRIDGE(dev)) {
8670                         /* FIXME: detect B0+ stepping and use auto training */
8671                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8672                         dev_priv->display.write_eld = ironlake_write_eld;
8673                         dev_priv->display.modeset_global_resources =
8674                                 ivb_modeset_global_resources;
8675                 } else if (IS_HASWELL(dev)) {
8676                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8677                         dev_priv->display.write_eld = haswell_write_eld;
8678                         dev_priv->display.modeset_global_resources =
8679                                 haswell_modeset_global_resources;
8680                 }
8681         } else if (IS_G4X(dev)) {
8682                 dev_priv->display.write_eld = g4x_write_eld;
8683         }
8684
8685         /* Default just returns -ENODEV to indicate unsupported */
8686         dev_priv->display.queue_flip = intel_default_queue_flip;
8687
8688         switch (INTEL_INFO(dev)->gen) {
8689         case 2:
8690                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8691                 break;
8692
8693         case 3:
8694                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8695                 break;
8696
8697         case 4:
8698         case 5:
8699                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8700                 break;
8701
8702         case 6:
8703                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8704                 break;
8705         case 7:
8706                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8707                 break;
8708         }
8709 }
8710
8711 /*
8712  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8713  * resume, or other times.  This quirk makes sure that's the case for
8714  * affected systems.
8715  */
8716 static void quirk_pipea_force(struct drm_device *dev)
8717 {
8718         struct drm_i915_private *dev_priv = dev->dev_private;
8719
8720         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8721         DRM_INFO("applying pipe a force quirk\n");
8722 }
8723
8724 /*
8725  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8726  */
8727 static void quirk_ssc_force_disable(struct drm_device *dev)
8728 {
8729         struct drm_i915_private *dev_priv = dev->dev_private;
8730         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8731         DRM_INFO("applying lvds SSC disable quirk\n");
8732 }
8733
8734 /*
8735  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8736  * brightness value
8737  */
8738 static void quirk_invert_brightness(struct drm_device *dev)
8739 {
8740         struct drm_i915_private *dev_priv = dev->dev_private;
8741         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8742         DRM_INFO("applying inverted panel brightness quirk\n");
8743 }
8744
8745 struct intel_quirk {
8746         int device;
8747         int subsystem_vendor;
8748         int subsystem_device;
8749         void (*hook)(struct drm_device *dev);
8750 };
8751
8752 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8753 struct intel_dmi_quirk {
8754         void (*hook)(struct drm_device *dev);
8755         const struct dmi_system_id (*dmi_id_list)[];
8756 };
8757
8758 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8759 {
8760         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8761         return 1;
8762 }
8763
8764 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8765         {
8766                 .dmi_id_list = &(const struct dmi_system_id[]) {
8767                         {
8768                                 .callback = intel_dmi_reverse_brightness,
8769                                 .ident = "NCR Corporation",
8770                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8771                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
8772                                 },
8773                         },
8774                         { }  /* terminating entry */
8775                 },
8776                 .hook = quirk_invert_brightness,
8777         },
8778 };
8779
8780 static struct intel_quirk intel_quirks[] = {
8781         /* HP Mini needs pipe A force quirk (LP: #322104) */
8782         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8783
8784         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8785         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8786
8787         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8788         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8789
8790         /* 830/845 need to leave pipe A & dpll A up */
8791         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8792         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8793
8794         /* Lenovo U160 cannot use SSC on LVDS */
8795         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8796
8797         /* Sony Vaio Y cannot use SSC on LVDS */
8798         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8799
8800         /* Acer Aspire 5734Z must invert backlight brightness */
8801         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8802
8803         /* Acer/eMachines G725 */
8804         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
8805
8806         /* Acer/eMachines e725 */
8807         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
8808
8809         /* Acer/Packard Bell NCL20 */
8810         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
8811
8812         /* Acer Aspire 4736Z */
8813         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
8814 };
8815
8816 static void intel_init_quirks(struct drm_device *dev)
8817 {
8818         device_t d;
8819         int i;
8820
8821         d = dev->dev;
8822         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8823                 struct intel_quirk *q = &intel_quirks[i];
8824                 if (pci_get_device(d) == q->device &&
8825                     (pci_get_subvendor(d) == q->subsystem_vendor ||
8826                      q->subsystem_vendor == PCI_ANY_ID) &&
8827                     (pci_get_subdevice(d) == q->subsystem_device ||
8828                      q->subsystem_device == PCI_ANY_ID))
8829                         q->hook(dev);
8830         }
8831         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8832                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8833                         intel_dmi_quirks[i].hook(dev);
8834         }
8835 }
8836
8837 /* Disable the VGA plane that we never use */
8838 static void i915_disable_vga(struct drm_device *dev)
8839 {
8840         struct drm_i915_private *dev_priv = dev->dev_private;
8841         u8 sr1;
8842         u32 vga_reg = i915_vgacntrl_reg(dev);
8843
8844 #if 0
8845         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8846 #endif
8847         outb(VGA_SR_INDEX, 1);
8848         sr1 = inb(VGA_SR_DATA);
8849         outb(VGA_SR_DATA, sr1 | 1 << 5);
8850 #if 0
8851         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8852 #endif
8853         udelay(300);
8854
8855         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8856         POSTING_READ(vga_reg);
8857 }
8858
8859 void intel_modeset_init_hw(struct drm_device *dev)
8860 {
8861         intel_init_power_well(dev);
8862
8863         intel_prepare_ddi(dev);
8864
8865         intel_init_clock_gating(dev);
8866
8867         mutex_lock(&dev->struct_mutex);
8868         intel_enable_gt_powersave(dev);
8869         mutex_unlock(&dev->struct_mutex);
8870 }
8871
8872 void intel_modeset_init(struct drm_device *dev)
8873 {
8874         struct drm_i915_private *dev_priv = dev->dev_private;
8875         int i, ret;
8876
8877         drm_mode_config_init(dev);
8878
8879         dev->mode_config.min_width = 0;
8880         dev->mode_config.min_height = 0;
8881
8882         dev->mode_config.preferred_depth = 24;
8883         dev->mode_config.prefer_shadow = 1;
8884
8885         dev->mode_config.funcs = &intel_mode_funcs;
8886
8887         intel_init_quirks(dev);
8888
8889         intel_init_pm(dev);
8890
8891         intel_init_display(dev);
8892
8893         if (IS_GEN2(dev)) {
8894                 dev->mode_config.max_width = 2048;
8895                 dev->mode_config.max_height = 2048;
8896         } else if (IS_GEN3(dev)) {
8897                 dev->mode_config.max_width = 4096;
8898                 dev->mode_config.max_height = 4096;
8899         } else {
8900                 dev->mode_config.max_width = 8192;
8901                 dev->mode_config.max_height = 8192;
8902         }
8903         dev->mode_config.fb_base = dev->agp->base;
8904
8905         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8906                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8907
8908         for (i = 0; i < dev_priv->num_pipe; i++) {
8909                 intel_crtc_init(dev, i);
8910                 ret = intel_plane_init(dev, i);
8911                 if (ret)
8912                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8913         }
8914
8915         intel_cpu_pll_init(dev);
8916         intel_pch_pll_init(dev);
8917
8918         /* Just disable it once at startup */
8919         i915_disable_vga(dev);
8920         intel_setup_outputs(dev);
8921
8922         /* Just in case the BIOS is doing something questionable. */
8923         intel_disable_fbc(dev);
8924 }
8925
8926 static void
8927 intel_connector_break_all_links(struct intel_connector *connector)
8928 {
8929         connector->base.dpms = DRM_MODE_DPMS_OFF;
8930         connector->base.encoder = NULL;
8931         connector->encoder->connectors_active = false;
8932         connector->encoder->base.crtc = NULL;
8933 }
8934
8935 static void intel_enable_pipe_a(struct drm_device *dev)
8936 {
8937         struct intel_connector *connector;
8938         struct drm_connector *crt = NULL;
8939         struct intel_load_detect_pipe load_detect_temp;
8940
8941         /* We can't just switch on the pipe A, we need to set things up with a
8942          * proper mode and output configuration. As a gross hack, enable pipe A
8943          * by enabling the load detect pipe once. */
8944         list_for_each_entry(connector,
8945                             &dev->mode_config.connector_list,
8946                             base.head) {
8947                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8948                         crt = &connector->base;
8949                         break;
8950                 }
8951         }
8952
8953         if (!crt)
8954                 return;
8955
8956         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8957                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8958
8959
8960 }
8961
8962 static bool
8963 intel_check_plane_mapping(struct intel_crtc *crtc)
8964 {
8965         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8966         u32 reg, val;
8967
8968         if (dev_priv->num_pipe == 1)
8969                 return true;
8970
8971         reg = DSPCNTR(!crtc->plane);
8972         val = I915_READ(reg);
8973
8974         if ((val & DISPLAY_PLANE_ENABLE) &&
8975             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8976                 return false;
8977
8978         return true;
8979 }
8980
8981 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8982 {
8983         struct drm_device *dev = crtc->base.dev;
8984         struct drm_i915_private *dev_priv = dev->dev_private;
8985         u32 reg;
8986
8987         /* Clear any frame start delays used for debugging left by the BIOS */
8988         reg = PIPECONF(crtc->cpu_transcoder);
8989         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8990
8991         /* We need to sanitize the plane -> pipe mapping first because this will
8992          * disable the crtc (and hence change the state) if it is wrong. Note
8993          * that gen4+ has a fixed plane -> pipe mapping.  */
8994         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8995                 struct intel_connector *connector;
8996                 bool plane;
8997
8998                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8999                               crtc->base.base.id);
9000
9001                 /* Pipe has the wrong plane attached and the plane is active.
9002                  * Temporarily change the plane mapping and disable everything
9003                  * ...  */
9004                 plane = crtc->plane;
9005                 crtc->plane = !plane;
9006                 dev_priv->display.crtc_disable(&crtc->base);
9007                 crtc->plane = plane;
9008
9009                 /* ... and break all links. */
9010                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9011                                     base.head) {
9012                         if (connector->encoder->base.crtc != &crtc->base)
9013                                 continue;
9014
9015                         intel_connector_break_all_links(connector);
9016                 }
9017
9018                 WARN_ON(crtc->active);
9019                 crtc->base.enabled = false;
9020         }
9021
9022         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9023             crtc->pipe == PIPE_A && !crtc->active) {
9024                 /* BIOS forgot to enable pipe A, this mostly happens after
9025                  * resume. Force-enable the pipe to fix this, the update_dpms
9026                  * call below we restore the pipe to the right state, but leave
9027                  * the required bits on. */
9028                 intel_enable_pipe_a(dev);
9029         }
9030
9031         /* Adjust the state of the output pipe according to whether we
9032          * have active connectors/encoders. */
9033         intel_crtc_update_dpms(&crtc->base);
9034
9035         if (crtc->active != crtc->base.enabled) {
9036                 struct intel_encoder *encoder;
9037
9038                 /* This can happen either due to bugs in the get_hw_state
9039                  * functions or because the pipe is force-enabled due to the
9040                  * pipe A quirk. */
9041                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9042                               crtc->base.base.id,
9043                               crtc->base.enabled ? "enabled" : "disabled",
9044                               crtc->active ? "enabled" : "disabled");
9045
9046                 crtc->base.enabled = crtc->active;
9047
9048                 /* Because we only establish the connector -> encoder ->
9049                  * crtc links if something is active, this means the
9050                  * crtc is now deactivated. Break the links. connector
9051                  * -> encoder links are only establish when things are
9052                  *  actually up, hence no need to break them. */
9053                 WARN_ON(crtc->active);
9054
9055                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9056                         WARN_ON(encoder->connectors_active);
9057                         encoder->base.crtc = NULL;
9058                 }
9059         }
9060 }
9061
9062 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9063 {
9064         struct intel_connector *connector;
9065         struct drm_device *dev = encoder->base.dev;
9066
9067         /* We need to check both for a crtc link (meaning that the
9068          * encoder is active and trying to read from a pipe) and the
9069          * pipe itself being active. */
9070         bool has_active_crtc = encoder->base.crtc &&
9071                 to_intel_crtc(encoder->base.crtc)->active;
9072
9073         if (encoder->connectors_active && !has_active_crtc) {
9074                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9075                               encoder->base.base.id,
9076                               drm_get_encoder_name(&encoder->base));
9077
9078                 /* Connector is active, but has no active pipe. This is
9079                  * fallout from our resume register restoring. Disable
9080                  * the encoder manually again. */
9081                 if (encoder->base.crtc) {
9082                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9083                                       encoder->base.base.id,
9084                                       drm_get_encoder_name(&encoder->base));
9085                         encoder->disable(encoder);
9086                 }
9087
9088                 /* Inconsistent output/port/pipe state happens presumably due to
9089                  * a bug in one of the get_hw_state functions. Or someplace else
9090                  * in our code, like the register restore mess on resume. Clamp
9091                  * things to off as a safer default. */
9092                 list_for_each_entry(connector,
9093                                     &dev->mode_config.connector_list,
9094                                     base.head) {
9095                         if (connector->encoder != encoder)
9096                                 continue;
9097
9098                         intel_connector_break_all_links(connector);
9099                 }
9100         }
9101         /* Enabled encoders without active connectors will be fixed in
9102          * the crtc fixup. */
9103 }
9104
9105 void i915_redisable_vga(struct drm_device *dev)
9106 {
9107         struct drm_i915_private *dev_priv = dev->dev_private;
9108         u32 vga_reg = i915_vgacntrl_reg(dev);
9109
9110         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9111                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9112                 i915_disable_vga(dev);
9113         }
9114 }
9115
9116 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9117  * and i915 state tracking structures. */
9118 void intel_modeset_setup_hw_state(struct drm_device *dev,
9119                                   bool force_restore)
9120 {
9121         struct drm_i915_private *dev_priv = dev->dev_private;
9122         enum i915_pipe pipe;
9123         u32 tmp;
9124         struct intel_crtc *crtc;
9125         struct intel_encoder *encoder;
9126         struct intel_connector *connector;
9127
9128         if (HAS_DDI(dev)) {
9129                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9130
9131                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9132                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9133                         case TRANS_DDI_EDP_INPUT_A_ON:
9134                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
9135                                 pipe = PIPE_A;
9136                                 break;
9137                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
9138                                 pipe = PIPE_B;
9139                                 break;
9140                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
9141                                 pipe = PIPE_C;
9142                                 break;
9143                         }
9144
9145                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9146                         crtc->cpu_transcoder = TRANSCODER_EDP;
9147
9148                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9149                                       pipe_name(pipe));
9150                 }
9151         }
9152
9153         for_each_pipe(pipe) {
9154                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9155
9156                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9157                 if (tmp & PIPECONF_ENABLE)
9158                         crtc->active = true;
9159                 else
9160                         crtc->active = false;
9161
9162                 crtc->base.enabled = crtc->active;
9163
9164                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9165                               crtc->base.base.id,
9166                               crtc->active ? "enabled" : "disabled");
9167         }
9168
9169         if (HAS_DDI(dev))
9170                 intel_ddi_setup_hw_pll_state(dev);
9171
9172         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9173                             base.head) {
9174                 pipe = 0;
9175
9176                 if (encoder->get_hw_state(encoder, &pipe)) {
9177                         encoder->base.crtc =
9178                                 dev_priv->pipe_to_crtc_mapping[pipe];
9179                 } else {
9180                         encoder->base.crtc = NULL;
9181                 }
9182
9183                 encoder->connectors_active = false;
9184                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9185                               encoder->base.base.id,
9186                               drm_get_encoder_name(&encoder->base),
9187                               encoder->base.crtc ? "enabled" : "disabled",
9188                               pipe);
9189         }
9190
9191         list_for_each_entry(connector, &dev->mode_config.connector_list,
9192                             base.head) {
9193                 if (connector->get_hw_state(connector)) {
9194                         connector->base.dpms = DRM_MODE_DPMS_ON;
9195                         connector->encoder->connectors_active = true;
9196                         connector->base.encoder = &connector->encoder->base;
9197                 } else {
9198                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9199                         connector->base.encoder = NULL;
9200                 }
9201                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9202                               connector->base.base.id,
9203                               drm_get_connector_name(&connector->base),
9204                               connector->base.encoder ? "enabled" : "disabled");
9205         }
9206
9207         /* HW state is read out, now we need to sanitize this mess. */
9208         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9209                             base.head) {
9210                 intel_sanitize_encoder(encoder);
9211         }
9212
9213         for_each_pipe(pipe) {
9214                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9215                 intel_sanitize_crtc(crtc);
9216         }
9217
9218         if (force_restore) {
9219                 /*
9220                  * We need to use raw interfaces for restoring state to avoid
9221                  * checking (bogus) intermediate states.
9222                  */
9223                 for_each_pipe(pipe) {
9224                         struct drm_crtc *crtc =
9225                                 dev_priv->pipe_to_crtc_mapping[pipe];
9226
9227                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9228                                          crtc->fb);
9229                 }
9230
9231                 i915_redisable_vga(dev);
9232         } else {
9233                 intel_modeset_update_staged_output_state(dev);
9234         }
9235
9236         intel_modeset_check_state(dev);
9237
9238         drm_mode_config_reset(dev);
9239 }
9240
9241 void intel_modeset_gem_init(struct drm_device *dev)
9242 {
9243         intel_modeset_init_hw(dev);
9244
9245         intel_setup_overlay(dev);
9246
9247         intel_modeset_setup_hw_state(dev, false);
9248 }
9249
9250 void intel_modeset_cleanup(struct drm_device *dev)
9251 {
9252         struct drm_i915_private *dev_priv = dev->dev_private;
9253         struct drm_crtc *crtc;
9254         struct intel_crtc *intel_crtc;
9255
9256         drm_kms_helper_poll_fini(dev);
9257         mutex_lock(&dev->struct_mutex);
9258
9259 #if 0
9260         intel_unregister_dsm_handler();
9261 #endif
9262
9263
9264         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9265                 /* Skip inactive CRTCs */
9266                 if (!crtc->fb)
9267                         continue;
9268
9269                 intel_crtc = to_intel_crtc(crtc);
9270                 intel_increase_pllclock(crtc);
9271         }
9272
9273         intel_disable_fbc(dev);
9274
9275         intel_disable_gt_powersave(dev);
9276
9277         ironlake_teardown_rc6(dev);
9278
9279         if (IS_VALLEYVIEW(dev))
9280                 vlv_init_dpio(dev);
9281
9282         mutex_unlock(&dev->struct_mutex);
9283
9284         /* Disable the irq before mode object teardown, for the irq might
9285          * enqueue unpin/hotplug work. */
9286         drm_irq_uninstall(dev);
9287         cancel_work_sync(&dev_priv->hotplug_work);
9288         cancel_work_sync(&dev_priv->rps.work);
9289
9290         /* flush any delayed tasks or pending work */
9291         flush_scheduled_work();
9292
9293         /* destroy backlight, if any, before the connectors */
9294         intel_panel_destroy_backlight(dev);
9295
9296         drm_mode_config_cleanup(dev);
9297
9298         intel_cleanup_overlay(dev);
9299 }
9300
9301 /*
9302  * Return which encoder is currently attached for connector.
9303  */
9304 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9305 {
9306         return &intel_attached_encoder(connector)->base;
9307 }
9308
9309 void intel_connector_attach_encoder(struct intel_connector *connector,
9310                                     struct intel_encoder *encoder)
9311 {
9312         connector->encoder = encoder;
9313         drm_mode_connector_attach_encoder(&connector->base,
9314                                           &encoder->base);
9315 }
9316
9317 /*
9318  * set vga decode state - true == enable VGA decode
9319  */
9320 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9321 {
9322         struct drm_i915_private *dev_priv = dev->dev_private;
9323         u16 gmch_ctrl;
9324
9325         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9326         if (state)
9327                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9328         else
9329                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9330         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9331         return 0;
9332 }
9333
9334 #ifdef CONFIG_DEBUG_FS
9335 #include <linux/seq_file.h>
9336
9337 struct intel_display_error_state {
9338         struct intel_cursor_error_state {
9339                 u32 control;
9340                 u32 position;
9341                 u32 base;
9342                 u32 size;
9343         } cursor[I915_MAX_PIPES];
9344
9345         struct intel_pipe_error_state {
9346                 u32 conf;
9347                 u32 source;
9348
9349                 u32 htotal;
9350                 u32 hblank;
9351                 u32 hsync;
9352                 u32 vtotal;
9353                 u32 vblank;
9354                 u32 vsync;
9355         } pipe[I915_MAX_PIPES];
9356
9357         struct intel_plane_error_state {
9358                 u32 control;
9359                 u32 stride;
9360                 u32 size;
9361                 u32 pos;
9362                 u32 addr;
9363                 u32 surface;
9364                 u32 tile_offset;
9365         } plane[I915_MAX_PIPES];
9366 };
9367
9368 struct intel_display_error_state *
9369 intel_display_capture_error_state(struct drm_device *dev)
9370 {
9371         drm_i915_private_t *dev_priv = dev->dev_private;
9372         struct intel_display_error_state *error;
9373         enum transcoder cpu_transcoder;
9374         int i;
9375
9376         error = kmalloc(sizeof(*error), M_DRM, M_WAITOK | M_NULLOK);
9377         if (error == NULL)
9378                 return NULL;
9379
9380         for_each_pipe(i) {
9381                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9382
9383                 error->cursor[i].control = I915_READ(CURCNTR(i));
9384                 error->cursor[i].position = I915_READ(CURPOS(i));
9385                 error->cursor[i].base = I915_READ(CURBASE(i));
9386
9387                 error->plane[i].control = I915_READ(DSPCNTR(i));
9388                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9389                 error->plane[i].size = I915_READ(DSPSIZE(i));
9390                 error->plane[i].pos = I915_READ(DSPPOS(i));
9391                 error->plane[i].addr = I915_READ(DSPADDR(i));
9392                 if (INTEL_INFO(dev)->gen >= 4) {
9393                         error->plane[i].surface = I915_READ(DSPSURF(i));
9394                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9395                 }
9396
9397                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9398                 error->pipe[i].source = I915_READ(PIPESRC(i));
9399                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9400                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9401                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9402                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9403                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9404                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9405         }
9406
9407         return error;
9408 }
9409
9410 void
9411 intel_display_print_error_state(struct seq_file *m,
9412                                 struct drm_device *dev,
9413                                 struct intel_display_error_state *error)
9414 {
9415         drm_i915_private_t *dev_priv = dev->dev_private;
9416         int i;
9417
9418         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9419         for_each_pipe(i) {
9420                 seq_printf(m, "Pipe [%d]:\n", i);
9421                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9422                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9423                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9424                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9425                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9426                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9427                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9428                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9429
9430                 seq_printf(m, "Plane [%d]:\n", i);
9431                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9432                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9433                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9434                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9435                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9436                 if (INTEL_INFO(dev)->gen >= 4) {
9437                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9438                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9439                 }
9440
9441                 seq_printf(m, "Cursor [%d]:\n", i);
9442                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9443                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9444                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9445         }
9446 }
9447 #endif