2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #include <sys/param.h>
36 #include <sys/bitops.h>
37 #include <sys/endian.h>
38 #include <sys/kernel.h>
40 #include <sys/interrupt.h>
41 #include <sys/malloc.h>
44 #include <sys/serialize.h>
45 #include <sys/socket.h>
46 #include <sys/sockio.h>
47 #include <sys/sysctl.h>
49 #include <net/ethernet.h>
52 #include <net/if_arp.h>
53 #include <net/if_dl.h>
54 #include <net/if_media.h>
55 #include <net/ifq_var.h>
57 #include <netproto/802_11/ieee80211_radiotap.h>
58 #include <netproto/802_11/ieee80211_var.h>
59 #include <netproto/802_11/wlan_ratectl/onoe/ieee80211_onoe_param.h>
61 #include <bus/pci/pcireg.h>
62 #include <bus/pci/pcivar.h>
63 #include <bus/pci/pcidevs.h>
65 #include <dev/netif/bwi/if_bwireg.h>
66 #include <dev/netif/bwi/if_bwivar.h>
67 #include <dev/netif/bwi/bwimac.h>
68 #include <dev/netif/bwi/bwirf.h>
70 struct bwi_clock_freq {
75 struct bwi_myaddr_bssid {
76 uint8_t myaddr[IEEE80211_ADDR_LEN];
77 uint8_t bssid[IEEE80211_ADDR_LEN];
80 static int bwi_probe(device_t);
81 static int bwi_attach(device_t);
82 static int bwi_detach(device_t);
83 static int bwi_shutdown(device_t);
85 static void bwi_init(void *);
86 static int bwi_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
87 static void bwi_start(struct ifnet *, struct ifaltq_subque *);
88 static void bwi_watchdog(struct ifnet *);
89 static int bwi_newstate(struct ieee80211com *, enum ieee80211_state, int);
90 static void bwi_updateslot(struct ifnet *);
91 static int bwi_media_change(struct ifnet *);
92 static void *bwi_ratectl_attach(struct ieee80211com *, u_int);
94 static void bwi_next_scan(void *);
95 static void bwi_calibrate(void *);
97 static void bwi_newstate_begin(struct bwi_softc *, enum ieee80211_state);
98 static void bwi_init_statechg(struct bwi_softc *, int);
99 static int bwi_stop(struct bwi_softc *, int);
100 static int bwi_newbuf(struct bwi_softc *, int, int);
101 static int bwi_encap(struct bwi_softc *, int, struct mbuf *,
102 struct ieee80211_node **, int);
104 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t,
105 bus_addr_t, int, int);
106 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t);
108 static int bwi_init_tx_ring32(struct bwi_softc *, int);
109 static int bwi_init_rx_ring32(struct bwi_softc *);
110 static int bwi_init_txstats32(struct bwi_softc *);
111 static void bwi_free_tx_ring32(struct bwi_softc *, int);
112 static void bwi_free_rx_ring32(struct bwi_softc *);
113 static void bwi_free_txstats32(struct bwi_softc *);
114 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int);
115 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *,
116 int, bus_addr_t, int);
117 static int bwi_rxeof32(struct bwi_softc *);
118 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int);
119 static void bwi_txeof_status32(struct bwi_softc *);
121 static int bwi_init_tx_ring64(struct bwi_softc *, int);
122 static int bwi_init_rx_ring64(struct bwi_softc *);
123 static int bwi_init_txstats64(struct bwi_softc *);
124 static void bwi_free_tx_ring64(struct bwi_softc *, int);
125 static void bwi_free_rx_ring64(struct bwi_softc *);
126 static void bwi_free_txstats64(struct bwi_softc *);
127 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int);
128 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *,
129 int, bus_addr_t, int);
130 static int bwi_rxeof64(struct bwi_softc *);
131 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int);
132 static void bwi_txeof_status64(struct bwi_softc *);
134 static void bwi_intr(void *);
135 static int bwi_rxeof(struct bwi_softc *, int);
136 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int);
137 static void bwi_txeof(struct bwi_softc *);
138 static void bwi_txeof_status(struct bwi_softc *, int);
139 static void bwi_enable_intrs(struct bwi_softc *, uint32_t);
140 static void bwi_disable_intrs(struct bwi_softc *, uint32_t);
141 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *);
142 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *,
143 struct bwi_rxbuf_hdr *, const void *, int, int);
145 static int bwi_dma_alloc(struct bwi_softc *);
146 static void bwi_dma_free(struct bwi_softc *);
147 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t,
148 struct bwi_ring_data *, bus_size_t,
150 static int bwi_dma_mbuf_create(struct bwi_softc *);
151 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int);
152 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t);
153 static void bwi_dma_txstats_free(struct bwi_softc *);
154 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
155 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int,
158 static void bwi_power_on(struct bwi_softc *, int);
159 static int bwi_power_off(struct bwi_softc *, int);
160 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode);
161 static int bwi_set_clock_delay(struct bwi_softc *);
162 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *);
163 static int bwi_get_pwron_delay(struct bwi_softc *sc);
164 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t,
166 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *);
167 static int bwi_set_chan(struct bwi_softc *, struct ieee80211_channel *);
169 static void bwi_get_card_flags(struct bwi_softc *);
170 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *);
172 static int bwi_bus_attach(struct bwi_softc *);
173 static int bwi_bbp_attach(struct bwi_softc *);
174 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode);
175 static void bwi_bbp_power_off(struct bwi_softc *);
177 static const char *bwi_regwin_name(const struct bwi_regwin *);
178 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *);
179 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *);
180 static int bwi_regwin_select(struct bwi_softc *, int);
182 static void bwi_led_attach(struct bwi_softc *);
183 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state);
184 static void bwi_led_event(struct bwi_softc *, int);
185 static void bwi_led_blink_start(struct bwi_softc *, int, int);
186 static void bwi_led_blink_next(void *);
187 static void bwi_led_blink_end(void *);
189 static const struct bwi_dev {
194 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4301,
195 "Broadcom BCM4301 802.11 Wireless Lan" },
197 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4307,
198 "Broadcom BCM4307 802.11 Wireless Lan" },
200 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4311,
201 "Broadcom BCM4311 802.11 Wireless Lan" },
203 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4312,
204 "Broadcom BCM4312 802.11 Wireless Lan" },
206 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_1,
207 "Broadcom BCM4306 802.11 Wireless Lan" },
209 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_2,
210 "Broadcom BCM4306 802.11 Wireless Lan" },
212 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_3,
213 "Broadcom BCM4306 802.11 Wireless Lan" },
215 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4309,
216 "Broadcom BCM4309 802.11 Wireless Lan" },
218 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4318,
219 "Broadcom BCM4318 802.11 Wireless Lan" },
221 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4319,
222 "Broadcom BCM4319 802.11 Wireless Lan" }
225 static device_method_t bwi_methods[] = {
226 DEVMETHOD(device_probe, bwi_probe),
227 DEVMETHOD(device_attach, bwi_attach),
228 DEVMETHOD(device_detach, bwi_detach),
229 DEVMETHOD(device_shutdown, bwi_shutdown),
231 DEVMETHOD(device_suspend, bwi_suspend),
232 DEVMETHOD(device_resume, bwi_resume),
237 static driver_t bwi_driver = {
240 sizeof(struct bwi_softc)
243 static devclass_t bwi_devclass;
245 DRIVER_MODULE(bwi, pci, bwi_driver, bwi_devclass, NULL, NULL);
246 DRIVER_MODULE(bwi, cardbus, bwi_driver, bwi_devclass, NULL, NULL);
248 MODULE_DEPEND(bwi, wlan, 1, 1, 1);
249 MODULE_DEPEND(bwi, wlan_ratectl_onoe, 1, 1, 1);
251 MODULE_DEPEND(bwi, wlan_ratectl_amrr, 1, 1, 1);
253 MODULE_DEPEND(bwi, pci, 1, 1, 1);
254 MODULE_DEPEND(bwi, cardbus, 1, 1, 1);
256 static const struct {
260 } bwi_bbpid_map[] = {
261 { 0x4301, 0x4301, 0x4301 },
262 { 0x4305, 0x4307, 0x4307 },
263 { 0x4403, 0x4403, 0x4402 },
264 { 0x4610, 0x4615, 0x4610 },
265 { 0x4710, 0x4715, 0x4710 },
266 { 0x4720, 0x4725, 0x4309 }
269 static const struct {
272 } bwi_regwin_count[] = {
285 #define CLKSRC(src) \
286 [BWI_CLKSRC_ ## src] = { \
287 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \
288 .freq_max = BWI_CLKSRC_ ##src## _FMAX \
291 static const struct {
294 } bwi_clkfreq[BWI_CLKSRC_MAX] = {
302 #define VENDOR_LED_ACT(vendor) \
304 .vid = PCI_VENDOR_##vendor, \
305 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \
308 static const struct {
310 uint8_t led_act[BWI_LED_MAX];
311 } bwi_vendor_led_act[] = {
312 VENDOR_LED_ACT(COMPAQ),
313 VENDOR_LED_ACT(LINKSYS)
316 static const uint8_t bwi_default_led_act[BWI_LED_MAX] =
317 { BWI_VENDOR_LED_ACT_DEFAULT };
319 #undef VENDOR_LED_ACT
321 static const struct {
324 } bwi_led_duration[109] = {
341 #ifdef BWI_DEBUG_VERBOSE
342 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER;
344 static uint32_t bwi_debug;
346 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug);
347 #endif /* BWI_DEBUG */
349 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN];
351 static const struct ieee80211_rateset bwi_rateset_11b =
352 { 4, { 2, 4, 11, 22 } };
353 static const struct ieee80211_rateset bwi_rateset_11g =
354 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
357 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs)
359 return CSR_READ_2(sc, ofs + BWI_SPROM_START);
363 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array,
364 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len,
367 struct bwi_desc32 *desc = &desc_array[desc_idx];
368 uint32_t ctrl, addr, addr_hi, addr_lo;
370 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK);
371 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK);
373 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) |
374 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK);
376 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) |
377 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK);
378 if (desc_idx == ndesc - 1)
379 ctrl |= BWI_DESC32_C_EOR;
382 ctrl |= BWI_DESC32_C_FRAME_START |
383 BWI_DESC32_C_FRAME_END |
387 desc->addr = htole32(addr);
388 desc->ctrl = htole32(ctrl);
391 /* XXX does not belong here */
393 bwi_rate2plcp(uint8_t rate)
395 rate &= IEEE80211_RATE_VAL;
400 case 11: return 0x37;
401 case 22: return 0x6e;
402 case 44: return 0xdc;
411 case 108: return 0xc;
414 panic("unsupported rate %u", rate);
418 /* XXX does not belong here */
419 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0)
420 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5)
423 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate)
427 plcp = __SHIFTIN(bwi_rate2plcp(rate), IEEE80211_OFDM_PLCP_RATE_MASK) |
428 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK);
429 *plcp0 = htole32(plcp);
432 /* XXX does not belong here */
433 struct ieee80211_ds_plcp_hdr {
440 #define IEEE80211_DS_PLCP_SERVICE_LOCKED 0x04
441 #define IEEE80211_DS_PLCL_SERVICE_PBCC 0x08
442 #define IEEE80211_DS_PLCP_SERVICE_LENEXT5 0x20
443 #define IEEE80211_DS_PLCP_SERVICE_LENEXT6 0x40
444 #define IEEE80211_DS_PLCP_SERVICE_LENEXT7 0x80
447 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len,
450 int len, service, pkt_bitlen;
452 pkt_bitlen = pkt_len * NBBY;
453 len = howmany(pkt_bitlen * 2, rate);
455 service = IEEE80211_DS_PLCP_SERVICE_LOCKED;
456 if (rate == (11 * 2)) {
460 * PLCP service field needs to be adjusted,
461 * if TX rate is 11Mbytes/s
463 pkt_bitlen1 = len * 11;
464 if (pkt_bitlen1 - pkt_bitlen >= NBBY)
465 service |= IEEE80211_DS_PLCP_SERVICE_LENEXT7;
468 plcp->i_signal = bwi_rate2plcp(rate);
469 plcp->i_service = service;
470 plcp->i_length = htole16(len);
471 /* NOTE: do NOT touch i_crc */
475 bwi_plcp_header(void *plcp, int pkt_len, uint8_t rate)
477 enum ieee80211_modtype modtype;
480 * Assume caller has zeroed 'plcp'
483 modtype = ieee80211_rate2modtype(rate);
484 if (modtype == IEEE80211_MODTYPE_OFDM)
485 bwi_ofdm_plcp_header(plcp, pkt_len, rate);
486 else if (modtype == IEEE80211_MODTYPE_DS)
487 bwi_ds_plcp_header(plcp, pkt_len, rate);
489 panic("unsupport modulation type %u", modtype);
492 static __inline uint8_t
493 bwi_ofdm_plcp2rate(const uint32_t *plcp0)
498 plcp = le32toh(*plcp0);
499 plcp_rate = __SHIFTOUT(plcp, IEEE80211_OFDM_PLCP_RATE_MASK);
500 return ieee80211_plcp2rate(plcp_rate, 1);
503 static __inline uint8_t
504 bwi_ds_plcp2rate(const struct ieee80211_ds_plcp_hdr *hdr)
506 return ieee80211_plcp2rate(hdr->i_signal, 0);
510 bwi_probe(device_t dev)
512 const struct bwi_dev *b;
515 did = pci_get_device(dev);
516 vid = pci_get_vendor(dev);
518 for (b = bwi_devices; b->desc != NULL; ++b) {
519 if (b->did == did && b->vid == vid) {
520 device_set_desc(dev, b->desc);
528 bwi_attach(device_t dev)
530 struct bwi_softc *sc = device_get_softc(dev);
531 struct ieee80211com *ic = &sc->sc_ic;
532 struct ifnet *ifp = &ic->ic_if;
535 char ethstr[ETHER_ADDRSTRLEN + 1];
538 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
542 * Initialize sysctl variables
544 sc->sc_fw_version = BWI_FW_VERSION3;
545 sc->sc_dwell_time = 200;
546 sc->sc_led_idle = (2350 * hz) / 1000;
547 sc->sc_led_blink = 1;
548 sc->sc_txpwr_calib = 1;
550 sc->sc_debug = bwi_debug;
553 callout_init(&sc->sc_scan_ch);
554 callout_init(&sc->sc_calib_ch);
557 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
560 /* XXX Save more PCIR */
561 irq = pci_read_config(dev, PCIR_INTLINE, 4);
562 mem = pci_read_config(dev, BWI_PCIR_BAR, 4);
564 device_printf(dev, "chip is in D%d power mode "
565 "-- setting to D0\n", pci_get_powerstate(dev));
567 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
569 pci_write_config(dev, PCIR_INTLINE, irq, 4);
570 pci_write_config(dev, BWI_PCIR_BAR, mem, 4);
572 #endif /* !BURN_BRIDGE */
574 pci_enable_busmaster(dev);
576 /* Get more PCI information */
577 sc->sc_pci_revid = pci_get_revid(dev);
578 sc->sc_pci_subvid = pci_get_subvendor(dev);
579 sc->sc_pci_subdid = pci_get_subdevice(dev);
584 sc->sc_mem_rid = BWI_PCIR_BAR;
585 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
586 &sc->sc_mem_rid, RF_ACTIVE);
587 if (sc->sc_mem_res == NULL) {
588 device_printf(dev, "can't allocate IO memory\n");
591 sc->sc_mem_bt = rman_get_bustag(sc->sc_mem_res);
592 sc->sc_mem_bh = rman_get_bushandle(sc->sc_mem_res);
598 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
600 RF_SHAREABLE | RF_ACTIVE);
601 if (sc->sc_irq_res == NULL) {
602 device_printf(dev, "can't allocate irq\n");
610 sysctl_ctx_init(&sc->sc_sysctl_ctx);
611 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
612 SYSCTL_STATIC_CHILDREN(_hw),
614 device_get_nameunit(dev),
616 if (sc->sc_sysctl_tree == NULL) {
617 device_printf(dev, "can't add sysctl node\n");
622 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
623 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
624 "dwell_time", CTLFLAG_RW, &sc->sc_dwell_time, 0,
625 "Channel dwell time during scan (msec)");
626 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
627 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
628 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0,
630 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
631 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
632 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0,
633 "# ticks before LED enters idle state");
634 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
635 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
636 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0,
637 "Allow LED to blink");
638 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
639 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
640 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0,
641 "Enable software TX power calibration");
643 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
644 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
645 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags");
650 error = bwi_bbp_attach(sc);
654 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
658 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) {
659 error = bwi_set_clock_delay(sc);
663 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST);
667 error = bwi_get_pwron_delay(sc);
672 error = bwi_bus_attach(sc);
676 bwi_get_card_flags(sc);
680 for (i = 0; i < sc->sc_nmac; ++i) {
681 struct bwi_regwin *old;
683 mac = &sc->sc_mac[i];
684 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old);
688 error = bwi_mac_lateattach(mac);
692 error = bwi_regwin_switch(sc, old, NULL);
698 * XXX First MAC is known to exist
701 mac = &sc->sc_mac[0];
704 bwi_bbp_power_off(sc);
706 error = bwi_dma_alloc(sc);
711 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
712 ifp->if_init = bwi_init;
713 ifp->if_ioctl = bwi_ioctl;
714 ifp->if_start = bwi_start;
715 ifp->if_watchdog = bwi_watchdog;
716 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
717 ifq_set_ready(&ifp->if_snd);
720 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO),
721 BWI_SPROM_CARD_INFO_LOCALE);
722 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale);
725 * Setup ratesets, phytype, channels and get MAC address
727 if (phy->phy_mode == IEEE80211_MODE_11B ||
728 phy->phy_mode == IEEE80211_MODE_11G) {
731 ic->ic_sup_rates[IEEE80211_MODE_11B] = bwi_rateset_11b;
733 if (phy->phy_mode == IEEE80211_MODE_11B) {
734 chan_flags = IEEE80211_CHAN_B;
735 ic->ic_phytype = IEEE80211_T_DS;
737 chan_flags = IEEE80211_CHAN_CCK |
738 IEEE80211_CHAN_OFDM |
741 ic->ic_phytype = IEEE80211_T_OFDM;
742 ic->ic_sup_rates[IEEE80211_MODE_11G] =
746 /* XXX depend on locale */
747 for (i = 1; i <= 14; ++i) {
748 ic->ic_channels[i].ic_freq =
749 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
750 ic->ic_channels[i].ic_flags = chan_flags;
753 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, ic->ic_myaddr);
754 if (IEEE80211_IS_MULTICAST(ic->ic_myaddr)) {
755 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, ic->ic_myaddr);
756 if (IEEE80211_IS_MULTICAST(ic->ic_myaddr)) {
757 device_printf(dev, "invalid MAC address: "
758 "%s\n", kether_ntoa(ic->ic_myaddr, ethstr));
761 } else if (phy->phy_mode == IEEE80211_MODE_11A) {
766 panic("unknown phymode %d", phy->phy_mode);
769 ic->ic_caps = IEEE80211_C_SHSLOT |
770 IEEE80211_C_SHPREAMBLE |
773 ic->ic_state = IEEE80211_S_INIT;
774 ic->ic_opmode = IEEE80211_M_STA;
776 IEEE80211_ONOE_PARAM_SETUP(&sc->sc_onoe_param);
777 ic->ic_ratectl.rc_st_ratectl_cap = IEEE80211_RATECTL_CAP_ONOE;
778 ic->ic_ratectl.rc_st_ratectl = IEEE80211_RATECTL_ONOE;
779 ic->ic_ratectl.rc_st_attach = bwi_ratectl_attach;
781 ic->ic_updateslot = bwi_updateslot;
783 ieee80211_ifattach(ic);
785 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr);
786 ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS;
788 sc->sc_newstate = ic->ic_newstate;
789 ic->ic_newstate = bwi_newstate;
791 ieee80211_media_init(ic, bwi_media_change, ieee80211_media_status);
796 bpfattach_dlt(ifp, DLT_IEEE802_11_RADIO,
797 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th),
800 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(uint32_t));
801 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len);
802 sc->sc_tx_th.wt_ihdr.it_present = htole32(BWI_TX_RADIOTAP_PRESENT);
804 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(uint32_t));
805 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len);
806 sc->sc_rx_th.wr_ihdr.it_present = htole32(BWI_RX_RADIOTAP_PRESENT);
808 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, bwi_intr, sc,
809 &sc->sc_irq_handle, ifp->if_serializer);
811 device_printf(dev, "can't setup intr\n");
813 ieee80211_ifdetach(ic);
817 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sc_irq_res));
820 ieee80211_announce(ic);
829 bwi_detach(device_t dev)
831 struct bwi_softc *sc = device_get_softc(dev);
833 if (device_is_attached(dev)) {
834 struct ifnet *ifp = &sc->sc_ic.ic_if;
837 lwkt_serialize_enter(ifp->if_serializer);
839 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle);
840 lwkt_serialize_exit(ifp->if_serializer);
843 ieee80211_ifdetach(&sc->sc_ic);
845 for (i = 0; i < sc->sc_nmac; ++i)
846 bwi_mac_detach(&sc->sc_mac[i]);
849 if (sc->sc_sysctl_tree != NULL)
850 sysctl_ctx_free(&sc->sc_sysctl_ctx);
852 if (sc->sc_irq_res != NULL) {
853 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
857 if (sc->sc_mem_res != NULL) {
858 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
868 bwi_shutdown(device_t dev)
870 struct bwi_softc *sc = device_get_softc(dev);
871 struct ifnet *ifp = &sc->sc_ic.ic_if;
873 lwkt_serialize_enter(ifp->if_serializer);
875 lwkt_serialize_exit(ifp->if_serializer);
880 bwi_power_on(struct bwi_softc *sc, int with_pll)
882 uint32_t gpio_in, gpio_out, gpio_en;
885 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4);
886 if (gpio_in & BWI_PCIM_GPIO_PWR_ON)
889 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
890 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
892 gpio_out |= BWI_PCIM_GPIO_PWR_ON;
893 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
895 /* Turn off PLL first */
896 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
897 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
900 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
901 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
906 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF;
907 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
912 /* Clear "Signaled Target Abort" */
913 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2);
914 status &= ~PCIM_STATUS_STABORT;
915 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2);
919 bwi_power_off(struct bwi_softc *sc, int with_pll)
921 uint32_t gpio_out, gpio_en;
923 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */
924 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
925 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
927 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON;
928 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
930 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
931 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
934 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
935 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
940 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw,
941 struct bwi_regwin **old_rw)
948 if (!BWI_REGWIN_EXIST(rw))
951 if (sc->sc_cur_regwin != rw) {
952 error = bwi_regwin_select(sc, rw->rw_id);
954 if_printf(&sc->sc_ic.ic_if, "can't select regwin %d\n",
961 *old_rw = sc->sc_cur_regwin;
962 sc->sc_cur_regwin = rw;
967 bwi_regwin_select(struct bwi_softc *sc, int id)
969 uint32_t win = BWI_PCIM_REGWIN(id);
973 for (i = 0; i < RETRY_MAX; ++i) {
974 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4);
975 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win)
985 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev)
989 val = CSR_READ_4(sc, BWI_ID_HI);
990 *type = BWI_ID_HI_REGWIN_TYPE(val);
991 *rev = BWI_ID_HI_REGWIN_REV(val);
993 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, "
994 "vendor 0x%04x\n", *type, *rev,
995 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK));
999 bwi_bbp_attach(struct bwi_softc *sc)
1001 uint16_t bbp_id, rw_type;
1004 int error, nregwin, i;
1007 * Get 0th regwin information
1008 * NOTE: 0th regwin should exist
1010 error = bwi_regwin_select(sc, 0);
1012 device_printf(sc->sc_dev, "can't select regwin 0\n");
1015 bwi_regwin_info(sc, &rw_type, &rw_rev);
1022 if (rw_type == BWI_REGWIN_T_COM) {
1023 info = CSR_READ_4(sc, BWI_INFO);
1024 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK);
1026 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev);
1028 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
1030 uint16_t did = pci_get_device(sc->sc_dev);
1031 uint8_t revid = pci_get_revid(sc->sc_dev);
1033 for (i = 0; i < NELEM(bwi_bbpid_map); ++i) {
1034 if (did >= bwi_bbpid_map[i].did_min &&
1035 did <= bwi_bbpid_map[i].did_max) {
1036 bbp_id = bwi_bbpid_map[i].bbp_id;
1041 device_printf(sc->sc_dev, "no BBP id for device id "
1046 info = __SHIFTIN(revid, BWI_INFO_BBPREV_MASK) |
1047 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK);
1051 * Find out number of regwins
1054 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) {
1055 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK);
1057 for (i = 0; i < NELEM(bwi_regwin_count); ++i) {
1058 if (bwi_regwin_count[i].bbp_id == bbp_id) {
1059 nregwin = bwi_regwin_count[i].nregwin;
1064 device_printf(sc->sc_dev, "no number of win for "
1065 "BBP id 0x%04x\n", bbp_id);
1070 /* Record BBP id/rev for later using */
1071 sc->sc_bbp_id = bbp_id;
1072 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK);
1073 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK);
1074 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n",
1075 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg);
1077 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n",
1078 nregwin, sc->sc_cap);
1081 * Create rest of the regwins
1084 /* Don't re-create common regwin, if it is already created */
1085 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0;
1087 for (; i < nregwin; ++i) {
1089 * Get regwin information
1091 error = bwi_regwin_select(sc, i);
1093 device_printf(sc->sc_dev,
1094 "can't select regwin %d\n", i);
1097 bwi_regwin_info(sc, &rw_type, &rw_rev);
1101 * 1) Bus (PCI/PCIE) regwin
1103 * Ignore rest types of regwin
1105 if (rw_type == BWI_REGWIN_T_BUSPCI ||
1106 rw_type == BWI_REGWIN_T_BUSPCIE) {
1107 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
1108 device_printf(sc->sc_dev,
1109 "bus regwin already exists\n");
1111 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i,
1114 } else if (rw_type == BWI_REGWIN_T_MAC) {
1115 /* XXX ignore return value */
1116 bwi_mac_attach(sc, i, rw_rev);
1120 /* At least one MAC shold exist */
1121 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) {
1122 device_printf(sc->sc_dev, "no MAC was found\n");
1125 KKASSERT(sc->sc_nmac > 0);
1127 /* Bus regwin must exist */
1128 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
1129 device_printf(sc->sc_dev, "no bus regwin was found\n");
1133 /* Start with first MAC */
1134 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL);
1142 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac)
1144 struct bwi_regwin *old, *bus;
1148 bus = &sc->sc_bus_regwin;
1149 KKASSERT(sc->sc_cur_regwin == &mac->mac_regwin);
1152 * Tell bus to generate requested interrupts
1154 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) {
1156 * NOTE: Read BWI_FLAGS from MAC regwin
1158 val = CSR_READ_4(sc, BWI_FLAGS);
1160 error = bwi_regwin_switch(sc, bus, &old);
1164 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK));
1168 mac_mask = 1 << mac->mac_id;
1170 error = bwi_regwin_switch(sc, bus, &old);
1174 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4);
1175 val |= mac_mask << 8;
1176 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4);
1179 if (sc->sc_flags & BWI_F_BUS_INITED)
1182 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) {
1184 * Enable prefetch and burst
1186 CSR_SETBITS_4(sc, BWI_BUS_CONFIG,
1187 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST);
1189 if (bus->rw_rev < 5) {
1190 struct bwi_regwin *com = &sc->sc_com_regwin;
1193 * Configure timeouts for bus operation
1197 * Set service timeout and request timeout
1199 CSR_SETBITS_4(sc, BWI_CONF_LO,
1200 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) |
1201 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK));
1204 * If there is common regwin, we switch to that regwin
1205 * and switch back to bus regwin once we have done.
1207 if (BWI_REGWIN_EXIST(com)) {
1208 error = bwi_regwin_switch(sc, com, NULL);
1213 /* Let bus know what we have changed */
1214 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC);
1215 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
1216 CSR_WRITE_4(sc, BWI_BUS_DATA, 0);
1217 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
1219 if (BWI_REGWIN_EXIST(com)) {
1220 error = bwi_regwin_switch(sc, bus, NULL);
1224 } else if (bus->rw_rev >= 11) {
1226 * Enable memory read multiple
1228 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM);
1234 sc->sc_flags |= BWI_F_BUS_INITED;
1236 return bwi_regwin_switch(sc, old, NULL);
1240 bwi_get_card_flags(struct bwi_softc *sc)
1242 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS);
1243 if (sc->sc_card_flags == 0xffff)
1244 sc->sc_card_flags = 0;
1246 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE &&
1247 sc->sc_pci_subdid == 0x4e && /* XXX */
1248 sc->sc_pci_revid > 0x40)
1249 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9;
1251 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags);
1255 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr)
1259 for (i = 0; i < 3; ++i) {
1260 *((uint16_t *)eaddr + i) =
1261 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i));
1266 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq)
1268 struct bwi_regwin *com;
1273 bzero(freq, sizeof(*freq));
1274 com = &sc->sc_com_regwin;
1276 KKASSERT(BWI_REGWIN_EXIST(com));
1277 KKASSERT(sc->sc_cur_regwin == com);
1278 KKASSERT(sc->sc_cap & BWI_CAP_CLKMODE);
1281 * Calculate clock frequency
1285 if (com->rw_rev < 6) {
1286 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
1287 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) {
1288 src = BWI_CLKSRC_PCI;
1291 src = BWI_CLKSRC_CS_OSC;
1294 } else if (com->rw_rev < 10) {
1295 val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1297 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC);
1298 if (src == BWI_CLKSRC_LP_OSC) {
1301 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;
1303 /* Unknown source */
1304 if (src >= BWI_CLKSRC_MAX)
1305 src = BWI_CLKSRC_CS_OSC;
1308 val = CSR_READ_4(sc, BWI_CLOCK_INFO);
1310 src = BWI_CLKSRC_CS_OSC;
1311 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;
1314 KKASSERT(src >= 0 && src < BWI_CLKSRC_MAX);
1317 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n",
1318 src == BWI_CLKSRC_PCI ? "PCI" :
1319 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC"));
1321 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div;
1322 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div;
1324 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n",
1325 freq->clkfreq_min, freq->clkfreq_max);
1329 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
1331 struct bwi_regwin *old, *com;
1332 uint32_t clk_ctrl, clk_src;
1333 int error, pwr_off = 0;
1335 com = &sc->sc_com_regwin;
1336 if (!BWI_REGWIN_EXIST(com))
1339 if (com->rw_rev >= 10 || com->rw_rev < 6)
1343 * For common regwin whose rev is [6, 10), the chip
1344 * must be capable to change clock mode.
1346 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
1349 error = bwi_regwin_switch(sc, com, &old);
1353 if (clk_mode == BWI_CLOCK_MODE_FAST)
1354 bwi_power_on(sc, 0); /* Don't turn on PLL */
1356 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1357 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC);
1360 case BWI_CLOCK_MODE_FAST:
1361 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW;
1362 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL;
1364 case BWI_CLOCK_MODE_SLOW:
1365 clk_ctrl |= BWI_CLOCK_CTRL_SLOW;
1367 case BWI_CLOCK_MODE_DYN:
1368 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW |
1369 BWI_CLOCK_CTRL_IGNPLL |
1370 BWI_CLOCK_CTRL_NODYN);
1371 if (clk_src != BWI_CLKSRC_CS_OSC) {
1372 clk_ctrl |= BWI_CLOCK_CTRL_NODYN;
1377 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl);
1380 bwi_power_off(sc, 0); /* Leave PLL as it is */
1382 return bwi_regwin_switch(sc, old, NULL);
1386 bwi_set_clock_delay(struct bwi_softc *sc)
1388 struct bwi_regwin *old, *com;
1391 com = &sc->sc_com_regwin;
1392 if (!BWI_REGWIN_EXIST(com))
1395 error = bwi_regwin_switch(sc, com, &old);
1399 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) {
1400 if (sc->sc_bbp_rev == 0)
1401 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0);
1402 else if (sc->sc_bbp_rev == 1)
1403 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1);
1406 if (sc->sc_cap & BWI_CAP_CLKMODE) {
1407 if (com->rw_rev >= 10) {
1408 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000);
1410 struct bwi_clock_freq freq;
1412 bwi_get_clock_freq(sc, &freq);
1413 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY,
1414 howmany(freq.clkfreq_max * 150, 1000000));
1415 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY,
1416 howmany(freq.clkfreq_max * 15, 1000000));
1420 return bwi_regwin_switch(sc, old, NULL);
1426 bwi_init_statechg(xsc, 1);
1430 bwi_init_statechg(struct bwi_softc *sc, int statechg)
1432 struct ieee80211com *ic = &sc->sc_ic;
1433 struct ifnet *ifp = &ic->ic_if;
1434 struct bwi_mac *mac;
1437 ASSERT_SERIALIZED(ifp->if_serializer);
1439 error = bwi_stop(sc, statechg);
1441 if_printf(ifp, "can't stop\n");
1445 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
1449 mac = &sc->sc_mac[0];
1450 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL);
1454 error = bwi_mac_init(mac);
1458 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN);
1460 bcopy(IF_LLADDR(ifp), ic->ic_myaddr, sizeof(ic->ic_myaddr));
1462 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */
1463 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, ic->ic_myaddr);
1465 bwi_mac_reset_hwkeys(mac);
1467 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) {
1472 * Drain any possible pending TX status
1474 for (i = 0; i < NRETRY; ++i) {
1475 if ((CSR_READ_4(sc, BWI_TXSTATUS0) &
1476 BWI_TXSTATUS0_VALID) == 0)
1478 CSR_READ_4(sc, BWI_TXSTATUS1);
1481 if_printf(ifp, "can't drain TX status\n");
1485 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G)
1486 bwi_mac_updateslot(mac, 1);
1489 error = bwi_mac_start(mac);
1494 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1496 ifp->if_flags |= IFF_RUNNING;
1497 ifq_clr_oactive(&ifp->if_snd);
1500 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1501 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
1502 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
1504 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
1507 ieee80211_new_state(ic, ic->ic_state, -1);
1517 bwi_ioctl(struct ifnet *ifp, u_long cmd, caddr_t req, struct ucred *cr)
1519 struct bwi_softc *sc = ifp->if_softc;
1522 ASSERT_SERIALIZED(ifp->if_serializer);
1526 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1527 (IFF_UP | IFF_RUNNING)) {
1528 struct bwi_mac *mac;
1531 KKASSERT(sc->sc_cur_regwin->rw_type ==
1533 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1535 if ((ifp->if_flags & IFF_PROMISC) &&
1536 (sc->sc_flags & BWI_F_PROMISC) == 0) {
1538 sc->sc_flags |= BWI_F_PROMISC;
1539 } else if ((ifp->if_flags & IFF_PROMISC) == 0 &&
1540 (sc->sc_flags & BWI_F_PROMISC)) {
1542 sc->sc_flags &= ~BWI_F_PROMISC;
1546 bwi_mac_set_promisc(mac, promisc);
1549 if (ifp->if_flags & IFF_UP) {
1550 if ((ifp->if_flags & IFF_RUNNING) == 0)
1553 if (ifp->if_flags & IFF_RUNNING)
1558 error = ieee80211_ioctl(&sc->sc_ic, cmd, req, cr);
1562 if (error == ENETRESET) {
1563 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1564 (IFF_UP | IFF_RUNNING))
1572 bwi_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1574 struct bwi_softc *sc = ifp->if_softc;
1575 struct ieee80211com *ic = &sc->sc_ic;
1576 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1579 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1580 ASSERT_SERIALIZED(ifp->if_serializer);
1582 if (ifq_is_oactive(&ifp->if_snd) || (ifp->if_flags & IFF_RUNNING) == 0)
1588 while (tbd->tbd_buf[idx].tb_mbuf == NULL) {
1589 struct ieee80211_frame *wh;
1590 struct ieee80211_node *ni;
1594 if (!IF_QEMPTY(&ic->ic_mgtq)) {
1595 IF_DEQUEUE(&ic->ic_mgtq, m);
1597 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1598 m->m_pkthdr.rcvif = NULL;
1601 } else if (!ifq_is_empty(&ifp->if_snd)) {
1602 struct ether_header *eh;
1604 if (ic->ic_state != IEEE80211_S_RUN) {
1605 ifq_purge(&ifp->if_snd);
1609 m = ifq_dequeue(&ifp->if_snd, NULL);
1613 if (m->m_len < sizeof(*eh)) {
1614 m = m_pullup(m, sizeof(*eh));
1620 eh = mtod(m, struct ether_header *);
1622 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
1633 m = ieee80211_encap(ic, m, ni);
1635 ieee80211_free_node(ni);
1643 if (ic->ic_rawbpf != NULL)
1644 bpf_mtap(ic->ic_rawbpf, m);
1646 wh = mtod(m, struct ieee80211_frame *);
1647 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1648 if (ieee80211_crypto_encap(ic, ni, m) == NULL) {
1649 ieee80211_free_node(ni);
1655 wh = NULL; /* Catch any invalid use */
1657 if (bwi_encap(sc, idx, m, &ni, mgt_pkt) != 0) {
1658 /* 'm' is freed in bwi_encap() if we reach here */
1660 ieee80211_free_node(ni);
1667 idx = (idx + 1) % BWI_TX_NDESC;
1669 if (tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) {
1670 ifq_set_oactive(&ifp->if_snd);
1677 sc->sc_tx_timer = 5;
1682 bwi_watchdog(struct ifnet *ifp)
1684 struct bwi_softc *sc = ifp->if_softc;
1686 ASSERT_SERIALIZED(ifp->if_serializer);
1690 if ((ifp->if_flags & IFF_RUNNING) == 0)
1693 if (sc->sc_tx_timer) {
1694 if (--sc->sc_tx_timer == 0) {
1695 if_printf(ifp, "watchdog timeout\n");
1702 ieee80211_watchdog(&sc->sc_ic);
1706 bwi_stop(struct bwi_softc *sc, int state_chg)
1708 struct ieee80211com *ic = &sc->sc_ic;
1709 struct ifnet *ifp = &ic->ic_if;
1710 struct bwi_mac *mac;
1711 int i, error, pwr_off = 0;
1713 ASSERT_SERIALIZED(ifp->if_serializer);
1716 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
1718 bwi_newstate_begin(sc, IEEE80211_S_INIT);
1720 if (ifp->if_flags & IFF_RUNNING) {
1721 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1722 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1724 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1725 CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1729 for (i = 0; i < sc->sc_nmac; ++i) {
1730 struct bwi_regwin *old_rw;
1732 mac = &sc->sc_mac[i];
1733 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0)
1736 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw);
1740 bwi_mac_shutdown(mac);
1743 bwi_regwin_switch(sc, old_rw, NULL);
1747 bwi_bbp_power_off(sc);
1749 sc->sc_tx_timer = 0;
1751 ifp->if_flags &= ~IFF_RUNNING;
1752 ifq_clr_oactive(&ifp->if_snd);
1759 struct bwi_softc *sc = xsc;
1760 struct bwi_mac *mac;
1761 struct ifnet *ifp = &sc->sc_ic.ic_if;
1762 uint32_t intr_status;
1763 uint32_t txrx_intr_status[BWI_TXRX_NRING];
1764 int i, txrx_error, tx = 0, rx_data = -1;
1766 ASSERT_SERIALIZED(ifp->if_serializer);
1768 if ((ifp->if_flags & IFF_RUNNING) == 0)
1772 * Get interrupt status
1774 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
1775 if (intr_status == 0xffffffff) /* Not for us */
1778 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status);
1780 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1781 if (intr_status == 0) /* Nothing is interesting */
1784 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1785 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1788 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr");
1789 for (i = 0; i < BWI_TXRX_NRING; ++i) {
1792 if (BWI_TXRX_IS_RX(i))
1793 mask = BWI_TXRX_RX_INTRS;
1795 mask = BWI_TXRX_TX_INTRS;
1797 txrx_intr_status[i] =
1798 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;
1800 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x",
1801 i, txrx_intr_status[i]);
1803 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) {
1804 if_printf(ifp, "intr fatal TX/RX (%d) error 0x%08x\n",
1805 i, txrx_intr_status[i]);
1809 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", "");
1812 * Acknowledge interrupt
1814 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status);
1816 for (i = 0; i < BWI_TXRX_NRING; ++i)
1817 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]);
1819 /* Disable all interrupts */
1820 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1822 if (intr_status & BWI_INTR_PHY_TXERR) {
1823 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) {
1824 if_printf(ifp, "intr PHY TX error\n");
1825 /* XXX to netisr0? */
1826 bwi_init_statechg(sc, 0);
1832 /* TODO: reset device */
1835 if (intr_status & BWI_INTR_TBTT)
1836 bwi_mac_config_ps(mac);
1838 if (intr_status & BWI_INTR_EO_ATIM)
1839 if_printf(ifp, "EO_ATIM\n");
1841 if (intr_status & BWI_INTR_PMQ) {
1843 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0)
1846 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
1849 if (intr_status & BWI_INTR_NOISE)
1850 if_printf(ifp, "intr noise\n");
1852 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX)
1853 rx_data = sc->sc_rxeof(sc);
1855 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) {
1856 sc->sc_txeof_status(sc);
1860 if (intr_status & BWI_INTR_TX_DONE) {
1865 /* Re-enable interrupts */
1866 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1868 if (sc->sc_blink_led != NULL && sc->sc_led_blink) {
1869 int evt = BWI_LED_EVENT_NONE;
1871 if (tx && rx_data > 0) {
1872 if (sc->sc_rx_rate > sc->sc_tx_rate)
1873 evt = BWI_LED_EVENT_RX;
1875 evt = BWI_LED_EVENT_TX;
1877 evt = BWI_LED_EVENT_TX;
1878 } else if (rx_data > 0) {
1879 evt = BWI_LED_EVENT_RX;
1880 } else if (rx_data == 0) {
1881 evt = BWI_LED_EVENT_POLL;
1884 if (evt != BWI_LED_EVENT_NONE)
1885 bwi_led_event(sc, evt);
1890 bwi_newstate_begin(struct bwi_softc *sc, enum ieee80211_state nstate)
1892 callout_stop(&sc->sc_scan_ch);
1893 callout_stop(&sc->sc_calib_ch);
1895 ieee80211_ratectl_newstate(&sc->sc_ic, nstate);
1896 bwi_led_newstate(sc, nstate);
1898 if (nstate == IEEE80211_S_INIT)
1899 sc->sc_txpwrcb_type = BWI_TXPWR_INIT;
1903 bwi_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
1905 struct bwi_softc *sc = ic->ic_if.if_softc;
1906 struct ifnet *ifp = &ic->ic_if;
1909 ASSERT_SERIALIZED(ifp->if_serializer);
1911 bwi_newstate_begin(sc, nstate);
1913 if (nstate == IEEE80211_S_INIT)
1916 error = bwi_set_chan(sc, ic->ic_curchan);
1918 if_printf(ifp, "can't set channel to %u\n",
1919 ieee80211_chan2ieee(ic, ic->ic_curchan));
1923 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
1925 } else if (nstate == IEEE80211_S_RUN) {
1926 struct bwi_mac *mac;
1928 bwi_set_bssid(sc, ic->ic_bss->ni_bssid);
1930 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1931 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1933 /* Initial TX power calibration */
1934 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT);
1936 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE;
1938 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
1941 bwi_set_bssid(sc, bwi_zero_addr);
1945 error = sc->sc_newstate(ic, nstate, arg);
1947 if (nstate == IEEE80211_S_SCAN) {
1948 callout_reset(&sc->sc_scan_ch,
1949 (sc->sc_dwell_time * hz) / 1000,
1951 } else if (nstate == IEEE80211_S_RUN) {
1952 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc);
1958 bwi_media_change(struct ifnet *ifp)
1962 ASSERT_SERIALIZED(ifp->if_serializer);
1964 error = ieee80211_media_change(ifp);
1965 if (error != ENETRESET)
1968 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING))
1969 bwi_init(ifp->if_softc);
1974 bwi_dma_alloc(struct bwi_softc *sc)
1976 int error, i, has_txstats;
1977 bus_addr_t lowaddr = 0;
1978 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0;
1979 uint32_t txrx_ctrl_step = 0;
1982 for (i = 0; i < sc->sc_nmac; ++i) {
1983 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) {
1989 switch (sc->sc_bus_space) {
1990 case BWI_BUS_SPACE_30BIT:
1991 case BWI_BUS_SPACE_32BIT:
1992 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT)
1993 lowaddr = BWI_BUS_SPACE_MAXADDR;
1995 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1996 desc_sz = sizeof(struct bwi_desc32);
1997 txrx_ctrl_step = 0x20;
1999 sc->sc_init_tx_ring = bwi_init_tx_ring32;
2000 sc->sc_free_tx_ring = bwi_free_tx_ring32;
2001 sc->sc_init_rx_ring = bwi_init_rx_ring32;
2002 sc->sc_free_rx_ring = bwi_free_rx_ring32;
2003 sc->sc_setup_rxdesc = bwi_setup_rx_desc32;
2004 sc->sc_setup_txdesc = bwi_setup_tx_desc32;
2005 sc->sc_rxeof = bwi_rxeof32;
2006 sc->sc_start_tx = bwi_start_tx32;
2008 sc->sc_init_txstats = bwi_init_txstats32;
2009 sc->sc_free_txstats = bwi_free_txstats32;
2010 sc->sc_txeof_status = bwi_txeof_status32;
2014 case BWI_BUS_SPACE_64BIT:
2015 lowaddr = BUS_SPACE_MAXADDR; /* XXX */
2016 desc_sz = sizeof(struct bwi_desc64);
2017 txrx_ctrl_step = 0x40;
2019 sc->sc_init_tx_ring = bwi_init_tx_ring64;
2020 sc->sc_free_tx_ring = bwi_free_tx_ring64;
2021 sc->sc_init_rx_ring = bwi_init_rx_ring64;
2022 sc->sc_free_rx_ring = bwi_free_rx_ring64;
2023 sc->sc_setup_rxdesc = bwi_setup_rx_desc64;
2024 sc->sc_setup_txdesc = bwi_setup_tx_desc64;
2025 sc->sc_rxeof = bwi_rxeof64;
2026 sc->sc_start_tx = bwi_start_tx64;
2028 sc->sc_init_txstats = bwi_init_txstats64;
2029 sc->sc_free_txstats = bwi_free_txstats64;
2030 sc->sc_txeof_status = bwi_txeof_status64;
2035 KKASSERT(lowaddr != 0);
2036 KKASSERT(desc_sz != 0);
2037 KKASSERT(txrx_ctrl_step != 0);
2039 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN);
2040 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN);
2043 * Create top level DMA tag
2045 error = bus_dma_tag_create(NULL, BWI_ALIGN, 0,
2046 lowaddr, BUS_SPACE_MAXADDR,
2049 BUS_SPACE_UNRESTRICTED,
2050 BUS_SPACE_MAXSIZE_32BIT,
2051 0, &sc->sc_parent_dtag);
2053 device_printf(sc->sc_dev, "can't create parent DMA tag\n");
2057 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step)
2060 * Create TX ring DMA stuffs
2062 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
2063 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2065 tx_ring_sz, 1, BUS_SPACE_MAXSIZE_32BIT,
2066 0, &sc->sc_txring_dtag);
2068 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n");
2072 for (i = 0; i < BWI_TX_NRING; ++i) {
2073 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag,
2074 &sc->sc_tx_rdata[i], tx_ring_sz,
2077 device_printf(sc->sc_dev, "%dth TX ring "
2078 "DMA alloc failed\n", i);
2084 * Create RX ring DMA stuffs
2086 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
2087 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2089 rx_ring_sz, 1, BUS_SPACE_MAXSIZE_32BIT,
2090 0, &sc->sc_rxring_dtag);
2092 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n");
2096 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata,
2097 rx_ring_sz, TXRX_CTRL(0));
2099 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n");
2104 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz);
2106 device_printf(sc->sc_dev,
2107 "TX stats DMA alloc failed\n");
2114 return bwi_dma_mbuf_create(sc);
2118 bwi_dma_free(struct bwi_softc *sc)
2120 if (sc->sc_txring_dtag != NULL) {
2123 for (i = 0; i < BWI_TX_NRING; ++i) {
2124 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i];
2126 if (rd->rdata_desc != NULL) {
2127 bus_dmamap_unload(sc->sc_txring_dtag,
2129 bus_dmamem_free(sc->sc_txring_dtag,
2134 bus_dma_tag_destroy(sc->sc_txring_dtag);
2137 if (sc->sc_rxring_dtag != NULL) {
2138 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2140 if (rd->rdata_desc != NULL) {
2141 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap);
2142 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc,
2145 bus_dma_tag_destroy(sc->sc_rxring_dtag);
2148 bwi_dma_txstats_free(sc);
2149 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1);
2151 if (sc->sc_parent_dtag != NULL)
2152 bus_dma_tag_destroy(sc->sc_parent_dtag);
2156 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag,
2157 struct bwi_ring_data *rd, bus_size_t size,
2162 error = bus_dmamem_alloc(dtag, &rd->rdata_desc,
2163 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2166 device_printf(sc->sc_dev, "can't allocate DMA mem\n");
2170 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size,
2171 bwi_dma_ring_addr, &rd->rdata_paddr,
2174 device_printf(sc->sc_dev, "can't load DMA mem\n");
2175 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap);
2176 rd->rdata_desc = NULL;
2180 rd->rdata_txrx_ctrl = txrx_ctrl;
2185 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base,
2188 struct bwi_txstats_data *st;
2189 bus_size_t dma_size;
2192 st = kmalloc(sizeof(*st), M_DEVBUF, M_WAITOK | M_ZERO);
2193 sc->sc_txstats = st;
2196 * Create TX stats descriptor DMA stuffs
2198 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN);
2200 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
2201 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2203 dma_size, 1, BUS_SPACE_MAXSIZE_32BIT,
2204 0, &st->stats_ring_dtag);
2206 device_printf(sc->sc_dev, "can't create txstats ring "
2211 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring,
2212 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2213 &st->stats_ring_dmap);
2215 device_printf(sc->sc_dev, "can't allocate txstats ring "
2217 bus_dma_tag_destroy(st->stats_ring_dtag);
2218 st->stats_ring_dtag = NULL;
2222 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap,
2223 st->stats_ring, dma_size,
2224 bwi_dma_ring_addr, &st->stats_ring_paddr,
2227 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n");
2228 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2229 st->stats_ring_dmap);
2230 bus_dma_tag_destroy(st->stats_ring_dtag);
2231 st->stats_ring_dtag = NULL;
2236 * Create TX stats DMA stuffs
2238 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC,
2241 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_ALIGN, 0,
2242 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2244 dma_size, 1, BUS_SPACE_MAXSIZE_32BIT,
2245 0, &st->stats_dtag);
2247 device_printf(sc->sc_dev, "can't create txstats DMA tag\n");
2251 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats,
2252 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2255 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n");
2256 bus_dma_tag_destroy(st->stats_dtag);
2257 st->stats_dtag = NULL;
2261 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats,
2262 dma_size, bwi_dma_ring_addr, &st->stats_paddr,
2265 device_printf(sc->sc_dev, "can't load txstats DMA mem\n");
2266 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2267 bus_dma_tag_destroy(st->stats_dtag);
2268 st->stats_dtag = NULL;
2272 st->stats_ctrl_base = ctrl_base;
2277 bwi_dma_txstats_free(struct bwi_softc *sc)
2279 struct bwi_txstats_data *st;
2281 if (sc->sc_txstats == NULL)
2283 st = sc->sc_txstats;
2285 if (st->stats_ring_dtag != NULL) {
2286 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap);
2287 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2288 st->stats_ring_dmap);
2289 bus_dma_tag_destroy(st->stats_ring_dtag);
2292 if (st->stats_dtag != NULL) {
2293 bus_dmamap_unload(st->stats_dtag, st->stats_dmap);
2294 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2295 bus_dma_tag_destroy(st->stats_dtag);
2298 kfree(st, M_DEVBUF);
2302 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2304 KASSERT(nseg == 1, ("too many segments"));
2305 *((bus_addr_t *)arg) = seg->ds_addr;
2309 bwi_dma_mbuf_create(struct bwi_softc *sc)
2311 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2312 int i, j, k, ntx, error;
2315 * Create TX/RX mbuf DMA tag
2317 error = bus_dma_tag_create(sc->sc_parent_dtag, 1, 0,
2318 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2319 NULL, NULL, MCLBYTES, 1,
2320 BUS_SPACE_MAXSIZE_32BIT,
2321 0, &sc->sc_buf_dtag);
2323 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
2330 * Create TX mbuf DMA map
2332 for (i = 0; i < BWI_TX_NRING; ++i) {
2333 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2335 for (j = 0; j < BWI_TX_NDESC; ++j) {
2336 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2337 &tbd->tbd_buf[j].tb_dmap);
2339 device_printf(sc->sc_dev, "can't create "
2340 "%dth tbd, %dth DMA map\n", i, j);
2343 for (k = 0; k < j; ++k) {
2344 bus_dmamap_destroy(sc->sc_buf_dtag,
2345 tbd->tbd_buf[k].tb_dmap);
2354 * Create RX mbuf DMA map and a spare DMA map
2356 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2357 &rbd->rbd_tmp_dmap);
2359 device_printf(sc->sc_dev,
2360 "can't create spare RX buf DMA map\n");
2364 for (j = 0; j < BWI_RX_NDESC; ++j) {
2365 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2366 &rbd->rbd_buf[j].rb_dmap);
2368 device_printf(sc->sc_dev, "can't create %dth "
2369 "RX buf DMA map\n", j);
2371 for (k = 0; k < j; ++k) {
2372 bus_dmamap_destroy(sc->sc_buf_dtag,
2373 rbd->rbd_buf[j].rb_dmap);
2375 bus_dmamap_destroy(sc->sc_buf_dtag,
2383 bwi_dma_mbuf_destroy(sc, ntx, 0);
2388 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx)
2392 if (sc->sc_buf_dtag == NULL)
2395 for (i = 0; i < ntx; ++i) {
2396 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2398 for (j = 0; j < BWI_TX_NDESC; ++j) {
2399 struct bwi_txbuf *tb = &tbd->tbd_buf[j];
2401 if (tb->tb_mbuf != NULL) {
2402 bus_dmamap_unload(sc->sc_buf_dtag,
2404 m_freem(tb->tb_mbuf);
2406 if (tb->tb_ni != NULL)
2407 ieee80211_free_node(tb->tb_ni);
2408 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap);
2413 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2415 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap);
2416 for (j = 0; j < BWI_RX_NDESC; ++j) {
2417 struct bwi_rxbuf *rb = &rbd->rbd_buf[j];
2419 if (rb->rb_mbuf != NULL) {
2420 bus_dmamap_unload(sc->sc_buf_dtag,
2422 m_freem(rb->rb_mbuf);
2424 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap);
2428 bus_dma_tag_destroy(sc->sc_buf_dtag);
2429 sc->sc_buf_dtag = NULL;
2433 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs)
2435 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs);
2439 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs)
2441 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs);
2445 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx)
2447 struct bwi_ring_data *rd;
2448 struct bwi_txbuf_data *tbd;
2449 uint32_t val, addr_hi, addr_lo;
2451 KKASSERT(ring_idx < BWI_TX_NRING);
2452 rd = &sc->sc_tx_rdata[ring_idx];
2453 tbd = &sc->sc_tx_bdata[ring_idx];
2458 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC);
2459 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
2460 BUS_DMASYNC_PREWRITE);
2462 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2463 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2465 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2466 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2467 BWI_TXRX32_RINGINFO_FUNC_MASK);
2468 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val);
2470 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2471 BWI_TXRX32_CTRL_ENABLE;
2472 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val);
2478 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base,
2479 bus_addr_t paddr, int hdr_size, int ndesc)
2481 uint32_t val, addr_hi, addr_lo;
2483 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2484 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2486 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2487 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2488 BWI_TXRX32_RINGINFO_FUNC_MASK);
2489 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val);
2491 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) |
2492 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2493 BWI_TXRX32_CTRL_ENABLE;
2494 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val);
2496 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
2497 (ndesc - 1) * sizeof(struct bwi_desc32));
2501 bwi_init_rx_ring32(struct bwi_softc *sc)
2503 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2506 sc->sc_rx_bdata.rbd_idx = 0;
2508 for (i = 0; i < BWI_RX_NDESC; ++i) {
2509 error = bwi_newbuf(sc, i, 1);
2511 if_printf(&sc->sc_ic.ic_if,
2512 "can't allocate %dth RX buffer\n", i);
2516 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2517 BUS_DMASYNC_PREWRITE);
2519 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr,
2520 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC);
2525 bwi_init_txstats32(struct bwi_softc *sc)
2527 struct bwi_txstats_data *st = sc->sc_txstats;
2528 bus_addr_t stats_paddr;
2531 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats));
2532 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE);
2536 stats_paddr = st->stats_paddr;
2537 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) {
2538 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i,
2539 stats_paddr, sizeof(struct bwi_txstats), 0);
2540 stats_paddr += sizeof(struct bwi_txstats);
2542 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap,
2543 BUS_DMASYNC_PREWRITE);
2545 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base,
2546 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC);
2551 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2554 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2556 KKASSERT(buf_idx < BWI_RX_NDESC);
2557 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx,
2562 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd,
2563 int buf_idx, bus_addr_t paddr, int buf_len)
2565 KKASSERT(buf_idx < BWI_TX_NDESC);
2566 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx,
2571 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx)
2578 bwi_init_rx_ring64(struct bwi_softc *sc)
2585 bwi_init_txstats64(struct bwi_softc *sc)
2592 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2599 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd,
2600 int buf_idx, bus_addr_t paddr, int buf_len)
2606 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg,
2607 bus_size_t mapsz __unused, int error)
2610 KASSERT(nseg == 1, ("too many segments(%d)", nseg));
2611 *((bus_addr_t *)arg) = seg->ds_addr;
2616 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init)
2618 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2619 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx];
2620 struct bwi_rxbuf_hdr *hdr;
2626 KKASSERT(buf_idx < BWI_RX_NDESC);
2628 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2633 * If the NIC is up and running, we need to:
2634 * - Clear RX buffer's header.
2635 * - Restore RX descriptor settings.
2642 m->m_len = m->m_pkthdr.len = MCLBYTES;
2645 * Try to load RX buf into temporary DMA map
2647 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m,
2648 bwi_dma_buf_addr, &paddr,
2649 init ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
2654 * See the comment above
2663 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap);
2665 rxbuf->rb_paddr = paddr;
2668 * Swap RX buf's DMA map with the loaded temporary one
2670 map = rxbuf->rb_dmap;
2671 rxbuf->rb_dmap = rbd->rbd_tmp_dmap;
2672 rbd->rbd_tmp_dmap = map;
2676 * Clear RX buf header
2678 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *);
2679 bzero(hdr, sizeof(*hdr));
2680 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE);
2683 * Setup RX buf descriptor
2685 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr,
2686 rxbuf->rb_mbuf->m_len - sizeof(*hdr));
2691 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs,
2692 const uint8_t *addr)
2696 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL,
2697 BWI_ADDR_FILTER_CTRL_SET | addr_ofs);
2699 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) {
2702 addr_val = (uint16_t)addr[i * 2] |
2703 (((uint16_t)addr[(i * 2) + 1]) << 8);
2704 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val);
2709 bwi_set_chan(struct bwi_softc *sc, struct ieee80211_channel *c)
2711 struct ieee80211com *ic = &sc->sc_ic;
2713 struct ifnet *ifp = &ic->ic_if;
2715 struct bwi_mac *mac;
2719 ASSERT_SERIALIZED(ifp->if_serializer);
2721 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
2722 mac = (struct bwi_mac *)sc->sc_cur_regwin;
2724 chan = ieee80211_chan2ieee(ic, c);
2726 bwi_rf_set_chan(mac, chan, 0);
2729 * Setup radio tap channel freq and flags
2731 if (IEEE80211_IS_CHAN_G(c))
2732 flags = IEEE80211_CHAN_G;
2734 flags = IEEE80211_CHAN_B;
2736 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq =
2737 htole16(c->ic_freq);
2738 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags =
2745 bwi_next_scan(void *xsc)
2747 struct bwi_softc *sc = xsc;
2748 struct ieee80211com *ic = &sc->sc_ic;
2749 struct ifnet *ifp = &ic->ic_if;
2751 lwkt_serialize_enter(ifp->if_serializer);
2753 if (ic->ic_state == IEEE80211_S_SCAN)
2754 ieee80211_next_scan(ic);
2756 lwkt_serialize_exit(ifp->if_serializer);
2760 bwi_rxeof(struct bwi_softc *sc, int end_idx)
2762 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2763 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2764 struct ieee80211com *ic = &sc->sc_ic;
2765 struct ifnet *ifp = &ic->ic_if;
2766 int idx, rx_data = 0;
2769 while (idx != end_idx) {
2770 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx];
2771 struct bwi_rxbuf_hdr *hdr;
2772 struct ieee80211_frame_min *wh;
2773 struct ieee80211_node *ni;
2777 int buflen, wh_ofs, hdr_extra, rssi, type, rate;
2780 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap,
2781 BUS_DMASYNC_POSTREAD);
2783 if (bwi_newbuf(sc, idx, 0)) {
2788 hdr = mtod(m, struct bwi_rxbuf_hdr *);
2789 flags2 = le16toh(hdr->rxh_flags2);
2792 if (flags2 & BWI_RXH_F2_TYPE2FRAME)
2794 wh_ofs = hdr_extra + 6; /* XXX magic number */
2796 buflen = le16toh(hdr->rxh_buflen);
2797 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) {
2798 if_printf(ifp, "short frame %d, hdr_extra %d\n",
2805 plcp = ((const uint8_t *)(hdr + 1) + hdr_extra);
2806 rssi = bwi_calc_rssi(sc, hdr);
2808 m->m_pkthdr.rcvif = ifp;
2809 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr);
2810 m_adj(m, sizeof(*hdr) + wh_ofs);
2812 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM)
2813 rate = bwi_ofdm_plcp2rate(plcp);
2815 rate = bwi_ds_plcp2rate(plcp);
2818 if (sc->sc_drvbpf != NULL)
2819 bwi_rx_radiotap(sc, m, hdr, plcp, rate, rssi);
2821 m_adj(m, -IEEE80211_CRC_LEN);
2823 wh = mtod(m, struct ieee80211_frame_min *);
2824 ni = ieee80211_find_rxnode(ic, wh);
2826 type = ieee80211_input(ic, m, ni, rssi - BWI_NOISE_FLOOR,
2827 le16toh(hdr->rxh_tsf));
2828 ieee80211_free_node(ni);
2830 if (type == IEEE80211_FC0_TYPE_DATA) {
2832 sc->sc_rx_rate = rate;
2835 idx = (idx + 1) % BWI_RX_NDESC;
2839 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2840 BUS_DMASYNC_PREWRITE);
2845 bwi_rxeof32(struct bwi_softc *sc)
2847 uint32_t val, rx_ctrl;
2848 int end_idx, rx_data;
2850 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl;
2852 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2853 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
2854 sizeof(struct bwi_desc32);
2856 rx_data = bwi_rxeof(sc, end_idx);
2858 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX,
2859 end_idx * sizeof(struct bwi_desc32));
2865 bwi_rxeof64(struct bwi_softc *sc)
2872 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl)
2876 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0);
2880 for (i = 0; i < NRETRY; ++i) {
2883 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2884 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) ==
2885 BWI_RX32_STATUS_STATE_DISABLED)
2891 if_printf(&sc->sc_ic.ic_if, "reset rx ring timedout\n");
2895 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0);
2899 bwi_free_txstats32(struct bwi_softc *sc)
2901 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base);
2905 bwi_free_rx_ring32(struct bwi_softc *sc)
2907 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2908 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2911 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl);
2913 for (i = 0; i < BWI_RX_NDESC; ++i) {
2914 struct bwi_rxbuf *rb = &rbd->rbd_buf[i];
2916 if (rb->rb_mbuf != NULL) {
2917 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap);
2918 m_freem(rb->rb_mbuf);
2925 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx)
2927 struct bwi_ring_data *rd;
2928 struct bwi_txbuf_data *tbd;
2929 struct ifnet *ifp = &sc->sc_ic.ic_if;
2930 uint32_t state, val;
2933 KKASSERT(ring_idx < BWI_TX_NRING);
2934 rd = &sc->sc_tx_rdata[ring_idx];
2935 tbd = &sc->sc_tx_bdata[ring_idx];
2939 for (i = 0; i < NRETRY; ++i) {
2940 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2941 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2942 if (state == BWI_TX32_STATUS_STATE_DISABLED ||
2943 state == BWI_TX32_STATUS_STATE_IDLE ||
2944 state == BWI_TX32_STATUS_STATE_STOPPED)
2950 if_printf(ifp, "wait for TX ring(%d) stable timed out\n",
2954 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0);
2955 for (i = 0; i < NRETRY; ++i) {
2956 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2957 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2958 if (state == BWI_TX32_STATUS_STATE_DISABLED)
2964 if_printf(ifp, "reset TX ring (%d) timed out\n", ring_idx);
2970 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0);
2972 for (i = 0; i < BWI_TX_NDESC; ++i) {
2973 struct bwi_txbuf *tb = &tbd->tbd_buf[i];
2975 if (tb->tb_mbuf != NULL) {
2976 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
2977 m_freem(tb->tb_mbuf);
2980 if (tb->tb_ni != NULL) {
2981 ieee80211_free_node(tb->tb_ni);
2988 bwi_free_txstats64(struct bwi_softc *sc)
2994 bwi_free_rx_ring64(struct bwi_softc *sc)
3000 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx)
3006 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m,
3007 struct ieee80211_node **ni0, int mgt_pkt)
3009 struct ieee80211com *ic = &sc->sc_ic;
3010 struct ieee80211_node *ni = *ni0;
3011 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
3012 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
3013 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
3014 struct bwi_mac *mac;
3015 struct bwi_txbuf_hdr *hdr;
3016 struct ieee80211_frame *wh;
3017 uint8_t rate, rate_fb;
3021 int pkt_len, error, mcast_pkt = 0;
3027 KKASSERT(ni != NULL);
3028 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3029 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3031 wh = mtod(m, struct ieee80211_frame *);
3033 /* Get 802.11 frame len before prepending TX header */
3034 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
3039 bzero(tb->tb_rateidx, sizeof(tb->tb_rateidx));
3041 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) {
3044 rate = IEEE80211_RS_RATE(&ni->ni_rates,
3047 if (ic->ic_fixed_rate >= 1)
3048 idx = ic->ic_fixed_rate - 1;
3051 rate_fb = IEEE80211_RS_RATE(&ni->ni_rates, idx);
3053 tb->tb_rateidx_cnt = ieee80211_ratectl_findrate(ni,
3054 m->m_pkthdr.len, tb->tb_rateidx, BWI_NTXRATE);
3056 rate = IEEE80211_RS_RATE(&ni->ni_rates,
3058 if (tb->tb_rateidx_cnt == BWI_NTXRATE) {
3059 rate_fb = IEEE80211_RS_RATE(&ni->ni_rates,
3064 tb->tb_buflen = m->m_pkthdr.len;
3067 /* Fixed at 1Mbits/s for mgt frames */
3068 rate = rate_fb = (1 * 2);
3071 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
3072 rate = rate_fb = ic->ic_mcast_rate;
3076 if (rate == 0 || rate_fb == 0) {
3077 /* XXX this should not happen */
3078 if_printf(&ic->ic_if, "invalid rate %u or fallback rate %u",
3080 rate = rate_fb = (1 * 2); /* Force 1Mbits/s */
3082 sc->sc_tx_rate = rate;
3087 if (sc->sc_drvbpf != NULL) {
3088 sc->sc_tx_th.wt_flags = 0;
3089 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3090 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3091 if (ieee80211_rate2modtype(rate) == IEEE80211_MODTYPE_DS &&
3092 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
3094 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3096 sc->sc_tx_th.wt_rate = rate;
3098 bpf_ptap(sc->sc_drvbpf, m, &sc->sc_tx_th, sc->sc_tx_th_len);
3102 * Setup the embedded TX header
3104 M_PREPEND(m, sizeof(*hdr), MB_DONTWAIT);
3106 if_printf(&ic->ic_if, "prepend TX header failed\n");
3109 hdr = mtod(m, struct bwi_txbuf_hdr *);
3111 bzero(hdr, sizeof(*hdr));
3113 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
3114 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
3120 ack_rate = ieee80211_ack_rate(ni, rate_fb);
3121 dur = ieee80211_txtime(ni,
3122 sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN,
3123 ack_rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE);
3125 hdr->txh_fb_duration = htole16(dur);
3128 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3129 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3131 bwi_plcp_header(hdr->txh_plcp, pkt_len, rate);
3132 bwi_plcp_header(hdr->txh_fb_plcp, pkt_len, rate_fb);
3134 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3135 BWI_TXH_PHY_C_ANTMODE_MASK);
3136 if (ieee80211_rate2modtype(rate) == IEEE80211_MODTYPE_OFDM)
3137 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3138 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1))
3139 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3141 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3142 if (!IEEE80211_IS_MULTICAST(wh->i_addr1))
3143 mac_ctrl |= BWI_TXH_MAC_C_ACK;
3144 if (ieee80211_rate2modtype(rate_fb) == IEEE80211_MODTYPE_OFDM)
3145 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3147 hdr->txh_mac_ctrl = htole32(mac_ctrl);
3148 hdr->txh_phy_ctrl = htole16(phy_ctrl);
3150 /* Catch any further usage */
3155 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3156 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3157 if (error && error != EFBIG) {
3158 if_printf(&ic->ic_if, "can't load TX buffer (1) %d\n", error);
3162 if (error) { /* error == EFBIG */
3165 m_new = m_defrag(m, MB_DONTWAIT);
3166 if (m_new == NULL) {
3167 if_printf(&ic->ic_if, "can't defrag TX buffer\n");
3174 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3175 bwi_dma_buf_addr, &paddr,
3178 if_printf(&ic->ic_if, "can't load TX buffer (2) %d\n",
3185 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3187 if (mgt_pkt || mcast_pkt) {
3188 /* Don't involve mcast/mgt packets into TX rate control */
3189 ieee80211_free_node(ni);
3196 p = mtod(m, const uint8_t *);
3197 for (i = 0; i < m->m_pkthdr.len; ++i) {
3198 if (i != 0 && i % 8 == 0)
3200 kprintf("%02x ", p[i]);
3205 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3206 idx, pkt_len, m->m_pkthdr.len);
3208 /* Setup TX descriptor */
3209 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3210 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3211 BUS_DMASYNC_PREWRITE);
3214 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3223 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3225 idx = (idx + 1) % BWI_TX_NDESC;
3226 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX,
3227 idx * sizeof(struct bwi_desc32));
3231 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3237 bwi_txeof_status32(struct bwi_softc *sc)
3239 struct ifnet *ifp = &sc->sc_ic.ic_if;
3240 uint32_t val, ctrl_base;
3243 ctrl_base = sc->sc_txstats->stats_ctrl_base;
3245 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);
3246 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
3247 sizeof(struct bwi_desc32);
3249 bwi_txeof_status(sc, end_idx);
3251 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
3252 end_idx * sizeof(struct bwi_desc32));
3254 if (!ifq_is_oactive(&ifp->if_snd))
3259 bwi_txeof_status64(struct bwi_softc *sc)
3265 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt)
3267 struct ifnet *ifp = &sc->sc_ic.ic_if;
3268 struct bwi_txbuf_data *tbd;
3269 struct bwi_txbuf *tb;
3270 int ring_idx, buf_idx;
3273 if_printf(ifp, "zero tx id\n");
3277 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK);
3278 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK);
3280 KKASSERT(ring_idx == BWI_TX_DATA_RING);
3281 KKASSERT(buf_idx < BWI_TX_NDESC);
3283 tbd = &sc->sc_tx_bdata[ring_idx];
3284 KKASSERT(tbd->tbd_used > 0);
3287 tb = &tbd->tbd_buf[buf_idx];
3289 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, "
3290 "acked %d, data_txcnt %d, ni %p\n",
3291 buf_idx, acked, data_txcnt, tb->tb_ni);
3293 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
3294 m_freem(tb->tb_mbuf);
3297 if (tb->tb_ni != NULL) {
3298 struct ieee80211_ratectl_res res[BWI_NTXRATE];
3301 if (data_txcnt <= BWI_SHRETRY_FB || tb->tb_rateidx_cnt == 1) {
3303 res[0].rc_res_rateidx = tb->tb_rateidx[0];
3304 res[0].rc_res_tries = data_txcnt;
3306 res_len = BWI_NTXRATE;
3307 res[0].rc_res_rateidx = tb->tb_rateidx[0];
3308 res[0].rc_res_tries = BWI_SHRETRY_FB;
3309 res[1].rc_res_rateidx = tb->tb_rateidx[1];
3310 res[1].rc_res_tries = data_txcnt - BWI_SHRETRY_FB;
3315 retry = data_txcnt > 0 ? data_txcnt - 1 : 0;
3321 ieee80211_ratectl_tx_complete(tb->tb_ni, tb->tb_buflen,
3322 res, res_len, retry, 0, !acked);
3324 ieee80211_free_node(tb->tb_ni);
3327 /* XXX mgt packet error */
3331 if (tbd->tbd_used == 0)
3332 sc->sc_tx_timer = 0;
3334 ifq_clr_oactive(&ifp->if_snd);
3338 bwi_txeof_status(struct bwi_softc *sc, int end_idx)
3340 struct bwi_txstats_data *st = sc->sc_txstats;
3343 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD);
3345 idx = st->stats_idx;
3346 while (idx != end_idx) {
3347 const struct bwi_txstats *stats = &st->stats[idx];
3349 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) {
3352 data_txcnt = __SHIFTOUT(stats->txs_txcnt,
3353 BWI_TXS_TXCNT_DATA);
3354 _bwi_txeof(sc, le16toh(stats->txs_id),
3355 stats->txs_flags & BWI_TXS_F_ACKED,
3358 idx = (idx + 1) % BWI_TXSTATS_NDESC;
3360 st->stats_idx = idx;
3364 bwi_txeof(struct bwi_softc *sc)
3366 struct ifnet *ifp = &sc->sc_ic.ic_if;
3369 uint32_t tx_status0, tx_status1;
3373 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0);
3374 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0)
3376 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1);
3378 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK);
3379 data_txcnt = __SHIFTOUT(tx_status0,
3380 BWI_TXSTATUS0_DATA_TXCNT_MASK);
3382 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING))
3385 _bwi_txeof(sc, tx_id, tx_status0 & BWI_TXSTATUS0_ACKED,
3389 if (!ifq_is_oactive(&ifp->if_snd))
3394 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
3396 bwi_power_on(sc, 1);
3397 return bwi_set_clock_mode(sc, clk_mode);
3401 bwi_bbp_power_off(struct bwi_softc *sc)
3403 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW);
3404 bwi_power_off(sc, 1);
3408 bwi_get_pwron_delay(struct bwi_softc *sc)
3410 struct bwi_regwin *com, *old;
3411 struct bwi_clock_freq freq;
3415 com = &sc->sc_com_regwin;
3416 KKASSERT(BWI_REGWIN_EXIST(com));
3418 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
3421 error = bwi_regwin_switch(sc, com, &old);
3425 bwi_get_clock_freq(sc, &freq);
3427 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);
3428 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min);
3429 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay);
3431 return bwi_regwin_switch(sc, old, NULL);
3435 bwi_bus_attach(struct bwi_softc *sc)
3437 struct bwi_regwin *bus, *old;
3440 bus = &sc->sc_bus_regwin;
3442 error = bwi_regwin_switch(sc, bus, &old);
3446 if (!bwi_regwin_is_enabled(sc, bus))
3447 bwi_regwin_enable(sc, bus, 0);
3449 /* Disable interripts */
3450 CSR_WRITE_4(sc, BWI_INTRVEC, 0);
3452 return bwi_regwin_switch(sc, old, NULL);
3456 bwi_regwin_name(const struct bwi_regwin *rw)
3458 switch (rw->rw_type) {
3459 case BWI_REGWIN_T_COM:
3461 case BWI_REGWIN_T_BUSPCI:
3463 case BWI_REGWIN_T_MAC:
3465 case BWI_REGWIN_T_BUSPCIE:
3468 panic("unknown regwin type 0x%04x", rw->rw_type);
3473 bwi_regwin_disable_bits(struct bwi_softc *sc)
3477 /* XXX cache this */
3478 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);
3479 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC,
3480 "bus rev %u\n", busrev);
3482 if (busrev == BWI_BUSREV_0)
3483 return BWI_STATE_LO_DISABLE1;
3484 else if (busrev == BWI_BUSREV_1)
3485 return BWI_STATE_LO_DISABLE2;
3487 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2);
3491 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw)
3493 uint32_t val, disable_bits;
3495 disable_bits = bwi_regwin_disable_bits(sc);
3496 val = CSR_READ_4(sc, BWI_STATE_LO);
3498 if ((val & (BWI_STATE_LO_CLOCK |
3499 BWI_STATE_LO_RESET |
3500 disable_bits)) == BWI_STATE_LO_CLOCK) {
3501 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n",
3502 bwi_regwin_name(rw));
3505 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n",
3506 bwi_regwin_name(rw));
3512 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3514 uint32_t state_lo, disable_bits;
3517 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3520 * If current regwin is in 'reset' state, it was already disabled.
3522 if (state_lo & BWI_STATE_LO_RESET) {
3523 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT,
3524 "%s was already disabled\n", bwi_regwin_name(rw));
3528 disable_bits = bwi_regwin_disable_bits(sc);
3531 * Disable normal clock
3533 state_lo = BWI_STATE_LO_CLOCK | disable_bits;
3534 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3537 * Wait until normal clock is disabled
3540 for (i = 0; i < NRETRY; ++i) {
3541 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3542 if (state_lo & disable_bits)
3547 device_printf(sc->sc_dev, "%s disable clock timeout\n",
3548 bwi_regwin_name(rw));
3551 for (i = 0; i < NRETRY; ++i) {
3554 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3555 if ((state_hi & BWI_STATE_HI_BUSY) == 0)
3560 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n",
3561 bwi_regwin_name(rw));
3566 * Reset and disable regwin with gated clock
3568 state_lo = BWI_STATE_LO_RESET | disable_bits |
3569 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK |
3570 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3571 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3573 /* Flush pending bus write */
3574 CSR_READ_4(sc, BWI_STATE_LO);
3577 /* Reset and disable regwin */
3578 state_lo = BWI_STATE_LO_RESET | disable_bits |
3579 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3580 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3582 /* Flush pending bus write */
3583 CSR_READ_4(sc, BWI_STATE_LO);
3588 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3590 uint32_t state_lo, state_hi, imstate;
3592 bwi_regwin_disable(sc, rw, flags);
3594 /* Reset regwin with gated clock */
3595 state_lo = BWI_STATE_LO_RESET |
3596 BWI_STATE_LO_CLOCK |
3597 BWI_STATE_LO_GATED_CLOCK |
3598 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3599 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3601 /* Flush pending bus write */
3602 CSR_READ_4(sc, BWI_STATE_LO);
3605 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3606 if (state_hi & BWI_STATE_HI_SERROR)
3607 CSR_WRITE_4(sc, BWI_STATE_HI, 0);
3609 imstate = CSR_READ_4(sc, BWI_IMSTATE);
3610 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) {
3611 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT);
3612 CSR_WRITE_4(sc, BWI_IMSTATE, imstate);
3615 /* Enable regwin with gated clock */
3616 state_lo = BWI_STATE_LO_CLOCK |
3617 BWI_STATE_LO_GATED_CLOCK |
3618 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3619 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3621 /* Flush pending bus write */
3622 CSR_READ_4(sc, BWI_STATE_LO);
3625 /* Enable regwin with normal clock */
3626 state_lo = BWI_STATE_LO_CLOCK |
3627 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3628 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3630 /* Flush pending bus write */
3631 CSR_READ_4(sc, BWI_STATE_LO);
3636 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid)
3638 struct ieee80211com *ic = &sc->sc_ic;
3639 struct bwi_mac *mac;
3640 struct bwi_myaddr_bssid buf;
3645 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3646 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3648 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid);
3650 bcopy(ic->ic_myaddr, buf.myaddr, sizeof(buf.myaddr));
3651 bcopy(bssid, buf.bssid, sizeof(buf.bssid));
3653 n = sizeof(buf) / sizeof(val);
3654 p = (const uint8_t *)&buf;
3655 for (i = 0; i < n; ++i) {
3659 for (j = 0; j < sizeof(val); ++j)
3660 val |= ((uint32_t)(*p++)) << (j * 8);
3662 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val);
3667 bwi_updateslot(struct ifnet *ifp)
3669 struct bwi_softc *sc = ifp->if_softc;
3670 struct ieee80211com *ic = &sc->sc_ic;
3671 struct bwi_mac *mac;
3673 if ((ifp->if_flags & IFF_RUNNING) == 0)
3676 ASSERT_SERIALIZED(ifp->if_serializer);
3678 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__);
3680 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3681 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3683 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT));
3687 bwi_calibrate(void *xsc)
3689 struct bwi_softc *sc = xsc;
3690 struct ieee80211com *ic = &sc->sc_ic;
3691 struct ifnet *ifp = &ic->ic_if;
3693 lwkt_serialize_enter(ifp->if_serializer);
3695 if (ic->ic_state == IEEE80211_S_RUN) {
3696 struct bwi_mac *mac;
3698 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3699 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3701 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
3702 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type);
3703 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
3706 /* XXX 15 seconds */
3707 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc);
3710 lwkt_serialize_exit(ifp->if_serializer);
3714 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr)
3716 struct bwi_mac *mac;
3718 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3719 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3721 return bwi_rf_calc_rssi(mac, hdr);
3725 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m,
3726 struct bwi_rxbuf_hdr *hdr, const void *plcp,
3729 const struct ieee80211_frame_min *wh;
3731 KKASSERT(sc->sc_drvbpf != NULL);
3733 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS;
3734 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE)
3735 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3737 wh = mtod(m, const struct ieee80211_frame_min *);
3738 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3739 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP;
3741 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian convertion */
3742 sc->sc_rx_th.wr_rate = rate;
3743 sc->sc_rx_th.wr_antsignal = rssi;
3744 sc->sc_rx_th.wr_antnoise = BWI_NOISE_FLOOR;
3746 bpf_ptap(sc->sc_drvbpf, m, &sc->sc_rx_th, sc->sc_rx_th_len);
3750 bwi_led_attach(struct bwi_softc *sc)
3752 const uint8_t *led_act = NULL;
3753 uint16_t gpio, val[BWI_LED_MAX];
3756 for (i = 0; i < NELEM(bwi_vendor_led_act); ++i) {
3757 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) {
3758 led_act = bwi_vendor_led_act[i].led_act;
3762 if (led_act == NULL)
3763 led_act = bwi_default_led_act;
3765 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01);
3766 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0);
3767 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1);
3769 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23);
3770 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2);
3771 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3);
3773 for (i = 0; i < BWI_LED_MAX; ++i) {
3774 struct bwi_led *led = &sc->sc_leds[i];
3776 if (val[i] == 0xff) {
3777 led->l_act = led_act[i];
3779 if (val[i] & BWI_LED_ACT_LOW)
3780 led->l_flags |= BWI_LED_F_ACTLOW;
3781 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK);
3783 led->l_mask = (1 << i);
3785 if (led->l_act == BWI_LED_ACT_BLINK_SLOW ||
3786 led->l_act == BWI_LED_ACT_BLINK_POLL ||
3787 led->l_act == BWI_LED_ACT_BLINK) {
3788 led->l_flags |= BWI_LED_F_BLINK;
3789 if (led->l_act == BWI_LED_ACT_BLINK_POLL)
3790 led->l_flags |= BWI_LED_F_POLLABLE;
3791 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW)
3792 led->l_flags |= BWI_LED_F_SLOW;
3794 if (sc->sc_blink_led == NULL) {
3795 sc->sc_blink_led = led;
3796 if (led->l_flags & BWI_LED_F_SLOW)
3797 BWI_LED_SLOWDOWN(sc->sc_led_idle);
3801 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH,
3802 "%dth led, act %d, lowact %d\n", i,
3803 led->l_act, led->l_flags & BWI_LED_F_ACTLOW);
3805 callout_init(&sc->sc_led_blink_ch);
3808 static __inline uint16_t
3809 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on)
3811 if (led->l_flags & BWI_LED_F_ACTLOW)
3816 val &= ~led->l_mask;
3821 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate)
3823 struct ieee80211com *ic = &sc->sc_ic;
3827 if (nstate == IEEE80211_S_INIT) {
3828 callout_stop(&sc->sc_led_blink_ch);
3829 sc->sc_led_blinking = 0;
3832 if ((ic->ic_if.if_flags & IFF_RUNNING) == 0)
3835 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3836 for (i = 0; i < BWI_LED_MAX; ++i) {
3837 struct bwi_led *led = &sc->sc_leds[i];
3840 if (led->l_act == BWI_LED_ACT_UNKN ||
3841 led->l_act == BWI_LED_ACT_NULL)
3844 if ((led->l_flags & BWI_LED_F_BLINK) &&
3845 nstate != IEEE80211_S_INIT)
3848 switch (led->l_act) {
3849 case BWI_LED_ACT_ON: /* Always on */
3852 case BWI_LED_ACT_OFF: /* Always off */
3853 case BWI_LED_ACT_5GHZ: /* TODO: 11A */
3859 case IEEE80211_S_INIT:
3862 case IEEE80211_S_RUN:
3863 if (led->l_act == BWI_LED_ACT_11G &&
3864 ic->ic_curmode != IEEE80211_MODE_11G)
3868 if (led->l_act == BWI_LED_ACT_ASSOC)
3875 val = bwi_led_onoff(led, val, on);
3877 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3881 bwi_led_event(struct bwi_softc *sc, int event)
3883 struct bwi_led *led = sc->sc_blink_led;
3886 if (event == BWI_LED_EVENT_POLL) {
3887 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0)
3889 if (ticks - sc->sc_led_ticks < sc->sc_led_idle)
3893 sc->sc_led_ticks = ticks;
3894 if (sc->sc_led_blinking)
3898 case BWI_LED_EVENT_RX:
3899 rate = sc->sc_rx_rate;
3901 case BWI_LED_EVENT_TX:
3902 rate = sc->sc_tx_rate;
3904 case BWI_LED_EVENT_POLL:
3908 panic("unknown LED event %d", event);
3911 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur,
3912 bwi_led_duration[rate].off_dur);
3916 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur)
3918 struct bwi_led *led = sc->sc_blink_led;
3921 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3922 val = bwi_led_onoff(led, val, 1);
3923 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3925 if (led->l_flags & BWI_LED_F_SLOW) {
3926 BWI_LED_SLOWDOWN(on_dur);
3927 BWI_LED_SLOWDOWN(off_dur);
3930 sc->sc_led_blinking = 1;
3931 sc->sc_led_blink_offdur = off_dur;
3933 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc);
3937 bwi_led_blink_next(void *xsc)
3939 struct bwi_softc *sc = xsc;
3942 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3943 val = bwi_led_onoff(sc->sc_blink_led, val, 0);
3944 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3946 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur,
3947 bwi_led_blink_end, sc);
3951 bwi_led_blink_end(void *xsc)
3953 struct bwi_softc *sc = xsc;
3955 sc->sc_led_blinking = 0;
3959 bwi_ratectl_attach(struct ieee80211com *ic, u_int rc)
3961 struct bwi_softc *sc = ic->ic_if.if_softc;
3964 case IEEE80211_RATECTL_ONOE:
3965 return &sc->sc_onoe_param;
3966 case IEEE80211_RATECTL_NONE:
3967 /* This could only happen during detaching */
3970 panic("unknown rate control algo %u", rc);