sys/dev/netif/igb/if_igb.c

   1 /*
   2  * Copyright (c) 2001-2011, Intel Corporation
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  *  1. Redistributions of source code must retain the above copyright notice,
   9  *     this list of conditions and the following disclaimer.
  10  *
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  3. Neither the name of the Intel Corporation nor the names of its
  16  *     contributors may be used to endorse or promote products derived from
  17  *     this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include "opt_ifpoll.h"
  33 #include "opt_igb.h"
  34
  35 #include <sys/param.h>
  36 #include <sys/bus.h>
  37 #include <sys/endian.h>
  38 #include <sys/interrupt.h>
  39 #include <sys/kernel.h>
  40 #include <sys/malloc.h>
  41 #include <sys/mbuf.h>
  42 #include <sys/proc.h>
  43 #include <sys/rman.h>
  44 #include <sys/serialize.h>
  45 #include <sys/serialize2.h>
  46 #include <sys/socket.h>
  47 #include <sys/sockio.h>
  48 #include <sys/sysctl.h>
  49 #include <sys/systm.h>
  50
  51 #include <net/bpf.h>
  52 #include <net/ethernet.h>
  53 #include <net/if.h>
  54 #include <net/if_arp.h>
  55 #include <net/if_dl.h>
  56 #include <net/if_media.h>
  57 #include <net/ifq_var.h>
  58 #include <net/toeplitz.h>
  59 #include <net/toeplitz2.h>
  60 #include <net/vlan/if_vlan_var.h>
  61 #include <net/vlan/if_vlan_ether.h>
  62 #include <net/if_poll.h>
  63
  64 #include <netinet/in_systm.h>
  65 #include <netinet/in.h>
  66 #include <netinet/ip.h>
  67 #include <netinet/tcp.h>
  68 #include <netinet/udp.h>
  69
  70 #include <bus/pci/pcivar.h>
  71 #include <bus/pci/pcireg.h>
  72
  73 #include <dev/netif/ig_hal/e1000_api.h>
  74 #include <dev/netif/ig_hal/e1000_82575.h>
  75 #include <dev/netif/igb/if_igb.h>
  76
  77 #ifdef IGB_RSS_DEBUG
  78 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
  79 do { \
  80         if (sc->rss_debug >= lvl) \
  81                 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
  82 } while (0)
  83 #else   /* !IGB_RSS_DEBUG */
  84 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
  85 #endif  /* IGB_RSS_DEBUG */
  86
  87 #define IGB_NAME        "Intel(R) PRO/1000 "
  88 #define IGB_DEVICE(id)  \
  89         { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
  90 #define IGB_DEVICE_NULL { 0, 0, NULL }
  91
  92 static struct igb_device {
  93         uint16_t        vid;
  94         uint16_t        did;
  95         const char      *desc;
  96 } igb_devices[] = {
  97         IGB_DEVICE(82575EB_COPPER),
  98         IGB_DEVICE(82575EB_FIBER_SERDES),
  99         IGB_DEVICE(82575GB_QUAD_COPPER),
 100         IGB_DEVICE(82576),
 101         IGB_DEVICE(82576_NS),
 102         IGB_DEVICE(82576_NS_SERDES),
 103         IGB_DEVICE(82576_FIBER),
 104         IGB_DEVICE(82576_SERDES),
 105         IGB_DEVICE(82576_SERDES_QUAD),
 106         IGB_DEVICE(82576_QUAD_COPPER),
 107         IGB_DEVICE(82576_QUAD_COPPER_ET2),
 108         IGB_DEVICE(82576_VF),
 109         IGB_DEVICE(82580_COPPER),
 110         IGB_DEVICE(82580_FIBER),
 111         IGB_DEVICE(82580_SERDES),
 112         IGB_DEVICE(82580_SGMII),
 113         IGB_DEVICE(82580_COPPER_DUAL),
 114         IGB_DEVICE(82580_QUAD_FIBER),
 115         IGB_DEVICE(DH89XXCC_SERDES),
 116         IGB_DEVICE(DH89XXCC_SGMII),
 117         IGB_DEVICE(DH89XXCC_SFP),
 118         IGB_DEVICE(DH89XXCC_BACKPLANE),
 119         IGB_DEVICE(I350_COPPER),
 120         IGB_DEVICE(I350_FIBER),
 121         IGB_DEVICE(I350_SERDES),
 122         IGB_DEVICE(I350_SGMII),
 123         IGB_DEVICE(I350_VF),
 124
 125         /* required last entry */
 126         IGB_DEVICE_NULL
 127 };
 128
 129 static int      igb_probe(device_t);
 130 static int      igb_attach(device_t);
 131 static int      igb_detach(device_t);
 132 static int      igb_shutdown(device_t);
 133 static int      igb_suspend(device_t);
 134 static int      igb_resume(device_t);
 135
 136 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
 137 static void     igb_setup_ifp(struct igb_softc *);
 138 static boolean_t igb_txcsum_ctx(struct igb_tx_ring *, struct mbuf *);
 139 static int      igb_tso_pullup(struct igb_tx_ring *, struct mbuf **);
 140 static void     igb_tso_ctx(struct igb_tx_ring *, struct mbuf *, uint32_t *);
 141 static void     igb_add_sysctl(struct igb_softc *);
 142 static int      igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
 143 static int      igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS);
 144 static int      igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
 145 static int      igb_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
 146 static int      igb_sysctl_rx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
 147 static void     igb_set_ring_inuse(struct igb_softc *, boolean_t);
 148 static int      igb_get_rxring_inuse(const struct igb_softc *, boolean_t);
 149 static int      igb_get_txring_inuse(const struct igb_softc *, boolean_t);
 150 #ifdef IFPOLL_ENABLE
 151 static int      igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
 152 static int      igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
 153 #endif
 154
 155 static void     igb_vf_init_stats(struct igb_softc *);
 156 static void     igb_reset(struct igb_softc *);
 157 static void     igb_update_stats_counters(struct igb_softc *);
 158 static void     igb_update_vf_stats_counters(struct igb_softc *);
 159 static void     igb_update_link_status(struct igb_softc *);
 160 static void     igb_init_tx_unit(struct igb_softc *);
 161 static void     igb_init_rx_unit(struct igb_softc *);
 162
 163 static void     igb_set_vlan(struct igb_softc *);
 164 static void     igb_set_multi(struct igb_softc *);
 165 static void     igb_set_promisc(struct igb_softc *);
 166 static void     igb_disable_promisc(struct igb_softc *);
 167
 168 static int      igb_alloc_rings(struct igb_softc *);
 169 static void     igb_free_rings(struct igb_softc *);
 170 static int      igb_create_tx_ring(struct igb_tx_ring *);
 171 static int      igb_create_rx_ring(struct igb_rx_ring *);
 172 static void     igb_free_tx_ring(struct igb_tx_ring *);
 173 static void     igb_free_rx_ring(struct igb_rx_ring *);
 174 static void     igb_destroy_tx_ring(struct igb_tx_ring *, int);
 175 static void     igb_destroy_rx_ring(struct igb_rx_ring *, int);
 176 static void     igb_init_tx_ring(struct igb_tx_ring *);
 177 static int      igb_init_rx_ring(struct igb_rx_ring *);
 178 static int      igb_newbuf(struct igb_rx_ring *, int, boolean_t);
 179 static int      igb_encap(struct igb_tx_ring *, struct mbuf **, int *, int *);
 180 static void     igb_rx_refresh(struct igb_rx_ring *, int);
 181
 182 static void     igb_stop(struct igb_softc *);
 183 static void     igb_init(void *);
 184 static int      igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 185 static void     igb_media_status(struct ifnet *, struct ifmediareq *);
 186 static int      igb_media_change(struct ifnet *);
 187 static void     igb_timer(void *);
 188 static void     igb_watchdog(struct ifaltq_subque *);
 189 static void     igb_start(struct ifnet *, struct ifaltq_subque *);
 190 #ifdef IFPOLL_ENABLE
 191 static void     igb_npoll(struct ifnet *, struct ifpoll_info *);
 192 static void     igb_npoll_rx(struct ifnet *, void *, int);
 193 static void     igb_npoll_tx(struct ifnet *, void *, int);
 194 static void     igb_npoll_status(struct ifnet *);
 195 #endif
 196 static void     igb_serialize(struct ifnet *, enum ifnet_serialize);
 197 static void     igb_deserialize(struct ifnet *, enum ifnet_serialize);
 198 static int      igb_tryserialize(struct ifnet *, enum ifnet_serialize);
 199 #ifdef INVARIANTS
 200 static void     igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
 201                     boolean_t);
 202 #endif
 203
 204 static void     igb_intr(void *);
 205 static void     igb_intr_shared(void *);
 206 static void     igb_rxeof(struct igb_rx_ring *, int);
 207 static void     igb_txeof(struct igb_tx_ring *);
 208 static void     igb_set_eitr(struct igb_softc *, int, int);
 209 static void     igb_enable_intr(struct igb_softc *);
 210 static void     igb_disable_intr(struct igb_softc *);
 211 static void     igb_init_unshared_intr(struct igb_softc *);
 212 static void     igb_init_intr(struct igb_softc *);
 213 static int      igb_setup_intr(struct igb_softc *);
 214 static void     igb_set_txintr_mask(struct igb_tx_ring *, int *, int);
 215 static void     igb_set_rxintr_mask(struct igb_rx_ring *, int *, int);
 216 static void     igb_set_intr_mask(struct igb_softc *);
 217 static int      igb_alloc_intr(struct igb_softc *);
 218 static void     igb_free_intr(struct igb_softc *);
 219 static void     igb_teardown_intr(struct igb_softc *);
 220 static void     igb_msix_try_alloc(struct igb_softc *);
 221 static void     igb_msix_free(struct igb_softc *, boolean_t);
 222 static int      igb_msix_setup(struct igb_softc *);
 223 static void     igb_msix_teardown(struct igb_softc *, int);
 224 static void     igb_msix_rx(void *);
 225 static void     igb_msix_tx(void *);
 226 static void     igb_msix_status(void *);
 227
 228 /* Management and WOL Support */
 229 static void     igb_get_mgmt(struct igb_softc *);
 230 static void     igb_rel_mgmt(struct igb_softc *);
 231 static void     igb_get_hw_control(struct igb_softc *);
 232 static void     igb_rel_hw_control(struct igb_softc *);
 233 static void     igb_enable_wol(device_t);
 234
 235 static device_method_t igb_methods[] = {
 236         /* Device interface */
 237         DEVMETHOD(device_probe,         igb_probe),
 238         DEVMETHOD(device_attach,        igb_attach),
 239         DEVMETHOD(device_detach,        igb_detach),
 240         DEVMETHOD(device_shutdown,      igb_shutdown),
 241         DEVMETHOD(device_suspend,       igb_suspend),
 242         DEVMETHOD(device_resume,        igb_resume),
 243         { 0, 0 }
 244 };
 245
 246 static driver_t igb_driver = {
 247         "igb",
 248         igb_methods,
 249         sizeof(struct igb_softc),
 250 };
 251
 252 static devclass_t igb_devclass;
 253
 254 DECLARE_DUMMY_MODULE(if_igb);
 255 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
 256 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
 257
 258 static int      igb_rxd = IGB_DEFAULT_RXD;
 259 static int      igb_txd = IGB_DEFAULT_TXD;
 260 static int      igb_rxr = 0;
 261 static int      igb_txr = 0;
 262 static int      igb_msi_enable = 1;
 263 static int      igb_msix_enable = 1;
 264 static int      igb_eee_disabled = 1;   /* Energy Efficient Ethernet */
 265 static int      igb_fc_setting = e1000_fc_full;
 266
 267 /*
 268  * DMA Coalescing, only for i350 - default to off,
 269  * this feature is for power savings
 270  */
 271 static int      igb_dma_coalesce = 0;
 272
 273 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
 274 TUNABLE_INT("hw.igb.txd", &igb_txd);
 275 TUNABLE_INT("hw.igb.rxr", &igb_rxr);
 276 TUNABLE_INT("hw.igb.txr", &igb_txr);
 277 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
 278 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
 279 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
 280
 281 /* i350 specific */
 282 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
 283 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
 284
 285 static __inline void
 286 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
 287 {
 288         /* Ignore Checksum bit is set */
 289         if (staterr & E1000_RXD_STAT_IXSM)
 290                 return;
 291
 292         if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
 293             E1000_RXD_STAT_IPCS)
 294                 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
 295
 296         if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
 297                 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
 298                         mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
 299                             CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
 300                         mp->m_pkthdr.csum_data = htons(0xffff);
 301                 }
 302         }
 303 }
 304
 305 static __inline struct pktinfo *
 306 igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
 307     uint32_t hash, uint32_t hashtype, uint32_t staterr)
 308 {
 309         switch (hashtype) {
 310         case E1000_RXDADV_RSSTYPE_IPV4_TCP:
 311                 pi->pi_netisr = NETISR_IP;
 312                 pi->pi_flags = 0;
 313                 pi->pi_l3proto = IPPROTO_TCP;
 314                 break;
 315
 316         case E1000_RXDADV_RSSTYPE_IPV4:
 317                 if (staterr & E1000_RXD_STAT_IXSM)
 318                         return NULL;
 319
 320                 if ((staterr &
 321                      (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
 322                     E1000_RXD_STAT_TCPCS) {
 323                         pi->pi_netisr = NETISR_IP;
 324                         pi->pi_flags = 0;
 325                         pi->pi_l3proto = IPPROTO_UDP;
 326                         break;
 327                 }
 328                 /* FALL THROUGH */
 329         default:
 330                 return NULL;
 331         }
 332
 333         m->m_flags |= M_HASH;
 334         m->m_pkthdr.hash = toeplitz_hash(hash);
 335         return pi;
 336 }
 337
 338 static int
 339 igb_probe(device_t dev)
 340 {
 341         const struct igb_device *d;
 342         uint16_t vid, did;
 343
 344         vid = pci_get_vendor(dev);
 345         did = pci_get_device(dev);
 346
 347         for (d = igb_devices; d->desc != NULL; ++d) {
 348                 if (vid == d->vid && did == d->did) {
 349                         device_set_desc(dev, d->desc);
 350                         return 0;
 351                 }
 352         }
 353         return ENXIO;
 354 }
 355
 356 static int
 357 igb_attach(device_t dev)
 358 {
 359         struct igb_softc *sc = device_get_softc(dev);
 360         uint16_t eeprom_data;
 361         int error = 0, i, j, ring_max;
 362 #ifdef IFPOLL_ENABLE
 363         int offset, offset_def;
 364 #endif
 365
 366 #ifdef notyet
 367         /* SYSCTL stuff */
 368         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 369             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 370             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 371             igb_sysctl_nvm_info, "I", "NVM Information");
 372         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 373             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 374             OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
 375             adapter, 0, igb_set_flowcntl, "I", "Flow Control");
 376 #endif
 377
 378         callout_init_mp(&sc->timer);
 379         lwkt_serialize_init(&sc->main_serialize);
 380
 381         if_initname(&sc->arpcom.ac_if, device_get_name(dev),
 382             device_get_unit(dev));
 383         sc->dev = sc->osdep.dev = dev;
 384
 385         /*
 386          * Determine hardware and mac type
 387          */
 388         sc->hw.vendor_id = pci_get_vendor(dev);
 389         sc->hw.device_id = pci_get_device(dev);
 390         sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
 391         sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
 392         sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
 393
 394         if (e1000_set_mac_type(&sc->hw))
 395                 return ENXIO;
 396
 397         /* Are we a VF device? */
 398         if (sc->hw.mac.type == e1000_vfadapt ||
 399             sc->hw.mac.type == e1000_vfadapt_i350)
 400                 sc->vf_ifp = 1;
 401         else
 402                 sc->vf_ifp = 0;
 403
 404         /*
 405          * Configure total supported RX/TX ring count
 406          */
 407         switch (sc->hw.mac.type) {
 408         case e1000_82575:
 409                 ring_max = IGB_MAX_RING_82575;
 410                 break;
 411         case e1000_82580:
 412                 ring_max = IGB_MAX_RING_82580;
 413                 break;
 414         case e1000_i350:
 415                 ring_max = IGB_MAX_RING_I350;
 416                 break;
 417         case e1000_82576:
 418                 ring_max = IGB_MAX_RING_82576;
 419                 break;
 420         default:
 421                 ring_max = IGB_MIN_RING;
 422                 break;
 423         }
 424
 425         sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
 426         sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
 427 #ifdef IGB_RSS_DEBUG
 428         sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
 429 #endif
 430         sc->rx_ring_inuse = sc->rx_ring_cnt;
 431
 432         sc->tx_ring_cnt = device_getenv_int(dev, "txr", igb_txr);
 433         sc->tx_ring_cnt = if_ring_count2(sc->tx_ring_cnt, /* XXX ring_max */1);
 434 #ifdef IGB_TSS_DEBUG
 435         sc->tx_ring_cnt = device_getenv_int(dev, "txr_debug", sc->tx_ring_cnt);
 436 #endif
 437         sc->tx_ring_inuse = sc->tx_ring_cnt;
 438
 439         /* Enable bus mastering */
 440         pci_enable_busmaster(dev);
 441
 442         /*
 443          * Allocate IO memory
 444          */
 445         sc->mem_rid = PCIR_BAR(0);
 446         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
 447             RF_ACTIVE);
 448         if (sc->mem_res == NULL) {
 449                 device_printf(dev, "Unable to allocate bus resource: memory\n");
 450                 error = ENXIO;
 451                 goto failed;
 452         }
 453         sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
 454         sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
 455
 456         sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
 457
 458         /* Save PCI command register for Shared Code */
 459         sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
 460         sc->hw.back = &sc->osdep;
 461
 462         /* Do Shared Code initialization */
 463         if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
 464                 device_printf(dev, "Setup of Shared code failed\n");
 465                 error = ENXIO;
 466                 goto failed;
 467         }
 468
 469         e1000_get_bus_info(&sc->hw);
 470
 471         sc->hw.mac.autoneg = DO_AUTO_NEG;
 472         sc->hw.phy.autoneg_wait_to_complete = FALSE;
 473         sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 474
 475         /* Copper options */
 476         if (sc->hw.phy.media_type == e1000_media_type_copper) {
 477                 sc->hw.phy.mdix = AUTO_ALL_MODES;
 478                 sc->hw.phy.disable_polarity_correction = FALSE;
 479                 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
 480         }
 481
 482         /* Set the frame limits assuming  standard ethernet sized frames. */
 483         sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
 484
 485         /* Allocate RX/TX rings */
 486         error = igb_alloc_rings(sc);
 487         if (error)
 488                 goto failed;
 489
 490 #ifdef IFPOLL_ENABLE
 491         /*
 492          * NPOLLING RX CPU offset
 493          */
 494         if (sc->rx_ring_cnt == ncpus2) {
 495                 offset = 0;
 496         } else {
 497                 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
 498                 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
 499                 if (offset >= ncpus2 ||
 500                     offset % sc->rx_ring_cnt != 0) {
 501                         device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
 502                             offset, offset_def);
 503                         offset = offset_def;
 504                 }
 505         }
 506         sc->rx_npoll_off = offset;
 507
 508         /*
 509          * NPOLLING TX CPU offset
 510          */
 511         if (sc->tx_ring_cnt == ncpus2) {
 512                 offset = 0;
 513         } else {
 514                 offset_def = (sc->tx_ring_cnt * device_get_unit(dev)) % ncpus2;
 515                 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
 516                 if (offset >= ncpus2 ||
 517                     offset % sc->tx_ring_cnt != 0) {
 518                         device_printf(dev, "invalid npoll.txoff %d, use %d\n",
 519                             offset, offset_def);
 520                         offset = offset_def;
 521                 }
 522         }
 523         sc->tx_npoll_off = offset;
 524 #endif
 525
 526         /* Allocate interrupt */
 527         error = igb_alloc_intr(sc);
 528         if (error)
 529                 goto failed;
 530
 531         /*
 532          * Setup serializers
 533          */
 534         i = 0;
 535         sc->serializes[i++] = &sc->main_serialize;
 536
 537         sc->tx_serialize = i;
 538         for (j = 0; j < sc->tx_ring_cnt; ++j)
 539                 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
 540
 541         sc->rx_serialize = i;
 542         for (j = 0; j < sc->rx_ring_cnt; ++j)
 543                 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
 544
 545         sc->serialize_cnt = i;
 546         KKASSERT(sc->serialize_cnt <= IGB_NSERIALIZE);
 547
 548         /* Allocate the appropriate stats memory */
 549         if (sc->vf_ifp) {
 550                 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
 551                     M_WAITOK | M_ZERO);
 552                 igb_vf_init_stats(sc);
 553         } else {
 554                 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
 555                     M_WAITOK | M_ZERO);
 556         }
 557
 558         /* Allocate multicast array memory. */
 559         sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
 560             M_DEVBUF, M_WAITOK);
 561
 562         /* Some adapter-specific advanced features */
 563         if (sc->hw.mac.type >= e1000_i350) {
 564 #ifdef notyet
 565                 igb_set_sysctl_value(adapter, "dma_coalesce",
 566                     "configure dma coalesce",
 567                     &adapter->dma_coalesce, igb_dma_coalesce);
 568                 igb_set_sysctl_value(adapter, "eee_disabled",
 569                     "enable Energy Efficient Ethernet",
 570                     &adapter->hw.dev_spec._82575.eee_disable,
 571                     igb_eee_disabled);
 572 #else
 573                 sc->dma_coalesce = igb_dma_coalesce;
 574                 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
 575 #endif
 576                 e1000_set_eee_i350(&sc->hw);
 577         }
 578
 579         /*
 580          * Start from a known state, this is important in reading the nvm and
 581          * mac from that.
 582          */
 583         e1000_reset_hw(&sc->hw);
 584
 585         /* Make sure we have a good EEPROM before we read from it */
 586         if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
 587                 /*
 588                  * Some PCI-E parts fail the first check due to
 589                  * the link being in sleep state, call it again,
 590                  * if it fails a second time its a real issue.
 591                  */
 592                 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
 593                         device_printf(dev,
 594                             "The EEPROM Checksum Is Not Valid\n");
 595                         error = EIO;
 596                         goto failed;
 597                 }
 598         }
 599
 600         /* Copy the permanent MAC address out of the EEPROM */
 601         if (e1000_read_mac_addr(&sc->hw) < 0) {
 602                 device_printf(dev, "EEPROM read error while reading MAC"
 603                     " address\n");
 604                 error = EIO;
 605                 goto failed;
 606         }
 607         if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
 608                 device_printf(dev, "Invalid MAC address\n");
 609                 error = EIO;
 610                 goto failed;
 611         }
 612
 613         /* Setup OS specific network interface */
 614         igb_setup_ifp(sc);
 615
 616         /* Add sysctl tree, must after igb_setup_ifp() */
 617         igb_add_sysctl(sc);
 618
 619         /* Now get a good starting state */
 620         igb_reset(sc);
 621
 622         /* Initialize statistics */
 623         igb_update_stats_counters(sc);
 624
 625         sc->hw.mac.get_link_status = 1;
 626         igb_update_link_status(sc);
 627
 628         /* Indicate SOL/IDER usage */
 629         if (e1000_check_reset_block(&sc->hw)) {
 630                 device_printf(dev,
 631                     "PHY reset is blocked due to SOL/IDER session.\n");
 632         }
 633
 634         /* Determine if we have to control management hardware */
 635         if (e1000_enable_mng_pass_thru(&sc->hw))
 636                 sc->flags |= IGB_FLAG_HAS_MGMT;
 637
 638         /*
 639          * Setup Wake-on-Lan
 640          */
 641         /* APME bit in EEPROM is mapped to WUC.APME */
 642         eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
 643         if (eeprom_data)
 644                 sc->wol = E1000_WUFC_MAG;
 645         /* XXX disable WOL */
 646         sc->wol = 0;
 647
 648 #ifdef notyet
 649         /* Register for VLAN events */
 650         adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
 651              igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 652         adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
 653              igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 654 #endif
 655
 656 #ifdef notyet
 657         igb_add_hw_stats(adapter);
 658 #endif
 659
 660         error = igb_setup_intr(sc);
 661         if (error) {
 662                 ether_ifdetach(&sc->arpcom.ac_if);
 663                 goto failed;
 664         }
 665
 666         for (i = 0; i < sc->tx_ring_cnt; ++i) {
 667                 struct ifaltq_subque *ifsq =
 668                     ifq_get_subq(&sc->arpcom.ac_if.if_snd, i);
 669                 struct igb_tx_ring *txr = &sc->tx_rings[i];
 670
 671                 ifsq_set_cpuid(ifsq, txr->tx_intr_cpuid);
 672                 ifsq_set_priv(ifsq, txr);
 673                 txr->ifsq = ifsq;
 674
 675                 ifsq_watchdog_init(&txr->tx_watchdog, ifsq, igb_watchdog);
 676         }
 677
 678         return 0;
 679
 680 failed:
 681         igb_detach(dev);
 682         return error;
 683 }
 684
 685 static int
 686 igb_detach(device_t dev)
 687 {
 688         struct igb_softc *sc = device_get_softc(dev);
 689
 690         if (device_is_attached(dev)) {
 691                 struct ifnet *ifp = &sc->arpcom.ac_if;
 692
 693                 ifnet_serialize_all(ifp);
 694
 695                 igb_stop(sc);
 696
 697                 e1000_phy_hw_reset(&sc->hw);
 698
 699                 /* Give control back to firmware */
 700                 igb_rel_mgmt(sc);
 701                 igb_rel_hw_control(sc);
 702
 703                 if (sc->wol) {
 704                         E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 705                         E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 706                         igb_enable_wol(dev);
 707                 }
 708
 709                 igb_teardown_intr(sc);
 710
 711                 ifnet_deserialize_all(ifp);
 712
 713                 ether_ifdetach(ifp);
 714         } else if (sc->mem_res != NULL) {
 715                 igb_rel_hw_control(sc);
 716         }
 717         bus_generic_detach(dev);
 718
 719         if (sc->sysctl_tree != NULL)
 720                 sysctl_ctx_free(&sc->sysctl_ctx);
 721
 722         igb_free_intr(sc);
 723
 724         if (sc->msix_mem_res != NULL) {
 725                 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_mem_rid,
 726                     sc->msix_mem_res);
 727         }
 728         if (sc->mem_res != NULL) {
 729                 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
 730                     sc->mem_res);
 731         }
 732
 733         igb_free_rings(sc);
 734
 735         if (sc->mta != NULL)
 736                 kfree(sc->mta, M_DEVBUF);
 737         if (sc->stats != NULL)
 738                 kfree(sc->stats, M_DEVBUF);
 739
 740         return 0;
 741 }
 742
 743 static int
 744 igb_shutdown(device_t dev)
 745 {
 746         return igb_suspend(dev);
 747 }
 748
 749 static int
 750 igb_suspend(device_t dev)
 751 {
 752         struct igb_softc *sc = device_get_softc(dev);
 753         struct ifnet *ifp = &sc->arpcom.ac_if;
 754
 755         ifnet_serialize_all(ifp);
 756
 757         igb_stop(sc);
 758
 759         igb_rel_mgmt(sc);
 760         igb_rel_hw_control(sc);
 761
 762         if (sc->wol) {
 763                 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 764                 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 765                 igb_enable_wol(dev);
 766         }
 767
 768         ifnet_deserialize_all(ifp);
 769
 770         return bus_generic_suspend(dev);
 771 }
 772
 773 static int
 774 igb_resume(device_t dev)
 775 {
 776         struct igb_softc *sc = device_get_softc(dev);
 777         struct ifnet *ifp = &sc->arpcom.ac_if;
 778         int i;
 779
 780         ifnet_serialize_all(ifp);
 781
 782         igb_init(sc);
 783         igb_get_mgmt(sc);
 784
 785         for (i = 0; i < sc->tx_ring_inuse; ++i)
 786                 ifsq_devstart_sched(sc->tx_rings[i].ifsq);
 787
 788         ifnet_deserialize_all(ifp);
 789
 790         return bus_generic_resume(dev);
 791 }
 792
 793 static int
 794 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
 795 {
 796         struct igb_softc *sc = ifp->if_softc;
 797         struct ifreq *ifr = (struct ifreq *)data;
 798         int max_frame_size, mask, reinit;
 799         int error = 0;
 800
 801         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 802
 803         switch (command) {
 804         case SIOCSIFMTU:
 805                 max_frame_size = 9234;
 806                 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
 807                     ETHER_CRC_LEN) {
 808                         error = EINVAL;
 809                         break;
 810                 }
 811
 812                 ifp->if_mtu = ifr->ifr_mtu;
 813                 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
 814                     ETHER_CRC_LEN;
 815
 816                 if (ifp->if_flags & IFF_RUNNING)
 817                         igb_init(sc);
 818                 break;
 819
 820         case SIOCSIFFLAGS:
 821                 if (ifp->if_flags & IFF_UP) {
 822                         if (ifp->if_flags & IFF_RUNNING) {
 823                                 if ((ifp->if_flags ^ sc->if_flags) &
 824                                     (IFF_PROMISC | IFF_ALLMULTI)) {
 825                                         igb_disable_promisc(sc);
 826                                         igb_set_promisc(sc);
 827                                 }
 828                         } else {
 829                                 igb_init(sc);
 830                         }
 831                 } else if (ifp->if_flags & IFF_RUNNING) {
 832                         igb_stop(sc);
 833                 }
 834                 sc->if_flags = ifp->if_flags;
 835                 break;
 836
 837         case SIOCADDMULTI:
 838         case SIOCDELMULTI:
 839                 if (ifp->if_flags & IFF_RUNNING) {
 840                         igb_disable_intr(sc);
 841                         igb_set_multi(sc);
 842 #ifdef IFPOLL_ENABLE
 843                         if (!(ifp->if_flags & IFF_NPOLLING))
 844 #endif
 845                                 igb_enable_intr(sc);
 846                 }
 847                 break;
 848
 849         case SIOCSIFMEDIA:
 850                 /*
 851                  * As the speed/duplex settings are being
 852                  * changed, we need toreset the PHY.
 853                  */
 854                 sc->hw.phy.reset_disable = FALSE;
 855
 856                 /* Check SOL/IDER usage */
 857                 if (e1000_check_reset_block(&sc->hw)) {
 858                         if_printf(ifp, "Media change is "
 859                             "blocked due to SOL/IDER session.\n");
 860                         break;
 861                 }
 862                 /* FALL THROUGH */
 863
 864         case SIOCGIFMEDIA:
 865                 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
 866                 break;
 867
 868         case SIOCSIFCAP:
 869                 reinit = 0;
 870                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 871                 if (mask & IFCAP_RXCSUM) {
 872                         ifp->if_capenable ^= IFCAP_RXCSUM;
 873                         reinit = 1;
 874                 }
 875                 if (mask & IFCAP_VLAN_HWTAGGING) {
 876                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
 877                         reinit = 1;
 878                 }
 879                 if (mask & IFCAP_TXCSUM) {
 880                         ifp->if_capenable ^= IFCAP_TXCSUM;
 881                         if (ifp->if_capenable & IFCAP_TXCSUM)
 882                                 ifp->if_hwassist |= IGB_CSUM_FEATURES;
 883                         else
 884                                 ifp->if_hwassist &= ~IGB_CSUM_FEATURES;
 885                 }
 886                 if (mask & IFCAP_TSO) {
 887                         ifp->if_capenable ^= IFCAP_TSO;
 888                         if (ifp->if_capenable & IFCAP_TSO)
 889                                 ifp->if_hwassist |= CSUM_TSO;
 890                         else
 891                                 ifp->if_hwassist &= ~CSUM_TSO;
 892                 }
 893                 if (mask & IFCAP_RSS)
 894                         ifp->if_capenable ^= IFCAP_RSS;
 895                 if (reinit && (ifp->if_flags & IFF_RUNNING))
 896                         igb_init(sc);
 897                 break;
 898
 899         default:
 900                 error = ether_ioctl(ifp, command, data);
 901                 break;
 902         }
 903         return error;
 904 }
 905
 906 static void
 907 igb_init(void *xsc)
 908 {
 909         struct igb_softc *sc = xsc;
 910         struct ifnet *ifp = &sc->arpcom.ac_if;
 911         boolean_t polling;
 912         int i;
 913
 914         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 915
 916         igb_stop(sc);
 917
 918         /* Get the latest mac address, User can use a LAA */
 919         bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
 920
 921         /* Put the address into the Receive Address Array */
 922         e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
 923
 924         igb_reset(sc);
 925         igb_update_link_status(sc);
 926
 927         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
 928
 929         /* Configure for OS presence */
 930         igb_get_mgmt(sc);
 931
 932         polling = FALSE;
 933 #ifdef IFPOLL_ENABLE
 934         if (ifp->if_flags & IFF_NPOLLING)
 935                 polling = TRUE;
 936 #endif
 937
 938         /* Configured used RX/TX rings */
 939         igb_set_ring_inuse(sc, polling);
 940
 941         /* Initialize interrupt */
 942         igb_init_intr(sc);
 943
 944         /* Prepare transmit descriptors and buffers */
 945         for (i = 0; i < sc->tx_ring_inuse; ++i)
 946                 igb_init_tx_ring(&sc->tx_rings[i]);
 947         igb_init_tx_unit(sc);
 948
 949         /* Setup Multicast table */
 950         igb_set_multi(sc);
 951
 952 #if 0
 953         /*
 954          * Figure out the desired mbuf pool
 955          * for doing jumbo/packetsplit
 956          */
 957         if (adapter->max_frame_size <= 2048)
 958                 adapter->rx_mbuf_sz = MCLBYTES;
 959         else if (adapter->max_frame_size <= 4096)
 960                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
 961         else
 962                 adapter->rx_mbuf_sz = MJUM9BYTES;
 963 #endif
 964
 965         /* Prepare receive descriptors and buffers */
 966         for (i = 0; i < sc->rx_ring_inuse; ++i) {
 967                 int error;
 968
 969                 error = igb_init_rx_ring(&sc->rx_rings[i]);
 970                 if (error) {
 971                         if_printf(ifp, "Could not setup receive structures\n");
 972                         igb_stop(sc);
 973                         return;
 974                 }
 975         }
 976         igb_init_rx_unit(sc);
 977
 978         /* Enable VLAN support */
 979         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
 980                 igb_set_vlan(sc);
 981
 982         /* Don't lose promiscuous settings */
 983         igb_set_promisc(sc);
 984
 985         ifp->if_flags |= IFF_RUNNING;
 986         for (i = 0; i < sc->tx_ring_inuse; ++i) {
 987                 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
 988                 ifsq_watchdog_start(&sc->tx_rings[i].tx_watchdog);
 989         }
 990
 991         if (polling || sc->intr_type == PCI_INTR_TYPE_MSIX)
 992                 sc->timer_cpuid = 0; /* XXX fixed */
 993         else
 994                 sc->timer_cpuid = rman_get_cpuid(sc->intr_res);
 995         callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
 996         e1000_clear_hw_cntrs_base_generic(&sc->hw);
 997
 998         /* This clears any pending interrupts */
 999         E1000_READ_REG(&sc->hw, E1000_ICR);
1000
1001         /*
1002          * Only enable interrupts if we are not polling, make sure
1003          * they are off otherwise.
1004          */
1005         if (polling) {
1006                 igb_disable_intr(sc);
1007         } else {
1008                 igb_enable_intr(sc);
1009                 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
1010         }
1011
1012         /* Set Energy Efficient Ethernet */
1013         e1000_set_eee_i350(&sc->hw);
1014
1015         /* Don't reset the phy next time init gets called */
1016         sc->hw.phy.reset_disable = TRUE;
1017 }
1018
1019 static void
1020 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1021 {
1022         struct igb_softc *sc = ifp->if_softc;
1023         u_char fiber_type = IFM_1000_SX;
1024
1025         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1026
1027         igb_update_link_status(sc);
1028
1029         ifmr->ifm_status = IFM_AVALID;
1030         ifmr->ifm_active = IFM_ETHER;
1031
1032         if (!sc->link_active)
1033                 return;
1034
1035         ifmr->ifm_status |= IFM_ACTIVE;
1036
1037         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1038             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1039                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1040         } else {
1041                 switch (sc->link_speed) {
1042                 case 10:
1043                         ifmr->ifm_active |= IFM_10_T;
1044                         break;
1045
1046                 case 100:
1047                         ifmr->ifm_active |= IFM_100_TX;
1048                         break;
1049
1050                 case 1000:
1051                         ifmr->ifm_active |= IFM_1000_T;
1052                         break;
1053                 }
1054                 if (sc->link_duplex == FULL_DUPLEX)
1055                         ifmr->ifm_active |= IFM_FDX;
1056                 else
1057                         ifmr->ifm_active |= IFM_HDX;
1058         }
1059 }
1060
1061 static int
1062 igb_media_change(struct ifnet *ifp)
1063 {
1064         struct igb_softc *sc = ifp->if_softc;
1065         struct ifmedia *ifm = &sc->media;
1066
1067         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1068
1069         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1070                 return EINVAL;
1071
1072         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1073         case IFM_AUTO:
1074                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1075                 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1076                 break;
1077
1078         case IFM_1000_LX:
1079         case IFM_1000_SX:
1080         case IFM_1000_T:
1081                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1082                 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1083                 break;
1084
1085         case IFM_100_TX:
1086                 sc->hw.mac.autoneg = FALSE;
1087                 sc->hw.phy.autoneg_advertised = 0;
1088                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1089                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1090                 else
1091                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1092                 break;
1093
1094         case IFM_10_T:
1095                 sc->hw.mac.autoneg = FALSE;
1096                 sc->hw.phy.autoneg_advertised = 0;
1097                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1098                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1099                 else
1100                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1101                 break;
1102
1103         default:
1104                 if_printf(ifp, "Unsupported media type\n");
1105                 break;
1106         }
1107
1108         igb_init(sc);
1109
1110         return 0;
1111 }
1112
1113 static void
1114 igb_set_promisc(struct igb_softc *sc)
1115 {
1116         struct ifnet *ifp = &sc->arpcom.ac_if;
1117         struct e1000_hw *hw = &sc->hw;
1118         uint32_t reg;
1119
1120         if (sc->vf_ifp) {
1121                 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1122                 return;
1123         }
1124
1125         reg = E1000_READ_REG(hw, E1000_RCTL);
1126         if (ifp->if_flags & IFF_PROMISC) {
1127                 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1128                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1129         } else if (ifp->if_flags & IFF_ALLMULTI) {
1130                 reg |= E1000_RCTL_MPE;
1131                 reg &= ~E1000_RCTL_UPE;
1132                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1133         }
1134 }
1135
1136 static void
1137 igb_disable_promisc(struct igb_softc *sc)
1138 {
1139         struct e1000_hw *hw = &sc->hw;
1140         uint32_t reg;
1141
1142         if (sc->vf_ifp) {
1143                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1144                 return;
1145         }
1146         reg = E1000_READ_REG(hw, E1000_RCTL);
1147         reg &= ~E1000_RCTL_UPE;
1148         reg &= ~E1000_RCTL_MPE;
1149         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1150 }
1151
1152 static void
1153 igb_set_multi(struct igb_softc *sc)
1154 {
1155         struct ifnet *ifp = &sc->arpcom.ac_if;
1156         struct ifmultiaddr *ifma;
1157         uint32_t reg_rctl = 0;
1158         uint8_t *mta;
1159         int mcnt = 0;
1160
1161         mta = sc->mta;
1162         bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1163
1164         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1165                 if (ifma->ifma_addr->sa_family != AF_LINK)
1166                         continue;
1167
1168                 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1169                         break;
1170
1171                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1172                     &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1173                 mcnt++;
1174         }
1175
1176         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1177                 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1178                 reg_rctl |= E1000_RCTL_MPE;
1179                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1180         } else {
1181                 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1182         }
1183 }
1184
1185 static void
1186 igb_timer(void *xsc)
1187 {
1188         struct igb_softc *sc = xsc;
1189
1190         lwkt_serialize_enter(&sc->main_serialize);
1191
1192         igb_update_link_status(sc);
1193         igb_update_stats_counters(sc);
1194
1195         callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
1196
1197         lwkt_serialize_exit(&sc->main_serialize);
1198 }
1199
1200 static void
1201 igb_update_link_status(struct igb_softc *sc)
1202 {
1203         struct ifnet *ifp = &sc->arpcom.ac_if;
1204         struct e1000_hw *hw = &sc->hw;
1205         uint32_t link_check, thstat, ctrl;
1206
1207         link_check = thstat = ctrl = 0;
1208
1209         /* Get the cached link value or read for real */
1210         switch (hw->phy.media_type) {
1211         case e1000_media_type_copper:
1212                 if (hw->mac.get_link_status) {
1213                         /* Do the work to read phy */
1214                         e1000_check_for_link(hw);
1215                         link_check = !hw->mac.get_link_status;
1216                 } else {
1217                         link_check = TRUE;
1218                 }
1219                 break;
1220
1221         case e1000_media_type_fiber:
1222                 e1000_check_for_link(hw);
1223                 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1224                 break;
1225
1226         case e1000_media_type_internal_serdes:
1227                 e1000_check_for_link(hw);
1228                 link_check = hw->mac.serdes_has_link;
1229                 break;
1230
1231         /* VF device is type_unknown */
1232         case e1000_media_type_unknown:
1233                 e1000_check_for_link(hw);
1234                 link_check = !hw->mac.get_link_status;
1235                 /* Fall thru */
1236         default:
1237                 break;
1238         }
1239
1240         /* Check for thermal downshift or shutdown */
1241         if (hw->mac.type == e1000_i350) {
1242                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1243                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1244         }
1245
1246         /* Now we check if a transition has happened */
1247         if (link_check && sc->link_active == 0) {
1248                 e1000_get_speed_and_duplex(hw,
1249                     &sc->link_speed, &sc->link_duplex);
1250                 if (bootverbose) {
1251                         if_printf(ifp, "Link is up %d Mbps %s\n",
1252                             sc->link_speed,
1253                             sc->link_duplex == FULL_DUPLEX ?
1254                             "Full Duplex" : "Half Duplex");
1255                 }
1256                 sc->link_active = 1;
1257
1258                 ifp->if_baudrate = sc->link_speed * 1000000;
1259                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1260                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1261                         if_printf(ifp, "Link: thermal downshift\n");
1262                 /* This can sleep */
1263                 ifp->if_link_state = LINK_STATE_UP;
1264                 if_link_state_change(ifp);
1265         } else if (!link_check && sc->link_active == 1) {
1266                 ifp->if_baudrate = sc->link_speed = 0;
1267                 sc->link_duplex = 0;
1268                 if (bootverbose)
1269                         if_printf(ifp, "Link is Down\n");
1270                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1271                     (thstat & E1000_THSTAT_PWR_DOWN))
1272                         if_printf(ifp, "Link: thermal shutdown\n");
1273                 sc->link_active = 0;
1274                 /* This can sleep */
1275                 ifp->if_link_state = LINK_STATE_DOWN;
1276                 if_link_state_change(ifp);
1277         }
1278 }
1279
1280 static void
1281 igb_stop(struct igb_softc *sc)
1282 {
1283         struct ifnet *ifp = &sc->arpcom.ac_if;
1284         int i;
1285
1286         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1287
1288         igb_disable_intr(sc);
1289
1290         callout_stop(&sc->timer);
1291
1292         ifp->if_flags &= ~IFF_RUNNING;
1293         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1294                 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
1295                 ifsq_watchdog_stop(&sc->tx_rings[i].tx_watchdog);
1296                 sc->tx_rings[i].tx_flags &= ~IGB_TXFLAG_ENABLED;
1297         }
1298
1299         e1000_reset_hw(&sc->hw);
1300         E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1301
1302         e1000_led_off(&sc->hw);
1303         e1000_cleanup_led(&sc->hw);
1304
1305         for (i = 0; i < sc->tx_ring_cnt; ++i)
1306                 igb_free_tx_ring(&sc->tx_rings[i]);
1307         for (i = 0; i < sc->rx_ring_cnt; ++i)
1308                 igb_free_rx_ring(&sc->rx_rings[i]);
1309 }
1310
1311 static void
1312 igb_reset(struct igb_softc *sc)
1313 {
1314         struct ifnet *ifp = &sc->arpcom.ac_if;
1315         struct e1000_hw *hw = &sc->hw;
1316         struct e1000_fc_info *fc = &hw->fc;
1317         uint32_t pba = 0;
1318         uint16_t hwm;
1319
1320         /* Let the firmware know the OS is in control */
1321         igb_get_hw_control(sc);
1322
1323         /*
1324          * Packet Buffer Allocation (PBA)
1325          * Writing PBA sets the receive portion of the buffer
1326          * the remainder is used for the transmit buffer.
1327          */
1328         switch (hw->mac.type) {
1329         case e1000_82575:
1330                 pba = E1000_PBA_32K;
1331                 break;
1332
1333         case e1000_82576:
1334         case e1000_vfadapt:
1335                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1336                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1337                 break;
1338
1339         case e1000_82580:
1340         case e1000_i350:
1341         case e1000_vfadapt_i350:
1342                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1343                 pba = e1000_rxpbs_adjust_82580(pba);
1344                 break;
1345                 /* XXX pba = E1000_PBA_35K; */
1346
1347         default:
1348                 break;
1349         }
1350
1351         /* Special needs in case of Jumbo frames */
1352         if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1353                 uint32_t tx_space, min_tx, min_rx;
1354
1355                 pba = E1000_READ_REG(hw, E1000_PBA);
1356                 tx_space = pba >> 16;
1357                 pba &= 0xffff;
1358
1359                 min_tx = (sc->max_frame_size +
1360                     sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1361                 min_tx = roundup2(min_tx, 1024);
1362                 min_tx >>= 10;
1363                 min_rx = sc->max_frame_size;
1364                 min_rx = roundup2(min_rx, 1024);
1365                 min_rx >>= 10;
1366                 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1367                         pba = pba - (min_tx - tx_space);
1368                         /*
1369                          * if short on rx space, rx wins
1370                          * and must trump tx adjustment
1371                          */
1372                         if (pba < min_rx)
1373                                 pba = min_rx;
1374                 }
1375                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1376         }
1377
1378         /*
1379          * These parameters control the automatic generation (Tx) and
1380          * response (Rx) to Ethernet PAUSE frames.
1381          * - High water mark should allow for at least two frames to be
1382          *   received after sending an XOFF.
1383          * - Low water mark works best when it is very near the high water mark.
1384          *   This allows the receiver to restart by sending XON when it has
1385          *   drained a bit.
1386          */
1387         hwm = min(((pba << 10) * 9 / 10),
1388             ((pba << 10) - 2 * sc->max_frame_size));
1389
1390         if (hw->mac.type < e1000_82576) {
1391                 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1392                 fc->low_water = fc->high_water - 8;
1393         } else {
1394                 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1395                 fc->low_water = fc->high_water - 16;
1396         }
1397         fc->pause_time = IGB_FC_PAUSE_TIME;
1398         fc->send_xon = TRUE;
1399
1400         /* Issue a global reset */
1401         e1000_reset_hw(hw);
1402         E1000_WRITE_REG(hw, E1000_WUC, 0);
1403
1404         if (e1000_init_hw(hw) < 0)
1405                 if_printf(ifp, "Hardware Initialization Failed\n");
1406
1407         /* Setup DMA Coalescing */
1408         if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1409                 uint32_t reg;
1410
1411                 hwm = (pba - 4) << 10;
1412                 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1413                     & E1000_DMACR_DMACTHR_MASK;
1414
1415                 /* transition to L0x or L1 if available..*/
1416                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1417
1418                 /* timer = +-1000 usec in 32usec intervals */
1419                 reg |= (1000 >> 5);
1420                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1421
1422                 /* No lower threshold */
1423                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1424
1425                 /* set hwm to PBA -  2 * max frame size */
1426                 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1427
1428                 /* Set the interval before transition */
1429                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1430                 reg |= 0x800000FF; /* 255 usec */
1431                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1432
1433                 /* free space in tx packet buffer to wake from DMA coal */
1434                 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1435                     (20480 - (2 * sc->max_frame_size)) >> 6);
1436
1437                 /* make low power state decision controlled by DMA coal */
1438                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1439                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1440                     reg | E1000_PCIEMISC_LX_DECISION);
1441                 if_printf(ifp, "DMA Coalescing enabled\n");
1442         }
1443
1444         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1445         e1000_get_phy_info(hw);
1446         e1000_check_for_link(hw);
1447 }
1448
1449 static void
1450 igb_setup_ifp(struct igb_softc *sc)
1451 {
1452         struct ifnet *ifp = &sc->arpcom.ac_if;
1453
1454         ifp->if_softc = sc;
1455         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1456         ifp->if_init = igb_init;
1457         ifp->if_ioctl = igb_ioctl;
1458         ifp->if_start = igb_start;
1459         ifp->if_serialize = igb_serialize;
1460         ifp->if_deserialize = igb_deserialize;
1461         ifp->if_tryserialize = igb_tryserialize;
1462 #ifdef INVARIANTS
1463         ifp->if_serialize_assert = igb_serialize_assert;
1464 #endif
1465 #ifdef IFPOLL_ENABLE
1466         ifp->if_npoll = igb_npoll;
1467 #endif
1468
1469         ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1470         ifq_set_ready(&ifp->if_snd);
1471         ifq_set_subq_cnt(&ifp->if_snd, sc->tx_ring_cnt);
1472
1473         ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1474
1475         ifp->if_capabilities =
1476             IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_TSO;
1477         if (IGB_ENABLE_HWRSS(sc))
1478                 ifp->if_capabilities |= IFCAP_RSS;
1479         ifp->if_capenable = ifp->if_capabilities;
1480         ifp->if_hwassist = IGB_CSUM_FEATURES | CSUM_TSO;
1481
1482         /*
1483          * Tell the upper layer(s) we support long frames
1484          */
1485         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1486
1487         /*
1488          * Specify the media types supported by this adapter and register
1489          * callbacks to update media and link information
1490          */
1491         ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1492         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1493             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1494                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1495                     0, NULL);
1496                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1497         } else {
1498                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1499                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1500                     0, NULL);
1501                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1502                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1503                     0, NULL);
1504                 if (sc->hw.phy.type != e1000_phy_ife) {
1505                         ifmedia_add(&sc->media,
1506                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1507                         ifmedia_add(&sc->media,
1508                             IFM_ETHER | IFM_1000_T, 0, NULL);
1509                 }
1510         }
1511         ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1512         ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1513 }
1514
1515 static void
1516 igb_add_sysctl(struct igb_softc *sc)
1517 {
1518         char node[32];
1519         int i;
1520
1521         sysctl_ctx_init(&sc->sysctl_ctx);
1522         sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1523             SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1524             device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1525         if (sc->sysctl_tree == NULL) {
1526                 device_printf(sc->dev, "can't add sysctl node\n");
1527                 return;
1528         }
1529
1530         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1531             OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1532         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1533             OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1534             "# of RX rings used");
1535         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1536             OID_AUTO, "txr", CTLFLAG_RD, &sc->tx_ring_cnt, 0, "# of TX rings");
1537         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1538             OID_AUTO, "txr_inuse", CTLFLAG_RD, &sc->tx_ring_inuse, 0,
1539             "# of TX rings used");
1540         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1541             OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1542             "# of RX descs");
1543         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1544             OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1545             "# of TX descs");
1546
1547         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
1548                 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1549                     SYSCTL_CHILDREN(sc->sysctl_tree),
1550                     OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1551                     sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1552         } else {
1553                 for (i = 0; i < sc->msix_cnt; ++i) {
1554                         struct igb_msix_data *msix = &sc->msix_data[i];
1555
1556                         ksnprintf(node, sizeof(node), "msix%d_rate", i);
1557                         SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1558                             SYSCTL_CHILDREN(sc->sysctl_tree),
1559                             OID_AUTO, node, CTLTYPE_INT | CTLFLAG_RW,
1560                             msix, 0, igb_sysctl_msix_rate, "I",
1561                             msix->msix_rate_desc);
1562                 }
1563         }
1564
1565         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1566             OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1567             sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1568             "# of segments per TX interrupt");
1569
1570         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1571             OID_AUTO, "tx_wreg_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1572             sc, 0, igb_sysctl_tx_wreg_nsegs, "I",
1573             "# of segments sent before write to hardware register");
1574
1575         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1576             OID_AUTO, "rx_wreg_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1577             sc, 0, igb_sysctl_rx_wreg_nsegs, "I",
1578             "# of segments received before write to hardware register");
1579
1580 #ifdef IFPOLL_ENABLE
1581         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1582             OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
1583             sc, 0, igb_sysctl_npoll_rxoff, "I", "NPOLLING RX cpu offset");
1584         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1585             OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
1586             sc, 0, igb_sysctl_npoll_txoff, "I", "NPOLLING TX cpu offset");
1587 #endif
1588
1589 #ifdef IGB_RSS_DEBUG
1590         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1591             OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1592             "RSS debug level");
1593         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1594                 ksnprintf(node, sizeof(node), "rx%d_pkt", i);
1595                 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1596                     SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1597                     CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1598         }
1599 #endif
1600 #ifdef IGB_TSS_DEBUG
1601         for  (i = 0; i < sc->tx_ring_cnt; ++i) {
1602                 ksnprintf(node, sizeof(node), "tx%d_pkt", i);
1603                 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1604                     SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1605                     CTLFLAG_RW, &sc->tx_rings[i].tx_packets, "TXed packets");
1606         }
1607 #endif
1608 }
1609
1610 static int
1611 igb_alloc_rings(struct igb_softc *sc)
1612 {
1613         int error, i;
1614
1615         /*
1616          * Create top level busdma tag
1617          */
1618         error = bus_dma_tag_create(NULL, 1, 0,
1619             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1620             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1621             &sc->parent_tag);
1622         if (error) {
1623                 device_printf(sc->dev, "could not create top level DMA tag\n");
1624                 return error;
1625         }
1626
1627         /*
1628          * Allocate TX descriptor rings and buffers
1629          */
1630         sc->tx_rings = kmalloc_cachealign(
1631             sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1632             M_DEVBUF, M_WAITOK | M_ZERO);
1633         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1634                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1635
1636                 /* Set up some basics */
1637                 txr->sc = sc;
1638                 txr->me = i;
1639                 lwkt_serialize_init(&txr->tx_serialize);
1640
1641                 error = igb_create_tx_ring(txr);
1642                 if (error)
1643                         return error;
1644         }
1645
1646         /*
1647          * Allocate RX descriptor rings and buffers
1648          */
1649         sc->rx_rings = kmalloc_cachealign(
1650             sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1651             M_DEVBUF, M_WAITOK | M_ZERO);
1652         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1653                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1654
1655                 /* Set up some basics */
1656                 rxr->sc = sc;
1657                 rxr->me = i;
1658                 lwkt_serialize_init(&rxr->rx_serialize);
1659
1660                 error = igb_create_rx_ring(rxr);
1661                 if (error)
1662                         return error;
1663         }
1664
1665         return 0;
1666 }
1667
1668 static void
1669 igb_free_rings(struct igb_softc *sc)
1670 {
1671         int i;
1672
1673         if (sc->tx_rings != NULL) {
1674                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1675                         struct igb_tx_ring *txr = &sc->tx_rings[i];
1676
1677                         igb_destroy_tx_ring(txr, txr->num_tx_desc);
1678                 }
1679                 kfree(sc->tx_rings, M_DEVBUF);
1680         }
1681
1682         if (sc->rx_rings != NULL) {
1683                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1684                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
1685
1686                         igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1687                 }
1688                 kfree(sc->rx_rings, M_DEVBUF);
1689         }
1690 }
1691
1692 static int
1693 igb_create_tx_ring(struct igb_tx_ring *txr)
1694 {
1695         int tsize, error, i, ntxd;
1696
1697         /*
1698          * Validate number of transmit descriptors. It must not exceed
1699          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1700          */
1701         ntxd = device_getenv_int(txr->sc->dev, "txd", igb_txd);
1702         if ((ntxd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN != 0 ||
1703             ntxd > IGB_MAX_TXD || ntxd < IGB_MIN_TXD) {
1704                 device_printf(txr->sc->dev,
1705                     "Using %d TX descriptors instead of %d!\n",
1706                     IGB_DEFAULT_TXD, ntxd);
1707                 txr->num_tx_desc = IGB_DEFAULT_TXD;
1708         } else {
1709                 txr->num_tx_desc = ntxd;
1710         }
1711
1712         /*
1713          * Allocate TX descriptor ring
1714          */
1715         tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1716             IGB_DBA_ALIGN);
1717         txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1718             IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1719             &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1720         if (txr->txdma.dma_vaddr == NULL) {
1721                 device_printf(txr->sc->dev,
1722                     "Unable to allocate TX Descriptor memory\n");
1723                 return ENOMEM;
1724         }
1725         txr->tx_base = txr->txdma.dma_vaddr;
1726         bzero(txr->tx_base, tsize);
1727
1728         tsize = __VM_CACHELINE_ALIGN(
1729             sizeof(struct igb_tx_buf) * txr->num_tx_desc);
1730         txr->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
1731
1732         /*
1733          * Allocate TX head write-back buffer
1734          */
1735         txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1736             __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1737             &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1738         if (txr->tx_hdr == NULL) {
1739                 device_printf(txr->sc->dev,
1740                     "Unable to allocate TX head write-back buffer\n");
1741                 return ENOMEM;
1742         }
1743
1744         /*
1745          * Create DMA tag for TX buffers
1746          */
1747         error = bus_dma_tag_create(txr->sc->parent_tag,
1748             1, 0,               /* alignment, bounds */
1749             BUS_SPACE_MAXADDR,  /* lowaddr */
1750             BUS_SPACE_MAXADDR,  /* highaddr */
1751             NULL, NULL,         /* filter, filterarg */
1752             IGB_TSO_SIZE,       /* maxsize */
1753             IGB_MAX_SCATTER,    /* nsegments */
1754             PAGE_SIZE,          /* maxsegsize */
1755             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1756             BUS_DMA_ONEBPAGE,   /* flags */
1757             &txr->tx_tag);
1758         if (error) {
1759                 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1760                 kfree(txr->tx_buf, M_DEVBUF);
1761                 txr->tx_buf = NULL;
1762                 return error;
1763         }
1764
1765         /*
1766          * Create DMA maps for TX buffers
1767          */
1768         for (i = 0; i < txr->num_tx_desc; ++i) {
1769                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1770
1771                 error = bus_dmamap_create(txr->tx_tag,
1772                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1773                 if (error) {
1774                         device_printf(txr->sc->dev,
1775                             "Unable to create TX DMA map\n");
1776                         igb_destroy_tx_ring(txr, i);
1777                         return error;
1778                 }
1779         }
1780
1781         if (txr->sc->hw.mac.type == e1000_82575)
1782                 txr->tx_flags |= IGB_TXFLAG_TSO_IPLEN0;
1783
1784         /*
1785          * Initialize various watermark
1786          */
1787         txr->spare_desc = IGB_TX_SPARE;
1788         txr->intr_nsegs = txr->num_tx_desc / 16;
1789         txr->wreg_nsegs = IGB_DEF_TXWREG_NSEGS;
1790         txr->oact_hi_desc = txr->num_tx_desc / 2;
1791         txr->oact_lo_desc = txr->num_tx_desc / 8;
1792         if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1793                 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1794         if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1795                 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1796
1797         return 0;
1798 }
1799
1800 static void
1801 igb_free_tx_ring(struct igb_tx_ring *txr)
1802 {
1803         int i;
1804
1805         for (i = 0; i < txr->num_tx_desc; ++i) {
1806                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1807
1808                 if (txbuf->m_head != NULL) {
1809                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1810                         m_freem(txbuf->m_head);
1811                         txbuf->m_head = NULL;
1812                 }
1813         }
1814 }
1815
1816 static void
1817 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1818 {
1819         int i;
1820
1821         if (txr->txdma.dma_vaddr != NULL) {
1822                 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1823                 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1824                     txr->txdma.dma_map);
1825                 bus_dma_tag_destroy(txr->txdma.dma_tag);
1826                 txr->txdma.dma_vaddr = NULL;
1827         }
1828
1829         if (txr->tx_hdr != NULL) {
1830                 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1831                 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1832                     txr->tx_hdr_dmap);
1833                 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1834                 txr->tx_hdr = NULL;
1835         }
1836
1837         if (txr->tx_buf == NULL)
1838                 return;
1839
1840         for (i = 0; i < ndesc; ++i) {
1841                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1842
1843                 KKASSERT(txbuf->m_head == NULL);
1844                 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1845         }
1846         bus_dma_tag_destroy(txr->tx_tag);
1847
1848         kfree(txr->tx_buf, M_DEVBUF);
1849         txr->tx_buf = NULL;
1850 }
1851
1852 static void
1853 igb_init_tx_ring(struct igb_tx_ring *txr)
1854 {
1855         /* Clear the old descriptor contents */
1856         bzero(txr->tx_base,
1857             sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1858
1859         /* Clear TX head write-back buffer */
1860         *(txr->tx_hdr) = 0;
1861
1862         /* Reset indices */
1863         txr->next_avail_desc = 0;
1864         txr->next_to_clean = 0;
1865         txr->tx_nsegs = 0;
1866
1867         /* Set number of descriptors available */
1868         txr->tx_avail = txr->num_tx_desc;
1869
1870         /* Enable this TX ring */
1871         txr->tx_flags |= IGB_TXFLAG_ENABLED;
1872 }
1873
1874 static void
1875 igb_init_tx_unit(struct igb_softc *sc)
1876 {
1877         struct e1000_hw *hw = &sc->hw;
1878         uint32_t tctl;
1879         int i;
1880
1881         /* Setup the Tx Descriptor Rings */
1882         for (i = 0; i < sc->tx_ring_inuse; ++i) {
1883                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1884                 uint64_t bus_addr = txr->txdma.dma_paddr;
1885                 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1886                 uint32_t txdctl = 0;
1887                 uint32_t dca_txctrl;
1888
1889                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1890                     txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1891                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1892                     (uint32_t)(bus_addr >> 32));
1893                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1894                     (uint32_t)bus_addr);
1895
1896                 /* Setup the HW Tx Head and Tail descriptor pointers */
1897                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1898                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1899
1900                 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1901                 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1902                 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1903
1904                 /*
1905                  * Don't set WB_on_EITR:
1906                  * - 82575 does not have it
1907                  * - It almost has no effect on 82576, see:
1908                  *   82576 specification update errata #26
1909                  * - It causes unnecessary bus traffic
1910                  */
1911                 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1912                     (uint32_t)(hdr_paddr >> 32));
1913                 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1914                     ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1915
1916                 /*
1917                  * WTHRESH is ignored by the hardware, since header
1918                  * write back mode is used.
1919                  */
1920                 txdctl |= IGB_TX_PTHRESH;
1921                 txdctl |= IGB_TX_HTHRESH << 8;
1922                 txdctl |= IGB_TX_WTHRESH << 16;
1923                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1924                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1925         }
1926
1927         if (sc->vf_ifp)
1928                 return;
1929
1930         e1000_config_collision_dist(hw);
1931
1932         /* Program the Transmit Control Register */
1933         tctl = E1000_READ_REG(hw, E1000_TCTL);
1934         tctl &= ~E1000_TCTL_CT;
1935         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1936             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1937
1938         /* This write will effectively turn on the transmit unit. */
1939         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1940 }
1941
1942 static boolean_t
1943 igb_txcsum_ctx(struct igb_tx_ring *txr, struct mbuf *mp)
1944 {
1945         struct e1000_adv_tx_context_desc *TXD;
1946         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1947         int ehdrlen, ctxd, ip_hlen = 0;
1948         boolean_t offload = TRUE;
1949
1950         if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1951                 offload = FALSE;
1952
1953         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1954
1955         ctxd = txr->next_avail_desc;
1956         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1957
1958         /*
1959          * In advanced descriptors the vlan tag must
1960          * be placed into the context descriptor, thus
1961          * we need to be here just for that setup.
1962          */
1963         if (mp->m_flags & M_VLANTAG) {
1964                 uint16_t vlantag;
1965
1966                 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1967                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1968         } else if (!offload) {
1969                 return FALSE;
1970         }
1971
1972         ehdrlen = mp->m_pkthdr.csum_lhlen;
1973         KASSERT(ehdrlen > 0, ("invalid ether hlen"));
1974
1975         /* Set the ether header length */
1976         vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1977         if (mp->m_pkthdr.csum_flags & CSUM_IP) {
1978                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1979                 ip_hlen = mp->m_pkthdr.csum_iphlen;
1980                 KASSERT(ip_hlen > 0, ("invalid ip hlen"));
1981         }
1982         vlan_macip_lens |= ip_hlen;
1983
1984         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1985         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1986                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1987         else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1988                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1989
1990         /* 82575 needs the queue index added */
1991         if (txr->sc->hw.mac.type == e1000_82575)
1992                 mss_l4len_idx = txr->me << 4;
1993
1994         /* Now copy bits into descriptor */
1995         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1996         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1997         TXD->seqnum_seed = htole32(0);
1998         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1999
2000         /* We've consumed the first desc, adjust counters */
2001         if (++ctxd == txr->num_tx_desc)
2002                 ctxd = 0;
2003         txr->next_avail_desc = ctxd;
2004         --txr->tx_avail;
2005
2006         return offload;
2007 }
2008
2009 static void
2010 igb_txeof(struct igb_tx_ring *txr)
2011 {
2012         struct ifnet *ifp = &txr->sc->arpcom.ac_if;
2013         int first, hdr, avail;
2014
2015         if (txr->tx_avail == txr->num_tx_desc)
2016                 return;
2017
2018         first = txr->next_to_clean;
2019         hdr = *(txr->tx_hdr);
2020
2021         if (first == hdr)
2022                 return;
2023
2024         avail = txr->tx_avail;
2025         while (first != hdr) {
2026                 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
2027
2028                 ++avail;
2029                 if (txbuf->m_head) {
2030                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
2031                         m_freem(txbuf->m_head);
2032                         txbuf->m_head = NULL;
2033                         ++ifp->if_opackets;
2034                 }
2035                 if (++first == txr->num_tx_desc)
2036                         first = 0;
2037         }
2038         txr->next_to_clean = first;
2039         txr->tx_avail = avail;
2040
2041         /*
2042          * If we have a minimum free, clear OACTIVE
2043          * to tell the stack that it is OK to send packets.
2044          */
2045         if (IGB_IS_NOT_OACTIVE(txr)) {
2046                 ifsq_clr_oactive(txr->ifsq);
2047
2048                 /*
2049                  * We have enough TX descriptors, turn off
2050                  * the watchdog.  We allow small amount of
2051                  * packets (roughly intr_nsegs) pending on
2052                  * the transmit ring.
2053                  */
2054                 txr->tx_watchdog.wd_timer = 0;
2055         }
2056 }
2057
2058 static int
2059 igb_create_rx_ring(struct igb_rx_ring *rxr)
2060 {
2061         int rsize, i, error, nrxd;
2062
2063         /*
2064          * Validate number of receive descriptors. It must not exceed
2065          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
2066          */
2067         nrxd = device_getenv_int(rxr->sc->dev, "rxd", igb_rxd);
2068         if ((nrxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN != 0 ||
2069             nrxd > IGB_MAX_RXD || nrxd < IGB_MIN_RXD) {
2070                 device_printf(rxr->sc->dev,
2071                     "Using %d RX descriptors instead of %d!\n",
2072                     IGB_DEFAULT_RXD, nrxd);
2073                 rxr->num_rx_desc = IGB_DEFAULT_RXD;
2074         } else {
2075                 rxr->num_rx_desc = nrxd;
2076         }
2077
2078         /*
2079          * Allocate RX descriptor ring
2080          */
2081         rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
2082             IGB_DBA_ALIGN);
2083         rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
2084             IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2085             &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
2086             &rxr->rxdma.dma_paddr);
2087         if (rxr->rxdma.dma_vaddr == NULL) {
2088                 device_printf(rxr->sc->dev,
2089                     "Unable to allocate RxDescriptor memory\n");
2090                 return ENOMEM;
2091         }
2092         rxr->rx_base = rxr->rxdma.dma_vaddr;
2093         bzero(rxr->rx_base, rsize);
2094
2095         rsize = __VM_CACHELINE_ALIGN(
2096             sizeof(struct igb_rx_buf) * rxr->num_rx_desc);
2097         rxr->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
2098
2099         /*
2100          * Create DMA tag for RX buffers
2101          */
2102         error = bus_dma_tag_create(rxr->sc->parent_tag,
2103             1, 0,               /* alignment, bounds */
2104             BUS_SPACE_MAXADDR,  /* lowaddr */
2105             BUS_SPACE_MAXADDR,  /* highaddr */
2106             NULL, NULL,         /* filter, filterarg */
2107             MCLBYTES,           /* maxsize */
2108             1,                  /* nsegments */
2109             MCLBYTES,           /* maxsegsize */
2110             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2111             &rxr->rx_tag);
2112         if (error) {
2113                 device_printf(rxr->sc->dev,
2114                     "Unable to create RX payload DMA tag\n");
2115                 kfree(rxr->rx_buf, M_DEVBUF);
2116                 rxr->rx_buf = NULL;
2117                 return error;
2118         }
2119
2120         /*
2121          * Create spare DMA map for RX buffers
2122          */
2123         error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2124             &rxr->rx_sparemap);
2125         if (error) {
2126                 device_printf(rxr->sc->dev,
2127                     "Unable to create spare RX DMA maps\n");
2128                 bus_dma_tag_destroy(rxr->rx_tag);
2129                 kfree(rxr->rx_buf, M_DEVBUF);
2130                 rxr->rx_buf = NULL;
2131                 return error;
2132         }
2133
2134         /*
2135          * Create DMA maps for RX buffers
2136          */
2137         for (i = 0; i < rxr->num_rx_desc; i++) {
2138                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2139
2140                 error = bus_dmamap_create(rxr->rx_tag,
2141                     BUS_DMA_WAITOK, &rxbuf->map);
2142                 if (error) {
2143                         device_printf(rxr->sc->dev,
2144                             "Unable to create RX DMA maps\n");
2145                         igb_destroy_rx_ring(rxr, i);
2146                         return error;
2147                 }
2148         }
2149
2150         /*
2151          * Initialize various watermark
2152          */
2153         rxr->wreg_nsegs = IGB_DEF_RXWREG_NSEGS;
2154
2155         return 0;
2156 }
2157
2158 static void
2159 igb_free_rx_ring(struct igb_rx_ring *rxr)
2160 {
2161         int i;
2162
2163         for (i = 0; i < rxr->num_rx_desc; ++i) {
2164                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2165
2166                 if (rxbuf->m_head != NULL) {
2167                         bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2168                         m_freem(rxbuf->m_head);
2169                         rxbuf->m_head = NULL;
2170                 }
2171         }
2172
2173         if (rxr->fmp != NULL)
2174                 m_freem(rxr->fmp);
2175         rxr->fmp = NULL;
2176         rxr->lmp = NULL;
2177 }
2178
2179 static void
2180 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2181 {
2182         int i;
2183
2184         if (rxr->rxdma.dma_vaddr != NULL) {
2185                 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2186                 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2187                     rxr->rxdma.dma_map);
2188                 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2189                 rxr->rxdma.dma_vaddr = NULL;
2190         }
2191
2192         if (rxr->rx_buf == NULL)
2193                 return;
2194
2195         for (i = 0; i < ndesc; ++i) {
2196                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2197
2198                 KKASSERT(rxbuf->m_head == NULL);
2199                 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2200         }
2201         bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2202         bus_dma_tag_destroy(rxr->rx_tag);
2203
2204         kfree(rxr->rx_buf, M_DEVBUF);
2205         rxr->rx_buf = NULL;
2206 }
2207
2208 static void
2209 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2210 {
2211         rxd->read.pkt_addr = htole64(rxbuf->paddr);
2212         rxd->wb.upper.status_error = 0;
2213 }
2214
2215 static int
2216 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2217 {
2218         struct mbuf *m;
2219         bus_dma_segment_t seg;
2220         bus_dmamap_t map;
2221         struct igb_rx_buf *rxbuf;
2222         int error, nseg;
2223
2224         m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2225         if (m == NULL) {
2226                 if (wait) {
2227                         if_printf(&rxr->sc->arpcom.ac_if,
2228                             "Unable to allocate RX mbuf\n");
2229                 }
2230                 return ENOBUFS;
2231         }
2232         m->m_len = m->m_pkthdr.len = MCLBYTES;
2233
2234         if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2235                 m_adj(m, ETHER_ALIGN);
2236
2237         error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2238             rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2239         if (error) {
2240                 m_freem(m);
2241                 if (wait) {
2242                         if_printf(&rxr->sc->arpcom.ac_if,
2243                             "Unable to load RX mbuf\n");
2244                 }
2245                 return error;
2246         }
2247
2248         rxbuf = &rxr->rx_buf[i];
2249         if (rxbuf->m_head != NULL)
2250                 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2251
2252         map = rxbuf->map;
2253         rxbuf->map = rxr->rx_sparemap;
2254         rxr->rx_sparemap = map;
2255
2256         rxbuf->m_head = m;
2257         rxbuf->paddr = seg.ds_addr;
2258
2259         igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2260         return 0;
2261 }
2262
2263 static int
2264 igb_init_rx_ring(struct igb_rx_ring *rxr)
2265 {
2266         int i;
2267
2268         /* Clear the ring contents */
2269         bzero(rxr->rx_base,
2270             rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2271
2272         /* Now replenish the ring mbufs */
2273         for (i = 0; i < rxr->num_rx_desc; ++i) {
2274                 int error;
2275
2276                 error = igb_newbuf(rxr, i, TRUE);
2277                 if (error)
2278                         return error;
2279         }
2280
2281         /* Setup our descriptor indices */
2282         rxr->next_to_check = 0;
2283
2284         rxr->fmp = NULL;
2285         rxr->lmp = NULL;
2286         rxr->discard = FALSE;
2287
2288         return 0;
2289 }
2290
2291 static void
2292 igb_init_rx_unit(struct igb_softc *sc)
2293 {
2294         struct ifnet *ifp = &sc->arpcom.ac_if;
2295         struct e1000_hw *hw = &sc->hw;
2296         uint32_t rctl, rxcsum, srrctl = 0;
2297         int i;
2298
2299         /*
2300          * Make sure receives are disabled while setting
2301          * up the descriptor ring
2302          */
2303         rctl = E1000_READ_REG(hw, E1000_RCTL);
2304         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2305
2306 #if 0
2307         /*
2308         ** Set up for header split
2309         */
2310         if (igb_header_split) {
2311                 /* Use a standard mbuf for the header */
2312                 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2313                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2314         } else
2315 #endif
2316                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2317
2318         /*
2319         ** Set up for jumbo frames
2320         */
2321         if (ifp->if_mtu > ETHERMTU) {
2322                 rctl |= E1000_RCTL_LPE;
2323 #if 0
2324                 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2325                         srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2326                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2327                 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2328                         srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2329                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2330                 }
2331                 /* Set maximum packet len */
2332                 psize = adapter->max_frame_size;
2333                 /* are we on a vlan? */
2334                 if (adapter->ifp->if_vlantrunk != NULL)
2335                         psize += VLAN_TAG_SIZE;
2336                 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2337 #else
2338                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2339                 rctl |= E1000_RCTL_SZ_2048;
2340 #endif
2341         } else {
2342                 rctl &= ~E1000_RCTL_LPE;
2343                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2344                 rctl |= E1000_RCTL_SZ_2048;
2345         }
2346
2347         /* Setup the Base and Length of the Rx Descriptor Rings */
2348         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2349                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2350                 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2351                 uint32_t rxdctl;
2352
2353                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2354                     rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
2355                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2356                     (uint32_t)(bus_addr >> 32));
2357                 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2358                     (uint32_t)bus_addr);
2359                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2360                 /* Enable this Queue */
2361                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2362                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2363                 rxdctl &= 0xFFF00000;
2364                 rxdctl |= IGB_RX_PTHRESH;
2365                 rxdctl |= IGB_RX_HTHRESH << 8;
2366                 /*
2367                  * Don't set WTHRESH to a value above 1 on 82576, see:
2368                  * 82576 specification update errata #26
2369                  */
2370                 rxdctl |= IGB_RX_WTHRESH << 16;
2371                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2372         }
2373
2374         rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2375         rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2376
2377         /*
2378          * Receive Checksum Offload for TCP and UDP
2379          *
2380          * Checksum offloading is also enabled if multiple receive
2381          * queue is to be supported, since we need it to figure out
2382          * fragments.
2383          */
2384         if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2385                 /*
2386                  * NOTE:
2387                  * PCSD must be enabled to enable multiple
2388                  * receive queues.
2389                  */
2390                 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2391                     E1000_RXCSUM_PCSD;
2392         } else {
2393                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2394                     E1000_RXCSUM_PCSD);
2395         }
2396         E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2397
2398         if (IGB_ENABLE_HWRSS(sc)) {
2399                 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
2400                 uint32_t reta_shift;
2401                 int j, r;
2402
2403                 /*
2404                  * NOTE:
2405                  * When we reach here, RSS has already been disabled
2406                  * in igb_stop(), so we could safely configure RSS key
2407                  * and redirect table.
2408                  */
2409
2410                 /*
2411                  * Configure RSS key
2412                  */
2413                 toeplitz_get_key(key, sizeof(key));
2414                 for (i = 0; i < IGB_NRSSRK; ++i) {
2415                         uint32_t rssrk;
2416
2417                         rssrk = IGB_RSSRK_VAL(key, i);
2418                         IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2419
2420                         E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
2421                 }
2422
2423                 /*
2424                  * Configure RSS redirect table in following fashion:
2425                  * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2426                  */
2427                 reta_shift = IGB_RETA_SHIFT;
2428                 if (hw->mac.type == e1000_82575)
2429                         reta_shift = IGB_RETA_SHIFT_82575;
2430
2431                 r = 0;
2432                 for (j = 0; j < IGB_NRETA; ++j) {
2433                         uint32_t reta = 0;
2434
2435                         for (i = 0; i < IGB_RETA_SIZE; ++i) {
2436                                 uint32_t q;
2437
2438                                 q = (r % sc->rx_ring_inuse) << reta_shift;
2439                                 reta |= q << (8 * i);
2440                                 ++r;
2441                         }
2442                         IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2443                         E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2444                 }
2445
2446                 /*
2447                  * Enable multiple receive queues.
2448                  * Enable IPv4 RSS standard hash functions.
2449                  * Disable RSS interrupt on 82575
2450                  */
2451                 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2452                                 E1000_MRQC_ENABLE_RSS_4Q |
2453                                 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2454                                 E1000_MRQC_RSS_FIELD_IPV4);
2455         }
2456
2457         /* Setup the Receive Control Register */
2458         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2459         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2460             E1000_RCTL_RDMTS_HALF |
2461             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2462         /* Strip CRC bytes. */
2463         rctl |= E1000_RCTL_SECRC;
2464         /* Make sure VLAN Filters are off */
2465         rctl &= ~E1000_RCTL_VFE;
2466         /* Don't store bad packets */
2467         rctl &= ~E1000_RCTL_SBP;
2468
2469         /* Enable Receives */
2470         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2471
2472         /*
2473          * Setup the HW Rx Head and Tail Descriptor Pointers
2474          *   - needs to be after enable
2475          */
2476         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2477                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2478
2479                 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2480                 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
2481         }
2482 }
2483
2484 static void
2485 igb_rx_refresh(struct igb_rx_ring *rxr, int i)
2486 {
2487         if (--i < 0)
2488                 i = rxr->num_rx_desc - 1;
2489         E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2490 }
2491
2492 static void
2493 igb_rxeof(struct igb_rx_ring *rxr, int count)
2494 {
2495         struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2496         union e1000_adv_rx_desc *cur;
2497         uint32_t staterr;
2498         int i, ncoll = 0;
2499
2500         i = rxr->next_to_check;
2501         cur = &rxr->rx_base[i];
2502         staterr = le32toh(cur->wb.upper.status_error);
2503
2504         if ((staterr & E1000_RXD_STAT_DD) == 0)
2505                 return;
2506
2507         while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2508                 struct pktinfo *pi = NULL, pi0;
2509                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2510                 struct mbuf *m = NULL;
2511                 boolean_t eop;
2512
2513                 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2514                 if (eop)
2515                         --count;
2516
2517                 ++ncoll;
2518                 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2519                     !rxr->discard) {
2520                         struct mbuf *mp = rxbuf->m_head;
2521                         uint32_t hash, hashtype;
2522                         uint16_t vlan;
2523                         int len;
2524
2525                         len = le16toh(cur->wb.upper.length);
2526                         if (rxr->sc->hw.mac.type == e1000_i350 &&
2527                             (staterr & E1000_RXDEXT_STATERR_LB))
2528                                 vlan = be16toh(cur->wb.upper.vlan);
2529                         else
2530                                 vlan = le16toh(cur->wb.upper.vlan);
2531
2532                         hash = le32toh(cur->wb.lower.hi_dword.rss);
2533                         hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2534                             E1000_RXDADV_RSSTYPE_MASK;
2535
2536                         IGB_RSS_DPRINTF(rxr->sc, 10,
2537                             "ring%d, hash 0x%08x, hashtype %u\n",
2538                             rxr->me, hash, hashtype);
2539
2540                         bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2541                             BUS_DMASYNC_POSTREAD);
2542
2543                         if (igb_newbuf(rxr, i, FALSE) != 0) {
2544                                 ifp->if_iqdrops++;
2545                                 goto discard;
2546                         }
2547
2548                         mp->m_len = len;
2549                         if (rxr->fmp == NULL) {
2550                                 mp->m_pkthdr.len = len;
2551                                 rxr->fmp = mp;
2552                                 rxr->lmp = mp;
2553                         } else {
2554                                 rxr->lmp->m_next = mp;
2555                                 rxr->lmp = rxr->lmp->m_next;
2556                                 rxr->fmp->m_pkthdr.len += len;
2557                         }
2558
2559                         if (eop) {
2560                                 m = rxr->fmp;
2561                                 rxr->fmp = NULL;
2562                                 rxr->lmp = NULL;
2563
2564                                 m->m_pkthdr.rcvif = ifp;
2565                                 ifp->if_ipackets++;
2566
2567                                 if (ifp->if_capenable & IFCAP_RXCSUM)
2568                                         igb_rxcsum(staterr, m);
2569
2570                                 if (staterr & E1000_RXD_STAT_VP) {
2571                                         m->m_pkthdr.ether_vlantag = vlan;
2572                                         m->m_flags |= M_VLANTAG;
2573                                 }
2574
2575                                 if (ifp->if_capenable & IFCAP_RSS) {
2576                                         pi = igb_rssinfo(m, &pi0,
2577                                             hash, hashtype, staterr);
2578                                 }
2579 #ifdef IGB_RSS_DEBUG
2580                                 rxr->rx_packets++;
2581 #endif
2582                         }
2583                 } else {
2584                         ifp->if_ierrors++;
2585 discard:
2586                         igb_setup_rxdesc(cur, rxbuf);
2587                         if (!eop)
2588                                 rxr->discard = TRUE;
2589                         else
2590                                 rxr->discard = FALSE;
2591                         if (rxr->fmp != NULL) {
2592                                 m_freem(rxr->fmp);
2593                                 rxr->fmp = NULL;
2594                                 rxr->lmp = NULL;
2595                         }
2596                         m = NULL;
2597                 }
2598
2599                 if (m != NULL)
2600                         ether_input_pkt(ifp, m, pi);
2601
2602                 /* Advance our pointers to the next descriptor. */
2603                 if (++i == rxr->num_rx_desc)
2604                         i = 0;
2605
2606                 if (ncoll >= rxr->wreg_nsegs) {
2607                         igb_rx_refresh(rxr, i);
2608                         ncoll = 0;
2609                 }
2610
2611                 cur = &rxr->rx_base[i];
2612                 staterr = le32toh(cur->wb.upper.status_error);
2613         }
2614         rxr->next_to_check = i;
2615
2616         if (ncoll > 0)
2617                 igb_rx_refresh(rxr, i);
2618 }
2619
2620
2621 static void
2622 igb_set_vlan(struct igb_softc *sc)
2623 {
2624         struct e1000_hw *hw = &sc->hw;
2625         uint32_t reg;
2626 #if 0
2627         struct ifnet *ifp = sc->arpcom.ac_if;
2628 #endif
2629
2630         if (sc->vf_ifp) {
2631                 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2632                 return;
2633         }
2634
2635         reg = E1000_READ_REG(hw, E1000_CTRL);
2636         reg |= E1000_CTRL_VME;
2637         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2638
2639 #if 0
2640         /* Enable the Filter Table */
2641         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2642                 reg = E1000_READ_REG(hw, E1000_RCTL);
2643                 reg &= ~E1000_RCTL_CFIEN;
2644                 reg |= E1000_RCTL_VFE;
2645                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2646         }
2647 #endif
2648
2649         /* Update the frame size */
2650         E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2651             sc->max_frame_size + VLAN_TAG_SIZE);
2652
2653 #if 0
2654         /* Don't bother with table if no vlans */
2655         if ((adapter->num_vlans == 0) ||
2656             ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2657                 return;
2658         /*
2659         ** A soft reset zero's out the VFTA, so
2660         ** we need to repopulate it now.
2661         */
2662         for (int i = 0; i < IGB_VFTA_SIZE; i++)
2663                 if (adapter->shadow_vfta[i] != 0) {
2664                         if (adapter->vf_ifp)
2665                                 e1000_vfta_set_vf(hw,
2666                                     adapter->shadow_vfta[i], TRUE);
2667                         else
2668                                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2669                                  i, adapter->shadow_vfta[i]);
2670                 }
2671 #endif
2672 }
2673
2674 static void
2675 igb_enable_intr(struct igb_softc *sc)
2676 {
2677         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2678                 lwkt_serialize_handler_enable(&sc->main_serialize);
2679         } else {
2680                 int i;
2681
2682                 for (i = 0; i < sc->msix_cnt; ++i) {
2683                         lwkt_serialize_handler_enable(
2684                             sc->msix_data[i].msix_serialize);
2685                 }
2686         }
2687
2688         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2689                 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
2690                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, sc->intr_mask);
2691                 else
2692                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2693                 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2694                 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2695                 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2696         } else {
2697                 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2698         }
2699         E1000_WRITE_FLUSH(&sc->hw);
2700 }
2701
2702 static void
2703 igb_disable_intr(struct igb_softc *sc)
2704 {
2705         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2706                 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2707                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2708         }
2709         E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2710         E1000_WRITE_FLUSH(&sc->hw);
2711
2712         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2713                 lwkt_serialize_handler_disable(&sc->main_serialize);
2714         } else {
2715                 int i;
2716
2717                 for (i = 0; i < sc->msix_cnt; ++i) {
2718                         lwkt_serialize_handler_disable(
2719                             sc->msix_data[i].msix_serialize);
2720                 }
2721         }
2722 }
2723
2724 /*
2725  * Bit of a misnomer, what this really means is
2726  * to enable OS management of the system... aka
2727  * to disable special hardware management features
2728  */
2729 static void
2730 igb_get_mgmt(struct igb_softc *sc)
2731 {
2732         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2733                 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2734                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2735
2736                 /* disable hardware interception of ARP */
2737                 manc &= ~E1000_MANC_ARP_EN;
2738
2739                 /* enable receiving management packets to the host */
2740                 manc |= E1000_MANC_EN_MNG2HOST;
2741                 manc2h |= 1 << 5; /* Mng Port 623 */
2742                 manc2h |= 1 << 6; /* Mng Port 664 */
2743                 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2744                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2745         }
2746 }
2747
2748 /*
2749  * Give control back to hardware management controller
2750  * if there is one.
2751  */
2752 static void
2753 igb_rel_mgmt(struct igb_softc *sc)
2754 {
2755         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2756                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2757
2758                 /* Re-enable hardware interception of ARP */
2759                 manc |= E1000_MANC_ARP_EN;
2760                 manc &= ~E1000_MANC_EN_MNG2HOST;
2761
2762                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2763         }
2764 }
2765
2766 /*
2767  * Sets CTRL_EXT:DRV_LOAD bit.
2768  *
2769  * For ASF and Pass Through versions of f/w this means that
2770  * the driver is loaded.
2771  */
2772 static void
2773 igb_get_hw_control(struct igb_softc *sc)
2774 {
2775         uint32_t ctrl_ext;
2776
2777         if (sc->vf_ifp)
2778                 return;
2779
2780         /* Let firmware know the driver has taken over */
2781         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2782         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2783             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2784 }
2785
2786 /*
2787  * Resets CTRL_EXT:DRV_LOAD bit.
2788  *
2789  * For ASF and Pass Through versions of f/w this means that the
2790  * driver is no longer loaded.
2791  */
2792 static void
2793 igb_rel_hw_control(struct igb_softc *sc)
2794 {
2795         uint32_t ctrl_ext;
2796
2797         if (sc->vf_ifp)
2798                 return;
2799
2800         /* Let firmware taken over control of h/w */
2801         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2802         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2803             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2804 }
2805
2806 static int
2807 igb_is_valid_ether_addr(const uint8_t *addr)
2808 {
2809         uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2810
2811         if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2812                 return FALSE;
2813         return TRUE;
2814 }
2815
2816 /*
2817  * Enable PCI Wake On Lan capability
2818  */
2819 static void
2820 igb_enable_wol(device_t dev)
2821 {
2822         uint16_t cap, status;
2823         uint8_t id;
2824
2825         /* First find the capabilities pointer*/
2826         cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2827
2828         /* Read the PM Capabilities */
2829         id = pci_read_config(dev, cap, 1);
2830         if (id != PCIY_PMG)     /* Something wrong */
2831                 return;
2832
2833         /*
2834          * OK, we have the power capabilities,
2835          * so now get the status register
2836          */
2837         cap += PCIR_POWER_STATUS;
2838         status = pci_read_config(dev, cap, 2);
2839         status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2840         pci_write_config(dev, cap, status, 2);
2841 }
2842
2843 static void
2844 igb_update_stats_counters(struct igb_softc *sc)
2845 {
2846         struct e1000_hw *hw = &sc->hw;
2847         struct e1000_hw_stats *stats;
2848         struct ifnet *ifp = &sc->arpcom.ac_if;
2849
2850         /*
2851          * The virtual function adapter has only a
2852          * small controlled set of stats, do only
2853          * those and return.
2854          */
2855         if (sc->vf_ifp) {
2856                 igb_update_vf_stats_counters(sc);
2857                 return;
2858         }
2859         stats = sc->stats;
2860
2861         if (sc->hw.phy.media_type == e1000_media_type_copper ||
2862             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2863                 stats->symerrs +=
2864                     E1000_READ_REG(hw,E1000_SYMERRS);
2865                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2866         }
2867
2868         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2869         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2870         stats->scc += E1000_READ_REG(hw, E1000_SCC);
2871         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2872
2873         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2874         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2875         stats->colc += E1000_READ_REG(hw, E1000_COLC);
2876         stats->dc += E1000_READ_REG(hw, E1000_DC);
2877         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2878         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2879         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2880
2881         /*
2882          * For watchdog management we need to know if we have been
2883          * paused during the last interval, so capture that here.
2884          */
2885         sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2886         stats->xoffrxc += sc->pause_frames;
2887         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2888         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2889         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2890         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2891         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2892         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2893         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2894         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2895         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2896         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2897         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2898         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2899
2900         /* For the 64-bit byte counters the low dword must be read first. */
2901         /* Both registers clear on the read of the high dword */
2902
2903         stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2904             ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2905         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2906             ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2907
2908         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2909         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2910         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2911         stats->roc += E1000_READ_REG(hw, E1000_ROC);
2912         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2913
2914         stats->tor += E1000_READ_REG(hw, E1000_TORH);
2915         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2916
2917         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2918         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2919         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2920         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2921         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2922         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2923         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2924         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2925         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2926         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2927
2928         /* Interrupt Counts */
2929
2930         stats->iac += E1000_READ_REG(hw, E1000_IAC);
2931         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2932         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2933         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2934         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2935         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2936         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2937         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2938         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2939
2940         /* Host to Card Statistics */
2941
2942         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2943         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2944         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2945         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2946         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2947         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2948         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2949         stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2950             ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2951         stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2952             ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2953         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2954         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2955         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2956
2957         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2958         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2959         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2960         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2961         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2962         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2963
2964         ifp->if_collisions = stats->colc;
2965
2966         /* Rx Errors */
2967         ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2968             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2969
2970         /* Tx Errors */
2971         ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2972
2973         /* Driver specific counters */
2974         sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2975         sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2976         sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2977         sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2978         sc->packet_buf_alloc_tx =
2979             ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2980         sc->packet_buf_alloc_rx =
2981             (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2982 }
2983
2984 static void
2985 igb_vf_init_stats(struct igb_softc *sc)
2986 {
2987         struct e1000_hw *hw = &sc->hw;
2988         struct e1000_vf_stats *stats;
2989
2990         stats = sc->stats;
2991         stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2992         stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2993         stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2994         stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2995         stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2996 }
2997
2998 static void
2999 igb_update_vf_stats_counters(struct igb_softc *sc)
3000 {
3001         struct e1000_hw *hw = &sc->hw;
3002         struct e1000_vf_stats *stats;
3003
3004         if (sc->link_speed == 0)
3005                 return;
3006
3007         stats = sc->stats;
3008         UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
3009         UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
3010         UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
3011         UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
3012         UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
3013 }
3014
3015 #ifdef IFPOLL_ENABLE
3016
3017 static void
3018 igb_npoll_status(struct ifnet *ifp)
3019 {
3020         struct igb_softc *sc = ifp->if_softc;
3021         uint32_t reg_icr;
3022
3023         ASSERT_SERIALIZED(&sc->main_serialize);
3024
3025         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3026         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3027                 sc->hw.mac.get_link_status = 1;
3028                 igb_update_link_status(sc);
3029         }
3030 }
3031
3032 static void
3033 igb_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
3034 {
3035         struct igb_tx_ring *txr = arg;
3036
3037         ASSERT_SERIALIZED(&txr->tx_serialize);
3038
3039         igb_txeof(txr);
3040         if (!ifsq_is_empty(txr->ifsq))
3041                 ifsq_devstart(txr->ifsq);
3042 }
3043
3044 static void
3045 igb_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
3046 {
3047         struct igb_rx_ring *rxr = arg;
3048
3049         ASSERT_SERIALIZED(&rxr->rx_serialize);
3050
3051         igb_rxeof(rxr, cycle);
3052 }
3053
3054 static void
3055 igb_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3056 {
3057         struct igb_softc *sc = ifp->if_softc;
3058         int i, txr_cnt, rxr_cnt;
3059
3060         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3061
3062         if (info) {
3063                 int off;
3064
3065                 info->ifpi_status.status_func = igb_npoll_status;
3066                 info->ifpi_status.serializer = &sc->main_serialize;
3067
3068                 txr_cnt = igb_get_txring_inuse(sc, TRUE);
3069                 off = sc->tx_npoll_off;
3070                 for (i = 0; i < txr_cnt; ++i) {
3071                         struct igb_tx_ring *txr = &sc->tx_rings[i];
3072                         int idx = i + off;
3073
3074                         KKASSERT(idx < ncpus2);
3075                         info->ifpi_tx[idx].poll_func = igb_npoll_tx;
3076                         info->ifpi_tx[idx].arg = txr;
3077                         info->ifpi_tx[idx].serializer = &txr->tx_serialize;
3078                         ifsq_set_cpuid(txr->ifsq, idx);
3079                 }
3080
3081                 rxr_cnt = igb_get_rxring_inuse(sc, TRUE);
3082                 off = sc->rx_npoll_off;
3083                 for (i = 0; i < rxr_cnt; ++i) {
3084                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
3085                         int idx = i + off;
3086
3087                         KKASSERT(idx < ncpus2);
3088                         info->ifpi_rx[idx].poll_func = igb_npoll_rx;
3089                         info->ifpi_rx[idx].arg = rxr;
3090                         info->ifpi_rx[idx].serializer = &rxr->rx_serialize;
3091                 }
3092
3093                 if (ifp->if_flags & IFF_RUNNING) {
3094                         if (rxr_cnt == sc->rx_ring_inuse &&
3095                             txr_cnt == sc->tx_ring_inuse)
3096                                 igb_disable_intr(sc);
3097                         else
3098                                 igb_init(sc);
3099                 }
3100         } else {
3101                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3102                         struct igb_tx_ring *txr = &sc->tx_rings[i];
3103
3104                         ifsq_set_cpuid(txr->ifsq, txr->tx_intr_cpuid);
3105                 }
3106
3107                 if (ifp->if_flags & IFF_RUNNING) {
3108                         txr_cnt = igb_get_txring_inuse(sc, FALSE);
3109                         rxr_cnt = igb_get_rxring_inuse(sc, FALSE);
3110
3111                         if (rxr_cnt == sc->rx_ring_inuse &&
3112                             txr_cnt == sc->tx_ring_inuse)
3113                                 igb_enable_intr(sc);
3114                         else
3115                                 igb_init(sc);
3116                 }
3117         }
3118 }
3119
3120 #endif /* IFPOLL_ENABLE */
3121
3122 static void
3123 igb_intr(void *xsc)
3124 {
3125         struct igb_softc *sc = xsc;
3126         struct ifnet *ifp = &sc->arpcom.ac_if;
3127         uint32_t eicr;
3128
3129         ASSERT_SERIALIZED(&sc->main_serialize);
3130
3131         eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
3132
3133         if (eicr == 0)
3134                 return;
3135
3136         if (ifp->if_flags & IFF_RUNNING) {
3137                 struct igb_tx_ring *txr = &sc->tx_rings[0];
3138                 int i;
3139
3140                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3141                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
3142
3143                         if (eicr & rxr->rx_intr_mask) {
3144                                 lwkt_serialize_enter(&rxr->rx_serialize);
3145                                 igb_rxeof(rxr, -1);
3146                                 lwkt_serialize_exit(&rxr->rx_serialize);
3147                         }
3148                 }
3149
3150                 if (eicr & txr->tx_intr_mask) {
3151                         lwkt_serialize_enter(&txr->tx_serialize);
3152                         igb_txeof(txr);
3153                         if (!ifsq_is_empty(txr->ifsq))
3154                                 ifsq_devstart(txr->ifsq);
3155                         lwkt_serialize_exit(&txr->tx_serialize);
3156                 }
3157         }
3158
3159         if (eicr & E1000_EICR_OTHER) {
3160                 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3161
3162                 /* Link status change */
3163                 if (icr & E1000_ICR_LSC) {
3164                         sc->hw.mac.get_link_status = 1;
3165                         igb_update_link_status(sc);
3166                 }
3167         }
3168
3169         /*
3170          * Reading EICR has the side effect to clear interrupt mask,
3171          * so all interrupts need to be enabled here.
3172          */
3173         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
3174 }
3175
3176 static void
3177 igb_intr_shared(void *xsc)
3178 {
3179         struct igb_softc *sc = xsc;
3180         struct ifnet *ifp = &sc->arpcom.ac_if;
3181         uint32_t reg_icr;
3182
3183         ASSERT_SERIALIZED(&sc->main_serialize);
3184
3185         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3186
3187         /* Hot eject?  */
3188         if (reg_icr == 0xffffffff)
3189                 return;
3190
3191         /* Definitely not our interrupt.  */
3192         if (reg_icr == 0x0)
3193                 return;
3194
3195         if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3196                 return;
3197
3198         if (ifp->if_flags & IFF_RUNNING) {
3199                 if (reg_icr &
3200                     (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3201                         int i;
3202
3203                         for (i = 0; i < sc->rx_ring_inuse; ++i) {
3204                                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3205
3206                                 lwkt_serialize_enter(&rxr->rx_serialize);
3207                                 igb_rxeof(rxr, -1);
3208                                 lwkt_serialize_exit(&rxr->rx_serialize);
3209                         }
3210                 }
3211
3212                 if (reg_icr & E1000_ICR_TXDW) {
3213                         struct igb_tx_ring *txr = &sc->tx_rings[0];
3214
3215                         lwkt_serialize_enter(&txr->tx_serialize);
3216                         igb_txeof(txr);
3217                         if (!ifsq_is_empty(txr->ifsq))
3218                                 ifsq_devstart(txr->ifsq);
3219                         lwkt_serialize_exit(&txr->tx_serialize);
3220                 }
3221         }
3222
3223         /* Link status change */
3224         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3225                 sc->hw.mac.get_link_status = 1;
3226                 igb_update_link_status(sc);
3227         }
3228
3229         if (reg_icr & E1000_ICR_RXO)
3230                 sc->rx_overruns++;
3231 }
3232
3233 static int
3234 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp,
3235     int *segs_used, int *idx)
3236 {
3237         bus_dma_segment_t segs[IGB_MAX_SCATTER];
3238         bus_dmamap_t map;
3239         struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3240         union e1000_adv_tx_desc *txd = NULL;
3241         struct mbuf *m_head = *m_headp;
3242         uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3243         int maxsegs, nsegs, i, j, error;
3244         uint32_t hdrlen = 0;
3245
3246         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3247                 error = igb_tso_pullup(txr, m_headp);
3248                 if (error)
3249                         return error;
3250                 m_head = *m_headp;
3251         }
3252
3253         /* Set basic descriptor constants */
3254         cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3255         cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3256         if (m_head->m_flags & M_VLANTAG)
3257                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3258
3259         /*
3260          * Map the packet for DMA.
3261          */
3262         tx_buf = &txr->tx_buf[txr->next_avail_desc];
3263         tx_buf_mapped = tx_buf;
3264         map = tx_buf->map;
3265
3266         maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3267         KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
3268         if (maxsegs > IGB_MAX_SCATTER)
3269                 maxsegs = IGB_MAX_SCATTER;
3270
3271         error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3272             segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3273         if (error) {
3274                 if (error == ENOBUFS)
3275                         txr->sc->mbuf_defrag_failed++;
3276                 else
3277                         txr->sc->no_tx_dma_setup++;
3278
3279                 m_freem(*m_headp);
3280                 *m_headp = NULL;
3281                 return error;
3282         }
3283         bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3284
3285         m_head = *m_headp;
3286
3287         /*
3288          * Set up the TX context descriptor, if any hardware offloading is
3289          * needed.  This includes CSUM, VLAN, and TSO.  It will consume one
3290          * TX descriptor.
3291          *
3292          * Unlike these chips' predecessors (em/emx), TX context descriptor
3293          * will _not_ interfere TX data fetching pipelining.
3294          */
3295         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3296                 igb_tso_ctx(txr, m_head, &hdrlen);
3297                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3298                 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3299                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3300                 txr->tx_nsegs++;
3301                 (*segs_used)++;
3302         } else if (igb_txcsum_ctx(txr, m_head)) {
3303                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3304                         olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
3305                 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3306                         olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
3307                 txr->tx_nsegs++;
3308                 (*segs_used)++;
3309         }
3310
3311         *segs_used += nsegs;
3312         txr->tx_nsegs += nsegs;
3313         if (txr->tx_nsegs >= txr->intr_nsegs) {
3314                 /*
3315                  * Report Status (RS) is turned on every intr_nsegs
3316                  * descriptors (roughly).
3317                  */
3318                 txr->tx_nsegs = 0;
3319                 cmd_rs = E1000_ADVTXD_DCMD_RS;
3320         }
3321
3322         /* Calculate payload length */
3323         olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3324             << E1000_ADVTXD_PAYLEN_SHIFT);
3325
3326         /* 82575 needs the queue index added */
3327         if (txr->sc->hw.mac.type == e1000_82575)
3328                 olinfo_status |= txr->me << 4;
3329
3330         /* Set up our transmit descriptors */
3331         i = txr->next_avail_desc;
3332         for (j = 0; j < nsegs; j++) {
3333                 bus_size_t seg_len;
3334                 bus_addr_t seg_addr;
3335
3336                 tx_buf = &txr->tx_buf[i];
3337                 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3338                 seg_addr = segs[j].ds_addr;
3339                 seg_len = segs[j].ds_len;
3340
3341                 txd->read.buffer_addr = htole64(seg_addr);
3342                 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3343                 txd->read.olinfo_status = htole32(olinfo_status);
3344                 if (++i == txr->num_tx_desc)
3345                         i = 0;
3346                 tx_buf->m_head = NULL;
3347         }
3348
3349         KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3350         txr->next_avail_desc = i;
3351         txr->tx_avail -= nsegs;
3352
3353         tx_buf->m_head = m_head;
3354         tx_buf_mapped->map = tx_buf->map;
3355         tx_buf->map = map;
3356
3357         /*
3358          * Last Descriptor of Packet needs End Of Packet (EOP)
3359          */
3360         txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3361
3362         /*
3363          * Defer TDT updating, until enough descrptors are setup
3364          */
3365         *idx = i;
3366 #ifdef IGB_TSS_DEBUG
3367         ++txr->tx_packets;
3368 #endif
3369
3370         return 0;
3371 }
3372
3373 static void
3374 igb_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
3375 {
3376         struct igb_softc *sc = ifp->if_softc;
3377         struct igb_tx_ring *txr = ifsq_get_priv(ifsq);
3378         struct mbuf *m_head;
3379         int idx = -1, nsegs = 0;
3380
3381         KKASSERT(txr->ifsq == ifsq);
3382         ASSERT_SERIALIZED(&txr->tx_serialize);
3383
3384         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
3385                 return;
3386
3387         if (!sc->link_active || (txr->tx_flags & IGB_TXFLAG_ENABLED) == 0) {
3388                 ifsq_purge(ifsq);
3389                 return;
3390         }
3391
3392         if (!IGB_IS_NOT_OACTIVE(txr))
3393                 igb_txeof(txr);
3394
3395         while (!ifsq_is_empty(ifsq)) {
3396                 if (IGB_IS_OACTIVE(txr)) {
3397                         ifsq_set_oactive(ifsq);
3398                         /* Set watchdog on */
3399                         txr->tx_watchdog.wd_timer = 5;
3400                         break;
3401                 }
3402
3403                 m_head = ifsq_dequeue(ifsq, NULL);
3404                 if (m_head == NULL)
3405                         break;
3406
3407                 if (igb_encap(txr, &m_head, &nsegs, &idx)) {
3408                         ifp->if_oerrors++;
3409                         continue;
3410                 }
3411
3412                 if (nsegs >= txr->wreg_nsegs) {
3413                         E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3414                         idx = -1;
3415                         nsegs = 0;
3416                 }
3417
3418                 /* Send a copy of the frame to the BPF listener */
3419                 ETHER_BPF_MTAP(ifp, m_head);
3420         }
3421         if (idx >= 0)
3422                 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3423 }
3424
3425 static void
3426 igb_watchdog(struct ifaltq_subque *ifsq)
3427 {
3428         struct igb_tx_ring *txr = ifsq_get_priv(ifsq);
3429         struct ifnet *ifp = ifsq_get_ifp(ifsq);
3430         struct igb_softc *sc = ifp->if_softc;
3431         int i;
3432
3433         KKASSERT(txr->ifsq == ifsq);
3434         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3435
3436         /*
3437          * If flow control has paused us since last checking
3438          * it invalidates the watchdog timing, so dont run it.
3439          */
3440         if (sc->pause_frames) {
3441                 sc->pause_frames = 0;
3442                 txr->tx_watchdog.wd_timer = 5;
3443                 return;
3444         }
3445
3446         if_printf(ifp, "Watchdog timeout -- resetting\n");
3447         if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3448             E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3449             E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3450         if_printf(ifp, "TX(%d) desc avail = %d, "
3451             "Next TX to Clean = %d\n",
3452             txr->me, txr->tx_avail, txr->next_to_clean);
3453
3454         ifp->if_oerrors++;
3455         sc->watchdog_events++;
3456
3457         igb_init(sc);
3458         for (i = 0; i < sc->tx_ring_inuse; ++i)
3459                 ifsq_devstart_sched(sc->tx_rings[i].ifsq);
3460 }
3461
3462 static void
3463 igb_set_eitr(struct igb_softc *sc, int idx, int rate)
3464 {
3465         uint32_t eitr = 0;
3466
3467         if (rate > 0) {
3468                 if (sc->hw.mac.type == e1000_82575) {
3469                         eitr = 1000000000 / 256 / rate;
3470                         /*
3471                          * NOTE:
3472                          * Document is wrong on the 2 bits left shift
3473                          */
3474                 } else {
3475                         eitr = 1000000 / rate;
3476                         eitr <<= IGB_EITR_INTVL_SHIFT;
3477                 }
3478
3479                 if (eitr == 0) {
3480                         /* Don't disable it */
3481                         eitr = 1 << IGB_EITR_INTVL_SHIFT;
3482                 } else if (eitr > IGB_EITR_INTVL_MASK) {
3483                         /* Don't allow it to be too large */
3484                         eitr = IGB_EITR_INTVL_MASK;
3485                 }
3486         }
3487         if (sc->hw.mac.type == e1000_82575)
3488                 eitr |= eitr << 16;
3489         else
3490                 eitr |= E1000_EITR_CNT_IGNR;
3491         E1000_WRITE_REG(&sc->hw, E1000_EITR(idx), eitr);
3492 }
3493
3494 static int
3495 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3496 {
3497         struct igb_softc *sc = (void *)arg1;
3498         struct ifnet *ifp = &sc->arpcom.ac_if;
3499         int error, intr_rate;
3500
3501         intr_rate = sc->intr_rate;
3502         error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3503         if (error || req->newptr == NULL)
3504                 return error;
3505         if (intr_rate < 0)
3506                 return EINVAL;
3507
3508         ifnet_serialize_all(ifp);
3509
3510         sc->intr_rate = intr_rate;
3511         if (ifp->if_flags & IFF_RUNNING)
3512                 igb_set_eitr(sc, 0, sc->intr_rate);
3513
3514         if (bootverbose)
3515                 if_printf(ifp, "interrupt rate set to %d/sec\n", sc->intr_rate);
3516
3517         ifnet_deserialize_all(ifp);
3518
3519         return 0;
3520 }
3521
3522 static int
3523 igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS)
3524 {
3525         struct igb_msix_data *msix = (void *)arg1;
3526         struct igb_softc *sc = msix->msix_sc;
3527         struct ifnet *ifp = &sc->arpcom.ac_if;
3528         int error, msix_rate;
3529
3530         msix_rate = msix->msix_rate;
3531         error = sysctl_handle_int(oidp, &msix_rate, 0, req);
3532         if (error || req->newptr == NULL)
3533                 return error;
3534         if (msix_rate < 0)
3535                 return EINVAL;
3536
3537         lwkt_serialize_enter(msix->msix_serialize);
3538
3539         msix->msix_rate = msix_rate;
3540         if (ifp->if_flags & IFF_RUNNING)
3541                 igb_set_eitr(sc, msix->msix_vector, msix->msix_rate);
3542
3543         if (bootverbose) {
3544                 if_printf(ifp, "%s set to %d/sec\n", msix->msix_rate_desc,
3545                     msix->msix_rate);
3546         }
3547
3548         lwkt_serialize_exit(msix->msix_serialize);
3549
3550         return 0;
3551 }
3552
3553 static int
3554 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3555 {
3556         struct igb_softc *sc = (void *)arg1;
3557         struct ifnet *ifp = &sc->arpcom.ac_if;
3558         struct igb_tx_ring *txr = &sc->tx_rings[0];
3559         int error, nsegs;
3560
3561         nsegs = txr->intr_nsegs;
3562         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3563         if (error || req->newptr == NULL)
3564                 return error;
3565         if (nsegs <= 0)
3566                 return EINVAL;
3567
3568         ifnet_serialize_all(ifp);
3569
3570         if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
3571             nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3572                 error = EINVAL;
3573         } else {
3574                 int i;
3575
3576                 error = 0;
3577                 for (i = 0; i < sc->tx_ring_cnt; ++i)
3578                         sc->tx_rings[i].intr_nsegs = nsegs;
3579         }
3580
3581         ifnet_deserialize_all(ifp);
3582
3583         return error;
3584 }
3585
3586 static int
3587 igb_sysctl_rx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3588 {
3589         struct igb_softc *sc = (void *)arg1;
3590         struct ifnet *ifp = &sc->arpcom.ac_if;
3591         int error, nsegs, i;
3592
3593         nsegs = sc->rx_rings[0].wreg_nsegs;
3594         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3595         if (error || req->newptr == NULL)
3596                 return error;
3597
3598         ifnet_serialize_all(ifp);
3599         for (i = 0; i < sc->rx_ring_cnt; ++i)
3600                 sc->rx_rings[i].wreg_nsegs =nsegs;
3601         ifnet_deserialize_all(ifp);
3602
3603         return 0;
3604 }
3605
3606 static int
3607 igb_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3608 {
3609         struct igb_softc *sc = (void *)arg1;
3610         struct ifnet *ifp = &sc->arpcom.ac_if;
3611         int error, nsegs, i;
3612
3613         nsegs = sc->tx_rings[0].wreg_nsegs;
3614         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3615         if (error || req->newptr == NULL)
3616                 return error;
3617
3618         ifnet_serialize_all(ifp);
3619         for (i = 0; i < sc->tx_ring_cnt; ++i)
3620                 sc->tx_rings[i].wreg_nsegs =nsegs;
3621         ifnet_deserialize_all(ifp);
3622
3623         return 0;
3624 }
3625
3626 #ifdef IFPOLL_ENABLE
3627
3628 static int
3629 igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3630 {
3631         struct igb_softc *sc = (void *)arg1;
3632         struct ifnet *ifp = &sc->arpcom.ac_if;
3633         int error, off;
3634
3635         off = sc->rx_npoll_off;
3636         error = sysctl_handle_int(oidp, &off, 0, req);
3637         if (error || req->newptr == NULL)
3638                 return error;
3639         if (off < 0)
3640                 return EINVAL;
3641
3642         ifnet_serialize_all(ifp);
3643         if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3644                 error = EINVAL;
3645         } else {
3646                 error = 0;
3647                 sc->rx_npoll_off = off;
3648         }
3649         ifnet_deserialize_all(ifp);
3650
3651         return error;
3652 }
3653
3654 static int
3655 igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3656 {
3657         struct igb_softc *sc = (void *)arg1;
3658         struct ifnet *ifp = &sc->arpcom.ac_if;
3659         int error, off;
3660
3661         off = sc->tx_npoll_off;
3662         error = sysctl_handle_int(oidp, &off, 0, req);
3663         if (error || req->newptr == NULL)
3664                 return error;
3665         if (off < 0)
3666                 return EINVAL;
3667
3668         ifnet_serialize_all(ifp);
3669         if (off >= ncpus2 || off % sc->tx_ring_cnt != 0) {
3670                 error = EINVAL;
3671         } else {
3672                 error = 0;
3673                 sc->tx_npoll_off = off;
3674         }
3675         ifnet_deserialize_all(ifp);
3676
3677         return error;
3678 }
3679
3680 #endif  /* IFPOLL_ENABLE */
3681
3682 static void
3683 igb_init_intr(struct igb_softc *sc)
3684 {
3685         igb_set_intr_mask(sc);
3686
3687         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0)
3688                 igb_init_unshared_intr(sc);
3689
3690         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3691                 igb_set_eitr(sc, 0, sc->intr_rate);
3692         } else {
3693                 int i;
3694
3695                 for (i = 0; i < sc->msix_cnt; ++i)
3696                         igb_set_eitr(sc, i, sc->msix_data[i].msix_rate);
3697         }
3698 }
3699
3700 static void
3701 igb_init_unshared_intr(struct igb_softc *sc)
3702 {
3703         struct e1000_hw *hw = &sc->hw;
3704         const struct igb_rx_ring *rxr;
3705         const struct igb_tx_ring *txr;
3706         uint32_t ivar, index;
3707         int i;
3708
3709         /*
3710          * Enable extended mode
3711          */
3712         if (sc->hw.mac.type != e1000_82575) {
3713                 uint32_t gpie;
3714                 int ivar_max;
3715
3716                 gpie = E1000_GPIE_NSICR;
3717                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3718                         gpie |= E1000_GPIE_MSIX_MODE |
3719                             E1000_GPIE_EIAME |
3720                             E1000_GPIE_PBA;
3721                 }
3722                 E1000_WRITE_REG(hw, E1000_GPIE, gpie);
3723
3724                 /*
3725                  * Clear IVARs
3726                  */
3727                 switch (sc->hw.mac.type) {
3728                 case e1000_82580:
3729                         ivar_max = IGB_MAX_IVAR_82580;
3730                         break;
3731
3732                 case e1000_i350:
3733                         ivar_max = IGB_MAX_IVAR_I350;
3734                         break;
3735
3736                 case e1000_vfadapt:
3737                 case e1000_vfadapt_i350:
3738                         ivar_max = IGB_MAX_IVAR_VF;
3739                         break;
3740
3741                 case e1000_82576:
3742                         ivar_max = IGB_MAX_IVAR_82576;
3743                         break;
3744
3745                 default:
3746                         panic("unknown mac type %d\n", sc->hw.mac.type);
3747                 }
3748                 for (i = 0; i < ivar_max; ++i)
3749                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, 0);
3750                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3751         } else {
3752                 uint32_t tmp;
3753
3754                 KASSERT(sc->intr_type != PCI_INTR_TYPE_MSIX,
3755                     ("82575 w/ MSI-X"));
3756                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3757                 tmp |= E1000_CTRL_EXT_IRCA;
3758                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3759         }
3760
3761         /*
3762          * Map TX/RX interrupts to EICR
3763          */
3764         switch (sc->hw.mac.type) {
3765         case e1000_82580:
3766         case e1000_i350:
3767         case e1000_vfadapt:
3768         case e1000_vfadapt_i350:
3769                 /* RX entries */
3770                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3771                         rxr = &sc->rx_rings[i];
3772
3773                         index = i >> 1;
3774                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3775
3776                         if (i & 1) {
3777                                 ivar &= 0xff00ffff;
3778                                 ivar |=
3779                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3780                         } else {
3781                                 ivar &= 0xffffff00;
3782                                 ivar |=
3783                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3784                         }
3785                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3786                 }
3787                 /* TX entries */
3788                 for (i = 0; i < sc->tx_ring_inuse; ++i) {
3789                         txr = &sc->tx_rings[i];
3790
3791                         index = i >> 1;
3792                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3793
3794                         if (i & 1) {
3795                                 ivar &= 0x00ffffff;
3796                                 ivar |=
3797                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3798                         } else {
3799                                 ivar &= 0xffff00ff;
3800                                 ivar |=
3801                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3802                         }
3803                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3804                 }
3805                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3806                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3807                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3808                 }
3809                 break;
3810
3811         case e1000_82576:
3812                 /* RX entries */
3813                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3814                         rxr = &sc->rx_rings[i];
3815
3816                         index = i & 0x7; /* Each IVAR has two entries */
3817                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3818
3819                         if (i < 8) {
3820                                 ivar &= 0xffffff00;
3821                                 ivar |=
3822                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3823                         } else {
3824                                 ivar &= 0xff00ffff;
3825                                 ivar |=
3826                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3827                         }
3828                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3829                 }
3830                 /* TX entries */
3831                 for (i = 0; i < sc->tx_ring_inuse; ++i) {
3832                         txr = &sc->tx_rings[i];
3833
3834                         index = i & 0x7; /* Each IVAR has two entries */
3835                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3836
3837                         if (i < 8) {
3838                                 ivar &= 0xffff00ff;
3839                                 ivar |=
3840                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3841                         } else {
3842                                 ivar &= 0x00ffffff;
3843                                 ivar |=
3844                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3845                         }
3846                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3847                 }
3848                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3849                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3850                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3851                 }
3852                 break;
3853
3854         case e1000_82575:
3855                 /*
3856                  * Enable necessary interrupt bits.
3857                  *
3858                  * The name of the register is confusing; in addition to
3859                  * configuring the first vector of MSI-X, it also configures
3860                  * which bits of EICR could be set by the hardware even when
3861                  * MSI or line interrupt is used; it thus controls interrupt
3862                  * generation.  It MUST be configured explicitly; the default
3863                  * value mentioned in the datasheet is wrong: RX queue0 and
3864                  * TX queue0 are NOT enabled by default.
3865                  */
3866                 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3867                 break;
3868
3869         default:
3870                 panic("unknown mac type %d\n", sc->hw.mac.type);
3871         }
3872 }
3873
3874 static int
3875 igb_setup_intr(struct igb_softc *sc)
3876 {
3877         int error;
3878
3879         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3880                 return igb_msix_setup(sc);
3881
3882         error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
3883             (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_intr_shared : igb_intr,
3884             sc, &sc->intr_tag, &sc->main_serialize);
3885         if (error) {
3886                 device_printf(sc->dev, "Failed to register interrupt handler");
3887                 return error;
3888         }
3889         sc->tx_rings[0].tx_intr_cpuid = rman_get_cpuid(sc->intr_res);
3890
3891         return 0;
3892 }
3893
3894 static void
3895 igb_set_txintr_mask(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
3896 {
3897         if (txr->sc->hw.mac.type == e1000_82575) {
3898                 txr->tx_intr_bit = 0;   /* unused */
3899                 switch (txr->me) {
3900                 case 0:
3901                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3902                         break;
3903                 case 1:
3904                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3905                         break;
3906                 case 2:
3907                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3908                         break;
3909                 case 3:
3910                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3911                         break;
3912                 default:
3913                         panic("unsupported # of TX ring, %d\n", txr->me);
3914                 }
3915         } else {
3916                 int intr_bit = *intr_bit0;
3917
3918                 txr->tx_intr_bit = intr_bit % intr_bitmax;
3919                 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
3920
3921                 *intr_bit0 = intr_bit + 1;
3922         }
3923 }
3924
3925 static void
3926 igb_set_rxintr_mask(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
3927 {
3928         if (rxr->sc->hw.mac.type == e1000_82575) {
3929                 rxr->rx_intr_bit = 0;   /* unused */
3930                 switch (rxr->me) {
3931                 case 0:
3932                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3933                         break;
3934                 case 1:
3935                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3936                         break;
3937                 case 2:
3938                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3939                         break;
3940                 case 3:
3941                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3942                         break;
3943                 default:
3944                         panic("unsupported # of RX ring, %d\n", rxr->me);
3945                 }
3946         } else {
3947                 int intr_bit = *intr_bit0;
3948
3949                 rxr->rx_intr_bit = intr_bit % intr_bitmax;
3950                 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
3951
3952                 *intr_bit0 = intr_bit + 1;
3953         }
3954 }
3955
3956 static void
3957 igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3958 {
3959         struct igb_softc *sc = ifp->if_softc;
3960
3961         ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt,
3962             sc->tx_serialize, sc->rx_serialize, slz);
3963 }
3964
3965 static void
3966 igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3967 {
3968         struct igb_softc *sc = ifp->if_softc;
3969
3970         ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt,
3971             sc->tx_serialize, sc->rx_serialize, slz);
3972 }
3973
3974 static int
3975 igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3976 {
3977         struct igb_softc *sc = ifp->if_softc;
3978
3979         return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
3980             sc->tx_serialize, sc->rx_serialize, slz);
3981 }
3982
3983 #ifdef INVARIANTS
3984
3985 static void
3986 igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3987     boolean_t serialized)
3988 {
3989         struct igb_softc *sc = ifp->if_softc;
3990
3991         ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
3992             sc->tx_serialize, sc->rx_serialize, slz, serialized);
3993 }
3994
3995 #endif  /* INVARIANTS */
3996
3997 static void
3998 igb_set_intr_mask(struct igb_softc *sc)
3999 {
4000         int i;
4001
4002         sc->intr_mask = sc->sts_intr_mask;
4003         for (i = 0; i < sc->rx_ring_inuse; ++i)
4004                 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
4005         for (i = 0; i < sc->tx_ring_inuse; ++i)
4006                 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
4007         if (bootverbose) {
4008                 if_printf(&sc->arpcom.ac_if, "intr mask 0x%08x\n",
4009                     sc->intr_mask);
4010         }
4011 }
4012
4013 static int
4014 igb_alloc_intr(struct igb_softc *sc)
4015 {
4016         int i, intr_bit, intr_bitmax;
4017         u_int intr_flags;
4018
4019         igb_msix_try_alloc(sc);
4020         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
4021                 goto done;
4022
4023         /*
4024          * Allocate MSI/legacy interrupt resource
4025          */
4026         sc->intr_type = pci_alloc_1intr(sc->dev, igb_msi_enable,
4027             &sc->intr_rid, &intr_flags);
4028
4029         if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
4030                 int unshared;
4031
4032                 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
4033                 if (!unshared) {
4034                         sc->flags |= IGB_FLAG_SHARED_INTR;
4035                         if (bootverbose)
4036                                 device_printf(sc->dev, "IRQ shared\n");
4037                 } else {
4038                         intr_flags &= ~RF_SHAREABLE;
4039                         if (bootverbose)
4040                                 device_printf(sc->dev, "IRQ unshared\n");
4041                 }
4042         }
4043
4044         sc->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
4045             &sc->intr_rid, intr_flags);
4046         if (sc->intr_res == NULL) {
4047                 device_printf(sc->dev, "Unable to allocate bus resource: "
4048                     "interrupt\n");
4049                 return ENXIO;
4050         }
4051
4052         /*
4053          * Setup MSI/legacy interrupt mask
4054          */
4055         switch (sc->hw.mac.type) {
4056         case e1000_82575:
4057                 intr_bitmax = IGB_MAX_TXRXINT_82575;
4058                 break;
4059         case e1000_82580:
4060                 intr_bitmax = IGB_MAX_TXRXINT_82580;
4061                 break;
4062         case e1000_i350:
4063                 intr_bitmax = IGB_MAX_TXRXINT_I350;
4064                 break;
4065         case e1000_82576:
4066                 intr_bitmax = IGB_MAX_TXRXINT_82576;
4067                 break;
4068         default:
4069                 intr_bitmax = IGB_MIN_TXRXINT;
4070                 break;
4071         }
4072         intr_bit = 0;
4073         for (i = 0; i < sc->tx_ring_cnt; ++i)
4074                 igb_set_txintr_mask(&sc->tx_rings[i], &intr_bit, intr_bitmax);
4075         for (i = 0; i < sc->rx_ring_cnt; ++i)
4076                 igb_set_rxintr_mask(&sc->rx_rings[i], &intr_bit, intr_bitmax);
4077         sc->sts_intr_bit = 0;
4078         sc->sts_intr_mask = E1000_EICR_OTHER;
4079
4080         /* Initialize interrupt rate */
4081         sc->intr_rate = IGB_INTR_RATE;
4082 done:
4083         igb_set_ring_inuse(sc, FALSE);
4084         igb_set_intr_mask(sc);
4085         return 0;
4086 }
4087
4088 static void
4089 igb_free_intr(struct igb_softc *sc)
4090 {
4091         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
4092                 if (sc->intr_res != NULL) {
4093                         bus_release_resource(sc->dev, SYS_RES_IRQ, sc->intr_rid,
4094                             sc->intr_res);
4095                 }
4096                 if (sc->intr_type == PCI_INTR_TYPE_MSI)
4097                         pci_release_msi(sc->dev);
4098         } else {
4099                 igb_msix_free(sc, TRUE);
4100         }
4101 }
4102
4103 static void
4104 igb_teardown_intr(struct igb_softc *sc)
4105 {
4106         if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4107                 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_tag);
4108         else
4109                 igb_msix_teardown(sc, sc->msix_cnt);
4110 }
4111
4112 static void
4113 igb_msix_try_alloc(struct igb_softc *sc)
4114 {
4115         int msix_enable, msix_cnt, msix_cnt2, alloc_cnt;
4116         int i, x, error;
4117         struct igb_msix_data *msix;
4118         boolean_t aggregate, setup = FALSE;
4119
4120         /*
4121          * Don't enable MSI-X on 82575, see:
4122          * 82575 specification update errata #25
4123          */
4124         if (sc->hw.mac.type == e1000_82575)
4125                 return;
4126
4127         /* Don't enable MSI-X on VF */
4128         if (sc->vf_ifp)
4129                 return;
4130
4131         msix_enable = device_getenv_int(sc->dev, "msix.enable",
4132             igb_msix_enable);
4133         if (!msix_enable)
4134                 return;
4135
4136         msix_cnt = pci_msix_count(sc->dev);
4137 #ifdef IGB_MSIX_DEBUG
4138         msix_cnt = device_getenv_int(sc->dev, "msix.count", msix_cnt);
4139 #endif
4140         if (msix_cnt <= 1) {
4141                 /* One MSI-X model does not make sense */
4142                 return;
4143         }
4144
4145         i = 0;
4146         while ((1 << (i + 1)) <= msix_cnt)
4147                 ++i;
4148         msix_cnt2 = 1 << i;
4149
4150         if (bootverbose) {
4151                 device_printf(sc->dev, "MSI-X count %d/%d\n",
4152                     msix_cnt2, msix_cnt);
4153         }
4154
4155         KKASSERT(msix_cnt2 <= msix_cnt);
4156         if (msix_cnt == msix_cnt2) {
4157                 /* We need at least one MSI-X for link status */
4158                 msix_cnt2 >>= 1;
4159                 if (msix_cnt2 <= 1) {
4160                         /* One MSI-X for RX/TX does not make sense */
4161                         device_printf(sc->dev, "not enough MSI-X for TX/RX, "
4162                             "MSI-X count %d/%d\n", msix_cnt2, msix_cnt);
4163                         return;
4164                 }
4165                 KKASSERT(msix_cnt > msix_cnt2);
4166
4167                 if (bootverbose) {
4168                         device_printf(sc->dev, "MSI-X count fixup %d/%d\n",
4169                             msix_cnt2, msix_cnt);
4170                 }
4171         }
4172
4173         sc->rx_ring_msix = sc->rx_ring_cnt;
4174         if (sc->rx_ring_msix > msix_cnt2)
4175                 sc->rx_ring_msix = msix_cnt2;
4176
4177         sc->tx_ring_msix = sc->tx_ring_cnt;
4178         if (sc->tx_ring_msix > msix_cnt2)
4179                 sc->tx_ring_msix = msix_cnt2;
4180
4181         if (msix_cnt >= sc->tx_ring_msix + sc->rx_ring_msix + 1) {
4182                 /*
4183                  * Independent TX/RX MSI-X
4184                  */
4185                 aggregate = FALSE;
4186                 if (bootverbose)
4187                         device_printf(sc->dev, "independent TX/RX MSI-X\n");
4188                 alloc_cnt = sc->tx_ring_msix + sc->rx_ring_msix;
4189         } else {
4190                 /*
4191                  * Aggregate TX/RX MSI-X
4192                  */
4193                 aggregate = TRUE;
4194                 if (bootverbose)
4195                         device_printf(sc->dev, "aggregate TX/RX MSI-X\n");
4196                 alloc_cnt = msix_cnt2;
4197                 if (alloc_cnt > ncpus2)
4198                         alloc_cnt = ncpus2;
4199                 if (sc->rx_ring_msix > alloc_cnt)
4200                         sc->rx_ring_msix = alloc_cnt;
4201         }
4202         ++alloc_cnt;    /* For link status */
4203
4204         if (bootverbose) {
4205                 device_printf(sc->dev, "MSI-X alloc %d, RX ring %d\n",
4206                     alloc_cnt, sc->rx_ring_msix);
4207         }
4208
4209         sc->msix_mem_rid = PCIR_BAR(IGB_MSIX_BAR);
4210         sc->msix_mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4211             &sc->msix_mem_rid, RF_ACTIVE);
4212         if (sc->msix_mem_res == NULL) {
4213                 device_printf(sc->dev, "Unable to map MSI-X table\n");
4214                 return;
4215         }
4216
4217         sc->msix_cnt = alloc_cnt;
4218         sc->msix_data = kmalloc_cachealign(
4219             sizeof(struct igb_msix_data) * sc->msix_cnt,
4220             M_DEVBUF, M_WAITOK | M_ZERO);
4221         for (x = 0; x < sc->msix_cnt; ++x) {
4222                 msix = &sc->msix_data[x];
4223
4224                 lwkt_serialize_init(&msix->msix_serialize0);
4225                 msix->msix_sc = sc;
4226                 msix->msix_rid = -1;
4227                 msix->msix_vector = x;
4228                 msix->msix_mask = 1 << msix->msix_vector;
4229                 msix->msix_rate = IGB_INTR_RATE;
4230         }
4231
4232         x = 0;
4233         if (!aggregate) {
4234                 int offset, offset_def;
4235
4236                 if (sc->rx_ring_msix == ncpus2) {
4237                         offset = 0;
4238                 } else {
4239                         offset_def = (sc->rx_ring_msix *
4240                             device_get_unit(sc->dev)) % ncpus2;
4241
4242                         offset = device_getenv_int(sc->dev,
4243                             "msix.rxoff", offset_def);
4244                         if (offset >= ncpus2 ||
4245                             offset % sc->rx_ring_msix != 0) {
4246                                 device_printf(sc->dev,
4247                                     "invalid msix.rxoff %d, use %d\n",
4248                                     offset, offset_def);
4249                                 offset = offset_def;
4250                         }
4251                 }
4252
4253                 /* RX rings */
4254                 for (i = 0; i < sc->rx_ring_msix; ++i) {
4255                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
4256
4257                         KKASSERT(x < sc->msix_cnt);
4258                         msix = &sc->msix_data[x++];
4259                         rxr->rx_intr_bit = msix->msix_vector;
4260                         rxr->rx_intr_mask = msix->msix_mask;
4261
4262                         msix->msix_serialize = &rxr->rx_serialize;
4263                         msix->msix_func = igb_msix_rx;
4264                         msix->msix_arg = rxr;
4265                         msix->msix_cpuid = i + offset;
4266                         KKASSERT(msix->msix_cpuid < ncpus2);
4267                         ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
4268                             "%s rx%d", device_get_nameunit(sc->dev), i);
4269                         msix->msix_rate = IGB_MSIX_RX_RATE;
4270                         ksnprintf(msix->msix_rate_desc,
4271                             sizeof(msix->msix_rate_desc),
4272                             "RX%d interrupt rate", i);
4273                 }
4274
4275                 offset_def = device_get_unit(sc->dev) % ncpus2;
4276                 offset = device_getenv_int(sc->dev, "msix.txoff", offset_def);
4277                 if (offset >= ncpus2) {
4278                         device_printf(sc->dev, "invalid msix.txoff %d, "
4279                             "use %d\n", offset, offset_def);
4280                         offset = offset_def;
4281                 }
4282
4283                 /* TX rings */
4284                 for (i = 0; i < sc->tx_ring_msix; ++i) {
4285                         struct igb_tx_ring *txr = &sc->tx_rings[i];
4286
4287                         KKASSERT(x < sc->msix_cnt);
4288                         msix = &sc->msix_data[x++];
4289                         txr->tx_intr_bit = msix->msix_vector;
4290                         txr->tx_intr_mask = msix->msix_mask;
4291
4292                         msix->msix_serialize = &txr->tx_serialize;
4293                         msix->msix_func = igb_msix_tx;
4294                         msix->msix_arg = txr;
4295                         msix->msix_cpuid = i + offset;
4296                         txr->tx_intr_cpuid = msix->msix_cpuid;
4297                         KKASSERT(msix->msix_cpuid < ncpus2);
4298                         ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
4299                             "%s tx%d", device_get_nameunit(sc->dev), i);
4300                         msix->msix_rate = IGB_MSIX_TX_RATE;
4301                         ksnprintf(msix->msix_rate_desc,
4302                             sizeof(msix->msix_rate_desc),
4303                             "TX%d interrupt rate", i);
4304                 }
4305         } else {
4306                 /* TODO */
4307                 error = EOPNOTSUPP;
4308                 goto back;
4309         }
4310
4311         /*
4312          * Link status
4313          */
4314         KKASSERT(x < sc->msix_cnt);
4315         msix = &sc->msix_data[x++];
4316         sc->sts_intr_bit = msix->msix_vector;
4317         sc->sts_intr_mask = msix->msix_mask;
4318
4319         msix->msix_serialize = &sc->main_serialize;
4320         msix->msix_func = igb_msix_status;
4321         msix->msix_arg = sc;
4322         msix->msix_cpuid = 0; /* TODO tunable */
4323         ksnprintf(msix->msix_desc, sizeof(msix->msix_desc), "%s sts",
4324             device_get_nameunit(sc->dev));
4325         ksnprintf(msix->msix_rate_desc, sizeof(msix->msix_rate_desc),
4326             "status interrupt rate");
4327
4328         KKASSERT(x == sc->msix_cnt);
4329
4330         error = pci_setup_msix(sc->dev);
4331         if (error) {
4332                 device_printf(sc->dev, "Setup MSI-X failed\n");
4333                 goto back;
4334         }
4335         setup = TRUE;
4336
4337         for (i = 0; i < sc->msix_cnt; ++i) {
4338                 msix = &sc->msix_data[i];
4339
4340                 error = pci_alloc_msix_vector(sc->dev, msix->msix_vector,
4341                     &msix->msix_rid, msix->msix_cpuid);
4342                 if (error) {
4343                         device_printf(sc->dev,
4344                             "Unable to allocate MSI-X %d on cpu%d\n",
4345                             msix->msix_vector, msix->msix_cpuid);
4346                         goto back;
4347                 }
4348
4349                 msix->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
4350                     &msix->msix_rid, RF_ACTIVE);
4351                 if (msix->msix_res == NULL) {
4352                         device_printf(sc->dev,
4353                             "Unable to allocate MSI-X %d resource\n",
4354                             msix->msix_vector);
4355                         error = ENOMEM;
4356                         goto back;
4357                 }
4358         }
4359
4360         pci_enable_msix(sc->dev);
4361         sc->intr_type = PCI_INTR_TYPE_MSIX;
4362 back:
4363         if (error)
4364                 igb_msix_free(sc, setup);
4365 }
4366
4367 static void
4368 igb_msix_free(struct igb_softc *sc, boolean_t setup)
4369 {
4370         int i;
4371
4372         KKASSERT(sc->msix_cnt > 1);
4373
4374         for (i = 0; i < sc->msix_cnt; ++i) {
4375                 struct igb_msix_data *msix = &sc->msix_data[i];
4376
4377                 if (msix->msix_res != NULL) {
4378                         bus_release_resource(sc->dev, SYS_RES_IRQ,
4379                             msix->msix_rid, msix->msix_res);
4380                 }
4381                 if (msix->msix_rid >= 0)
4382                         pci_release_msix_vector(sc->dev, msix->msix_rid);
4383         }
4384         if (setup)
4385                 pci_teardown_msix(sc->dev);
4386
4387         sc->msix_cnt = 0;
4388         kfree(sc->msix_data, M_DEVBUF);
4389         sc->msix_data = NULL;
4390 }
4391
4392 static int
4393 igb_msix_setup(struct igb_softc *sc)
4394 {
4395         int i;
4396
4397         for (i = 0; i < sc->msix_cnt; ++i) {
4398                 struct igb_msix_data *msix = &sc->msix_data[i];
4399                 int error;
4400
4401                 error = bus_setup_intr_descr(sc->dev, msix->msix_res,
4402                     INTR_MPSAFE, msix->msix_func, msix->msix_arg,
4403                     &msix->msix_handle, msix->msix_serialize, msix->msix_desc);
4404                 if (error) {
4405                         device_printf(sc->dev, "could not set up %s "
4406                             "interrupt handler.\n", msix->msix_desc);
4407                         igb_msix_teardown(sc, i);
4408                         return error;
4409                 }
4410         }
4411         return 0;
4412 }
4413
4414 static void
4415 igb_msix_teardown(struct igb_softc *sc, int msix_cnt)
4416 {
4417         int i;
4418
4419         for (i = 0; i < msix_cnt; ++i) {
4420                 struct igb_msix_data *msix = &sc->msix_data[i];
4421
4422                 bus_teardown_intr(sc->dev, msix->msix_res, msix->msix_handle);
4423         }
4424 }
4425
4426 static void
4427 igb_msix_rx(void *arg)
4428 {
4429         struct igb_rx_ring *rxr = arg;
4430
4431         ASSERT_SERIALIZED(&rxr->rx_serialize);
4432         igb_rxeof(rxr, -1);
4433
4434         E1000_WRITE_REG(&rxr->sc->hw, E1000_EIMS, rxr->rx_intr_mask);
4435 }
4436
4437 static void
4438 igb_msix_tx(void *arg)
4439 {
4440         struct igb_tx_ring *txr = arg;
4441
4442         ASSERT_SERIALIZED(&txr->tx_serialize);
4443
4444         igb_txeof(txr);
4445         if (!ifsq_is_empty(txr->ifsq))
4446                 ifsq_devstart(txr->ifsq);
4447
4448         E1000_WRITE_REG(&txr->sc->hw, E1000_EIMS, txr->tx_intr_mask);
4449 }
4450
4451 static void
4452 igb_msix_status(void *arg)
4453 {
4454         struct igb_softc *sc = arg;
4455         uint32_t icr;
4456
4457         ASSERT_SERIALIZED(&sc->main_serialize);
4458
4459         icr = E1000_READ_REG(&sc->hw, E1000_ICR);
4460         if (icr & E1000_ICR_LSC) {
4461                 sc->hw.mac.get_link_status = 1;
4462                 igb_update_link_status(sc);
4463         }
4464
4465         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->sts_intr_mask);
4466 }
4467
4468 static void
4469 igb_set_ring_inuse(struct igb_softc *sc, boolean_t polling)
4470 {
4471         sc->rx_ring_inuse = igb_get_rxring_inuse(sc, polling);
4472         sc->tx_ring_inuse = igb_get_txring_inuse(sc, polling);
4473         if (bootverbose) {
4474                 if_printf(&sc->arpcom.ac_if, "RX rings %d/%d, TX rings %d/%d\n",
4475                     sc->rx_ring_inuse, sc->rx_ring_cnt,
4476                     sc->tx_ring_inuse, sc->tx_ring_cnt);
4477         }
4478 }
4479
4480 static int
4481 igb_get_rxring_inuse(const struct igb_softc *sc, boolean_t polling)
4482 {
4483         if (!IGB_ENABLE_HWRSS(sc))
4484                 return 1;
4485
4486         if (polling)
4487                 return sc->rx_ring_cnt;
4488         else if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4489                 return IGB_MIN_RING_RSS;
4490         else
4491                 return sc->rx_ring_msix;
4492 }
4493
4494 static int
4495 igb_get_txring_inuse(const struct igb_softc *sc, boolean_t polling)
4496 {
4497         if (!IGB_ENABLE_HWTSS(sc))
4498                 return 1;
4499
4500         if (polling)
4501                 return sc->tx_ring_cnt;
4502         else if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4503                 return IGB_MIN_RING;
4504         else
4505                 return sc->tx_ring_msix;
4506 }
4507
4508 static int
4509 igb_tso_pullup(struct igb_tx_ring *txr, struct mbuf **mp)
4510 {
4511         int hoff, iphlen, thoff;
4512         struct mbuf *m;
4513
4514         m = *mp;
4515         KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4516
4517         iphlen = m->m_pkthdr.csum_iphlen;
4518         thoff = m->m_pkthdr.csum_thlen;
4519         hoff = m->m_pkthdr.csum_lhlen;
4520
4521         KASSERT(iphlen > 0, ("invalid ip hlen"));
4522         KASSERT(thoff > 0, ("invalid tcp hlen"));
4523         KASSERT(hoff > 0, ("invalid ether hlen"));
4524
4525         if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
4526                 m = m_pullup(m, hoff + iphlen + thoff);
4527                 if (m == NULL) {
4528                         *mp = NULL;
4529                         return ENOBUFS;
4530                 }
4531                 *mp = m;
4532         }
4533         if (txr->tx_flags & IGB_TXFLAG_TSO_IPLEN0) {
4534                 struct ip *ip;
4535
4536                 ip = mtodoff(m, struct ip *, hoff);
4537                 ip->ip_len = 0;
4538         }
4539
4540         return 0;
4541 }
4542
4543 static void
4544 igb_tso_ctx(struct igb_tx_ring *txr, struct mbuf *m, uint32_t *hlen)
4545 {
4546         struct e1000_adv_tx_context_desc *TXD;
4547         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
4548         int hoff, ctxd, iphlen, thoff;
4549
4550         iphlen = m->m_pkthdr.csum_iphlen;
4551         thoff = m->m_pkthdr.csum_thlen;
4552         hoff = m->m_pkthdr.csum_lhlen;
4553
4554         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
4555
4556         ctxd = txr->next_avail_desc;
4557         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
4558
4559         if (m->m_flags & M_VLANTAG) {
4560                 uint16_t vlantag;
4561
4562                 vlantag = htole16(m->m_pkthdr.ether_vlantag);
4563                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
4564         }
4565
4566         vlan_macip_lens |= (hoff << E1000_ADVTXD_MACLEN_SHIFT);
4567         vlan_macip_lens |= iphlen;
4568
4569         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4570         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
4571         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
4572
4573         mss_l4len_idx |= (m->m_pkthdr.tso_segsz << E1000_ADVTXD_MSS_SHIFT);
4574         mss_l4len_idx |= (thoff << E1000_ADVTXD_L4LEN_SHIFT);
4575         /* 82575 needs the queue index added */
4576         if (txr->sc->hw.mac.type == e1000_82575)
4577                 mss_l4len_idx |= txr->me << 4;
4578
4579         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
4580         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
4581         TXD->seqnum_seed = htole32(0);
4582         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
4583
4584         /* We've consumed the first desc, adjust counters */
4585         if (++ctxd == txr->num_tx_desc)
4586                 ctxd = 0;
4587         txr->next_avail_desc = ctxd;
4588         --txr->tx_avail;
4589
4590         *hlen = hoff + iphlen + thoff;
4591 }