2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 * $FreeBSD: head/sys/dev/drm2/radeon/rs690.c 254885 2013-08-25 19:37:15Z dumbbell $
33 #include "radeon_asic.h"
37 int rs690_mc_wait_for_idle(struct radeon_device *rdev)
42 for (i = 0; i < rdev->usec_timeout; i++) {
44 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
45 if (G_000090_MC_SYSTEM_IDLE(tmp))
52 static void rs690_gpu_init(struct radeon_device *rdev)
54 /* FIXME: is this correct ? */
55 r420_pipes_init(rdev);
56 if (rs690_mc_wait_for_idle(rdev)) {
57 DRM_ERROR("Failed to wait MC idle while "
58 "programming pipes. Bad things might happen.\n");
63 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
64 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
67 void rs690_pm_info(struct radeon_device *rdev)
69 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
75 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
76 &frev, &crev, &data_offset)) {
77 info = (union igp_info *)((uintptr_t)rdev->mode_info.atom_context->bios + data_offset);
79 /* Get various system informations from bios */
82 tmp.full = dfixed_const(100);
83 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock));
84 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
85 if (le16_to_cpu(info->info.usK8MemoryClock))
86 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
87 else if (rdev->clock.default_mclk) {
88 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
89 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
91 rdev->pm.igp_system_mclk.full = dfixed_const(400);
92 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
93 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
96 tmp.full = dfixed_const(100);
97 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock));
98 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
99 if (le32_to_cpu(info->info_v2.ulBootUpUMAClock))
100 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock));
101 else if (rdev->clock.default_mclk)
102 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
104 rdev->pm.igp_system_mclk.full = dfixed_const(66700);
105 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
106 rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq));
107 rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
108 rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
111 /* We assume the slower possible clock ie worst case */
112 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
113 rdev->pm.igp_system_mclk.full = dfixed_const(200);
114 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
115 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
116 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
120 /* We assume the slower possible clock ie worst case */
121 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
122 rdev->pm.igp_system_mclk.full = dfixed_const(200);
123 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
124 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
125 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
127 /* Compute various bandwidth */
128 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */
129 tmp.full = dfixed_const(4);
130 rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
131 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
132 * = ht_clk * ht_width / 5
134 tmp.full = dfixed_const(5);
135 rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
136 rdev->pm.igp_ht_link_width);
137 rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
138 if (tmp.full < rdev->pm.max_bandwidth.full) {
139 /* HT link is a limiting factor */
140 rdev->pm.max_bandwidth.full = tmp.full;
142 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
143 * = (sideport_clk * 14) / 10
145 tmp.full = dfixed_const(14);
146 rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
147 tmp.full = dfixed_const(10);
148 rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
151 static void rs690_mc_init(struct radeon_device *rdev)
155 rs400_gart_adjust_size(rdev);
156 rdev->mc.vram_is_ddr = true;
157 rdev->mc.vram_width = 128;
158 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
159 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
160 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
161 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
162 rdev->mc.visible_vram_size = rdev->mc.aper_size;
163 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
164 base = G_000100_MC_FB_START(base) << 16;
165 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
167 radeon_vram_location(rdev, &rdev->mc, base);
168 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
169 radeon_gtt_location(rdev, &rdev->mc);
170 radeon_update_bandwidth_info(rdev);
173 void rs690_line_buffer_adjust(struct radeon_device *rdev,
174 struct drm_display_mode *mode1,
175 struct drm_display_mode *mode2)
181 * There is a single line buffer shared by both display controllers.
182 * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
183 * the display controllers. The paritioning can either be done
184 * manually or via one of four preset allocations specified in bits 1:0:
185 * 0 - line buffer is divided in half and shared between crtc
186 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
187 * 2 - D1 gets the whole buffer
188 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
189 * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
190 * allocation mode. In manual allocation mode, D1 always starts at 0,
191 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
193 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
194 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
196 if (mode1 && mode2) {
197 if (mode1->hdisplay > mode2->hdisplay) {
198 if (mode1->hdisplay > 2560)
199 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
201 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
202 } else if (mode2->hdisplay > mode1->hdisplay) {
203 if (mode2->hdisplay > 2560)
204 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
206 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
208 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
210 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
212 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
214 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
217 struct rs690_watermark {
218 u32 lb_request_fifo_depth;
219 fixed20_12 num_line_pair;
220 fixed20_12 estimated_width;
221 fixed20_12 worst_case_latency;
222 fixed20_12 consumption_rate;
223 fixed20_12 active_time;
225 fixed20_12 priority_mark_max;
226 fixed20_12 priority_mark;
230 static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
231 struct radeon_crtc *crtc,
232 struct rs690_watermark *wm)
234 struct drm_display_mode *mode = &crtc->base.mode;
236 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
237 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
239 if (!crtc->base.enabled) {
240 /* FIXME: wouldn't it better to set priority mark to maximum */
241 wm->lb_request_fifo_depth = 4;
245 if (crtc->vsc.full > dfixed_const(2))
246 wm->num_line_pair.full = dfixed_const(2);
248 wm->num_line_pair.full = dfixed_const(1);
250 b.full = dfixed_const(mode->crtc_hdisplay);
251 c.full = dfixed_const(256);
252 a.full = dfixed_div(b, c);
253 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
254 request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
255 if (a.full < dfixed_const(4)) {
256 wm->lb_request_fifo_depth = 4;
258 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
261 /* Determine consumption rate
262 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
263 * vtaps = number of vertical taps,
264 * vsc = vertical scaling ratio, defined as source/destination
265 * hsc = horizontal scaling ration, defined as source/destination
267 a.full = dfixed_const(mode->clock);
268 b.full = dfixed_const(1000);
269 a.full = dfixed_div(a, b);
270 pclk.full = dfixed_div(b, a);
271 if (crtc->rmx_type != RMX_OFF) {
272 b.full = dfixed_const(2);
273 if (crtc->vsc.full > b.full)
274 b.full = crtc->vsc.full;
275 b.full = dfixed_mul(b, crtc->hsc);
276 c.full = dfixed_const(2);
277 b.full = dfixed_div(b, c);
278 consumption_time.full = dfixed_div(pclk, b);
280 consumption_time.full = pclk.full;
282 a.full = dfixed_const(1);
283 wm->consumption_rate.full = dfixed_div(a, consumption_time);
286 /* Determine line time
287 * LineTime = total time for one line of displayhtotal
288 * LineTime = total number of horizontal pixels
289 * pclk = pixel clock period(ns)
291 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
292 line_time.full = dfixed_mul(a, pclk);
294 /* Determine active time
295 * ActiveTime = time of active region of display within one line,
296 * hactive = total number of horizontal active pixels
297 * htotal = total number of horizontal pixels
299 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
300 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
301 wm->active_time.full = dfixed_mul(line_time, b);
302 wm->active_time.full = dfixed_div(wm->active_time, a);
304 /* Maximun bandwidth is the minimun bandwidth of all component */
305 rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
306 if (rdev->mc.igp_sideport_enabled) {
307 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
308 rdev->pm.sideport_bandwidth.full)
309 rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
311 read_delay_latency.full = dfixed_const(370 * 800 * 1000);
312 #endif /* DUMBBELL_WIP */
313 read_delay_latency.full = UINT_MAX;
314 read_delay_latency.full = dfixed_div(read_delay_latency,
315 rdev->pm.igp_sideport_mclk);
317 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
318 rdev->pm.k8_bandwidth.full)
319 rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
320 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
321 rdev->pm.ht_bandwidth.full)
322 rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
323 read_delay_latency.full = dfixed_const(5000);
326 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
327 a.full = dfixed_const(16);
328 rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a);
329 a.full = dfixed_const(1000);
330 rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk);
331 /* Determine chunk time
332 * ChunkTime = the time it takes the DCP to send one chunk of data
333 * to the LB which consists of pipeline delay and inter chunk gap
334 * sclk = system clock(ns)
336 a.full = dfixed_const(256 * 13);
337 chunk_time.full = dfixed_mul(rdev->pm.sclk, a);
338 a.full = dfixed_const(10);
339 chunk_time.full = dfixed_div(chunk_time, a);
341 /* Determine the worst case latency
342 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
343 * WorstCaseLatency = worst case time from urgent to when the MC starts
345 * READ_DELAY_IDLE_MAX = constant of 1us
346 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
347 * which consists of pipeline delay and inter chunk gap
349 if (dfixed_trunc(wm->num_line_pair) > 1) {
350 a.full = dfixed_const(3);
351 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
352 wm->worst_case_latency.full += read_delay_latency.full;
354 a.full = dfixed_const(2);
355 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
356 wm->worst_case_latency.full += read_delay_latency.full;
359 /* Determine the tolerable latency
360 * TolerableLatency = Any given request has only 1 line time
361 * for the data to be returned
362 * LBRequestFifoDepth = Number of chunk requests the LB can
363 * put into the request FIFO for a display
364 * LineTime = total time for one line of display
365 * ChunkTime = the time it takes the DCP to send one chunk
366 * of data to the LB which consists of
367 * pipeline delay and inter chunk gap
369 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
370 tolerable_latency.full = line_time.full;
372 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
373 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
374 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
375 tolerable_latency.full = line_time.full - tolerable_latency.full;
377 /* We assume worst case 32bits (4 bytes) */
378 wm->dbpp.full = dfixed_const(4 * 8);
380 /* Determine the maximum priority mark
381 * width = viewport width in pixels
383 a.full = dfixed_const(16);
384 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
385 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
386 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
388 /* Determine estimated width */
389 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
390 estimated_width.full = dfixed_div(estimated_width, consumption_time);
391 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
392 wm->priority_mark.full = dfixed_const(10);
394 a.full = dfixed_const(16);
395 wm->priority_mark.full = dfixed_div(estimated_width, a);
396 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
397 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
401 void rs690_bandwidth_update(struct radeon_device *rdev)
403 struct drm_display_mode *mode0 = NULL;
404 struct drm_display_mode *mode1 = NULL;
405 struct rs690_watermark wm0;
406 struct rs690_watermark wm1;
408 u32 d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
409 u32 d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
410 fixed20_12 priority_mark02, priority_mark12, fill_rate;
413 radeon_update_display_priority(rdev);
415 if (rdev->mode_info.crtcs[0]->base.enabled)
416 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
417 if (rdev->mode_info.crtcs[1]->base.enabled)
418 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
420 * Set display0/1 priority up in the memory controller for
421 * modes if the user specifies HIGH for displaypriority
424 if ((rdev->disp_priority == 2) &&
425 ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
426 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
427 tmp &= C_000104_MC_DISP0R_INIT_LAT;
428 tmp &= C_000104_MC_DISP1R_INIT_LAT;
430 tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
432 tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
433 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
435 rs690_line_buffer_adjust(rdev, mode0, mode1);
437 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
438 WREG32(R_006C9C_DCP_CONTROL, 0);
439 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
440 WREG32(R_006C9C_DCP_CONTROL, 2);
442 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
443 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
445 tmp = (wm0.lb_request_fifo_depth - 1);
446 tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
447 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
449 if (mode0 && mode1) {
450 if (dfixed_trunc(wm0.dbpp) > 64)
451 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
453 a.full = wm0.num_line_pair.full;
454 if (dfixed_trunc(wm1.dbpp) > 64)
455 b.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
457 b.full = wm1.num_line_pair.full;
459 fill_rate.full = dfixed_div(wm0.sclk, a);
460 if (wm0.consumption_rate.full > fill_rate.full) {
461 b.full = wm0.consumption_rate.full - fill_rate.full;
462 b.full = dfixed_mul(b, wm0.active_time);
463 a.full = dfixed_mul(wm0.worst_case_latency,
464 wm0.consumption_rate);
465 a.full = a.full + b.full;
466 b.full = dfixed_const(16 * 1000);
467 priority_mark02.full = dfixed_div(a, b);
469 a.full = dfixed_mul(wm0.worst_case_latency,
470 wm0.consumption_rate);
471 b.full = dfixed_const(16 * 1000);
472 priority_mark02.full = dfixed_div(a, b);
474 if (wm1.consumption_rate.full > fill_rate.full) {
475 b.full = wm1.consumption_rate.full - fill_rate.full;
476 b.full = dfixed_mul(b, wm1.active_time);
477 a.full = dfixed_mul(wm1.worst_case_latency,
478 wm1.consumption_rate);
479 a.full = a.full + b.full;
480 b.full = dfixed_const(16 * 1000);
481 priority_mark12.full = dfixed_div(a, b);
483 a.full = dfixed_mul(wm1.worst_case_latency,
484 wm1.consumption_rate);
485 b.full = dfixed_const(16 * 1000);
486 priority_mark12.full = dfixed_div(a, b);
488 if (wm0.priority_mark.full > priority_mark02.full)
489 priority_mark02.full = wm0.priority_mark.full;
490 if (dfixed_trunc(priority_mark02) < 0)
491 priority_mark02.full = 0;
492 if (wm0.priority_mark_max.full > priority_mark02.full)
493 priority_mark02.full = wm0.priority_mark_max.full;
494 if (wm1.priority_mark.full > priority_mark12.full)
495 priority_mark12.full = wm1.priority_mark.full;
496 if (dfixed_trunc(priority_mark12) < 0)
497 priority_mark12.full = 0;
498 if (wm1.priority_mark_max.full > priority_mark12.full)
499 priority_mark12.full = wm1.priority_mark_max.full;
500 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
501 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
502 if (rdev->disp_priority == 2) {
503 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
504 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
507 if (dfixed_trunc(wm0.dbpp) > 64)
508 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
510 a.full = wm0.num_line_pair.full;
511 fill_rate.full = dfixed_div(wm0.sclk, a);
512 if (wm0.consumption_rate.full > fill_rate.full) {
513 b.full = wm0.consumption_rate.full - fill_rate.full;
514 b.full = dfixed_mul(b, wm0.active_time);
515 a.full = dfixed_mul(wm0.worst_case_latency,
516 wm0.consumption_rate);
517 a.full = a.full + b.full;
518 b.full = dfixed_const(16 * 1000);
519 priority_mark02.full = dfixed_div(a, b);
521 a.full = dfixed_mul(wm0.worst_case_latency,
522 wm0.consumption_rate);
523 b.full = dfixed_const(16 * 1000);
524 priority_mark02.full = dfixed_div(a, b);
526 if (wm0.priority_mark.full > priority_mark02.full)
527 priority_mark02.full = wm0.priority_mark.full;
528 if (dfixed_trunc(priority_mark02) < 0)
529 priority_mark02.full = 0;
530 if (wm0.priority_mark_max.full > priority_mark02.full)
531 priority_mark02.full = wm0.priority_mark_max.full;
532 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
533 if (rdev->disp_priority == 2)
534 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
536 if (dfixed_trunc(wm1.dbpp) > 64)
537 a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
539 a.full = wm1.num_line_pair.full;
540 fill_rate.full = dfixed_div(wm1.sclk, a);
541 if (wm1.consumption_rate.full > fill_rate.full) {
542 b.full = wm1.consumption_rate.full - fill_rate.full;
543 b.full = dfixed_mul(b, wm1.active_time);
544 a.full = dfixed_mul(wm1.worst_case_latency,
545 wm1.consumption_rate);
546 a.full = a.full + b.full;
547 b.full = dfixed_const(16 * 1000);
548 priority_mark12.full = dfixed_div(a, b);
550 a.full = dfixed_mul(wm1.worst_case_latency,
551 wm1.consumption_rate);
552 b.full = dfixed_const(16 * 1000);
553 priority_mark12.full = dfixed_div(a, b);
555 if (wm1.priority_mark.full > priority_mark12.full)
556 priority_mark12.full = wm1.priority_mark.full;
557 if (dfixed_trunc(priority_mark12) < 0)
558 priority_mark12.full = 0;
559 if (wm1.priority_mark_max.full > priority_mark12.full)
560 priority_mark12.full = wm1.priority_mark_max.full;
561 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
562 if (rdev->disp_priority == 2)
563 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
566 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
567 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
568 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
569 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
572 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
576 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
577 r = RREG32(R_00007C_MC_DATA);
578 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
582 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
584 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
585 S_000078_MC_IND_WR_EN(1));
586 WREG32(R_00007C_MC_DATA, v);
587 WREG32(R_000078_MC_INDEX, 0x7F);
590 static void rs690_mc_program(struct radeon_device *rdev)
592 struct rv515_mc_save save;
594 /* Stops all mc clients */
595 rv515_mc_stop(rdev, &save);
597 /* Wait for mc idle */
598 if (rs690_mc_wait_for_idle(rdev))
599 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
600 /* Program MC, should be a 32bits limited address space */
601 WREG32_MC(R_000100_MCCFG_FB_LOCATION,
602 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
603 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
604 WREG32(R_000134_HDP_FB_LOCATION,
605 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
607 rv515_mc_resume(rdev, &save);
610 static int rs690_startup(struct radeon_device *rdev)
614 rs690_mc_program(rdev);
616 rv515_clock_startup(rdev);
617 /* Initialize GPU configuration (# pipes, ...) */
618 rs690_gpu_init(rdev);
619 /* Initialize GART (initialize after TTM so we can allocate
620 * memory through TTM but finalize after TTM) */
621 r = rs400_gart_enable(rdev);
625 /* allocate wb buffer */
626 r = radeon_wb_init(rdev);
630 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
632 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
638 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
640 r = r100_cp_init(rdev, 1024 * 1024);
642 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
646 r = radeon_ib_pool_init(rdev);
648 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
652 r = r600_audio_init(rdev);
654 dev_err(rdev->dev, "failed initializing audio\n");
661 int rs690_resume(struct radeon_device *rdev)
665 /* Make sur GART are not working */
666 rs400_gart_disable(rdev);
667 /* Resume clock before doing reset */
668 rv515_clock_startup(rdev);
669 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
670 if (radeon_asic_reset(rdev)) {
671 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
672 RREG32(R_000E40_RBBM_STATUS),
673 RREG32(R_0007C0_CP_STAT));
676 atom_asic_init(rdev->mode_info.atom_context);
677 /* Resume clock after posting */
678 rv515_clock_startup(rdev);
679 /* Initialize surface registers */
680 radeon_surface_init(rdev);
682 rdev->accel_working = true;
683 r = rs690_startup(rdev);
685 rdev->accel_working = false;
690 int rs690_suspend(struct radeon_device *rdev)
692 r600_audio_fini(rdev);
693 r100_cp_disable(rdev);
694 radeon_wb_disable(rdev);
695 rs600_irq_disable(rdev);
696 rs400_gart_disable(rdev);
700 void rs690_fini(struct radeon_device *rdev)
702 r600_audio_fini(rdev);
704 radeon_wb_fini(rdev);
705 radeon_ib_pool_fini(rdev);
706 radeon_gem_fini(rdev);
707 rs400_gart_fini(rdev);
708 radeon_irq_kms_fini(rdev);
709 radeon_fence_driver_fini(rdev);
710 radeon_bo_fini(rdev);
711 radeon_atombios_fini(rdev);
712 drm_free(rdev->bios, DRM_MEM_DRIVER);
716 int rs690_init(struct radeon_device *rdev)
721 rv515_vga_render_disable(rdev);
722 /* Initialize scratch registers */
723 radeon_scratch_init(rdev);
724 /* Initialize surface registers */
725 radeon_surface_init(rdev);
726 /* restore some register to sane defaults */
727 r100_restore_sanity(rdev);
728 /* TODO: disable VGA need to use VGA request */
730 if (!radeon_get_bios(rdev)) {
731 if (ASIC_IS_AVIVO(rdev))
734 if (rdev->is_atom_bios) {
735 r = radeon_atombios_init(rdev);
739 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
742 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
743 if (radeon_asic_reset(rdev)) {
745 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
746 RREG32(R_000E40_RBBM_STATUS),
747 RREG32(R_0007C0_CP_STAT));
749 /* check if cards are posted or not */
750 if (radeon_boot_test_post_card(rdev) == false)
753 /* Initialize clocks */
754 radeon_get_clock_info(rdev->ddev);
755 /* initialize memory controller */
759 r = radeon_fence_driver_init(rdev);
762 r = radeon_irq_kms_init(rdev);
766 r = radeon_bo_init(rdev);
769 r = rs400_gart_init(rdev);
772 rs600_set_safe_registers(rdev);
774 rdev->accel_working = true;
775 r = rs690_startup(rdev);
777 /* Somethings want wront with the accel init stop accel */
778 dev_err(rdev->dev, "Disabling GPU acceleration\n");
780 radeon_wb_fini(rdev);
781 radeon_ib_pool_fini(rdev);
782 rs400_gart_fini(rdev);
783 radeon_irq_kms_fini(rdev);
784 rdev->accel_working = false;