1 @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001,
2 @c 2002, 2003, 2004 Free Software Foundation, Inc.
3 @c This is part of the GCC manual.
4 @c For copying conditions, see the file gcc.texi.
8 @chapter Machine Descriptions
9 @cindex machine descriptions
11 A machine description has two parts: a file of instruction patterns
12 (@file{.md} file) and a C header file of macro definitions.
14 The @file{.md} file for a target machine contains a pattern for each
15 instruction that the target machine supports (or at least each instruction
16 that is worth telling the compiler about). It may also contain comments.
17 A semicolon causes the rest of the line to be a comment, unless the semicolon
18 is inside a quoted string.
20 See the next chapter for information on the C header file.
23 * Overview:: How the machine description is used.
24 * Patterns:: How to write instruction patterns.
25 * Example:: An explained example of a @code{define_insn} pattern.
26 * RTL Template:: The RTL template defines what insns match a pattern.
27 * Output Template:: The output template says how to make assembler code
29 * Output Statement:: For more generality, write C code to output
31 * Constraints:: When not all operands are general operands.
32 * Standard Names:: Names mark patterns to use for code generation.
33 * Pattern Ordering:: When the order of patterns makes a difference.
34 * Dependent Patterns:: Having one pattern may make you need another.
35 * Jump Patterns:: Special considerations for patterns for jump insns.
36 * Looping Patterns:: How to define patterns for special looping insns.
37 * Insn Canonicalizations::Canonicalization of Instructions
38 * Expander Definitions::Generating a sequence of several RTL insns
39 for a standard operation.
40 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
41 * Including Patterns:: Including Patterns in Machine Descriptions.
42 * Peephole Definitions::Defining machine-specific peephole optimizations.
43 * Insn Attributes:: Specifying the value of attributes for generated insns.
44 * Conditional Execution::Generating @code{define_insn} patterns for
46 * Constant Definitions::Defining symbolic constants that can be used in the
51 @section Overview of How the Machine Description is Used
53 There are three main conversions that happen in the compiler:
58 The front end reads the source code and builds a parse tree.
61 The parse tree is used to generate an RTL insn list based on named
65 The insn list is matched against the RTL templates to produce assembler
70 For the generate pass, only the names of the insns matter, from either a
71 named @code{define_insn} or a @code{define_expand}. The compiler will
72 choose the pattern with the right name and apply the operands according
73 to the documentation later in this chapter, without regard for the RTL
74 template or operand constraints. Note that the names the compiler looks
75 for are hard-coded in the compiler---it will ignore unnamed patterns and
76 patterns with names it doesn't know about, but if you don't provide a
77 named pattern it needs, it will abort.
79 If a @code{define_insn} is used, the template given is inserted into the
80 insn list. If a @code{define_expand} is used, one of three things
81 happens, based on the condition logic. The condition logic may manually
82 create new insns for the insn list, say via @code{emit_insn()}, and
83 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
84 compiler to use an alternate way of performing that task. If it invokes
85 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
86 is inserted, as if the @code{define_expand} were a @code{define_insn}.
88 Once the insn list is generated, various optimization passes convert,
89 replace, and rearrange the insns in the insn list. This is where the
90 @code{define_split} and @code{define_peephole} patterns get used, for
93 Finally, the insn list's RTL is matched up with the RTL templates in the
94 @code{define_insn} patterns, and those patterns are used to emit the
95 final assembly code. For this purpose, each named @code{define_insn}
96 acts like it's unnamed, since the names are ignored.
99 @section Everything about Instruction Patterns
101 @cindex instruction patterns
104 Each instruction pattern contains an incomplete RTL expression, with pieces
105 to be filled in later, operand constraints that restrict how the pieces can
106 be filled in, and an output pattern or C code to generate the assembler
107 output, all wrapped up in a @code{define_insn} expression.
109 A @code{define_insn} is an RTL expression containing four or five operands:
113 An optional name. The presence of a name indicate that this instruction
114 pattern can perform a certain standard job for the RTL-generation
115 pass of the compiler. This pass knows certain names and will use
116 the instruction patterns with those names, if the names are defined
117 in the machine description.
119 The absence of a name is indicated by writing an empty string
120 where the name should go. Nameless instruction patterns are never
121 used for generating RTL code, but they may permit several simpler insns
122 to be combined later on.
124 Names that are not thus known and used in RTL-generation have no
125 effect; they are equivalent to no name at all.
127 For the purpose of debugging the compiler, you may also specify a
128 name beginning with the @samp{*} character. Such a name is used only
129 for identifying the instruction in RTL dumps; it is entirely equivalent
130 to having a nameless pattern for all other purposes.
133 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
134 RTL expressions which show what the instruction should look like. It is
135 incomplete because it may contain @code{match_operand},
136 @code{match_operator}, and @code{match_dup} expressions that stand for
137 operands of the instruction.
139 If the vector has only one element, that element is the template for the
140 instruction pattern. If the vector has multiple elements, then the
141 instruction pattern is a @code{parallel} expression containing the
145 @cindex pattern conditions
146 @cindex conditions, in patterns
147 A condition. This is a string which contains a C expression that is
148 the final test to decide whether an insn body matches this pattern.
150 @cindex named patterns and conditions
151 For a named pattern, the condition (if present) may not depend on
152 the data in the insn being matched, but only the target-machine-type
153 flags. The compiler needs to test these conditions during
154 initialization in order to learn exactly which named instructions are
155 available in a particular run.
158 For nameless patterns, the condition is applied only when matching an
159 individual insn, and only after the insn has matched the pattern's
160 recognition template. The insn's operands may be found in the vector
161 @code{operands}. For an insn where the condition has once matched, it
162 can't be used to control register allocation, for example by excluding
163 certain hard registers or hard register combinations.
166 The @dfn{output template}: a string that says how to output matching
167 insns as assembler code. @samp{%} in this string specifies where
168 to substitute the value of an operand. @xref{Output Template}.
170 When simple substitution isn't general enough, you can specify a piece
171 of C code to compute the output. @xref{Output Statement}.
174 Optionally, a vector containing the values of attributes for insns matching
175 this pattern. @xref{Insn Attributes}.
179 @section Example of @code{define_insn}
180 @cindex @code{define_insn} example
182 Here is an actual example of an instruction pattern, for the 68000/68020.
187 (match_operand:SI 0 "general_operand" "rm"))]
191 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
193 return \"cmpl #0,%0\";
198 This can also be written using braced strings:
203 (match_operand:SI 0 "general_operand" "rm"))]
206 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
212 This is an instruction that sets the condition codes based on the value of
213 a general operand. It has no condition, so any insn whose RTL description
214 has the form shown may be handled according to this pattern. The name
215 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
216 pass that, when it is necessary to test such a value, an insn to do so
217 can be constructed using this pattern.
219 The output control string is a piece of C code which chooses which
220 output template to return based on the kind of operand and the specific
221 type of CPU for which code is being generated.
223 @samp{"rm"} is an operand constraint. Its meaning is explained below.
226 @section RTL Template
227 @cindex RTL insn template
228 @cindex generating insns
229 @cindex insns, generating
230 @cindex recognizing insns
231 @cindex insns, recognizing
233 The RTL template is used to define which insns match the particular pattern
234 and how to find their operands. For named patterns, the RTL template also
235 says how to construct an insn from specified operands.
237 Construction involves substituting specified operands into a copy of the
238 template. Matching involves determining the values that serve as the
239 operands in the insn being matched. Both of these activities are
240 controlled by special expression types that direct matching and
241 substitution of the operands.
244 @findex match_operand
245 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
246 This expression is a placeholder for operand number @var{n} of
247 the insn. When constructing an insn, operand number @var{n}
248 will be substituted at this point. When matching an insn, whatever
249 appears at this position in the insn will be taken as operand
250 number @var{n}; but it must satisfy @var{predicate} or this instruction
251 pattern will not match at all.
253 Operand numbers must be chosen consecutively counting from zero in
254 each instruction pattern. There may be only one @code{match_operand}
255 expression in the pattern for each operand number. Usually operands
256 are numbered in the order of appearance in @code{match_operand}
257 expressions. In the case of a @code{define_expand}, any operand numbers
258 used only in @code{match_dup} expressions have higher values than all
259 other operand numbers.
261 @var{predicate} is a string that is the name of a C function that accepts two
262 arguments, an expression and a machine mode. During matching, the
263 function will be called with the putative operand as the expression and
264 @var{m} as the mode argument (if @var{m} is not specified,
265 @code{VOIDmode} will be used, which normally causes @var{predicate} to accept
266 any mode). If it returns zero, this instruction pattern fails to match.
267 @var{predicate} may be an empty string; then it means no test is to be done
268 on the operand, so anything which occurs in this position is valid.
270 Most of the time, @var{predicate} will reject modes other than @var{m}---but
271 not always. For example, the predicate @code{address_operand} uses
272 @var{m} as the mode of memory ref that the address should be valid for.
273 Many predicates accept @code{const_int} nodes even though their mode is
276 @var{constraint} controls reloading and the choice of the best register
277 class to use for a value, as explained later (@pxref{Constraints}).
279 People are often unclear on the difference between the constraint and the
280 predicate. The predicate helps decide whether a given insn matches the
281 pattern. The constraint plays no role in this decision; instead, it
282 controls various decisions in the case of an insn which does match.
284 @findex general_operand
285 On CISC machines, the most common @var{predicate} is
286 @code{"general_operand"}. This function checks that the putative
287 operand is either a constant, a register or a memory reference, and that
288 it is valid for mode @var{m}.
290 @findex register_operand
291 For an operand that must be a register, @var{predicate} should be
292 @code{"register_operand"}. Using @code{"general_operand"} would be
293 valid, since the reload pass would copy any non-register operands
294 through registers, but this would make GCC do extra work, it would
295 prevent invariant operands (such as constant) from being removed from
296 loops, and it would prevent the register allocator from doing the best
297 possible job. On RISC machines, it is usually most efficient to allow
298 @var{predicate} to accept only objects that the constraints allow.
300 @findex immediate_operand
301 For an operand that must be a constant, you must be sure to either use
302 @code{"immediate_operand"} for @var{predicate}, or make the instruction
303 pattern's extra condition require a constant, or both. You cannot
304 expect the constraints to do this work! If the constraints allow only
305 constants, but the predicate allows something else, the compiler will
306 crash when that case arises.
308 @findex match_scratch
309 @item (match_scratch:@var{m} @var{n} @var{constraint})
310 This expression is also a placeholder for operand number @var{n}
311 and indicates that operand must be a @code{scratch} or @code{reg}
314 When matching patterns, this is equivalent to
317 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
320 but, when generating RTL, it produces a (@code{scratch}:@var{m})
323 If the last few expressions in a @code{parallel} are @code{clobber}
324 expressions whose operands are either a hard register or
325 @code{match_scratch}, the combiner can add or delete them when
326 necessary. @xref{Side Effects}.
329 @item (match_dup @var{n})
330 This expression is also a placeholder for operand number @var{n}.
331 It is used when the operand needs to appear more than once in the
334 In construction, @code{match_dup} acts just like @code{match_operand}:
335 the operand is substituted into the insn being constructed. But in
336 matching, @code{match_dup} behaves differently. It assumes that operand
337 number @var{n} has already been determined by a @code{match_operand}
338 appearing earlier in the recognition template, and it matches only an
339 identical-looking expression.
341 Note that @code{match_dup} should not be used to tell the compiler that
342 a particular register is being used for two operands (example:
343 @code{add} that adds one register to another; the second register is
344 both an input operand and the output operand). Use a matching
345 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
346 operand is used in two places in the template, such as an instruction
347 that computes both a quotient and a remainder, where the opcode takes
348 two input operands but the RTL template has to refer to each of those
349 twice; once for the quotient pattern and once for the remainder pattern.
351 @findex match_operator
352 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
353 This pattern is a kind of placeholder for a variable RTL expression
356 When constructing an insn, it stands for an RTL expression whose
357 expression code is taken from that of operand @var{n}, and whose
358 operands are constructed from the patterns @var{operands}.
360 When matching an expression, it matches an expression if the function
361 @var{predicate} returns nonzero on that expression @emph{and} the
362 patterns @var{operands} match the operands of the expression.
364 Suppose that the function @code{commutative_operator} is defined as
365 follows, to match any expression whose operator is one of the
366 commutative arithmetic operators of RTL and whose mode is @var{mode}:
370 commutative_operator (x, mode)
372 enum machine_mode mode;
374 enum rtx_code code = GET_CODE (x);
375 if (GET_MODE (x) != mode)
377 return (GET_RTX_CLASS (code) == 'c'
378 || code == EQ || code == NE);
382 Then the following pattern will match any RTL expression consisting
383 of a commutative operator applied to two general operands:
386 (match_operator:SI 3 "commutative_operator"
387 [(match_operand:SI 1 "general_operand" "g")
388 (match_operand:SI 2 "general_operand" "g")])
391 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
392 because the expressions to be matched all contain two operands.
394 When this pattern does match, the two operands of the commutative
395 operator are recorded as operands 1 and 2 of the insn. (This is done
396 by the two instances of @code{match_operand}.) Operand 3 of the insn
397 will be the entire commutative expression: use @code{GET_CODE
398 (operands[3])} to see which commutative operator was used.
400 The machine mode @var{m} of @code{match_operator} works like that of
401 @code{match_operand}: it is passed as the second argument to the
402 predicate function, and that function is solely responsible for
403 deciding whether the expression to be matched ``has'' that mode.
405 When constructing an insn, argument 3 of the gen-function will specify
406 the operation (i.e.@: the expression code) for the expression to be
407 made. It should be an RTL expression, whose expression code is copied
408 into a new expression whose operands are arguments 1 and 2 of the
409 gen-function. The subexpressions of argument 3 are not used;
410 only its expression code matters.
412 When @code{match_operator} is used in a pattern for matching an insn,
413 it usually best if the operand number of the @code{match_operator}
414 is higher than that of the actual operands of the insn. This improves
415 register allocation because the register allocator often looks at
416 operands 1 and 2 of insns to see if it can do register tying.
418 There is no way to specify constraints in @code{match_operator}. The
419 operand of the insn which corresponds to the @code{match_operator}
420 never has any constraints because it is never reloaded as a whole.
421 However, if parts of its @var{operands} are matched by
422 @code{match_operand} patterns, those parts may have constraints of
426 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
427 Like @code{match_dup}, except that it applies to operators instead of
428 operands. When constructing an insn, operand number @var{n} will be
429 substituted at this point. But in matching, @code{match_op_dup} behaves
430 differently. It assumes that operand number @var{n} has already been
431 determined by a @code{match_operator} appearing earlier in the
432 recognition template, and it matches only an identical-looking
435 @findex match_parallel
436 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
437 This pattern is a placeholder for an insn that consists of a
438 @code{parallel} expression with a variable number of elements. This
439 expression should only appear at the top level of an insn pattern.
441 When constructing an insn, operand number @var{n} will be substituted at
442 this point. When matching an insn, it matches if the body of the insn
443 is a @code{parallel} expression with at least as many elements as the
444 vector of @var{subpat} expressions in the @code{match_parallel}, if each
445 @var{subpat} matches the corresponding element of the @code{parallel},
446 @emph{and} the function @var{predicate} returns nonzero on the
447 @code{parallel} that is the body of the insn. It is the responsibility
448 of the predicate to validate elements of the @code{parallel} beyond
449 those listed in the @code{match_parallel}.
451 A typical use of @code{match_parallel} is to match load and store
452 multiple expressions, which can contain a variable number of elements
453 in a @code{parallel}. For example,
457 [(match_parallel 0 "load_multiple_operation"
458 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
459 (match_operand:SI 2 "memory_operand" "m"))
461 (clobber (reg:SI 179))])]
466 This example comes from @file{a29k.md}. The function
467 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
468 that subsequent elements in the @code{parallel} are the same as the
469 @code{set} in the pattern, except that they are referencing subsequent
470 registers and memory locations.
472 An insn that matches this pattern might look like:
476 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
478 (clobber (reg:SI 179))
480 (mem:SI (plus:SI (reg:SI 100)
483 (mem:SI (plus:SI (reg:SI 100)
487 @findex match_par_dup
488 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
489 Like @code{match_op_dup}, but for @code{match_parallel} instead of
490 @code{match_operator}.
493 @item (match_insn @var{predicate})
494 Match a complete insn. Unlike the other @code{match_*} recognizers,
495 @code{match_insn} does not take an operand number.
497 The machine mode @var{m} of @code{match_insn} works like that of
498 @code{match_operand}: it is passed as the second argument to the
499 predicate function, and that function is solely responsible for
500 deciding whether the expression to be matched ``has'' that mode.
503 @item (match_insn2 @var{n} @var{predicate})
504 Match a complete insn.
506 The machine mode @var{m} of @code{match_insn2} works like that of
507 @code{match_operand}: it is passed as the second argument to the
508 predicate function, and that function is solely responsible for
509 deciding whether the expression to be matched ``has'' that mode.
513 @node Output Template
514 @section Output Templates and Operand Substitution
515 @cindex output templates
516 @cindex operand substitution
518 @cindex @samp{%} in template
520 The @dfn{output template} is a string which specifies how to output the
521 assembler code for an instruction pattern. Most of the template is a
522 fixed string which is output literally. The character @samp{%} is used
523 to specify where to substitute an operand; it can also be used to
524 identify places where different variants of the assembler require
527 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
528 operand @var{n} at that point in the string.
530 @samp{%} followed by a letter and a digit says to output an operand in an
531 alternate fashion. Four letters have standard, built-in meanings described
532 below. The machine description macro @code{PRINT_OPERAND} can define
533 additional letters with nonstandard meanings.
535 @samp{%c@var{digit}} can be used to substitute an operand that is a
536 constant value without the syntax that normally indicates an immediate
539 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
540 the constant is negated before printing.
542 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
543 memory reference, with the actual operand treated as the address. This may
544 be useful when outputting a ``load address'' instruction, because often the
545 assembler syntax for such an instruction requires you to write the operand
546 as if it were a memory reference.
548 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
551 @samp{%=} outputs a number which is unique to each instruction in the
552 entire compilation. This is useful for making local labels to be
553 referred to more than once in a single template that generates multiple
554 assembler instructions.
556 @samp{%} followed by a punctuation character specifies a substitution that
557 does not use an operand. Only one case is standard: @samp{%%} outputs a
558 @samp{%} into the assembler code. Other nonstandard cases can be
559 defined in the @code{PRINT_OPERAND} macro. You must also define
560 which punctuation characters are valid with the
561 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
565 The template may generate multiple assembler instructions. Write the text
566 for the instructions, with @samp{\;} between them.
568 @cindex matching operands
569 When the RTL contains two operands which are required by constraint to match
570 each other, the output template must refer only to the lower-numbered operand.
571 Matching operands are not always identical, and the rest of the compiler
572 arranges to put the proper RTL expression for printing into the lower-numbered
575 One use of nonstandard letters or punctuation following @samp{%} is to
576 distinguish between different assembler languages for the same machine; for
577 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
578 requires periods in most opcode names, while MIT syntax does not. For
579 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
580 syntax. The same file of patterns is used for both kinds of output syntax,
581 but the character sequence @samp{%.} is used in each place where Motorola
582 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
583 defines the sequence to output a period; the macro for MIT syntax defines
586 @cindex @code{#} in template
587 As a special case, a template consisting of the single character @code{#}
588 instructs the compiler to first split the insn, and then output the
589 resulting instructions separately. This helps eliminate redundancy in the
590 output templates. If you have a @code{define_insn} that needs to emit
591 multiple assembler instructions, and there is an matching @code{define_split}
592 already defined, then you can simply use @code{#} as the output template
593 instead of writing an output template that emits the multiple assembler
596 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
597 of the form @samp{@{option0|option1|option2@}} in the templates. These
598 describe multiple variants of assembler language syntax.
599 @xref{Instruction Output}.
601 @node Output Statement
602 @section C Statements for Assembler Output
603 @cindex output statements
604 @cindex C statements for assembler output
605 @cindex generating assembler output
607 Often a single fixed template string cannot produce correct and efficient
608 assembler code for all the cases that are recognized by a single
609 instruction pattern. For example, the opcodes may depend on the kinds of
610 operands; or some unfortunate combinations of operands may require extra
611 machine instructions.
613 If the output control string starts with a @samp{@@}, then it is actually
614 a series of templates, each on a separate line. (Blank lines and
615 leading spaces and tabs are ignored.) The templates correspond to the
616 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
617 if a target machine has a two-address add instruction @samp{addr} to add
618 into a register and another @samp{addm} to add a register to memory, you
619 might write this pattern:
622 (define_insn "addsi3"
623 [(set (match_operand:SI 0 "general_operand" "=r,m")
624 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
625 (match_operand:SI 2 "general_operand" "g,r")))]
632 @cindex @code{*} in template
633 @cindex asterisk in template
634 If the output control string starts with a @samp{*}, then it is not an
635 output template but rather a piece of C program that should compute a
636 template. It should execute a @code{return} statement to return the
637 template-string you want. Most such templates use C string literals, which
638 require doublequote characters to delimit them. To include these
639 doublequote characters in the string, prefix each one with @samp{\}.
641 If the output control string is written as a brace block instead of a
642 double-quoted string, it is automatically assumed to be C code. In that
643 case, it is not necessary to put in a leading asterisk, or to escape the
644 doublequotes surrounding C string literals.
646 The operands may be found in the array @code{operands}, whose C data type
649 It is very common to select different ways of generating assembler code
650 based on whether an immediate operand is within a certain range. Be
651 careful when doing this, because the result of @code{INTVAL} is an
652 integer on the host machine. If the host machine has more bits in an
653 @code{int} than the target machine has in the mode in which the constant
654 will be used, then some of the bits you get from @code{INTVAL} will be
655 superfluous. For proper results, you must carefully disregard the
656 values of those bits.
658 @findex output_asm_insn
659 It is possible to output an assembler instruction and then go on to output
660 or compute more of them, using the subroutine @code{output_asm_insn}. This
661 receives two arguments: a template-string and a vector of operands. The
662 vector may be @code{operands}, or it may be another array of @code{rtx}
663 that you declare locally and initialize yourself.
665 @findex which_alternative
666 When an insn pattern has multiple alternatives in its constraints, often
667 the appearance of the assembler code is determined mostly by which alternative
668 was matched. When this is so, the C code can test the variable
669 @code{which_alternative}, which is the ordinal number of the alternative
670 that was actually satisfied (0 for the first, 1 for the second alternative,
673 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
674 for registers and @samp{clrmem} for memory locations. Here is how
675 a pattern could use @code{which_alternative} to choose between them:
679 [(set (match_operand:SI 0 "general_operand" "=r,m")
683 return (which_alternative == 0
684 ? "clrreg %0" : "clrmem %0");
688 The example above, where the assembler code to generate was
689 @emph{solely} determined by the alternative, could also have been specified
690 as follows, having the output control string start with a @samp{@@}:
695 [(set (match_operand:SI 0 "general_operand" "=r,m")
705 @c Most of this node appears by itself (in a different place) even
706 @c when the INTERNALS flag is clear. Passages that require the internals
707 @c manual's context are conditionalized to appear only in the internals manual.
710 @section Operand Constraints
711 @cindex operand constraints
714 Each @code{match_operand} in an instruction pattern can specify a
715 constraint for the type of operands allowed.
719 @section Constraints for @code{asm} Operands
720 @cindex operand constraints, @code{asm}
721 @cindex constraints, @code{asm}
722 @cindex @code{asm} constraints
724 Here are specific details on what constraint letters you can use with
727 Constraints can say whether
728 an operand may be in a register, and which kinds of register; whether the
729 operand can be a memory reference, and which kinds of address; whether the
730 operand may be an immediate constant, and which possible values it may
731 have. Constraints can also require two operands to match.
735 * Simple Constraints:: Basic use of constraints.
736 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
737 * Class Preferences:: Constraints guide which hard register to put things in.
738 * Modifiers:: More precise control over effects of constraints.
739 * Machine Constraints:: Existing constraints for some particular machines.
745 * Simple Constraints:: Basic use of constraints.
746 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
747 * Modifiers:: More precise control over effects of constraints.
748 * Machine Constraints:: Special constraints for some particular machines.
752 @node Simple Constraints
753 @subsection Simple Constraints
754 @cindex simple constraints
756 The simplest kind of constraint is a string full of letters, each of
757 which describes one kind of operand that is permitted. Here are
758 the letters that are allowed:
762 Whitespace characters are ignored and can be inserted at any position
763 except the first. This enables each alternative for different operands to
764 be visually aligned in the machine description even if they have different
765 number of constraints and modifiers.
767 @cindex @samp{m} in constraint
768 @cindex memory references in constraints
770 A memory operand is allowed, with any kind of address that the machine
773 @cindex offsettable address
774 @cindex @samp{o} in constraint
776 A memory operand is allowed, but only if the address is
777 @dfn{offsettable}. This means that adding a small integer (actually,
778 the width in bytes of the operand, as determined by its machine mode)
779 may be added to the address and the result is also a valid memory
782 @cindex autoincrement/decrement addressing
783 For example, an address which is constant is offsettable; so is an
784 address that is the sum of a register and a constant (as long as a
785 slightly larger constant is also within the range of address-offsets
786 supported by the machine); but an autoincrement or autodecrement
787 address is not offsettable. More complicated indirect/indexed
788 addresses may or may not be offsettable depending on the other
789 addressing modes that the machine supports.
791 Note that in an output operand which can be matched by another
792 operand, the constraint letter @samp{o} is valid only when accompanied
793 by both @samp{<} (if the target machine has predecrement addressing)
794 and @samp{>} (if the target machine has preincrement addressing).
796 @cindex @samp{V} in constraint
798 A memory operand that is not offsettable. In other words, anything that
799 would fit the @samp{m} constraint but not the @samp{o} constraint.
801 @cindex @samp{<} in constraint
803 A memory operand with autodecrement addressing (either predecrement or
804 postdecrement) is allowed.
806 @cindex @samp{>} in constraint
808 A memory operand with autoincrement addressing (either preincrement or
809 postincrement) is allowed.
811 @cindex @samp{r} in constraint
812 @cindex registers in constraints
814 A register operand is allowed provided that it is in a general
817 @cindex constants in constraints
818 @cindex @samp{i} in constraint
820 An immediate integer operand (one with constant value) is allowed.
821 This includes symbolic constants whose values will be known only at
824 @cindex @samp{n} in constraint
826 An immediate integer operand with a known numeric value is allowed.
827 Many systems cannot support assembly-time constants for operands less
828 than a word wide. Constraints for these operands should use @samp{n}
829 rather than @samp{i}.
831 @cindex @samp{I} in constraint
832 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
833 Other letters in the range @samp{I} through @samp{P} may be defined in
834 a machine-dependent fashion to permit immediate integer operands with
835 explicit integer values in specified ranges. For example, on the
836 68000, @samp{I} is defined to stand for the range of values 1 to 8.
837 This is the range permitted as a shift count in the shift
840 @cindex @samp{E} in constraint
842 An immediate floating operand (expression code @code{const_double}) is
843 allowed, but only if the target floating point format is the same as
844 that of the host machine (on which the compiler is running).
846 @cindex @samp{F} in constraint
848 An immediate floating operand (expression code @code{const_double} or
849 @code{const_vector}) is allowed.
851 @cindex @samp{G} in constraint
852 @cindex @samp{H} in constraint
853 @item @samp{G}, @samp{H}
854 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
855 permit immediate floating operands in particular ranges of values.
857 @cindex @samp{s} in constraint
859 An immediate integer operand whose value is not an explicit integer is
862 This might appear strange; if an insn allows a constant operand with a
863 value not known at compile time, it certainly must allow any known
864 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
865 better code to be generated.
867 For example, on the 68000 in a fullword instruction it is possible to
868 use an immediate operand; but if the immediate value is between @minus{}128
869 and 127, better code results from loading the value into a register and
870 using the register. This is because the load into the register can be
871 done with a @samp{moveq} instruction. We arrange for this to happen
872 by defining the letter @samp{K} to mean ``any integer outside the
873 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
876 @cindex @samp{g} in constraint
878 Any register, memory or immediate integer operand is allowed, except for
879 registers that are not general registers.
881 @cindex @samp{X} in constraint
884 Any operand whatsoever is allowed, even if it does not satisfy
885 @code{general_operand}. This is normally used in the constraint of
886 a @code{match_scratch} when certain alternatives will not actually
887 require a scratch register.
890 Any operand whatsoever is allowed.
893 @cindex @samp{0} in constraint
894 @cindex digits in constraint
895 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
896 An operand that matches the specified operand number is allowed. If a
897 digit is used together with letters within the same alternative, the
898 digit should come last.
900 This number is allowed to be more than a single digit. If multiple
901 digits are encountered consecutively, they are interpreted as a single
902 decimal integer. There is scant chance for ambiguity, since to-date
903 it has never been desirable that @samp{10} be interpreted as matching
904 either operand 1 @emph{or} operand 0. Should this be desired, one
905 can use multiple alternatives instead.
907 @cindex matching constraint
908 @cindex constraint, matching
909 This is called a @dfn{matching constraint} and what it really means is
910 that the assembler has only a single operand that fills two roles
912 considered separate in the RTL insn. For example, an add insn has two
913 input operands and one output operand in the RTL, but on most CISC
916 which @code{asm} distinguishes. For example, an add instruction uses
917 two input operands and an output operand, but on most CISC
919 machines an add instruction really has only two operands, one of them an
920 input-output operand:
926 Matching constraints are used in these circumstances.
927 More precisely, the two operands that match must include one input-only
928 operand and one output-only operand. Moreover, the digit must be a
929 smaller number than the number of the operand that uses it in the
933 For operands to match in a particular case usually means that they
934 are identical-looking RTL expressions. But in a few special cases
935 specific kinds of dissimilarity are allowed. For example, @code{*x}
936 as an input operand will match @code{*x++} as an output operand.
937 For proper results in such cases, the output template should always
938 use the output-operand's number when printing the operand.
941 @cindex load address instruction
942 @cindex push address instruction
943 @cindex address constraints
944 @cindex @samp{p} in constraint
946 An operand that is a valid memory address is allowed. This is
947 for ``load address'' and ``push address'' instructions.
949 @findex address_operand
950 @samp{p} in the constraint must be accompanied by @code{address_operand}
951 as the predicate in the @code{match_operand}. This predicate interprets
952 the mode specified in the @code{match_operand} as the mode of the memory
953 reference for which the address would be valid.
955 @cindex other register constraints
956 @cindex extensible constraints
957 @item @var{other-letters}
958 Other letters can be defined in machine-dependent fashion to stand for
959 particular classes of registers or other arbitrary operand types.
960 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
961 for data, address and floating point registers.
964 The machine description macro @code{REG_CLASS_FROM_LETTER} has first
965 cut at the otherwise unused letters. If it evaluates to @code{NO_REGS},
966 then @code{EXTRA_CONSTRAINT} is evaluated.
968 A typical use for @code{EXTRA_CONSTRAINT} would be to distinguish certain
969 types of memory references that affect other insn operands.
974 In order to have valid assembler code, each operand must satisfy
975 its constraint. But a failure to do so does not prevent the pattern
976 from applying to an insn. Instead, it directs the compiler to modify
977 the code so that the constraint will be satisfied. Usually this is
978 done by copying an operand into a register.
980 Contrast, therefore, the two instruction patterns that follow:
984 [(set (match_operand:SI 0 "general_operand" "=r")
985 (plus:SI (match_dup 0)
986 (match_operand:SI 1 "general_operand" "r")))]
992 which has two operands, one of which must appear in two places, and
996 [(set (match_operand:SI 0 "general_operand" "=r")
997 (plus:SI (match_operand:SI 1 "general_operand" "0")
998 (match_operand:SI 2 "general_operand" "r")))]
1004 which has three operands, two of which are required by a constraint to be
1005 identical. If we are considering an insn of the form
1008 (insn @var{n} @var{prev} @var{next}
1010 (plus:SI (reg:SI 6) (reg:SI 109)))
1015 the first pattern would not apply at all, because this insn does not
1016 contain two identical subexpressions in the right place. The pattern would
1017 say, ``That does not look like an add instruction; try other patterns.''
1018 The second pattern would say, ``Yes, that's an add instruction, but there
1019 is something wrong with it.'' It would direct the reload pass of the
1020 compiler to generate additional insns to make the constraint true. The
1021 results might look like this:
1024 (insn @var{n2} @var{prev} @var{n}
1025 (set (reg:SI 3) (reg:SI 6))
1028 (insn @var{n} @var{n2} @var{next}
1030 (plus:SI (reg:SI 3) (reg:SI 109)))
1034 It is up to you to make sure that each operand, in each pattern, has
1035 constraints that can handle any RTL expression that could be present for
1036 that operand. (When multiple alternatives are in use, each pattern must,
1037 for each possible combination of operand expressions, have at least one
1038 alternative which can handle that combination of operands.) The
1039 constraints don't need to @emph{allow} any possible operand---when this is
1040 the case, they do not constrain---but they must at least point the way to
1041 reloading any possible operand so that it will fit.
1045 If the constraint accepts whatever operands the predicate permits,
1046 there is no problem: reloading is never necessary for this operand.
1048 For example, an operand whose constraints permit everything except
1049 registers is safe provided its predicate rejects registers.
1051 An operand whose predicate accepts only constant values is safe
1052 provided its constraints include the letter @samp{i}. If any possible
1053 constant value is accepted, then nothing less than @samp{i} will do;
1054 if the predicate is more selective, then the constraints may also be
1058 Any operand expression can be reloaded by copying it into a register.
1059 So if an operand's constraints allow some kind of register, it is
1060 certain to be safe. It need not permit all classes of registers; the
1061 compiler knows how to copy a register into another register of the
1062 proper class in order to make an instruction valid.
1064 @cindex nonoffsettable memory reference
1065 @cindex memory reference, nonoffsettable
1067 A nonoffsettable memory reference can be reloaded by copying the
1068 address into a register. So if the constraint uses the letter
1069 @samp{o}, all memory references are taken care of.
1072 A constant operand can be reloaded by allocating space in memory to
1073 hold it as preinitialized data. Then the memory reference can be used
1074 in place of the constant. So if the constraint uses the letters
1075 @samp{o} or @samp{m}, constant operands are not a problem.
1078 If the constraint permits a constant and a pseudo register used in an insn
1079 was not allocated to a hard register and is equivalent to a constant,
1080 the register will be replaced with the constant. If the predicate does
1081 not permit a constant and the insn is re-recognized for some reason, the
1082 compiler will crash. Thus the predicate must always recognize any
1083 objects allowed by the constraint.
1086 If the operand's predicate can recognize registers, but the constraint does
1087 not permit them, it can make the compiler crash. When this operand happens
1088 to be a register, the reload pass will be stymied, because it does not know
1089 how to copy a register temporarily into memory.
1091 If the predicate accepts a unary operator, the constraint applies to the
1092 operand. For example, the MIPS processor at ISA level 3 supports an
1093 instruction which adds two registers in @code{SImode} to produce a
1094 @code{DImode} result, but only if the registers are correctly sign
1095 extended. This predicate for the input operands accepts a
1096 @code{sign_extend} of an @code{SImode} register. Write the constraint
1097 to indicate the type of register that is required for the operand of the
1101 @node Multi-Alternative
1102 @subsection Multiple Alternative Constraints
1103 @cindex multiple alternative constraints
1105 Sometimes a single instruction has multiple alternative sets of possible
1106 operands. For example, on the 68000, a logical-or instruction can combine
1107 register or an immediate value into memory, or it can combine any kind of
1108 operand into a register; but it cannot combine one memory location into
1111 These constraints are represented as multiple alternatives. An alternative
1112 can be described by a series of letters for each operand. The overall
1113 constraint for an operand is made from the letters for this operand
1114 from the first alternative, a comma, the letters for this operand from
1115 the second alternative, a comma, and so on until the last alternative.
1117 Here is how it is done for fullword logical-or on the 68000:
1120 (define_insn "iorsi3"
1121 [(set (match_operand:SI 0 "general_operand" "=m,d")
1122 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1123 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1127 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1128 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1129 2. The second alternative has @samp{d} (data register) for operand 0,
1130 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1131 @samp{%} in the constraints apply to all the alternatives; their
1132 meaning is explained in the next section (@pxref{Class Preferences}).
1135 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1136 If all the operands fit any one alternative, the instruction is valid.
1137 Otherwise, for each alternative, the compiler counts how many instructions
1138 must be added to copy the operands so that that alternative applies.
1139 The alternative requiring the least copying is chosen. If two alternatives
1140 need the same amount of copying, the one that comes first is chosen.
1141 These choices can be altered with the @samp{?} and @samp{!} characters:
1144 @cindex @samp{?} in constraint
1145 @cindex question mark
1147 Disparage slightly the alternative that the @samp{?} appears in,
1148 as a choice when no alternative applies exactly. The compiler regards
1149 this alternative as one unit more costly for each @samp{?} that appears
1152 @cindex @samp{!} in constraint
1153 @cindex exclamation point
1155 Disparage severely the alternative that the @samp{!} appears in.
1156 This alternative can still be used if it fits without reloading,
1157 but if reloading is needed, some other alternative will be used.
1161 When an insn pattern has multiple alternatives in its constraints, often
1162 the appearance of the assembler code is determined mostly by which
1163 alternative was matched. When this is so, the C code for writing the
1164 assembler code can use the variable @code{which_alternative}, which is
1165 the ordinal number of the alternative that was actually satisfied (0 for
1166 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1170 @node Class Preferences
1171 @subsection Register Class Preferences
1172 @cindex class preference constraints
1173 @cindex register class preference constraints
1175 @cindex voting between constraint alternatives
1176 The operand constraints have another function: they enable the compiler
1177 to decide which kind of hardware register a pseudo register is best
1178 allocated to. The compiler examines the constraints that apply to the
1179 insns that use the pseudo register, looking for the machine-dependent
1180 letters such as @samp{d} and @samp{a} that specify classes of registers.
1181 The pseudo register is put in whichever class gets the most ``votes''.
1182 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1183 favor of a general register. The machine description says which registers
1184 are considered general.
1186 Of course, on some machines all registers are equivalent, and no register
1187 classes are defined. Then none of this complexity is relevant.
1191 @subsection Constraint Modifier Characters
1192 @cindex modifiers in constraints
1193 @cindex constraint modifier characters
1195 @c prevent bad page break with this line
1196 Here are constraint modifier characters.
1199 @cindex @samp{=} in constraint
1201 Means that this operand is write-only for this instruction: the previous
1202 value is discarded and replaced by output data.
1204 @cindex @samp{+} in constraint
1206 Means that this operand is both read and written by the instruction.
1208 When the compiler fixes up the operands to satisfy the constraints,
1209 it needs to know which operands are inputs to the instruction and
1210 which are outputs from it. @samp{=} identifies an output; @samp{+}
1211 identifies an operand that is both input and output; all other operands
1212 are assumed to be input only.
1214 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1215 first character of the constraint string.
1217 @cindex @samp{&} in constraint
1218 @cindex earlyclobber operand
1220 Means (in a particular alternative) that this operand is an
1221 @dfn{earlyclobber} operand, which is modified before the instruction is
1222 finished using the input operands. Therefore, this operand may not lie
1223 in a register that is used as an input operand or as part of any memory
1226 @samp{&} applies only to the alternative in which it is written. In
1227 constraints with multiple alternatives, sometimes one alternative
1228 requires @samp{&} while others do not. See, for example, the
1229 @samp{movdf} insn of the 68000.
1231 An input operand can be tied to an earlyclobber operand if its only
1232 use as an input occurs before the early result is written. Adding
1233 alternatives of this form often allows GCC to produce better code
1234 when only some of the inputs can be affected by the earlyclobber.
1235 See, for example, the @samp{mulsi3} insn of the ARM@.
1237 @samp{&} does not obviate the need to write @samp{=}.
1239 @cindex @samp{%} in constraint
1241 Declares the instruction to be commutative for this operand and the
1242 following operand. This means that the compiler may interchange the
1243 two operands if that is the cheapest way to make all operands fit the
1246 This is often used in patterns for addition instructions
1247 that really have only two operands: the result must go in one of the
1248 arguments. Here for example, is how the 68000 halfword-add
1249 instruction is defined:
1252 (define_insn "addhi3"
1253 [(set (match_operand:HI 0 "general_operand" "=m,r")
1254 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1255 (match_operand:HI 2 "general_operand" "di,g")))]
1259 GCC can only handle one commutative pair in an asm; if you use more,
1260 the compiler may fail.
1262 @cindex @samp{#} in constraint
1264 Says that all following characters, up to the next comma, are to be
1265 ignored as a constraint. They are significant only for choosing
1266 register preferences.
1268 @cindex @samp{*} in constraint
1270 Says that the following character should be ignored when choosing
1271 register preferences. @samp{*} has no effect on the meaning of the
1272 constraint as a constraint, and no effect on reloading.
1275 Here is an example: the 68000 has an instruction to sign-extend a
1276 halfword in a data register, and can also sign-extend a value by
1277 copying it into an address register. While either kind of register is
1278 acceptable, the constraints on an address-register destination are
1279 less strict, so it is best if register allocation makes an address
1280 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1281 constraint letter (for data register) is ignored when computing
1282 register preferences.
1285 (define_insn "extendhisi2"
1286 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1288 (match_operand:HI 1 "general_operand" "0,g")))]
1294 @node Machine Constraints
1295 @subsection Constraints for Particular Machines
1296 @cindex machine specific constraints
1297 @cindex constraints, machine specific
1299 Whenever possible, you should use the general-purpose constraint letters
1300 in @code{asm} arguments, since they will convey meaning more readily to
1301 people reading your code. Failing that, use the constraint letters
1302 that usually have very similar meanings across architectures. The most
1303 commonly used constraints are @samp{m} and @samp{r} (for memory and
1304 general-purpose registers respectively; @pxref{Simple Constraints}), and
1305 @samp{I}, usually the letter indicating the most common
1306 immediate-constant format.
1308 For each machine architecture, the
1309 @file{config/@var{machine}/@var{machine}.h} file defines additional
1310 constraints. These constraints are used by the compiler itself for
1311 instruction generation, as well as for @code{asm} statements; therefore,
1312 some of the constraints are not particularly interesting for @code{asm}.
1313 The constraints are defined through these macros:
1316 @item REG_CLASS_FROM_LETTER
1317 Register class constraints (usually lowercase).
1319 @item CONST_OK_FOR_LETTER_P
1320 Immediate constant constraints, for non-floating point constants of
1321 word size or smaller precision (usually uppercase).
1323 @item CONST_DOUBLE_OK_FOR_LETTER_P
1324 Immediate constant constraints, for all floating point constants and for
1325 constants of greater than word size precision (usually uppercase).
1327 @item EXTRA_CONSTRAINT
1328 Special cases of registers or memory. This macro is not required, and
1329 is only defined for some machines.
1332 Inspecting these macro definitions in the compiler source for your
1333 machine is the best way to be certain you have the right constraints.
1334 However, here is a summary of the machine-dependent constraints
1335 available on some particular machines.
1338 @item ARM family---@file{arm.h}
1341 Floating-point register
1344 One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
1348 Floating-point constant that would satisfy the constraint @samp{F} if it
1352 Integer that is valid as an immediate operand in a data processing
1353 instruction. That is, an integer in the range 0 to 255 rotated by a
1357 Integer in the range @minus{}4095 to 4095
1360 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1363 Integer that satisfies constraint @samp{I} when negated (twos complement)
1366 Integer in the range 0 to 32
1369 A memory reference where the exact address is in a single register
1370 (`@samp{m}' is preferable for @code{asm} statements)
1373 An item in the constant pool
1376 A symbol in the text segment of the current file
1379 @item AVR family---@file{avr.h}
1382 Registers from r0 to r15
1385 Registers from r16 to r23
1388 Registers from r16 to r31
1391 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1394 Pointer register (r26--r31)
1397 Base pointer register (r28--r31)
1400 Stack pointer register (SPH:SPL)
1403 Temporary register r0
1406 Register pair X (r27:r26)
1409 Register pair Y (r29:r28)
1412 Register pair Z (r31:r30)
1415 Constant greater than @minus{}1, less than 64
1418 Constant greater than @minus{}64, less than 1
1427 Constant that fits in 8 bits
1430 Constant integer @minus{}1
1433 Constant integer 8, 16, or 24
1439 A floating point constant 0.0
1442 @item PowerPC and IBM RS6000---@file{rs6000.h}
1445 Address base register
1448 Floating point register
1454 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
1463 @samp{LINK} register
1466 @samp{CR} register (condition register) number 0
1469 @samp{CR} register (condition register)
1472 @samp{FPMEM} stack memory for FPR-GPR transfers
1475 Signed 16-bit constant
1478 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
1479 @code{SImode} constants)
1482 Unsigned 16-bit constant
1485 Signed 16-bit constant shifted left 16 bits
1488 Constant larger than 31
1497 Constant whose negation is a signed 16-bit constant
1500 Floating point constant that can be loaded into a register with one
1501 instruction per word
1504 Memory operand that is an offset from a register (@samp{m} is preferable
1505 for @code{asm} statements)
1511 Constant suitable as a 64-bit mask operand
1514 Constant suitable as a 32-bit mask operand
1517 System V Release 4 small data area reference
1520 @item Intel 386---@file{i386.h}
1523 @samp{a}, @code{b}, @code{c}, or @code{d} register for the i386.
1524 For x86-64 it is equivalent to @samp{r} class. (for 8-bit instructions that
1525 do not use upper halves)
1528 @samp{a}, @code{b}, @code{c}, or @code{d} register. (for 8-bit instructions,
1529 that do use upper halves)
1532 Legacy register---equivalent to @code{r} class in i386 mode.
1533 (for non-8-bit registers used together with 8-bit upper halves in a single
1537 Specifies the @samp{a} or @samp{d} registers. This is primarily useful
1538 for 64-bit integer values (when in 32-bit mode) intended to be returned
1539 with the @samp{d} register holding the most significant bits and the
1540 @samp{a} register holding the least significant bits.
1543 Floating point register
1546 First (top of stack) floating point register
1549 Second floating point register
1561 Specifies constant that can be easily constructed in SSE register without
1562 loading it from memory.
1574 @samp{xmm} SSE register
1580 Constant in range 0 to 31 (for 32-bit shifts)
1583 Constant in range 0 to 63 (for 64-bit shifts)
1592 0, 1, 2, or 3 (shifts for @code{lea} instruction)
1595 Constant in range 0 to 255 (for @code{out} instruction)
1598 Constant in range 0 to @code{0xffffffff} or symbolic reference known to fit specified range.
1599 (for using immediates in zero extending 32-bit to 64-bit x86-64 instructions)
1602 Constant in range @minus{}2147483648 to 2147483647 or symbolic reference known to fit specified range.
1603 (for using immediates in 64-bit x86-64 instructions)
1606 Standard 80387 floating point constant
1609 @item Intel 960---@file{i960.h}
1612 Floating point register (@code{fp0} to @code{fp3})
1615 Local register (@code{r0} to @code{r15})
1618 Global register (@code{g0} to @code{g15})
1621 Any local or global register
1624 Integers from 0 to 31
1630 Integers from @minus{}31 to 0
1639 @item Intel IA-64---@file{ia64.h}
1642 General register @code{r0} to @code{r3} for @code{addl} instruction
1648 Predicate register (@samp{c} as in ``conditional'')
1651 Application register residing in M-unit
1654 Application register residing in I-unit
1657 Floating-point register
1661 Remember that @samp{m} allows postincrement and postdecrement which
1662 require printing with @samp{%Pn} on IA-64.
1663 Use @samp{S} to disallow postincrement and postdecrement.
1666 Floating-point constant 0.0 or 1.0
1669 14-bit signed integer constant
1672 22-bit signed integer constant
1675 8-bit signed integer constant for logical instructions
1678 8-bit adjusted signed integer constant for compare pseudo-ops
1681 6-bit unsigned integer constant for shift counts
1684 9-bit signed integer constant for load and store postincrements
1690 0 or -1 for @code{dep} instruction
1693 Non-volatile memory for floating-point loads and stores
1696 Integer constant in the range 1 to 4 for @code{shladd} instruction
1699 Memory operand except postincrement and postdecrement
1702 @item FRV---@file{frv.h}
1705 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
1708 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
1711 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
1712 @code{icc0} to @code{icc3}).
1715 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
1718 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
1719 Odd registers are excluded not in the class but through the use of a machine
1720 mode larger than 4 bytes.
1723 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
1726 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
1727 Odd registers are excluded not in the class but through the use of a machine
1728 mode larger than 4 bytes.
1731 Register in the class @code{LR_REG} (the @code{lr} register).
1734 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
1735 Register numbers not divisible by 4 are excluded not in the class but through
1736 the use of a machine mode larger than 8 bytes.
1739 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
1742 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
1745 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
1748 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
1751 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
1752 Register numbers not divisible by 4 are excluded not in the class but through
1753 the use of a machine mode larger than 8 bytes.
1756 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
1759 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
1762 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
1765 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
1768 Floating point constant zero
1771 6-bit signed integer constant
1774 10-bit signed integer constant
1777 16-bit signed integer constant
1780 16-bit unsigned integer constant
1783 12-bit signed integer constant that is negative---i.e.@: in the
1784 range of @minus{}2048 to @minus{}1
1790 12-bit signed integer constant that is greater than zero---i.e.@: in the
1795 @item IP2K---@file{ip2k.h}
1798 @samp{DP} or @samp{IP} registers (general address)
1822 @samp{DP} or @samp{SP} registers (offsettable address)
1825 Non-pointer registers (not @samp{SP}, @samp{DP}, @samp{IP})
1828 Non-SP registers (everything except @samp{SP})
1831 Indirect through @samp{IP} - Avoid this except for @code{QImode}, since we
1832 can't access extra bytes
1835 Indirect through @samp{SP} or @samp{DP} with short displacement (0..127)
1838 Data-section immediate value
1841 Integers from @minus{}255 to @minus{}1
1844 Integers from 0 to 7---valid bit number in a register
1847 Integers from 0 to 127---valid displacement for addressing mode
1850 Integers from 1 to 127
1862 Integers from 0 to 255
1865 @item MIPS---@file{mips.h}
1868 General-purpose integer register
1871 Floating-point register (if available)
1880 @samp{Hi} or @samp{Lo} register
1883 General-purpose integer register
1886 Floating-point status register
1889 Signed 16-bit constant (for arithmetic instructions)
1895 Zero-extended 16-bit constant (for logic instructions)
1898 Constant with low 16 bits zero (can be loaded with @code{lui})
1901 32-bit constant which requires two instructions to load (a constant
1902 which is not @samp{I}, @samp{K}, or @samp{L})
1905 Negative 16-bit constant
1911 Positive 16-bit constant
1917 Memory reference that can be loaded with more than one instruction
1918 (@samp{m} is preferable for @code{asm} statements)
1921 Memory reference that can be loaded with one instruction
1922 (@samp{m} is preferable for @code{asm} statements)
1925 Memory reference in external OSF/rose PIC format
1926 (@samp{m} is preferable for @code{asm} statements)
1929 @item Motorola 680x0---@file{m68k.h}
1938 68881 floating-point register, if available
1941 Integer in the range 1 to 8
1944 16-bit signed number
1947 Signed number whose magnitude is greater than 0x80
1950 Integer in the range @minus{}8 to @minus{}1
1953 Signed number whose magnitude is greater than 0x100
1956 Floating point constant that is not a 68881 constant
1959 @item Motorola 68HC11 & 68HC12 families---@file{m68hc11.h}
1974 Temporary soft register _.tmp
1977 A soft register _.d1 to _.d31
1980 Stack pointer register
1989 Pseudo register 'z' (replaced by 'x' or 'y' at the end)
1992 An address register: x, y or z
1995 An address register: x or y
1998 Register pair (x:d) to form a 32-bit value
2001 Constants in the range @minus{}65536 to 65535
2004 Constants whose 16-bit low part is zero
2007 Constant integer 1 or @minus{}1
2013 Constants in the range @minus{}8 to 2
2018 @item SPARC---@file{sparc.h}
2021 Floating-point register on the SPARC-V8 architecture and
2022 lower floating-point register on the SPARC-V9 architecture.
2025 Floating-point register. It is equivalent to @samp{f} on the
2026 SPARC-V8 architecture and contains both lower and upper
2027 floating-point registers on the SPARC-V9 architecture.
2030 Floating-point condition code register.
2033 Lower floating-point register. It is only valid on the SPARC-V9
2034 architecture when the Visual Instruction Set is available.
2037 Floating-point register. It is only valid on the SPARC-V9 architecture
2038 when the Visual Instruction Set is available.
2041 64-bit global or out register for the SPARC-V8+ architecture.
2044 Signed 13-bit constant
2050 32-bit constant with the low 12 bits clear (a constant that can be
2051 loaded with the @code{sethi} instruction)
2054 A constant in the range supported by @code{movcc} instructions
2057 A constant in the range supported by @code{movrcc} instructions
2060 Same as @samp{K}, except that it verifies that bits that are not in the
2061 lower 32-bit range are all zero. Must be used instead of @samp{K} for
2062 modes wider than @code{SImode}
2071 Signed 13-bit constant, sign-extended to 32 or 64 bits
2074 Floating-point constant whose integral representation can
2075 be moved into an integer register using a single sethi
2079 Floating-point constant whose integral representation can
2080 be moved into an integer register using a single mov
2084 Floating-point constant whose integral representation can
2085 be moved into an integer register using a high/lo_sum
2086 instruction sequence
2089 Memory address aligned to an 8-byte boundary
2095 Memory address for @samp{e} constraint registers.
2099 @item TMS320C3x/C4x---@file{c4x.h}
2102 Auxiliary (address) register (ar0-ar7)
2105 Stack pointer register (sp)
2108 Standard (32-bit) precision integer register
2111 Extended (40-bit) precision register (r0-r11)
2114 Block count register (bk)
2117 Extended (40-bit) precision low register (r0-r7)
2120 Extended (40-bit) precision register (r0-r1)
2123 Extended (40-bit) precision register (r2-r3)
2126 Repeat count register (rc)
2129 Index register (ir0-ir1)
2132 Status (condition code) register (st)
2135 Data page register (dp)
2141 Immediate 16-bit floating-point constant
2144 Signed 16-bit constant
2147 Signed 8-bit constant
2150 Signed 5-bit constant
2153 Unsigned 16-bit constant
2156 Unsigned 8-bit constant
2159 Ones complement of unsigned 16-bit constant
2162 High 16-bit constant (32-bit constant with 16 LSBs zero)
2165 Indirect memory reference with signed 8-bit or index register displacement
2168 Indirect memory reference with unsigned 5-bit displacement
2171 Indirect memory reference with 1 bit or index register displacement
2174 Direct memory reference
2181 @item S/390 and zSeries---@file{s390.h}
2184 Address register (general purpose register except r0)
2187 Data register (arbitrary general purpose register)
2190 Floating-point register
2193 Unsigned 8-bit constant (0--255)
2196 Unsigned 12-bit constant (0--4095)
2199 Signed 16-bit constant (@minus{}32768--32767)
2202 Value appropriate as displacement.
2205 for short displacement
2206 @item (-524288..524287)
2207 for long displacement
2211 Constant integer with a value of 0x7fffffff.
2214 Multiple letter constraint followed by 4 parameter letters.
2217 number of the part counting from most to least significant
2221 mode of the containing operand
2223 value of the other parts (F - all bits set)
2225 The constraint matches if the specified part of a constant
2226 has a value different from it's other parts.
2229 Memory reference without index register and with short displacement.
2232 Memory reference with index register and short displacement.
2235 Memory reference without index register but with long displacement.
2238 Memory reference with index register and long displacement.
2241 Pointer with short displacement.
2244 Pointer with long displacement.
2247 Shift count operand.
2251 @item Xstormy16---@file{stormy16.h}
2266 Registers r0 through r7.
2269 Registers r0 and r1.
2275 Registers r8 and r9.
2278 A constant between 0 and 3 inclusive.
2281 A constant that has exactly one bit set.
2284 A constant that has exactly one bit clear.
2287 A constant between 0 and 255 inclusive.
2290 A constant between @minus{}255 and 0 inclusive.
2293 A constant between @minus{}3 and 0 inclusive.
2296 A constant between 1 and 4 inclusive.
2299 A constant between @minus{}4 and @minus{}1 inclusive.
2302 A memory reference that is a stack push.
2305 A memory reference that is a stack pop.
2308 A memory reference that refers to a constant address of known value.
2311 The register indicated by Rx (not implemented yet).
2314 A constant that is not between 2 and 15 inclusive.
2321 @item Xtensa---@file{xtensa.h}
2324 General-purpose 32-bit register
2327 One-bit boolean register
2330 MAC16 40-bit accumulator register
2333 Signed 12-bit integer constant, for use in MOVI instructions
2336 Signed 8-bit integer constant, for use in ADDI instructions
2339 Integer constant valid for BccI instructions
2342 Unsigned constant valid for BccUI instructions
2349 @node Standard Names
2350 @section Standard Pattern Names For Generation
2351 @cindex standard pattern names
2352 @cindex pattern names
2353 @cindex names, pattern
2355 Here is a table of the instruction names that are meaningful in the RTL
2356 generation pass of the compiler. Giving one of these names to an
2357 instruction pattern tells the RTL generation pass that it can use the
2358 pattern to accomplish a certain task.
2361 @cindex @code{mov@var{m}} instruction pattern
2362 @item @samp{mov@var{m}}
2363 Here @var{m} stands for a two-letter machine mode name, in lowercase.
2364 This instruction pattern moves data with that machine mode from operand
2365 1 to operand 0. For example, @samp{movsi} moves full-word data.
2367 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
2368 own mode is wider than @var{m}, the effect of this instruction is
2369 to store the specified value in the part of the register that corresponds
2370 to mode @var{m}. Bits outside of @var{m}, but which are within the
2371 same target word as the @code{subreg} are undefined. Bits which are
2372 outside the target word are left unchanged.
2374 This class of patterns is special in several ways. First of all, each
2375 of these names up to and including full word size @emph{must} be defined,
2376 because there is no other way to copy a datum from one place to another.
2377 If there are patterns accepting operands in larger modes,
2378 @samp{mov@var{m}} must be defined for integer modes of those sizes.
2380 Second, these patterns are not used solely in the RTL generation pass.
2381 Even the reload pass can generate move insns to copy values from stack
2382 slots into temporary registers. When it does so, one of the operands is
2383 a hard register and the other is an operand that can need to be reloaded
2387 Therefore, when given such a pair of operands, the pattern must generate
2388 RTL which needs no reloading and needs no temporary registers---no
2389 registers other than the operands. For example, if you support the
2390 pattern with a @code{define_expand}, then in such a case the
2391 @code{define_expand} mustn't call @code{force_reg} or any other such
2392 function which might generate new pseudo registers.
2394 This requirement exists even for subword modes on a RISC machine where
2395 fetching those modes from memory normally requires several insns and
2396 some temporary registers.
2398 @findex change_address
2399 During reload a memory reference with an invalid address may be passed
2400 as an operand. Such an address will be replaced with a valid address
2401 later in the reload pass. In this case, nothing may be done with the
2402 address except to use it as it stands. If it is copied, it will not be
2403 replaced with a valid address. No attempt should be made to make such
2404 an address into a valid address and no routine (such as
2405 @code{change_address}) that will do so may be called. Note that
2406 @code{general_operand} will fail when applied to such an address.
2408 @findex reload_in_progress
2409 The global variable @code{reload_in_progress} (which must be explicitly
2410 declared if required) can be used to determine whether such special
2411 handling is required.
2413 The variety of operands that have reloads depends on the rest of the
2414 machine description, but typically on a RISC machine these can only be
2415 pseudo registers that did not get hard registers, while on other
2416 machines explicit memory references will get optional reloads.
2418 If a scratch register is required to move an object to or from memory,
2419 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
2421 If there are cases which need scratch registers during or after reload,
2422 you must define @code{SECONDARY_INPUT_RELOAD_CLASS} and/or
2423 @code{SECONDARY_OUTPUT_RELOAD_CLASS} to detect them, and provide
2424 patterns @samp{reload_in@var{m}} or @samp{reload_out@var{m}} to handle
2425 them. @xref{Register Classes}.
2427 @findex no_new_pseudos
2428 The global variable @code{no_new_pseudos} can be used to determine if it
2429 is unsafe to create new pseudo registers. If this variable is nonzero, then
2430 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
2432 The constraints on a @samp{mov@var{m}} must permit moving any hard
2433 register to any other hard register provided that
2434 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
2435 @code{REGISTER_MOVE_COST} applied to their classes returns a value of 2.
2437 It is obligatory to support floating point @samp{mov@var{m}}
2438 instructions into and out of any registers that can hold fixed point
2439 values, because unions and structures (which have modes @code{SImode} or
2440 @code{DImode}) can be in those registers and they may have floating
2443 There may also be a need to support fixed point @samp{mov@var{m}}
2444 instructions in and out of floating point registers. Unfortunately, I
2445 have forgotten why this was so, and I don't know whether it is still
2446 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
2447 floating point registers, then the constraints of the fixed point
2448 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
2449 reload into a floating point register.
2451 @cindex @code{reload_in} instruction pattern
2452 @cindex @code{reload_out} instruction pattern
2453 @item @samp{reload_in@var{m}}
2454 @itemx @samp{reload_out@var{m}}
2455 Like @samp{mov@var{m}}, but used when a scratch register is required to
2456 move between operand 0 and operand 1. Operand 2 describes the scratch
2457 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
2458 macro in @pxref{Register Classes}.
2460 There are special restrictions on the form of the @code{match_operand}s
2461 used in these patterns. First, only the predicate for the reload
2462 operand is examined, i.e., @code{reload_in} examines operand 1, but not
2463 the predicates for operand 0 or 2. Second, there may be only one
2464 alternative in the constraints. Third, only a single register class
2465 letter may be used for the constraint; subsequent constraint letters
2466 are ignored. As a special exception, an empty constraint string
2467 matches the @code{ALL_REGS} register class. This may relieve ports
2468 of the burden of defining an @code{ALL_REGS} constraint letter just
2471 @cindex @code{movstrict@var{m}} instruction pattern
2472 @item @samp{movstrict@var{m}}
2473 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
2474 with mode @var{m} of a register whose natural mode is wider,
2475 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
2476 any of the register except the part which belongs to mode @var{m}.
2478 @cindex @code{load_multiple} instruction pattern
2479 @item @samp{load_multiple}
2480 Load several consecutive memory locations into consecutive registers.
2481 Operand 0 is the first of the consecutive registers, operand 1
2482 is the first memory location, and operand 2 is a constant: the
2483 number of consecutive registers.
2485 Define this only if the target machine really has such an instruction;
2486 do not define this if the most efficient way of loading consecutive
2487 registers from memory is to do them one at a time.
2489 On some machines, there are restrictions as to which consecutive
2490 registers can be stored into memory, such as particular starting or
2491 ending register numbers or only a range of valid counts. For those
2492 machines, use a @code{define_expand} (@pxref{Expander Definitions})
2493 and make the pattern fail if the restrictions are not met.
2495 Write the generated insn as a @code{parallel} with elements being a
2496 @code{set} of one register from the appropriate memory location (you may
2497 also need @code{use} or @code{clobber} elements). Use a
2498 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
2499 @file{rs6000.md} for examples of the use of this insn pattern.
2501 @cindex @samp{store_multiple} instruction pattern
2502 @item @samp{store_multiple}
2503 Similar to @samp{load_multiple}, but store several consecutive registers
2504 into consecutive memory locations. Operand 0 is the first of the
2505 consecutive memory locations, operand 1 is the first register, and
2506 operand 2 is a constant: the number of consecutive registers.
2508 @cindex @code{push@var{m}} instruction pattern
2509 @item @samp{push@var{m}}
2510 Output a push instruction. Operand 0 is value to push. Used only when
2511 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
2512 missing and in such case an @code{mov} expander is used instead, with a
2513 @code{MEM} expression forming the push operation. The @code{mov} expander
2514 method is deprecated.
2516 @cindex @code{add@var{m}3} instruction pattern
2517 @item @samp{add@var{m}3}
2518 Add operand 2 and operand 1, storing the result in operand 0. All operands
2519 must have mode @var{m}. This can be used even on two-address machines, by
2520 means of constraints requiring operands 1 and 0 to be the same location.
2522 @cindex @code{sub@var{m}3} instruction pattern
2523 @cindex @code{mul@var{m}3} instruction pattern
2524 @cindex @code{div@var{m}3} instruction pattern
2525 @cindex @code{udiv@var{m}3} instruction pattern
2526 @cindex @code{mod@var{m}3} instruction pattern
2527 @cindex @code{umod@var{m}3} instruction pattern
2528 @cindex @code{smin@var{m}3} instruction pattern
2529 @cindex @code{smax@var{m}3} instruction pattern
2530 @cindex @code{umin@var{m}3} instruction pattern
2531 @cindex @code{umax@var{m}3} instruction pattern
2532 @cindex @code{and@var{m}3} instruction pattern
2533 @cindex @code{ior@var{m}3} instruction pattern
2534 @cindex @code{xor@var{m}3} instruction pattern
2535 @item @samp{sub@var{m}3}, @samp{mul@var{m}3}
2536 @itemx @samp{div@var{m}3}, @samp{udiv@var{m}3}, @samp{mod@var{m}3}, @samp{umod@var{m}3}
2537 @itemx @samp{smin@var{m}3}, @samp{smax@var{m}3}, @samp{umin@var{m}3}, @samp{umax@var{m}3}
2538 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
2539 Similar, for other arithmetic operations.
2540 @cindex @code{min@var{m}3} instruction pattern
2541 @cindex @code{max@var{m}3} instruction pattern
2542 @itemx @samp{min@var{m}3}, @samp{max@var{m}3}
2543 Floating point min and max operations. If both operands are zeros,
2544 or if either operand is NaN, then it is unspecified which of the two
2545 operands is returned as the result.
2548 @cindex @code{mulhisi3} instruction pattern
2549 @item @samp{mulhisi3}
2550 Multiply operands 1 and 2, which have mode @code{HImode}, and store
2551 a @code{SImode} product in operand 0.
2553 @cindex @code{mulqihi3} instruction pattern
2554 @cindex @code{mulsidi3} instruction pattern
2555 @item @samp{mulqihi3}, @samp{mulsidi3}
2556 Similar widening-multiplication instructions of other widths.
2558 @cindex @code{umulqihi3} instruction pattern
2559 @cindex @code{umulhisi3} instruction pattern
2560 @cindex @code{umulsidi3} instruction pattern
2561 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
2562 Similar widening-multiplication instructions that do unsigned
2565 @cindex @code{smul@var{m}3_highpart} instruction pattern
2566 @item @samp{smul@var{m}3_highpart}
2567 Perform a signed multiplication of operands 1 and 2, which have mode
2568 @var{m}, and store the most significant half of the product in operand 0.
2569 The least significant half of the product is discarded.
2571 @cindex @code{umul@var{m}3_highpart} instruction pattern
2572 @item @samp{umul@var{m}3_highpart}
2573 Similar, but the multiplication is unsigned.
2575 @cindex @code{divmod@var{m}4} instruction pattern
2576 @item @samp{divmod@var{m}4}
2577 Signed division that produces both a quotient and a remainder.
2578 Operand 1 is divided by operand 2 to produce a quotient stored
2579 in operand 0 and a remainder stored in operand 3.
2581 For machines with an instruction that produces both a quotient and a
2582 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
2583 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
2584 allows optimization in the relatively common case when both the quotient
2585 and remainder are computed.
2587 If an instruction that just produces a quotient or just a remainder
2588 exists and is more efficient than the instruction that produces both,
2589 write the output routine of @samp{divmod@var{m}4} to call
2590 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
2591 quotient or remainder and generate the appropriate instruction.
2593 @cindex @code{udivmod@var{m}4} instruction pattern
2594 @item @samp{udivmod@var{m}4}
2595 Similar, but does unsigned division.
2597 @cindex @code{ashl@var{m}3} instruction pattern
2598 @item @samp{ashl@var{m}3}
2599 Arithmetic-shift operand 1 left by a number of bits specified by operand
2600 2, and store the result in operand 0. Here @var{m} is the mode of
2601 operand 0 and operand 1; operand 2's mode is specified by the
2602 instruction pattern, and the compiler will convert the operand to that
2603 mode before generating the instruction.
2605 @cindex @code{ashr@var{m}3} instruction pattern
2606 @cindex @code{lshr@var{m}3} instruction pattern
2607 @cindex @code{rotl@var{m}3} instruction pattern
2608 @cindex @code{rotr@var{m}3} instruction pattern
2609 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
2610 Other shift and rotate instructions, analogous to the
2611 @code{ashl@var{m}3} instructions.
2613 @cindex @code{neg@var{m}2} instruction pattern
2614 @item @samp{neg@var{m}2}
2615 Negate operand 1 and store the result in operand 0.
2617 @cindex @code{abs@var{m}2} instruction pattern
2618 @item @samp{abs@var{m}2}
2619 Store the absolute value of operand 1 into operand 0.
2621 @cindex @code{sqrt@var{m}2} instruction pattern
2622 @item @samp{sqrt@var{m}2}
2623 Store the square root of operand 1 into operand 0.
2625 The @code{sqrt} built-in function of C always uses the mode which
2626 corresponds to the C data type @code{double} and the @code{sqrtf}
2627 built-in function uses the mode which corresponds to the C data
2630 @cindex @code{cos@var{m}2} instruction pattern
2631 @item @samp{cos@var{m}2}
2632 Store the cosine of operand 1 into operand 0.
2634 The @code{cos} built-in function of C always uses the mode which
2635 corresponds to the C data type @code{double} and the @code{cosf}
2636 built-in function uses the mode which corresponds to the C data
2639 @cindex @code{sin@var{m}2} instruction pattern
2640 @item @samp{sin@var{m}2}
2641 Store the sine of operand 1 into operand 0.
2643 The @code{sin} built-in function of C always uses the mode which
2644 corresponds to the C data type @code{double} and the @code{sinf}
2645 built-in function uses the mode which corresponds to the C data
2648 @cindex @code{exp@var{m}2} instruction pattern
2649 @item @samp{exp@var{m}2}
2650 Store the exponential of operand 1 into operand 0.
2652 The @code{exp} built-in function of C always uses the mode which
2653 corresponds to the C data type @code{double} and the @code{expf}
2654 built-in function uses the mode which corresponds to the C data
2657 @cindex @code{log@var{m}2} instruction pattern
2658 @item @samp{log@var{m}2}
2659 Store the natural logarithm of operand 1 into operand 0.
2661 The @code{log} built-in function of C always uses the mode which
2662 corresponds to the C data type @code{double} and the @code{logf}
2663 built-in function uses the mode which corresponds to the C data
2666 @cindex @code{pow@var{m}3} instruction pattern
2667 @item @samp{pow@var{m}3}
2668 Store the value of operand 1 raised to the exponent operand 2
2671 The @code{pow} built-in function of C always uses the mode which
2672 corresponds to the C data type @code{double} and the @code{powf}
2673 built-in function uses the mode which corresponds to the C data
2676 @cindex @code{atan2@var{m}3} instruction pattern
2677 @item @samp{atan2@var{m}3}
2678 Store the arc tangent (inverse tangent) of operand 1 divided by
2679 operand 2 into operand 0, using the signs of both arguments to
2680 determine the quadrant of the result.
2682 The @code{atan2} built-in function of C always uses the mode which
2683 corresponds to the C data type @code{double} and the @code{atan2f}
2684 built-in function uses the mode which corresponds to the C data
2687 @cindex @code{floor@var{m}2} instruction pattern
2688 @item @samp{floor@var{m}2}
2689 Store the largest integral value not greater than argument.
2691 The @code{floor} built-in function of C always uses the mode which
2692 corresponds to the C data type @code{double} and the @code{floorf}
2693 built-in function uses the mode which corresponds to the C data
2696 @cindex @code{trunc@var{m}2} instruction pattern
2697 @item @samp{trunc@var{m}2}
2698 Store the argument rounded to integer towards zero.
2700 The @code{trunc} built-in function of C always uses the mode which
2701 corresponds to the C data type @code{double} and the @code{truncf}
2702 built-in function uses the mode which corresponds to the C data
2705 @cindex @code{round@var{m}2} instruction pattern
2706 @item @samp{round@var{m}2}
2707 Store the argument rounded to integer away from zero.
2709 The @code{round} built-in function of C always uses the mode which
2710 corresponds to the C data type @code{double} and the @code{roundf}
2711 built-in function uses the mode which corresponds to the C data
2714 @cindex @code{ceil@var{m}2} instruction pattern
2715 @item @samp{ceil@var{m}2}
2716 Store the argument rounded to integer away from zero.
2718 The @code{ceil} built-in function of C always uses the mode which
2719 corresponds to the C data type @code{double} and the @code{ceilf}
2720 built-in function uses the mode which corresponds to the C data
2723 @cindex @code{nearbyint@var{m}2} instruction pattern
2724 @item @samp{nearbyint@var{m}2}
2725 Store the argument rounded according to the default rounding mode
2727 The @code{nearbyint} built-in function of C always uses the mode which
2728 corresponds to the C data type @code{double} and the @code{nearbyintf}
2729 built-in function uses the mode which corresponds to the C data
2732 @cindex @code{ffs@var{m}2} instruction pattern
2733 @item @samp{ffs@var{m}2}
2734 Store into operand 0 one plus the index of the least significant 1-bit
2735 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
2736 of operand 0; operand 1's mode is specified by the instruction
2737 pattern, and the compiler will convert the operand to that mode before
2738 generating the instruction.
2740 The @code{ffs} built-in function of C always uses the mode which
2741 corresponds to the C data type @code{int}.
2743 @cindex @code{clz@var{m}2} instruction pattern
2744 @item @samp{clz@var{m}2}
2745 Store into operand 0 the number of leading 0-bits in @var{x}, starting
2746 at the most significant bit position. If @var{x} is 0, the result is
2747 undefined. @var{m} is the mode of operand 0; operand 1's mode is
2748 specified by the instruction pattern, and the compiler will convert the
2749 operand to that mode before generating the instruction.
2751 @cindex @code{ctz@var{m}2} instruction pattern
2752 @item @samp{ctz@var{m}2}
2753 Store into operand 0 the number of trailing 0-bits in @var{x}, starting
2754 at the least significant bit position. If @var{x} is 0, the result is
2755 undefined. @var{m} is the mode of operand 0; operand 1's mode is
2756 specified by the instruction pattern, and the compiler will convert the
2757 operand to that mode before generating the instruction.
2759 @cindex @code{popcount@var{m}2} instruction pattern
2760 @item @samp{popcount@var{m}2}
2761 Store into operand 0 the number of 1-bits in @var{x}. @var{m} is the
2762 mode of operand 0; operand 1's mode is specified by the instruction
2763 pattern, and the compiler will convert the operand to that mode before
2764 generating the instruction.
2766 @cindex @code{parity@var{m}2} instruction pattern
2767 @item @samp{parity@var{m}2}
2768 Store into operand 0 the parity of @var{x}, i.@:e. the number of 1-bits
2769 in @var{x} modulo 2. @var{m} is the mode of operand 0; operand 1's mode
2770 is specified by the instruction pattern, and the compiler will convert
2771 the operand to that mode before generating the instruction.
2773 @cindex @code{one_cmpl@var{m}2} instruction pattern
2774 @item @samp{one_cmpl@var{m}2}
2775 Store the bitwise-complement of operand 1 into operand 0.
2777 @cindex @code{cmp@var{m}} instruction pattern
2778 @item @samp{cmp@var{m}}
2779 Compare operand 0 and operand 1, and set the condition codes.
2780 The RTL pattern should look like this:
2783 (set (cc0) (compare (match_operand:@var{m} 0 @dots{})
2784 (match_operand:@var{m} 1 @dots{})))
2787 @cindex @code{tst@var{m}} instruction pattern
2788 @item @samp{tst@var{m}}
2789 Compare operand 0 against zero, and set the condition codes.
2790 The RTL pattern should look like this:
2793 (set (cc0) (match_operand:@var{m} 0 @dots{}))
2796 @samp{tst@var{m}} patterns should not be defined for machines that do
2797 not use @code{(cc0)}. Doing so would confuse the optimizer since it
2798 would no longer be clear which @code{set} operations were comparisons.
2799 The @samp{cmp@var{m}} patterns should be used instead.
2801 @cindex @code{movstr@var{m}} instruction pattern
2802 @item @samp{movstr@var{m}}
2803 Block move instruction. The addresses of the destination and source
2804 strings are the first two operands, and both are in mode @code{Pmode}.
2806 The number of bytes to move is the third operand, in mode @var{m}.
2807 Usually, you specify @code{word_mode} for @var{m}. However, if you can
2808 generate better code knowing the range of valid lengths is smaller than
2809 those representable in a full word, you should provide a pattern with a
2810 mode corresponding to the range of values you can handle efficiently
2811 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
2812 that appear negative) and also a pattern with @code{word_mode}.
2814 The fourth operand is the known shared alignment of the source and
2815 destination, in the form of a @code{const_int} rtx. Thus, if the
2816 compiler knows that both source and destination are word-aligned,
2817 it may provide the value 4 for this operand.
2819 Descriptions of multiple @code{movstr@var{m}} patterns can only be
2820 beneficial if the patterns for smaller modes have fewer restrictions
2821 on their first, second and fourth operands. Note that the mode @var{m}
2822 in @code{movstr@var{m}} does not impose any restriction on the mode of
2823 individually moved data units in the block.
2825 These patterns need not give special consideration to the possibility
2826 that the source and destination strings might overlap.
2828 @cindex @code{clrstr@var{m}} instruction pattern
2829 @item @samp{clrstr@var{m}}
2830 Block clear instruction. The addresses of the destination string is the
2831 first operand, in mode @code{Pmode}. The number of bytes to clear is
2832 the second operand, in mode @var{m}. See @samp{movstr@var{m}} for
2833 a discussion of the choice of mode.
2835 The third operand is the known alignment of the destination, in the form
2836 of a @code{const_int} rtx. Thus, if the compiler knows that the
2837 destination is word-aligned, it may provide the value 4 for this
2840 The use for multiple @code{clrstr@var{m}} is as for @code{movstr@var{m}}.
2842 @cindex @code{cmpstr@var{m}} instruction pattern
2843 @item @samp{cmpstr@var{m}}
2844 String compare instruction, with five operands. Operand 0 is the output;
2845 it has mode @var{m}. The remaining four operands are like the operands
2846 of @samp{movstr@var{m}}. The two memory blocks specified are compared
2847 byte by byte in lexicographic order starting at the beginning of each
2848 string. The instruction is not allowed to prefetch more than one byte
2849 at a time since either string may end in the first byte and reading past
2850 that may access an invalid page or segment and cause a fault. The
2851 effect of the instruction is to store a value in operand 0 whose sign
2852 indicates the result of the comparison.
2854 @cindex @code{cmpmem@var{m}} instruction pattern
2855 @item @samp{cmpmem@var{m}}
2856 Block compare instruction, with five operands like the operands
2857 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
2858 byte by byte in lexicographic order starting at the beginning of each
2859 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
2860 any bytes in the two memory blocks. The effect of the instruction is
2861 to store a value in operand 0 whose sign indicates the result of the
2864 @cindex @code{strlen@var{m}} instruction pattern
2865 @item @samp{strlen@var{m}}
2866 Compute the length of a string, with three operands.
2867 Operand 0 is the result (of mode @var{m}), operand 1 is
2868 a @code{mem} referring to the first character of the string,
2869 operand 2 is the character to search for (normally zero),
2870 and operand 3 is a constant describing the known alignment
2871 of the beginning of the string.
2873 @cindex @code{float@var{mn}2} instruction pattern
2874 @item @samp{float@var{m}@var{n}2}
2875 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
2876 floating point mode @var{n} and store in operand 0 (which has mode
2879 @cindex @code{floatuns@var{mn}2} instruction pattern
2880 @item @samp{floatuns@var{m}@var{n}2}
2881 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
2882 to floating point mode @var{n} and store in operand 0 (which has mode
2885 @cindex @code{fix@var{mn}2} instruction pattern
2886 @item @samp{fix@var{m}@var{n}2}
2887 Convert operand 1 (valid for floating point mode @var{m}) to fixed
2888 point mode @var{n} as a signed number and store in operand 0 (which
2889 has mode @var{n}). This instruction's result is defined only when
2890 the value of operand 1 is an integer.
2892 @cindex @code{fixuns@var{mn}2} instruction pattern
2893 @item @samp{fixuns@var{m}@var{n}2}
2894 Convert operand 1 (valid for floating point mode @var{m}) to fixed
2895 point mode @var{n} as an unsigned number and store in operand 0 (which
2896 has mode @var{n}). This instruction's result is defined only when the
2897 value of operand 1 is an integer.
2899 @cindex @code{ftrunc@var{m}2} instruction pattern
2900 @item @samp{ftrunc@var{m}2}
2901 Convert operand 1 (valid for floating point mode @var{m}) to an
2902 integer value, still represented in floating point mode @var{m}, and
2903 store it in operand 0 (valid for floating point mode @var{m}).
2905 @cindex @code{fix_trunc@var{mn}2} instruction pattern
2906 @item @samp{fix_trunc@var{m}@var{n}2}
2907 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
2908 of mode @var{m} by converting the value to an integer.
2910 @cindex @code{fixuns_trunc@var{mn}2} instruction pattern
2911 @item @samp{fixuns_trunc@var{m}@var{n}2}
2912 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
2913 value of mode @var{m} by converting the value to an integer.
2915 @cindex @code{trunc@var{mn}2} instruction pattern
2916 @item @samp{trunc@var{m}@var{n}2}
2917 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
2918 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2919 point or both floating point.
2921 @cindex @code{extend@var{mn}2} instruction pattern
2922 @item @samp{extend@var{m}@var{n}2}
2923 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
2924 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2925 point or both floating point.
2927 @cindex @code{zero_extend@var{mn}2} instruction pattern
2928 @item @samp{zero_extend@var{m}@var{n}2}
2929 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
2930 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2933 @cindex @code{extv} instruction pattern
2935 Extract a bit-field from operand 1 (a register or memory operand), where
2936 operand 2 specifies the width in bits and operand 3 the starting bit,
2937 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
2938 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
2939 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
2940 be valid for @code{word_mode}.
2942 The RTL generation pass generates this instruction only with constants
2943 for operands 2 and 3.
2945 The bit-field value is sign-extended to a full word integer
2946 before it is stored in operand 0.
2948 @cindex @code{extzv} instruction pattern
2950 Like @samp{extv} except that the bit-field value is zero-extended.
2952 @cindex @code{insv} instruction pattern
2954 Store operand 3 (which must be valid for @code{word_mode}) into a
2955 bit-field in operand 0, where operand 1 specifies the width in bits and
2956 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
2957 @code{word_mode}; often @code{word_mode} is allowed only for registers.
2958 Operands 1 and 2 must be valid for @code{word_mode}.
2960 The RTL generation pass generates this instruction only with constants
2961 for operands 1 and 2.
2963 @cindex @code{mov@var{mode}cc} instruction pattern
2964 @item @samp{mov@var{mode}cc}
2965 Conditionally move operand 2 or operand 3 into operand 0 according to the
2966 comparison in operand 1. If the comparison is true, operand 2 is moved
2967 into operand 0, otherwise operand 3 is moved.
2969 The mode of the operands being compared need not be the same as the operands
2970 being moved. Some machines, sparc64 for example, have instructions that
2971 conditionally move an integer value based on the floating point condition
2972 codes and vice versa.
2974 If the machine does not have conditional move instructions, do not
2975 define these patterns.
2977 @cindex @code{add@var{mode}cc} instruction pattern
2978 @item @samp{add@var{mode}cc}
2979 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
2980 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
2981 comparison in operand 1. If the comparison is true, operand 2 is moved into
2982 operand 0, otherwise (operand 2 + operand 3) is moved.
2984 @cindex @code{s@var{cond}} instruction pattern
2985 @item @samp{s@var{cond}}
2986 Store zero or nonzero in the operand according to the condition codes.
2987 Value stored is nonzero iff the condition @var{cond} is true.
2988 @var{cond} is the name of a comparison operation expression code, such
2989 as @code{eq}, @code{lt} or @code{leu}.
2991 You specify the mode that the operand must have when you write the
2992 @code{match_operand} expression. The compiler automatically sees
2993 which mode you have used and supplies an operand of that mode.
2995 The value stored for a true condition must have 1 as its low bit, or
2996 else must be negative. Otherwise the instruction is not suitable and
2997 you should omit it from the machine description. You describe to the
2998 compiler exactly which value is stored by defining the macro
2999 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
3000 found that can be used for all the @samp{s@var{cond}} patterns, you
3001 should omit those operations from the machine description.
3003 These operations may fail, but should do so only in relatively
3004 uncommon cases; if they would fail for common cases involving
3005 integer comparisons, it is best to omit these patterns.
3007 If these operations are omitted, the compiler will usually generate code
3008 that copies the constant one to the target and branches around an
3009 assignment of zero to the target. If this code is more efficient than
3010 the potential instructions used for the @samp{s@var{cond}} pattern
3011 followed by those required to convert the result into a 1 or a zero in
3012 @code{SImode}, you should omit the @samp{s@var{cond}} operations from
3013 the machine description.
3015 @cindex @code{b@var{cond}} instruction pattern
3016 @item @samp{b@var{cond}}
3017 Conditional branch instruction. Operand 0 is a @code{label_ref} that
3018 refers to the label to jump to. Jump if the condition codes meet
3019 condition @var{cond}.
3021 Some machines do not follow the model assumed here where a comparison
3022 instruction is followed by a conditional branch instruction. In that
3023 case, the @samp{cmp@var{m}} (and @samp{tst@var{m}}) patterns should
3024 simply store the operands away and generate all the required insns in a
3025 @code{define_expand} (@pxref{Expander Definitions}) for the conditional
3026 branch operations. All calls to expand @samp{b@var{cond}} patterns are
3027 immediately preceded by calls to expand either a @samp{cmp@var{m}}
3028 pattern or a @samp{tst@var{m}} pattern.
3030 Machines that use a pseudo register for the condition code value, or
3031 where the mode used for the comparison depends on the condition being
3032 tested, should also use the above mechanism. @xref{Jump Patterns}.
3034 The above discussion also applies to the @samp{mov@var{mode}cc} and
3035 @samp{s@var{cond}} patterns.
3037 @cindex @code{jump} instruction pattern
3039 A jump inside a function; an unconditional branch. Operand 0 is the
3040 @code{label_ref} of the label to jump to. This pattern name is mandatory
3043 @cindex @code{call} instruction pattern
3045 Subroutine call instruction returning no value. Operand 0 is the
3046 function to call; operand 1 is the number of bytes of arguments pushed
3047 as a @code{const_int}; operand 2 is the number of registers used as
3050 On most machines, operand 2 is not actually stored into the RTL
3051 pattern. It is supplied for the sake of some RISC machines which need
3052 to put this information into the assembler code; they can put it in
3053 the RTL instead of operand 1.
3055 Operand 0 should be a @code{mem} RTX whose address is the address of the
3056 function. Note, however, that this address can be a @code{symbol_ref}
3057 expression even if it would not be a legitimate memory address on the
3058 target machine. If it is also not a valid argument for a call
3059 instruction, the pattern for this operation should be a
3060 @code{define_expand} (@pxref{Expander Definitions}) that places the
3061 address into a register and uses that register in the call instruction.
3063 @cindex @code{call_value} instruction pattern
3064 @item @samp{call_value}
3065 Subroutine call instruction returning a value. Operand 0 is the hard
3066 register in which the value is returned. There are three more
3067 operands, the same as the three operands of the @samp{call}
3068 instruction (but with numbers increased by one).
3070 Subroutines that return @code{BLKmode} objects use the @samp{call}
3073 @cindex @code{call_pop} instruction pattern
3074 @cindex @code{call_value_pop} instruction pattern
3075 @item @samp{call_pop}, @samp{call_value_pop}
3076 Similar to @samp{call} and @samp{call_value}, except used if defined and
3077 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
3078 that contains both the function call and a @code{set} to indicate the
3079 adjustment made to the frame pointer.
3081 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
3082 patterns increases the number of functions for which the frame pointer
3083 can be eliminated, if desired.
3085 @cindex @code{untyped_call} instruction pattern
3086 @item @samp{untyped_call}
3087 Subroutine call instruction returning a value of any type. Operand 0 is
3088 the function to call; operand 1 is a memory location where the result of
3089 calling the function is to be stored; operand 2 is a @code{parallel}
3090 expression where each element is a @code{set} expression that indicates
3091 the saving of a function return value into the result block.
3093 This instruction pattern should be defined to support
3094 @code{__builtin_apply} on machines where special instructions are needed
3095 to call a subroutine with arbitrary arguments or to save the value
3096 returned. This instruction pattern is required on machines that have
3097 multiple registers that can hold a return value
3098 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
3100 @cindex @code{return} instruction pattern
3102 Subroutine return instruction. This instruction pattern name should be
3103 defined only if a single instruction can do all the work of returning
3106 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
3107 RTL generation phase. In this case it is to support machines where
3108 multiple instructions are usually needed to return from a function, but
3109 some class of functions only requires one instruction to implement a
3110 return. Normally, the applicable functions are those which do not need
3111 to save any registers or allocate stack space.
3113 @findex reload_completed
3114 @findex leaf_function_p
3115 For such machines, the condition specified in this pattern should only
3116 be true when @code{reload_completed} is nonzero and the function's
3117 epilogue would only be a single instruction. For machines with register
3118 windows, the routine @code{leaf_function_p} may be used to determine if
3119 a register window push is required.
3121 Machines that have conditional return instructions should define patterns
3127 (if_then_else (match_operator
3128 0 "comparison_operator"
3129 [(cc0) (const_int 0)])
3136 where @var{condition} would normally be the same condition specified on the
3137 named @samp{return} pattern.
3139 @cindex @code{untyped_return} instruction pattern
3140 @item @samp{untyped_return}
3141 Untyped subroutine return instruction. This instruction pattern should
3142 be defined to support @code{__builtin_return} on machines where special
3143 instructions are needed to return a value of any type.
3145 Operand 0 is a memory location where the result of calling a function
3146 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
3147 expression where each element is a @code{set} expression that indicates
3148 the restoring of a function return value from the result block.
3150 @cindex @code{nop} instruction pattern
3152 No-op instruction. This instruction pattern name should always be defined
3153 to output a no-op in assembler code. @code{(const_int 0)} will do as an
3156 @cindex @code{indirect_jump} instruction pattern
3157 @item @samp{indirect_jump}
3158 An instruction to jump to an address which is operand zero.
3159 This pattern name is mandatory on all machines.
3161 @cindex @code{casesi} instruction pattern
3163 Instruction to jump through a dispatch table, including bounds checking.
3164 This instruction takes five operands:
3168 The index to dispatch on, which has mode @code{SImode}.
3171 The lower bound for indices in the table, an integer constant.
3174 The total range of indices in the table---the largest index
3175 minus the smallest one (both inclusive).
3178 A label that precedes the table itself.
3181 A label to jump to if the index has a value outside the bounds.
3182 (If the machine-description macro @code{CASE_DROPS_THROUGH} is defined,
3183 then an out-of-bounds index drops through to the code following
3184 the jump table instead of jumping to this label. In that case,
3185 this label is not actually used by the @samp{casesi} instruction,
3186 but it is always provided as an operand.)
3189 The table is a @code{addr_vec} or @code{addr_diff_vec} inside of a
3190 @code{jump_insn}. The number of elements in the table is one plus the
3191 difference between the upper bound and the lower bound.
3193 @cindex @code{tablejump} instruction pattern
3194 @item @samp{tablejump}
3195 Instruction to jump to a variable address. This is a low-level
3196 capability which can be used to implement a dispatch table when there
3197 is no @samp{casesi} pattern.
3199 This pattern requires two operands: the address or offset, and a label
3200 which should immediately precede the jump table. If the macro
3201 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
3202 operand is an offset which counts from the address of the table; otherwise,
3203 it is an absolute address to jump to. In either case, the first operand has
3206 The @samp{tablejump} insn is always the last insn before the jump
3207 table it uses. Its assembler code normally has no need to use the
3208 second operand, but you should incorporate it in the RTL pattern so
3209 that the jump optimizer will not delete the table as unreachable code.
3212 @cindex @code{decrement_and_branch_until_zero} instruction pattern
3213 @item @samp{decrement_and_branch_until_zero}
3214 Conditional branch instruction that decrements a register and
3215 jumps if the register is nonzero. Operand 0 is the register to
3216 decrement and test; operand 1 is the label to jump to if the
3217 register is nonzero. @xref{Looping Patterns}.
3219 This optional instruction pattern is only used by the combiner,
3220 typically for loops reversed by the loop optimizer when strength
3221 reduction is enabled.
3223 @cindex @code{doloop_end} instruction pattern
3224 @item @samp{doloop_end}
3225 Conditional branch instruction that decrements a register and jumps if
3226 the register is nonzero. This instruction takes five operands: Operand
3227 0 is the register to decrement and test; operand 1 is the number of loop
3228 iterations as a @code{const_int} or @code{const0_rtx} if this cannot be
3229 determined until run-time; operand 2 is the actual or estimated maximum
3230 number of iterations as a @code{const_int}; operand 3 is the number of
3231 enclosed loops as a @code{const_int} (an innermost loop has a value of
3232 1); operand 4 is the label to jump to if the register is nonzero.
3233 @xref{Looping Patterns}.
3235 This optional instruction pattern should be defined for machines with
3236 low-overhead looping instructions as the loop optimizer will try to
3237 modify suitable loops to utilize it. If nested low-overhead looping is
3238 not supported, use a @code{define_expand} (@pxref{Expander Definitions})
3239 and make the pattern fail if operand 3 is not @code{const1_rtx}.
3240 Similarly, if the actual or estimated maximum number of iterations is
3241 too large for this instruction, make it fail.
3243 @cindex @code{doloop_begin} instruction pattern
3244 @item @samp{doloop_begin}
3245 Companion instruction to @code{doloop_end} required for machines that
3246 need to perform some initialization, such as loading special registers
3247 used by a low-overhead looping instruction. If initialization insns do
3248 not always need to be emitted, use a @code{define_expand}
3249 (@pxref{Expander Definitions}) and make it fail.
3252 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
3253 @item @samp{canonicalize_funcptr_for_compare}
3254 Canonicalize the function pointer in operand 1 and store the result
3257 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
3258 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
3259 and also has mode @code{Pmode}.
3261 Canonicalization of a function pointer usually involves computing
3262 the address of the function which would be called if the function
3263 pointer were used in an indirect call.
3265 Only define this pattern if function pointers on the target machine
3266 can have different values but still call the same function when
3267 used in an indirect call.
3269 @cindex @code{save_stack_block} instruction pattern
3270 @cindex @code{save_stack_function} instruction pattern
3271 @cindex @code{save_stack_nonlocal} instruction pattern
3272 @cindex @code{restore_stack_block} instruction pattern
3273 @cindex @code{restore_stack_function} instruction pattern
3274 @cindex @code{restore_stack_nonlocal} instruction pattern
3275 @item @samp{save_stack_block}
3276 @itemx @samp{save_stack_function}
3277 @itemx @samp{save_stack_nonlocal}
3278 @itemx @samp{restore_stack_block}
3279 @itemx @samp{restore_stack_function}
3280 @itemx @samp{restore_stack_nonlocal}
3281 Most machines save and restore the stack pointer by copying it to or
3282 from an object of mode @code{Pmode}. Do not define these patterns on
3285 Some machines require special handling for stack pointer saves and
3286 restores. On those machines, define the patterns corresponding to the
3287 non-standard cases by using a @code{define_expand} (@pxref{Expander
3288 Definitions}) that produces the required insns. The three types of
3289 saves and restores are:
3293 @samp{save_stack_block} saves the stack pointer at the start of a block
3294 that allocates a variable-sized object, and @samp{restore_stack_block}
3295 restores the stack pointer when the block is exited.
3298 @samp{save_stack_function} and @samp{restore_stack_function} do a
3299 similar job for the outermost block of a function and are used when the
3300 function allocates variable-sized objects or calls @code{alloca}. Only
3301 the epilogue uses the restored stack pointer, allowing a simpler save or
3302 restore sequence on some machines.
3305 @samp{save_stack_nonlocal} is used in functions that contain labels
3306 branched to by nested functions. It saves the stack pointer in such a
3307 way that the inner function can use @samp{restore_stack_nonlocal} to
3308 restore the stack pointer. The compiler generates code to restore the
3309 frame and argument pointer registers, but some machines require saving
3310 and restoring additional data such as register window information or
3311 stack backchains. Place insns in these patterns to save and restore any
3315 When saving the stack pointer, operand 0 is the save area and operand 1
3316 is the stack pointer. The mode used to allocate the save area defaults
3317 to @code{Pmode} but you can override that choice by defining the
3318 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
3319 specify an integral mode, or @code{VOIDmode} if no save area is needed
3320 for a particular type of save (either because no save is needed or
3321 because a machine-specific save area can be used). Operand 0 is the
3322 stack pointer and operand 1 is the save area for restore operations. If
3323 @samp{save_stack_block} is defined, operand 0 must not be
3324 @code{VOIDmode} since these saves can be arbitrarily nested.
3326 A save area is a @code{mem} that is at a constant offset from
3327 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
3328 nonlocal gotos and a @code{reg} in the other two cases.
3330 @cindex @code{allocate_stack} instruction pattern
3331 @item @samp{allocate_stack}
3332 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
3333 the stack pointer to create space for dynamically allocated data.
3335 Store the resultant pointer to this space into operand 0. If you
3336 are allocating space from the main stack, do this by emitting a
3337 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
3338 If you are allocating the space elsewhere, generate code to copy the
3339 location of the space to operand 0. In the latter case, you must
3340 ensure this space gets freed when the corresponding space on the main
3343 Do not define this pattern if all that must be done is the subtraction.
3344 Some machines require other operations such as stack probes or
3345 maintaining the back chain. Define this pattern to emit those
3346 operations in addition to updating the stack pointer.
3348 @cindex @code{check_stack} instruction pattern
3349 @item @samp{check_stack}
3350 If stack checking cannot be done on your system by probing the stack with
3351 a load or store instruction (@pxref{Stack Checking}), define this pattern
3352 to perform the needed check and signaling an error if the stack
3353 has overflowed. The single operand is the location in the stack furthest
3354 from the current stack pointer that you need to validate. Normally,
3355 on machines where this pattern is needed, you would obtain the stack
3356 limit from a global or thread-specific variable or register.
3358 @cindex @code{nonlocal_goto} instruction pattern
3359 @item @samp{nonlocal_goto}
3360 Emit code to generate a non-local goto, e.g., a jump from one function
3361 to a label in an outer function. This pattern has four arguments,
3362 each representing a value to be used in the jump. The first
3363 argument is to be loaded into the frame pointer, the second is
3364 the address to branch to (code to dispatch to the actual label),
3365 the third is the address of a location where the stack is saved,
3366 and the last is the address of the label, to be placed in the
3367 location for the incoming static chain.
3369 On most machines you need not define this pattern, since GCC will
3370 already generate the correct code, which is to load the frame pointer
3371 and static chain, restore the stack (using the
3372 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
3373 to the dispatcher. You need only define this pattern if this code will
3374 not work on your machine.
3376 @cindex @code{nonlocal_goto_receiver} instruction pattern
3377 @item @samp{nonlocal_goto_receiver}
3378 This pattern, if defined, contains code needed at the target of a
3379 nonlocal goto after the code already generated by GCC@. You will not
3380 normally need to define this pattern. A typical reason why you might
3381 need this pattern is if some value, such as a pointer to a global table,
3382 must be restored when the frame pointer is restored. Note that a nonlocal
3383 goto only occurs within a unit-of-translation, so a global table pointer
3384 that is shared by all functions of a given module need not be restored.
3385 There are no arguments.
3387 @cindex @code{exception_receiver} instruction pattern
3388 @item @samp{exception_receiver}
3389 This pattern, if defined, contains code needed at the site of an
3390 exception handler that isn't needed at the site of a nonlocal goto. You
3391 will not normally need to define this pattern. A typical reason why you
3392 might need this pattern is if some value, such as a pointer to a global
3393 table, must be restored after control flow is branched to the handler of
3394 an exception. There are no arguments.
3396 @cindex @code{builtin_setjmp_setup} instruction pattern
3397 @item @samp{builtin_setjmp_setup}
3398 This pattern, if defined, contains additional code needed to initialize
3399 the @code{jmp_buf}. You will not normally need to define this pattern.
3400 A typical reason why you might need this pattern is if some value, such
3401 as a pointer to a global table, must be restored. Though it is
3402 preferred that the pointer value be recalculated if possible (given the
3403 address of a label for instance). The single argument is a pointer to
3404 the @code{jmp_buf}. Note that the buffer is five words long and that
3405 the first three are normally used by the generic mechanism.
3407 @cindex @code{builtin_setjmp_receiver} instruction pattern
3408 @item @samp{builtin_setjmp_receiver}
3409 This pattern, if defined, contains code needed at the site of an
3410 built-in setjmp that isn't needed at the site of a nonlocal goto. You
3411 will not normally need to define this pattern. A typical reason why you
3412 might need this pattern is if some value, such as a pointer to a global
3413 table, must be restored. It takes one argument, which is the label
3414 to which builtin_longjmp transfered control; this pattern may be emitted
3415 at a small offset from that label.
3417 @cindex @code{builtin_longjmp} instruction pattern
3418 @item @samp{builtin_longjmp}
3419 This pattern, if defined, performs the entire action of the longjmp.
3420 You will not normally need to define this pattern unless you also define
3421 @code{builtin_setjmp_setup}. The single argument is a pointer to the
3424 @cindex @code{eh_return} instruction pattern
3425 @item @samp{eh_return}
3426 This pattern, if defined, affects the way @code{__builtin_eh_return},
3427 and thence the call frame exception handling library routines, are
3428 built. It is intended to handle non-trivial actions needed along
3429 the abnormal return path.
3431 The address of the exception handler to which the function should return
3432 is passed as operand to this pattern. It will normally need to copied by
3433 the pattern to some special register or memory location.
3434 If the pattern needs to determine the location of the target call
3435 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
3436 if defined; it will have already been assigned.
3438 If this pattern is not defined, the default action will be to simply
3439 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
3440 that macro or this pattern needs to be defined if call frame exception
3441 handling is to be used.
3443 @cindex @code{prologue} instruction pattern
3444 @anchor{prologue instruction pattern}
3445 @item @samp{prologue}
3446 This pattern, if defined, emits RTL for entry to a function. The function
3447 entry is responsible for setting up the stack frame, initializing the frame
3448 pointer register, saving callee saved registers, etc.
3450 Using a prologue pattern is generally preferred over defining
3451 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
3453 The @code{prologue} pattern is particularly useful for targets which perform
3454 instruction scheduling.
3456 @cindex @code{epilogue} instruction pattern
3457 @anchor{epilogue instruction pattern}
3458 @item @samp{epilogue}
3459 This pattern emits RTL for exit from a function. The function
3460 exit is responsible for deallocating the stack frame, restoring callee saved
3461 registers and emitting the return instruction.
3463 Using an epilogue pattern is generally preferred over defining
3464 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
3466 The @code{epilogue} pattern is particularly useful for targets which perform
3467 instruction scheduling or which have delay slots for their return instruction.
3469 @cindex @code{sibcall_epilogue} instruction pattern
3470 @item @samp{sibcall_epilogue}
3471 This pattern, if defined, emits RTL for exit from a function without the final
3472 branch back to the calling function. This pattern will be emitted before any
3473 sibling call (aka tail call) sites.
3475 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
3476 parameter passing or any stack slots for arguments passed to the current
3479 @cindex @code{trap} instruction pattern
3481 This pattern, if defined, signals an error, typically by causing some
3482 kind of signal to be raised. Among other places, it is used by the Java
3483 front end to signal `invalid array index' exceptions.
3485 @cindex @code{conditional_trap} instruction pattern
3486 @item @samp{conditional_trap}
3487 Conditional trap instruction. Operand 0 is a piece of RTL which
3488 performs a comparison. Operand 1 is the trap code, an integer.
3490 A typical @code{conditional_trap} pattern looks like
3493 (define_insn "conditional_trap"
3494 [(trap_if (match_operator 0 "trap_operator"
3495 [(cc0) (const_int 0)])
3496 (match_operand 1 "const_int_operand" "i"))]
3501 @cindex @code{prefetch} instruction pattern
3502 @item @samp{prefetch}
3504 This pattern, if defined, emits code for a non-faulting data prefetch
3505 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
3506 is a constant 1 if the prefetch is preparing for a write to the memory
3507 address, or a constant 0 otherwise. Operand 2 is the expected degree of
3508 temporal locality of the data and is a value between 0 and 3, inclusive; 0
3509 means that the data has no temporal locality, so it need not be left in the
3510 cache after the access; 3 means that the data has a high degree of temporal
3511 locality and should be left in all levels of cache possible; 1 and 2 mean,
3512 respectively, a low or moderate degree of temporal locality.
3514 Targets that do not support write prefetches or locality hints can ignore
3515 the values of operands 1 and 2.
3520 @c Each of the following nodes are wrapped in separate
3521 @c "@ifset INTERNALS" to work around memory limits for the default
3522 @c configuration in older tetex distributions. Known to not work:
3523 @c tetex-1.0.7, known to work: tetex-2.0.2.
3525 @node Pattern Ordering
3526 @section When the Order of Patterns Matters
3527 @cindex Pattern Ordering
3528 @cindex Ordering of Patterns
3530 Sometimes an insn can match more than one instruction pattern. Then the
3531 pattern that appears first in the machine description is the one used.
3532 Therefore, more specific patterns (patterns that will match fewer things)
3533 and faster instructions (those that will produce better code when they
3534 do match) should usually go first in the description.
3536 In some cases the effect of ordering the patterns can be used to hide
3537 a pattern when it is not valid. For example, the 68000 has an
3538 instruction for converting a fullword to floating point and another
3539 for converting a byte to floating point. An instruction converting
3540 an integer to floating point could match either one. We put the
3541 pattern to convert the fullword first to make sure that one will
3542 be used rather than the other. (Otherwise a large integer might
3543 be generated as a single-byte immediate quantity, which would not work.)
3544 Instead of using this pattern ordering it would be possible to make the
3545 pattern for convert-a-byte smart enough to deal properly with any
3550 @node Dependent Patterns
3551 @section Interdependence of Patterns
3552 @cindex Dependent Patterns
3553 @cindex Interdependence of Patterns
3555 Every machine description must have a named pattern for each of the
3556 conditional branch names @samp{b@var{cond}}. The recognition template
3557 must always have the form
3561 (if_then_else (@var{cond} (cc0) (const_int 0))
3562 (label_ref (match_operand 0 "" ""))
3567 In addition, every machine description must have an anonymous pattern
3568 for each of the possible reverse-conditional branches. Their templates
3573 (if_then_else (@var{cond} (cc0) (const_int 0))
3575 (label_ref (match_operand 0 "" ""))))
3579 They are necessary because jump optimization can turn direct-conditional
3580 branches into reverse-conditional branches.
3582 It is often convenient to use the @code{match_operator} construct to
3583 reduce the number of patterns that must be specified for branches. For
3589 (if_then_else (match_operator 0 "comparison_operator"
3590 [(cc0) (const_int 0)])
3592 (label_ref (match_operand 1 "" ""))))]
3597 In some cases machines support instructions identical except for the
3598 machine mode of one or more operands. For example, there may be
3599 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
3603 (set (match_operand:SI 0 @dots{})
3604 (extend:SI (match_operand:HI 1 @dots{})))
3606 (set (match_operand:SI 0 @dots{})
3607 (extend:SI (match_operand:QI 1 @dots{})))
3611 Constant integers do not specify a machine mode, so an instruction to
3612 extend a constant value could match either pattern. The pattern it
3613 actually will match is the one that appears first in the file. For correct
3614 results, this must be the one for the widest possible mode (@code{HImode},
3615 here). If the pattern matches the @code{QImode} instruction, the results
3616 will be incorrect if the constant value does not actually fit that mode.
3618 Such instructions to extend constants are rarely generated because they are
3619 optimized away, but they do occasionally happen in nonoptimized
3622 If a constraint in a pattern allows a constant, the reload pass may
3623 replace a register with a constant permitted by the constraint in some
3624 cases. Similarly for memory references. Because of this substitution,
3625 you should not provide separate patterns for increment and decrement
3626 instructions. Instead, they should be generated from the same pattern
3627 that supports register-register add insns by examining the operands and
3628 generating the appropriate machine instruction.
3633 @section Defining Jump Instruction Patterns
3634 @cindex jump instruction patterns
3635 @cindex defining jump instruction patterns
3637 For most machines, GCC assumes that the machine has a condition code.
3638 A comparison insn sets the condition code, recording the results of both
3639 signed and unsigned comparison of the given operands. A separate branch
3640 insn tests the condition code and branches or not according its value.
3641 The branch insns come in distinct signed and unsigned flavors. Many
3642 common machines, such as the VAX, the 68000 and the 32000, work this
3645 Some machines have distinct signed and unsigned compare instructions, and
3646 only one set of conditional branch instructions. The easiest way to handle
3647 these machines is to treat them just like the others until the final stage
3648 where assembly code is written. At this time, when outputting code for the
3649 compare instruction, peek ahead at the following branch using
3650 @code{next_cc0_user (insn)}. (The variable @code{insn} refers to the insn
3651 being output, in the output-writing code in an instruction pattern.) If
3652 the RTL says that is an unsigned branch, output an unsigned compare;
3653 otherwise output a signed compare. When the branch itself is output, you
3654 can treat signed and unsigned branches identically.
3656 The reason you can do this is that GCC always generates a pair of
3657 consecutive RTL insns, possibly separated by @code{note} insns, one to
3658 set the condition code and one to test it, and keeps the pair inviolate
3661 To go with this technique, you must define the machine-description macro
3662 @code{NOTICE_UPDATE_CC} to do @code{CC_STATUS_INIT}; in other words, no
3663 compare instruction is superfluous.
3665 Some machines have compare-and-branch instructions and no condition code.
3666 A similar technique works for them. When it is time to ``output'' a
3667 compare instruction, record its operands in two static variables. When
3668 outputting the branch-on-condition-code instruction that follows, actually
3669 output a compare-and-branch instruction that uses the remembered operands.
3671 It also works to define patterns for compare-and-branch instructions.
3672 In optimizing compilation, the pair of compare and branch instructions
3673 will be combined according to these patterns. But this does not happen
3674 if optimization is not requested. So you must use one of the solutions
3675 above in addition to any special patterns you define.
3677 In many RISC machines, most instructions do not affect the condition
3678 code and there may not even be a separate condition code register. On
3679 these machines, the restriction that the definition and use of the
3680 condition code be adjacent insns is not necessary and can prevent
3681 important optimizations. For example, on the IBM RS/6000, there is a
3682 delay for taken branches unless the condition code register is set three
3683 instructions earlier than the conditional branch. The instruction
3684 scheduler cannot perform this optimization if it is not permitted to
3685 separate the definition and use of the condition code register.
3687 On these machines, do not use @code{(cc0)}, but instead use a register
3688 to represent the condition code. If there is a specific condition code
3689 register in the machine, use a hard register. If the condition code or
3690 comparison result can be placed in any general register, or if there are
3691 multiple condition registers, use a pseudo register.
3693 @findex prev_cc0_setter
3694 @findex next_cc0_user
3695 On some machines, the type of branch instruction generated may depend on
3696 the way the condition code was produced; for example, on the 68k and
3697 SPARC, setting the condition code directly from an add or subtract
3698 instruction does not clear the overflow bit the way that a test
3699 instruction does, so a different branch instruction must be used for
3700 some conditional branches. For machines that use @code{(cc0)}, the set
3701 and use of the condition code must be adjacent (separated only by
3702 @code{note} insns) allowing flags in @code{cc_status} to be used.
3703 (@xref{Condition Code}.) Also, the comparison and branch insns can be
3704 located from each other by using the functions @code{prev_cc0_setter}
3705 and @code{next_cc0_user}.
3707 However, this is not true on machines that do not use @code{(cc0)}. On
3708 those machines, no assumptions can be made about the adjacency of the
3709 compare and branch insns and the above methods cannot be used. Instead,
3710 we use the machine mode of the condition code register to record
3711 different formats of the condition code register.
3713 Registers used to store the condition code value should have a mode that
3714 is in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If
3715 additional modes are required (as for the add example mentioned above in
3716 the SPARC), define the macro @code{EXTRA_CC_MODES} to list the
3717 additional modes required (@pxref{Condition Code}). Also define
3718 @code{SELECT_CC_MODE} to choose a mode given an operand of a compare.
3720 If it is known during RTL generation that a different mode will be
3721 required (for example, if the machine has separate compare instructions
3722 for signed and unsigned quantities, like most IBM processors), they can
3723 be specified at that time.
3725 If the cases that require different modes would be made by instruction
3726 combination, the macro @code{SELECT_CC_MODE} determines which machine
3727 mode should be used for the comparison result. The patterns should be
3728 written using that mode. To support the case of the add on the SPARC
3729 discussed above, we have the pattern
3733 [(set (reg:CC_NOOV 0)
3735 (plus:SI (match_operand:SI 0 "register_operand" "%r")
3736 (match_operand:SI 1 "arith_operand" "rI"))
3742 The @code{SELECT_CC_MODE} macro on the SPARC returns @code{CC_NOOVmode}
3743 for comparisons whose argument is a @code{plus}.
3747 @node Looping Patterns
3748 @section Defining Looping Instruction Patterns
3749 @cindex looping instruction patterns
3750 @cindex defining looping instruction patterns
3752 Some machines have special jump instructions that can be utilized to
3753 make loops more efficient. A common example is the 68000 @samp{dbra}
3754 instruction which performs a decrement of a register and a branch if the
3755 result was greater than zero. Other machines, in particular digital
3756 signal processors (DSPs), have special block repeat instructions to
3757 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
3758 DSPs have a block repeat instruction that loads special registers to
3759 mark the top and end of a loop and to count the number of loop
3760 iterations. This avoids the need for fetching and executing a
3761 @samp{dbra}-like instruction and avoids pipeline stalls associated with
3764 GCC has three special named patterns to support low overhead looping.
3765 They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
3766 and @samp{doloop_end}. The first pattern,
3767 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
3768 generation but may be emitted during the instruction combination phase.
3769 This requires the assistance of the loop optimizer, using information
3770 collected during strength reduction, to reverse a loop to count down to
3771 zero. Some targets also require the loop optimizer to add a
3772 @code{REG_NONNEG} note to indicate that the iteration count is always
3773 positive. This is needed if the target performs a signed loop
3774 termination test. For example, the 68000 uses a pattern similar to the
3775 following for its @code{dbra} instruction:
3779 (define_insn "decrement_and_branch_until_zero"
3782 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
3785 (label_ref (match_operand 1 "" ""))
3788 (plus:SI (match_dup 0)
3790 "find_reg_note (insn, REG_NONNEG, 0)"
3795 Note that since the insn is both a jump insn and has an output, it must
3796 deal with its own reloads, hence the `m' constraints. Also note that
3797 since this insn is generated by the instruction combination phase
3798 combining two sequential insns together into an implicit parallel insn,
3799 the iteration counter needs to be biased by the same amount as the
3800 decrement operation, in this case @minus{}1. Note that the following similar
3801 pattern will not be matched by the combiner.
3805 (define_insn "decrement_and_branch_until_zero"
3808 (ge (match_operand:SI 0 "general_operand" "+d*am")
3810 (label_ref (match_operand 1 "" ""))
3813 (plus:SI (match_dup 0)
3815 "find_reg_note (insn, REG_NONNEG, 0)"
3820 The other two special looping patterns, @samp{doloop_begin} and
3821 @samp{doloop_end}, are emitted by the loop optimizer for certain
3822 well-behaved loops with a finite number of loop iterations using
3823 information collected during strength reduction.
3825 The @samp{doloop_end} pattern describes the actual looping instruction
3826 (or the implicit looping operation) and the @samp{doloop_begin} pattern
3827 is an optional companion pattern that can be used for initialization
3828 needed for some low-overhead looping instructions.
3830 Note that some machines require the actual looping instruction to be
3831 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
3832 the true RTL for a looping instruction at the top of the loop can cause
3833 problems with flow analysis. So instead, a dummy @code{doloop} insn is
3834 emitted at the end of the loop. The machine dependent reorg pass checks
3835 for the presence of this @code{doloop} insn and then searches back to
3836 the top of the loop, where it inserts the true looping insn (provided
3837 there are no instructions in the loop which would cause problems). Any
3838 additional labels can be emitted at this point. In addition, if the
3839 desired special iteration counter register was not allocated, this
3840 machine dependent reorg pass could emit a traditional compare and jump
3843 The essential difference between the
3844 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
3845 patterns is that the loop optimizer allocates an additional pseudo
3846 register for the latter as an iteration counter. This pseudo register
3847 cannot be used within the loop (i.e., general induction variables cannot
3848 be derived from it), however, in many cases the loop induction variable
3849 may become redundant and removed by the flow pass.
3854 @node Insn Canonicalizations
3855 @section Canonicalization of Instructions
3856 @cindex canonicalization of instructions
3857 @cindex insn canonicalization
3859 There are often cases where multiple RTL expressions could represent an
3860 operation performed by a single machine instruction. This situation is
3861 most commonly encountered with logical, branch, and multiply-accumulate
3862 instructions. In such cases, the compiler attempts to convert these
3863 multiple RTL expressions into a single canonical form to reduce the
3864 number of insn patterns required.
3866 In addition to algebraic simplifications, following canonicalizations
3871 For commutative and comparison operators, a constant is always made the
3872 second operand. If a machine only supports a constant as the second
3873 operand, only patterns that match a constant in the second operand need
3876 @cindex @code{neg}, canonicalization of
3877 @cindex @code{not}, canonicalization of
3878 @cindex @code{mult}, canonicalization of
3879 @cindex @code{plus}, canonicalization of
3880 @cindex @code{minus}, canonicalization of
3881 For these operators, if only one operand is a @code{neg}, @code{not},
3882 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
3886 In combinations of @code{neg}, @code{mult}, @code{plus}, and
3887 @code{minus}, the @code{neg} operations (if any) will be moved inside
3888 the operations as far as possible. For instance,
3889 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
3890 @code{(plus (mult (neg A) B) C)} is canonicalized as
3891 @code{(minus A (mult B C))}.
3893 @cindex @code{compare}, canonicalization of
3895 For the @code{compare} operator, a constant is always the second operand
3896 on machines where @code{cc0} is used (@pxref{Jump Patterns}). On other
3897 machines, there are rare cases where the compiler might want to construct
3898 a @code{compare} with a constant as the first operand. However, these
3899 cases are not common enough for it to be worthwhile to provide a pattern
3900 matching a constant as the first operand unless the machine actually has
3901 such an instruction.
3903 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
3904 @code{minus} is made the first operand under the same conditions as
3908 @code{(minus @var{x} (const_int @var{n}))} is converted to
3909 @code{(plus @var{x} (const_int @var{-n}))}.
3912 Within address computations (i.e., inside @code{mem}), a left shift is
3913 converted into the appropriate multiplication by a power of two.
3915 @cindex @code{ior}, canonicalization of
3916 @cindex @code{and}, canonicalization of
3917 @cindex De Morgan's law
3919 De`Morgan's Law is used to move bitwise negation inside a bitwise
3920 logical-and or logical-or operation. If this results in only one
3921 operand being a @code{not} expression, it will be the first one.
3923 A machine that has an instruction that performs a bitwise logical-and of one
3924 operand with the bitwise negation of the other should specify the pattern
3925 for that instruction as
3929 [(set (match_operand:@var{m} 0 @dots{})
3930 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
3931 (match_operand:@var{m} 2 @dots{})))]
3937 Similarly, a pattern for a ``NAND'' instruction should be written
3941 [(set (match_operand:@var{m} 0 @dots{})
3942 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
3943 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
3948 In both cases, it is not necessary to include patterns for the many
3949 logically equivalent RTL expressions.
3951 @cindex @code{xor}, canonicalization of
3953 The only possible RTL expressions involving both bitwise exclusive-or
3954 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
3955 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
3958 The sum of three items, one of which is a constant, will only appear in
3962 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
3966 On machines that do not use @code{cc0},
3967 @code{(compare @var{x} (const_int 0))} will be converted to
3970 @cindex @code{zero_extract}, canonicalization of
3971 @cindex @code{sign_extract}, canonicalization of
3973 Equality comparisons of a group of bits (usually a single bit) with zero
3974 will be written using @code{zero_extract} rather than the equivalent
3975 @code{and} or @code{sign_extract} operations.
3981 @node Expander Definitions
3982 @section Defining RTL Sequences for Code Generation
3983 @cindex expander definitions
3984 @cindex code generation RTL sequences
3985 @cindex defining RTL sequences for code generation
3987 On some target machines, some standard pattern names for RTL generation
3988 cannot be handled with single insn, but a sequence of RTL insns can
3989 represent them. For these target machines, you can write a
3990 @code{define_expand} to specify how to generate the sequence of RTL@.
3992 @findex define_expand
3993 A @code{define_expand} is an RTL expression that looks almost like a
3994 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
3995 only for RTL generation and it can produce more than one RTL insn.
3997 A @code{define_expand} RTX has four operands:
4001 The name. Each @code{define_expand} must have a name, since the only
4002 use for it is to refer to it by name.
4005 The RTL template. This is a vector of RTL expressions representing
4006 a sequence of separate instructions. Unlike @code{define_insn}, there
4007 is no implicit surrounding @code{PARALLEL}.
4010 The condition, a string containing a C expression. This expression is
4011 used to express how the availability of this pattern depends on
4012 subclasses of target machine, selected by command-line options when GCC
4013 is run. This is just like the condition of a @code{define_insn} that
4014 has a standard name. Therefore, the condition (if present) may not
4015 depend on the data in the insn being matched, but only the
4016 target-machine-type flags. The compiler needs to test these conditions
4017 during initialization in order to learn exactly which named instructions
4018 are available in a particular run.
4021 The preparation statements, a string containing zero or more C
4022 statements which are to be executed before RTL code is generated from
4025 Usually these statements prepare temporary registers for use as
4026 internal operands in the RTL template, but they can also generate RTL
4027 insns directly by calling routines such as @code{emit_insn}, etc.
4028 Any such insns precede the ones that come from the RTL template.
4031 Every RTL insn emitted by a @code{define_expand} must match some
4032 @code{define_insn} in the machine description. Otherwise, the compiler
4033 will crash when trying to generate code for the insn or trying to optimize
4036 The RTL template, in addition to controlling generation of RTL insns,
4037 also describes the operands that need to be specified when this pattern
4038 is used. In particular, it gives a predicate for each operand.
4040 A true operand, which needs to be specified in order to generate RTL from
4041 the pattern, should be described with a @code{match_operand} in its first
4042 occurrence in the RTL template. This enters information on the operand's
4043 predicate into the tables that record such things. GCC uses the
4044 information to preload the operand into a register if that is required for
4045 valid RTL code. If the operand is referred to more than once, subsequent
4046 references should use @code{match_dup}.
4048 The RTL template may also refer to internal ``operands'' which are
4049 temporary registers or labels used only within the sequence made by the
4050 @code{define_expand}. Internal operands are substituted into the RTL
4051 template with @code{match_dup}, never with @code{match_operand}. The
4052 values of the internal operands are not passed in as arguments by the
4053 compiler when it requests use of this pattern. Instead, they are computed
4054 within the pattern, in the preparation statements. These statements
4055 compute the values and store them into the appropriate elements of
4056 @code{operands} so that @code{match_dup} can find them.
4058 There are two special macros defined for use in the preparation statements:
4059 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
4066 Use the @code{DONE} macro to end RTL generation for the pattern. The
4067 only RTL insns resulting from the pattern on this occasion will be
4068 those already emitted by explicit calls to @code{emit_insn} within the
4069 preparation statements; the RTL template will not be generated.
4073 Make the pattern fail on this occasion. When a pattern fails, it means
4074 that the pattern was not truly available. The calling routines in the
4075 compiler will try other strategies for code generation using other patterns.
4077 Failure is currently supported only for binary (addition, multiplication,
4078 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
4082 If the preparation falls through (invokes neither @code{DONE} nor
4083 @code{FAIL}), then the @code{define_expand} acts like a
4084 @code{define_insn} in that the RTL template is used to generate the
4087 The RTL template is not used for matching, only for generating the
4088 initial insn list. If the preparation statement always invokes
4089 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
4090 list of operands, such as this example:
4094 (define_expand "addsi3"
4095 [(match_operand:SI 0 "register_operand" "")
4096 (match_operand:SI 1 "register_operand" "")
4097 (match_operand:SI 2 "register_operand" "")]
4103 handle_add (operands[0], operands[1], operands[2]);
4109 Here is an example, the definition of left-shift for the SPUR chip:
4113 (define_expand "ashlsi3"
4114 [(set (match_operand:SI 0 "register_operand" "")
4118 (match_operand:SI 1 "register_operand" "")
4119 (match_operand:SI 2 "nonmemory_operand" "")))]
4128 if (GET_CODE (operands[2]) != CONST_INT
4129 || (unsigned) INTVAL (operands[2]) > 3)
4136 This example uses @code{define_expand} so that it can generate an RTL insn
4137 for shifting when the shift-count is in the supported range of 0 to 3 but
4138 fail in other cases where machine insns aren't available. When it fails,
4139 the compiler tries another strategy using different patterns (such as, a
4142 If the compiler were able to handle nontrivial condition-strings in
4143 patterns with names, then it would be possible to use a
4144 @code{define_insn} in that case. Here is another case (zero-extension
4145 on the 68000) which makes more use of the power of @code{define_expand}:
4148 (define_expand "zero_extendhisi2"
4149 [(set (match_operand:SI 0 "general_operand" "")
4151 (set (strict_low_part
4155 (match_operand:HI 1 "general_operand" ""))]
4157 "operands[1] = make_safe_from (operands[1], operands[0]);")
4161 @findex make_safe_from
4162 Here two RTL insns are generated, one to clear the entire output operand
4163 and the other to copy the input operand into its low half. This sequence
4164 is incorrect if the input operand refers to [the old value of] the output
4165 operand, so the preparation statement makes sure this isn't so. The
4166 function @code{make_safe_from} copies the @code{operands[1]} into a
4167 temporary register if it refers to @code{operands[0]}. It does this
4168 by emitting another RTL insn.
4170 Finally, a third example shows the use of an internal operand.
4171 Zero-extension on the SPUR chip is done by @code{and}-ing the result
4172 against a halfword mask. But this mask cannot be represented by a
4173 @code{const_int} because the constant value is too large to be legitimate
4174 on this machine. So it must be copied into a register with
4175 @code{force_reg} and then the register used in the @code{and}.
4178 (define_expand "zero_extendhisi2"
4179 [(set (match_operand:SI 0 "register_operand" "")
4181 (match_operand:HI 1 "register_operand" "")
4186 = force_reg (SImode, GEN_INT (65535)); ")
4189 @strong{Note:} If the @code{define_expand} is used to serve a
4190 standard binary or unary arithmetic operation or a bit-field operation,
4191 then the last insn it generates must not be a @code{code_label},
4192 @code{barrier} or @code{note}. It must be an @code{insn},
4193 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
4194 at the end, emit an insn to copy the result of the operation into
4195 itself. Such an insn will generate no code, but it can avoid problems
4200 @node Insn Splitting
4201 @section Defining How to Split Instructions
4202 @cindex insn splitting
4203 @cindex instruction splitting
4204 @cindex splitting instructions
4206 There are two cases where you should specify how to split a pattern
4207 into multiple insns. On machines that have instructions requiring
4208 delay slots (@pxref{Delay Slots}) or that have instructions whose
4209 output is not available for multiple cycles (@pxref{Processor pipeline
4210 description}), the compiler phases that optimize these cases need to
4211 be able to move insns into one-instruction delay slots. However, some
4212 insns may generate more than one machine instruction. These insns
4213 cannot be placed into a delay slot.
4215 Often you can rewrite the single insn as a list of individual insns,
4216 each corresponding to one machine instruction. The disadvantage of
4217 doing so is that it will cause the compilation to be slower and require
4218 more space. If the resulting insns are too complex, it may also
4219 suppress some optimizations. The compiler splits the insn if there is a
4220 reason to believe that it might improve instruction or delay slot
4223 The insn combiner phase also splits putative insns. If three insns are
4224 merged into one insn with a complex expression that cannot be matched by
4225 some @code{define_insn} pattern, the combiner phase attempts to split
4226 the complex pattern into two insns that are recognized. Usually it can
4227 break the complex pattern into two patterns by splitting out some
4228 subexpression. However, in some other cases, such as performing an
4229 addition of a large constant in two insns on a RISC machine, the way to
4230 split the addition into two insns is machine-dependent.
4232 @findex define_split
4233 The @code{define_split} definition tells the compiler how to split a
4234 complex insn into several simpler insns. It looks like this:
4238 [@var{insn-pattern}]
4240 [@var{new-insn-pattern-1}
4241 @var{new-insn-pattern-2}
4243 "@var{preparation-statements}")
4246 @var{insn-pattern} is a pattern that needs to be split and
4247 @var{condition} is the final condition to be tested, as in a
4248 @code{define_insn}. When an insn matching @var{insn-pattern} and
4249 satisfying @var{condition} is found, it is replaced in the insn list
4250 with the insns given by @var{new-insn-pattern-1},
4251 @var{new-insn-pattern-2}, etc.
4253 The @var{preparation-statements} are similar to those statements that
4254 are specified for @code{define_expand} (@pxref{Expander Definitions})
4255 and are executed before the new RTL is generated to prepare for the
4256 generated code or emit some insns whose pattern is not fixed. Unlike
4257 those in @code{define_expand}, however, these statements must not
4258 generate any new pseudo-registers. Once reload has completed, they also
4259 must not allocate any space in the stack frame.
4261 Patterns are matched against @var{insn-pattern} in two different
4262 circumstances. If an insn needs to be split for delay slot scheduling
4263 or insn scheduling, the insn is already known to be valid, which means
4264 that it must have been matched by some @code{define_insn} and, if
4265 @code{reload_completed} is nonzero, is known to satisfy the constraints
4266 of that @code{define_insn}. In that case, the new insn patterns must
4267 also be insns that are matched by some @code{define_insn} and, if
4268 @code{reload_completed} is nonzero, must also satisfy the constraints
4269 of those definitions.
4271 As an example of this usage of @code{define_split}, consider the following
4272 example from @file{a29k.md}, which splits a @code{sign_extend} from
4273 @code{HImode} to @code{SImode} into a pair of shift insns:
4277 [(set (match_operand:SI 0 "gen_reg_operand" "")
4278 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
4281 (ashift:SI (match_dup 1)
4284 (ashiftrt:SI (match_dup 0)
4287 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
4290 When the combiner phase tries to split an insn pattern, it is always the
4291 case that the pattern is @emph{not} matched by any @code{define_insn}.
4292 The combiner pass first tries to split a single @code{set} expression
4293 and then the same @code{set} expression inside a @code{parallel}, but
4294 followed by a @code{clobber} of a pseudo-reg to use as a scratch
4295 register. In these cases, the combiner expects exactly two new insn
4296 patterns to be generated. It will verify that these patterns match some
4297 @code{define_insn} definitions, so you need not do this test in the
4298 @code{define_split} (of course, there is no point in writing a
4299 @code{define_split} that will never produce insns that match).
4301 Here is an example of this use of @code{define_split}, taken from
4306 [(set (match_operand:SI 0 "gen_reg_operand" "")
4307 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
4308 (match_operand:SI 2 "non_add_cint_operand" "")))]
4310 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
4311 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
4314 int low = INTVAL (operands[2]) & 0xffff;
4315 int high = (unsigned) INTVAL (operands[2]) >> 16;
4318 high++, low |= 0xffff0000;
4320 operands[3] = GEN_INT (high << 16);
4321 operands[4] = GEN_INT (low);
4325 Here the predicate @code{non_add_cint_operand} matches any
4326 @code{const_int} that is @emph{not} a valid operand of a single add
4327 insn. The add with the smaller displacement is written so that it
4328 can be substituted into the address of a subsequent operation.
4330 An example that uses a scratch register, from the same file, generates
4331 an equality comparison of a register and a large constant:
4335 [(set (match_operand:CC 0 "cc_reg_operand" "")
4336 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
4337 (match_operand:SI 2 "non_short_cint_operand" "")))
4338 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
4339 "find_single_use (operands[0], insn, 0)
4340 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
4341 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
4342 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
4343 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
4346 /* Get the constant we are comparing against, C, and see what it
4347 looks like sign-extended to 16 bits. Then see what constant
4348 could be XOR'ed with C to get the sign-extended value. */
4350 int c = INTVAL (operands[2]);
4351 int sextc = (c << 16) >> 16;
4352 int xorv = c ^ sextc;
4354 operands[4] = GEN_INT (xorv);
4355 operands[5] = GEN_INT (sextc);
4359 To avoid confusion, don't write a single @code{define_split} that
4360 accepts some insns that match some @code{define_insn} as well as some
4361 insns that don't. Instead, write two separate @code{define_split}
4362 definitions, one for the insns that are valid and one for the insns that
4365 The splitter is allowed to split jump instructions into sequence of
4366 jumps or create new jumps in while splitting non-jump instructions. As
4367 the central flowgraph and branch prediction information needs to be updated,
4368 several restriction apply.
4370 Splitting of jump instruction into sequence that over by another jump
4371 instruction is always valid, as compiler expect identical behavior of new
4372 jump. When new sequence contains multiple jump instructions or new labels,
4373 more assistance is needed. Splitter is required to create only unconditional
4374 jumps, or simple conditional jump instructions. Additionally it must attach a
4375 @code{REG_BR_PROB} note to each conditional jump. A global variable
4376 @code{split_branch_probability} hold the probability of original branch in case
4377 it was an simple conditional jump, @minus{}1 otherwise. To simplify
4378 recomputing of edge frequencies, new sequence is required to have only
4379 forward jumps to the newly created labels.
4381 @findex define_insn_and_split
4382 For the common case where the pattern of a define_split exactly matches the
4383 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
4387 (define_insn_and_split
4388 [@var{insn-pattern}]
4390 "@var{output-template}"
4391 "@var{split-condition}"
4392 [@var{new-insn-pattern-1}
4393 @var{new-insn-pattern-2}
4395 "@var{preparation-statements}"
4396 [@var{insn-attributes}])
4400 @var{insn-pattern}, @var{condition}, @var{output-template}, and
4401 @var{insn-attributes} are used as in @code{define_insn}. The
4402 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
4403 in a @code{define_split}. The @var{split-condition} is also used as in
4404 @code{define_split}, with the additional behavior that if the condition starts
4405 with @samp{&&}, the condition used for the split will be the constructed as a
4406 logical ``and'' of the split condition with the insn condition. For example,
4410 (define_insn_and_split "zero_extendhisi2_and"
4411 [(set (match_operand:SI 0 "register_operand" "=r")
4412 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
4413 (clobber (reg:CC 17))]
4414 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
4416 "&& reload_completed"
4417 [(parallel [(set (match_dup 0)
4418 (and:SI (match_dup 0) (const_int 65535)))
4419 (clobber (reg:CC 17))])]
4421 [(set_attr "type" "alu1")])
4425 In this case, the actual split condition will be
4426 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
4428 The @code{define_insn_and_split} construction provides exactly the same
4429 functionality as two separate @code{define_insn} and @code{define_split}
4430 patterns. It exists for compactness, and as a maintenance tool to prevent
4431 having to ensure the two patterns' templates match.
4435 @node Including Patterns
4436 @section Including Patterns in Machine Descriptions.
4437 @cindex insn includes
4440 The @code{include} pattern tells the compiler tools where to
4441 look for patterns that are in files other than in the file
4442 @file{.md}. This is used only at build time and there is no preprocessing allowed.
4456 (include "filestuff")
4460 Where @var{pathname} is a string that specifies the location of the file,
4461 specifies the include file to be in @file{gcc/config/target/filestuff}. The
4462 directory @file{gcc/config/target} is regarded as the default directory.
4465 Machine descriptions may be split up into smaller more manageable subsections
4466 and placed into subdirectories.
4472 (include "BOGUS/filestuff")
4476 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
4478 Specifying an absolute path for the include file such as;
4481 (include "/u2/BOGUS/filestuff")
4484 is permitted but is not encouraged.
4486 @subsection RTL Generation Tool Options for Directory Search
4487 @cindex directory options .md
4488 @cindex options, directory search
4489 @cindex search options
4491 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
4496 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
4501 Add the directory @var{dir} to the head of the list of directories to be
4502 searched for header files. This can be used to override a system machine definition
4503 file, substituting your own version, since these directories are
4504 searched before the default machine description file directories. If you use more than
4505 one @option{-I} option, the directories are scanned in left-to-right
4506 order; the standard default directory come after.
4511 @node Peephole Definitions
4512 @section Machine-Specific Peephole Optimizers
4513 @cindex peephole optimizer definitions
4514 @cindex defining peephole optimizers
4516 In addition to instruction patterns the @file{md} file may contain
4517 definitions of machine-specific peephole optimizations.
4519 The combiner does not notice certain peephole optimizations when the data
4520 flow in the program does not suggest that it should try them. For example,
4521 sometimes two consecutive insns related in purpose can be combined even
4522 though the second one does not appear to use a register computed in the
4523 first one. A machine-specific peephole optimizer can detect such
4526 There are two forms of peephole definitions that may be used. The
4527 original @code{define_peephole} is run at assembly output time to
4528 match insns and substitute assembly text. Use of @code{define_peephole}
4531 A newer @code{define_peephole2} matches insns and substitutes new
4532 insns. The @code{peephole2} pass is run after register allocation
4533 but before scheduling, which may result in much better code for
4534 targets that do scheduling.
4537 * define_peephole:: RTL to Text Peephole Optimizers
4538 * define_peephole2:: RTL to RTL Peephole Optimizers
4543 @node define_peephole
4544 @subsection RTL to Text Peephole Optimizers
4545 @findex define_peephole
4548 A definition looks like this:
4552 [@var{insn-pattern-1}
4553 @var{insn-pattern-2}
4557 "@var{optional-insn-attributes}")
4561 The last string operand may be omitted if you are not using any
4562 machine-specific information in this machine description. If present,
4563 it must obey the same rules as in a @code{define_insn}.
4565 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
4566 consecutive insns. The optimization applies to a sequence of insns when
4567 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
4568 the next, and so on.
4570 Each of the insns matched by a peephole must also match a
4571 @code{define_insn}. Peepholes are checked only at the last stage just
4572 before code generation, and only optionally. Therefore, any insn which
4573 would match a peephole but no @code{define_insn} will cause a crash in code
4574 generation in an unoptimized compilation, or at various optimization
4577 The operands of the insns are matched with @code{match_operands},
4578 @code{match_operator}, and @code{match_dup}, as usual. What is not
4579 usual is that the operand numbers apply to all the insn patterns in the
4580 definition. So, you can check for identical operands in two insns by
4581 using @code{match_operand} in one insn and @code{match_dup} in the
4584 The operand constraints used in @code{match_operand} patterns do not have
4585 any direct effect on the applicability of the peephole, but they will
4586 be validated afterward, so make sure your constraints are general enough
4587 to apply whenever the peephole matches. If the peephole matches
4588 but the constraints are not satisfied, the compiler will crash.
4590 It is safe to omit constraints in all the operands of the peephole; or
4591 you can write constraints which serve as a double-check on the criteria
4594 Once a sequence of insns matches the patterns, the @var{condition} is
4595 checked. This is a C expression which makes the final decision whether to
4596 perform the optimization (we do so if the expression is nonzero). If
4597 @var{condition} is omitted (in other words, the string is empty) then the
4598 optimization is applied to every sequence of insns that matches the
4601 The defined peephole optimizations are applied after register allocation
4602 is complete. Therefore, the peephole definition can check which
4603 operands have ended up in which kinds of registers, just by looking at
4606 @findex prev_active_insn
4607 The way to refer to the operands in @var{condition} is to write
4608 @code{operands[@var{i}]} for operand number @var{i} (as matched by
4609 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
4610 to refer to the last of the insns being matched; use
4611 @code{prev_active_insn} to find the preceding insns.
4613 @findex dead_or_set_p
4614 When optimizing computations with intermediate results, you can use
4615 @var{condition} to match only when the intermediate results are not used
4616 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
4617 @var{op})}, where @var{insn} is the insn in which you expect the value
4618 to be used for the last time (from the value of @code{insn}, together
4619 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
4620 value (from @code{operands[@var{i}]}).
4622 Applying the optimization means replacing the sequence of insns with one
4623 new insn. The @var{template} controls ultimate output of assembler code
4624 for this combined insn. It works exactly like the template of a
4625 @code{define_insn}. Operand numbers in this template are the same ones
4626 used in matching the original sequence of insns.
4628 The result of a defined peephole optimizer does not need to match any of
4629 the insn patterns in the machine description; it does not even have an
4630 opportunity to match them. The peephole optimizer definition itself serves
4631 as the insn pattern to control how the insn is output.
4633 Defined peephole optimizers are run as assembler code is being output,
4634 so the insns they produce are never combined or rearranged in any way.
4636 Here is an example, taken from the 68000 machine description:
4640 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
4641 (set (match_operand:DF 0 "register_operand" "=f")
4642 (match_operand:DF 1 "register_operand" "ad"))]
4643 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
4646 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4648 output_asm_insn ("move.l %1,(sp)", xoperands);
4649 output_asm_insn ("move.l %1,-(sp)", operands);
4650 return "fmove.d (sp)+,%0";
4652 output_asm_insn ("movel %1,sp@@", xoperands);
4653 output_asm_insn ("movel %1,sp@@-", operands);
4654 return "fmoved sp@@+,%0";
4660 The effect of this optimization is to change
4686 If a peephole matches a sequence including one or more jump insns, you must
4687 take account of the flags such as @code{CC_REVERSED} which specify that the
4688 condition codes are represented in an unusual manner. The compiler
4689 automatically alters any ordinary conditional jumps which occur in such
4690 situations, but the compiler cannot alter jumps which have been replaced by
4691 peephole optimizations. So it is up to you to alter the assembler code
4692 that the peephole produces. Supply C code to write the assembler output,
4693 and in this C code check the condition code status flags and change the
4694 assembler code as appropriate.
4697 @var{insn-pattern-1} and so on look @emph{almost} like the second
4698 operand of @code{define_insn}. There is one important difference: the
4699 second operand of @code{define_insn} consists of one or more RTX's
4700 enclosed in square brackets. Usually, there is only one: then the same
4701 action can be written as an element of a @code{define_peephole}. But
4702 when there are multiple actions in a @code{define_insn}, they are
4703 implicitly enclosed in a @code{parallel}. Then you must explicitly
4704 write the @code{parallel}, and the square brackets within it, in the
4705 @code{define_peephole}. Thus, if an insn pattern looks like this,
4708 (define_insn "divmodsi4"
4709 [(set (match_operand:SI 0 "general_operand" "=d")
4710 (div:SI (match_operand:SI 1 "general_operand" "0")
4711 (match_operand:SI 2 "general_operand" "dmsK")))
4712 (set (match_operand:SI 3 "general_operand" "=d")
4713 (mod:SI (match_dup 1) (match_dup 2)))]
4715 "divsl%.l %2,%3:%0")
4719 then the way to mention this insn in a peephole is as follows:
4725 [(set (match_operand:SI 0 "general_operand" "=d")
4726 (div:SI (match_operand:SI 1 "general_operand" "0")
4727 (match_operand:SI 2 "general_operand" "dmsK")))
4728 (set (match_operand:SI 3 "general_operand" "=d")
4729 (mod:SI (match_dup 1) (match_dup 2)))])
4736 @node define_peephole2
4737 @subsection RTL to RTL Peephole Optimizers
4738 @findex define_peephole2
4740 The @code{define_peephole2} definition tells the compiler how to
4741 substitute one sequence of instructions for another sequence,
4742 what additional scratch registers may be needed and what their
4747 [@var{insn-pattern-1}
4748 @var{insn-pattern-2}
4751 [@var{new-insn-pattern-1}
4752 @var{new-insn-pattern-2}
4754 "@var{preparation-statements}")
4757 The definition is almost identical to @code{define_split}
4758 (@pxref{Insn Splitting}) except that the pattern to match is not a
4759 single instruction, but a sequence of instructions.
4761 It is possible to request additional scratch registers for use in the
4762 output template. If appropriate registers are not free, the pattern
4763 will simply not match.
4765 @findex match_scratch
4767 Scratch registers are requested with a @code{match_scratch} pattern at
4768 the top level of the input pattern. The allocated register (initially) will
4769 be dead at the point requested within the original sequence. If the scratch
4770 is used at more than a single point, a @code{match_dup} pattern at the
4771 top level of the input pattern marks the last position in the input sequence
4772 at which the register must be available.
4774 Here is an example from the IA-32 machine description:
4778 [(match_scratch:SI 2 "r")
4779 (parallel [(set (match_operand:SI 0 "register_operand" "")
4780 (match_operator:SI 3 "arith_or_logical_operator"
4782 (match_operand:SI 1 "memory_operand" "")]))
4783 (clobber (reg:CC 17))])]
4784 "! optimize_size && ! TARGET_READ_MODIFY"
4785 [(set (match_dup 2) (match_dup 1))
4786 (parallel [(set (match_dup 0)
4787 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
4788 (clobber (reg:CC 17))])]
4793 This pattern tries to split a load from its use in the hopes that we'll be
4794 able to schedule around the memory load latency. It allocates a single
4795 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
4796 to be live only at the point just before the arithmetic.
4798 A real example requiring extended scratch lifetimes is harder to come by,
4799 so here's a silly made-up example:
4803 [(match_scratch:SI 4 "r")
4804 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
4805 (set (match_operand:SI 2 "" "") (match_dup 1))
4807 (set (match_operand:SI 3 "" "") (match_dup 1))]
4808 "/* @r{determine 1 does not overlap 0 and 2} */"
4809 [(set (match_dup 4) (match_dup 1))
4810 (set (match_dup 0) (match_dup 4))
4811 (set (match_dup 2) (match_dup 4))]
4812 (set (match_dup 3) (match_dup 4))]
4817 If we had not added the @code{(match_dup 4)} in the middle of the input
4818 sequence, it might have been the case that the register we chose at the
4819 beginning of the sequence is killed by the first or second @code{set}.
4823 @node Insn Attributes
4824 @section Instruction Attributes
4825 @cindex insn attributes
4826 @cindex instruction attributes
4828 In addition to describing the instruction supported by the target machine,
4829 the @file{md} file also defines a group of @dfn{attributes} and a set of
4830 values for each. Every generated insn is assigned a value for each attribute.
4831 One possible attribute would be the effect that the insn has on the machine's
4832 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
4833 to track the condition codes.
4836 * Defining Attributes:: Specifying attributes and their values.
4837 * Expressions:: Valid expressions for attribute values.
4838 * Tagging Insns:: Assigning attribute values to insns.
4839 * Attr Example:: An example of assigning attributes.
4840 * Insn Lengths:: Computing the length of insns.
4841 * Constant Attributes:: Defining attributes that are constant.
4842 * Delay Slots:: Defining delay slots required for a machine.
4843 * Processor pipeline description:: Specifying information for insn scheduling.
4848 @node Defining Attributes
4849 @subsection Defining Attributes and their Values
4850 @cindex defining attributes and their values
4851 @cindex attributes, defining
4854 The @code{define_attr} expression is used to define each attribute required
4855 by the target machine. It looks like:
4858 (define_attr @var{name} @var{list-of-values} @var{default})
4861 @var{name} is a string specifying the name of the attribute being defined.
4863 @var{list-of-values} is either a string that specifies a comma-separated
4864 list of values that can be assigned to the attribute, or a null string to
4865 indicate that the attribute takes numeric values.
4867 @var{default} is an attribute expression that gives the value of this
4868 attribute for insns that match patterns whose definition does not include
4869 an explicit value for this attribute. @xref{Attr Example}, for more
4870 information on the handling of defaults. @xref{Constant Attributes},
4871 for information on attributes that do not depend on any particular insn.
4874 For each defined attribute, a number of definitions are written to the
4875 @file{insn-attr.h} file. For cases where an explicit set of values is
4876 specified for an attribute, the following are defined:
4880 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
4883 An enumerated class is defined for @samp{attr_@var{name}} with
4884 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
4885 the attribute name and value are first converted to uppercase.
4888 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
4889 returns the attribute value for that insn.
4892 For example, if the following is present in the @file{md} file:
4895 (define_attr "type" "branch,fp,load,store,arith" @dots{})
4899 the following lines will be written to the file @file{insn-attr.h}.
4902 #define HAVE_ATTR_type
4903 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
4904 TYPE_STORE, TYPE_ARITH@};
4905 extern enum attr_type get_attr_type ();
4908 If the attribute takes numeric values, no @code{enum} type will be
4909 defined and the function to obtain the attribute's value will return
4915 @subsection Attribute Expressions
4916 @cindex attribute expressions
4918 RTL expressions used to define attributes use the codes described above
4919 plus a few specific to attribute definitions, to be discussed below.
4920 Attribute value expressions must have one of the following forms:
4923 @cindex @code{const_int} and attributes
4924 @item (const_int @var{i})
4925 The integer @var{i} specifies the value of a numeric attribute. @var{i}
4926 must be non-negative.
4928 The value of a numeric attribute can be specified either with a
4929 @code{const_int}, or as an integer represented as a string in
4930 @code{const_string}, @code{eq_attr} (see below), @code{attr},
4931 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
4932 overrides on specific instructions (@pxref{Tagging Insns}).
4934 @cindex @code{const_string} and attributes
4935 @item (const_string @var{value})
4936 The string @var{value} specifies a constant attribute value.
4937 If @var{value} is specified as @samp{"*"}, it means that the default value of
4938 the attribute is to be used for the insn containing this expression.
4939 @samp{"*"} obviously cannot be used in the @var{default} expression
4940 of a @code{define_attr}.
4942 If the attribute whose value is being specified is numeric, @var{value}
4943 must be a string containing a non-negative integer (normally
4944 @code{const_int} would be used in this case). Otherwise, it must
4945 contain one of the valid values for the attribute.
4947 @cindex @code{if_then_else} and attributes
4948 @item (if_then_else @var{test} @var{true-value} @var{false-value})
4949 @var{test} specifies an attribute test, whose format is defined below.
4950 The value of this expression is @var{true-value} if @var{test} is true,
4951 otherwise it is @var{false-value}.
4953 @cindex @code{cond} and attributes
4954 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
4955 The first operand of this expression is a vector containing an even
4956 number of expressions and consisting of pairs of @var{test} and @var{value}
4957 expressions. The value of the @code{cond} expression is that of the
4958 @var{value} corresponding to the first true @var{test} expression. If
4959 none of the @var{test} expressions are true, the value of the @code{cond}
4960 expression is that of the @var{default} expression.
4963 @var{test} expressions can have one of the following forms:
4966 @cindex @code{const_int} and attribute tests
4967 @item (const_int @var{i})
4968 This test is true if @var{i} is nonzero and false otherwise.
4970 @cindex @code{not} and attributes
4971 @cindex @code{ior} and attributes
4972 @cindex @code{and} and attributes
4973 @item (not @var{test})
4974 @itemx (ior @var{test1} @var{test2})
4975 @itemx (and @var{test1} @var{test2})
4976 These tests are true if the indicated logical function is true.
4978 @cindex @code{match_operand} and attributes
4979 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
4980 This test is true if operand @var{n} of the insn whose attribute value
4981 is being determined has mode @var{m} (this part of the test is ignored
4982 if @var{m} is @code{VOIDmode}) and the function specified by the string
4983 @var{pred} returns a nonzero value when passed operand @var{n} and mode
4984 @var{m} (this part of the test is ignored if @var{pred} is the null
4987 The @var{constraints} operand is ignored and should be the null string.
4989 @cindex @code{le} and attributes
4990 @cindex @code{leu} and attributes
4991 @cindex @code{lt} and attributes
4992 @cindex @code{gt} and attributes
4993 @cindex @code{gtu} and attributes
4994 @cindex @code{ge} and attributes
4995 @cindex @code{geu} and attributes
4996 @cindex @code{ne} and attributes
4997 @cindex @code{eq} and attributes
4998 @cindex @code{plus} and attributes
4999 @cindex @code{minus} and attributes
5000 @cindex @code{mult} and attributes
5001 @cindex @code{div} and attributes
5002 @cindex @code{mod} and attributes
5003 @cindex @code{abs} and attributes
5004 @cindex @code{neg} and attributes
5005 @cindex @code{ashift} and attributes
5006 @cindex @code{lshiftrt} and attributes
5007 @cindex @code{ashiftrt} and attributes
5008 @item (le @var{arith1} @var{arith2})
5009 @itemx (leu @var{arith1} @var{arith2})
5010 @itemx (lt @var{arith1} @var{arith2})
5011 @itemx (ltu @var{arith1} @var{arith2})
5012 @itemx (gt @var{arith1} @var{arith2})
5013 @itemx (gtu @var{arith1} @var{arith2})
5014 @itemx (ge @var{arith1} @var{arith2})
5015 @itemx (geu @var{arith1} @var{arith2})
5016 @itemx (ne @var{arith1} @var{arith2})
5017 @itemx (eq @var{arith1} @var{arith2})
5018 These tests are true if the indicated comparison of the two arithmetic
5019 expressions is true. Arithmetic expressions are formed with
5020 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
5021 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
5022 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
5025 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
5026 Lengths},for additional forms). @code{symbol_ref} is a string
5027 denoting a C expression that yields an @code{int} when evaluated by the
5028 @samp{get_attr_@dots{}} routine. It should normally be a global
5032 @item (eq_attr @var{name} @var{value})
5033 @var{name} is a string specifying the name of an attribute.
5035 @var{value} is a string that is either a valid value for attribute
5036 @var{name}, a comma-separated list of values, or @samp{!} followed by a
5037 value or list. If @var{value} does not begin with a @samp{!}, this
5038 test is true if the value of the @var{name} attribute of the current
5039 insn is in the list specified by @var{value}. If @var{value} begins
5040 with a @samp{!}, this test is true if the attribute's value is
5041 @emph{not} in the specified list.
5046 (eq_attr "type" "load,store")
5053 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
5056 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
5057 value of the compiler variable @code{which_alternative}
5058 (@pxref{Output Statement}) and the values must be small integers. For
5062 (eq_attr "alternative" "2,3")
5069 (ior (eq (symbol_ref "which_alternative") (const_int 2))
5070 (eq (symbol_ref "which_alternative") (const_int 3)))
5073 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
5074 where the value of the attribute being tested is known for all insns matching
5075 a particular pattern. This is by far the most common case.
5078 @item (attr_flag @var{name})
5079 The value of an @code{attr_flag} expression is true if the flag
5080 specified by @var{name} is true for the @code{insn} currently being
5083 @var{name} is a string specifying one of a fixed set of flags to test.
5084 Test the flags @code{forward} and @code{backward} to determine the
5085 direction of a conditional branch. Test the flags @code{very_likely},
5086 @code{likely}, @code{very_unlikely}, and @code{unlikely} to determine
5087 if a conditional branch is expected to be taken.
5089 If the @code{very_likely} flag is true, then the @code{likely} flag is also
5090 true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
5092 This example describes a conditional branch delay slot which
5093 can be nullified for forward branches that are taken (annul-true) or
5094 for backward branches which are not taken (annul-false).
5097 (define_delay (eq_attr "type" "cbranch")
5098 [(eq_attr "in_branch_delay" "true")
5099 (and (eq_attr "in_branch_delay" "true")
5100 (attr_flag "forward"))
5101 (and (eq_attr "in_branch_delay" "true")
5102 (attr_flag "backward"))])
5105 The @code{forward} and @code{backward} flags are false if the current
5106 @code{insn} being scheduled is not a conditional branch.
5108 The @code{very_likely} and @code{likely} flags are true if the
5109 @code{insn} being scheduled is not a conditional branch.
5110 The @code{very_unlikely} and @code{unlikely} flags are false if the
5111 @code{insn} being scheduled is not a conditional branch.
5113 @code{attr_flag} is only used during delay slot scheduling and has no
5114 meaning to other passes of the compiler.
5117 @item (attr @var{name})
5118 The value of another attribute is returned. This is most useful
5119 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
5120 produce more efficient code for non-numeric attributes.
5126 @subsection Assigning Attribute Values to Insns
5127 @cindex tagging insns
5128 @cindex assigning attribute values to insns
5130 The value assigned to an attribute of an insn is primarily determined by
5131 which pattern is matched by that insn (or which @code{define_peephole}
5132 generated it). Every @code{define_insn} and @code{define_peephole} can
5133 have an optional last argument to specify the values of attributes for
5134 matching insns. The value of any attribute not specified in a particular
5135 insn is set to the default value for that attribute, as specified in its
5136 @code{define_attr}. Extensive use of default values for attributes
5137 permits the specification of the values for only one or two attributes
5138 in the definition of most insn patterns, as seen in the example in the
5141 The optional last argument of @code{define_insn} and
5142 @code{define_peephole} is a vector of expressions, each of which defines
5143 the value for a single attribute. The most general way of assigning an
5144 attribute's value is to use a @code{set} expression whose first operand is an
5145 @code{attr} expression giving the name of the attribute being set. The
5146 second operand of the @code{set} is an attribute expression
5147 (@pxref{Expressions}) giving the value of the attribute.
5149 When the attribute value depends on the @samp{alternative} attribute
5150 (i.e., which is the applicable alternative in the constraint of the
5151 insn), the @code{set_attr_alternative} expression can be used. It
5152 allows the specification of a vector of attribute expressions, one for
5156 When the generality of arbitrary attribute expressions is not required,
5157 the simpler @code{set_attr} expression can be used, which allows
5158 specifying a string giving either a single attribute value or a list
5159 of attribute values, one for each alternative.
5161 The form of each of the above specifications is shown below. In each case,
5162 @var{name} is a string specifying the attribute to be set.
5165 @item (set_attr @var{name} @var{value-string})
5166 @var{value-string} is either a string giving the desired attribute value,
5167 or a string containing a comma-separated list giving the values for
5168 succeeding alternatives. The number of elements must match the number
5169 of alternatives in the constraint of the insn pattern.
5171 Note that it may be useful to specify @samp{*} for some alternative, in
5172 which case the attribute will assume its default value for insns matching
5175 @findex set_attr_alternative
5176 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
5177 Depending on the alternative of the insn, the value will be one of the
5178 specified values. This is a shorthand for using a @code{cond} with
5179 tests on the @samp{alternative} attribute.
5182 @item (set (attr @var{name}) @var{value})
5183 The first operand of this @code{set} must be the special RTL expression
5184 @code{attr}, whose sole operand is a string giving the name of the
5185 attribute being set. @var{value} is the value of the attribute.
5188 The following shows three different ways of representing the same
5189 attribute value specification:
5192 (set_attr "type" "load,store,arith")
5194 (set_attr_alternative "type"
5195 [(const_string "load") (const_string "store")
5196 (const_string "arith")])
5199 (cond [(eq_attr "alternative" "1") (const_string "load")
5200 (eq_attr "alternative" "2") (const_string "store")]
5201 (const_string "arith")))
5205 @findex define_asm_attributes
5206 The @code{define_asm_attributes} expression provides a mechanism to
5207 specify the attributes assigned to insns produced from an @code{asm}
5208 statement. It has the form:
5211 (define_asm_attributes [@var{attr-sets}])
5215 where @var{attr-sets} is specified the same as for both the
5216 @code{define_insn} and the @code{define_peephole} expressions.
5218 These values will typically be the ``worst case'' attribute values. For
5219 example, they might indicate that the condition code will be clobbered.
5221 A specification for a @code{length} attribute is handled specially. The
5222 way to compute the length of an @code{asm} insn is to multiply the
5223 length specified in the expression @code{define_asm_attributes} by the
5224 number of machine instructions specified in the @code{asm} statement,
5225 determined by counting the number of semicolons and newlines in the
5226 string. Therefore, the value of the @code{length} attribute specified
5227 in a @code{define_asm_attributes} should be the maximum possible length
5228 of a single machine instruction.
5233 @subsection Example of Attribute Specifications
5234 @cindex attribute specifications example
5235 @cindex attribute specifications
5237 The judicious use of defaulting is important in the efficient use of
5238 insn attributes. Typically, insns are divided into @dfn{types} and an
5239 attribute, customarily called @code{type}, is used to represent this
5240 value. This attribute is normally used only to define the default value
5241 for other attributes. An example will clarify this usage.
5243 Assume we have a RISC machine with a condition code and in which only
5244 full-word operations are performed in registers. Let us assume that we
5245 can divide all insns into loads, stores, (integer) arithmetic
5246 operations, floating point operations, and branches.
5248 Here we will concern ourselves with determining the effect of an insn on
5249 the condition code and will limit ourselves to the following possible
5250 effects: The condition code can be set unpredictably (clobbered), not
5251 be changed, be set to agree with the results of the operation, or only
5252 changed if the item previously set into the condition code has been
5255 Here is part of a sample @file{md} file for such a machine:
5258 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
5260 (define_attr "cc" "clobber,unchanged,set,change0"
5261 (cond [(eq_attr "type" "load")
5262 (const_string "change0")
5263 (eq_attr "type" "store,branch")
5264 (const_string "unchanged")
5265 (eq_attr "type" "arith")
5266 (if_then_else (match_operand:SI 0 "" "")
5267 (const_string "set")
5268 (const_string "clobber"))]
5269 (const_string "clobber")))
5272 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
5273 (match_operand:SI 1 "general_operand" "r,m,r"))]
5279 [(set_attr "type" "arith,load,store")])
5282 Note that we assume in the above example that arithmetic operations
5283 performed on quantities smaller than a machine word clobber the condition
5284 code since they will set the condition code to a value corresponding to the
5290 @subsection Computing the Length of an Insn
5291 @cindex insn lengths, computing
5292 @cindex computing the length of an insn
5294 For many machines, multiple types of branch instructions are provided, each
5295 for different length branch displacements. In most cases, the assembler
5296 will choose the correct instruction to use. However, when the assembler
5297 cannot do so, GCC can when a special attribute, the @samp{length}
5298 attribute, is defined. This attribute must be defined to have numeric
5299 values by specifying a null string in its @code{define_attr}.
5301 In the case of the @samp{length} attribute, two additional forms of
5302 arithmetic terms are allowed in test expressions:
5305 @cindex @code{match_dup} and attributes
5306 @item (match_dup @var{n})
5307 This refers to the address of operand @var{n} of the current insn, which
5308 must be a @code{label_ref}.
5310 @cindex @code{pc} and attributes
5312 This refers to the address of the @emph{current} insn. It might have
5313 been more consistent with other usage to make this the address of the
5314 @emph{next} insn but this would be confusing because the length of the
5315 current insn is to be computed.
5318 @cindex @code{addr_vec}, length of
5319 @cindex @code{addr_diff_vec}, length of
5320 For normal insns, the length will be determined by value of the
5321 @samp{length} attribute. In the case of @code{addr_vec} and
5322 @code{addr_diff_vec} insn patterns, the length is computed as
5323 the number of vectors multiplied by the size of each vector.
5325 Lengths are measured in addressable storage units (bytes).
5327 The following macros can be used to refine the length computation:
5330 @findex ADJUST_INSN_LENGTH
5331 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
5332 If defined, modifies the length assigned to instruction @var{insn} as a
5333 function of the context in which it is used. @var{length} is an lvalue
5334 that contains the initially computed length of the insn and should be
5335 updated with the correct length of the insn.
5337 This macro will normally not be required. A case in which it is
5338 required is the ROMP@. On this machine, the size of an @code{addr_vec}
5339 insn must be increased by two to compensate for the fact that alignment
5343 @findex get_attr_length
5344 The routine that returns @code{get_attr_length} (the value of the
5345 @code{length} attribute) can be used by the output routine to
5346 determine the form of the branch instruction to be written, as the
5347 example below illustrates.
5349 As an example of the specification of variable-length branches, consider
5350 the IBM 360. If we adopt the convention that a register will be set to
5351 the starting address of a function, we can jump to labels within 4k of
5352 the start using a four-byte instruction. Otherwise, we need a six-byte
5353 sequence to load the address from memory and then branch to it.
5355 On such a machine, a pattern for a branch instruction might be specified
5361 (label_ref (match_operand 0 "" "")))]
5364 return (get_attr_length (insn) == 4
5365 ? "b %l0" : "l r15,=a(%l0); br r15");
5367 [(set (attr "length")
5368 (if_then_else (lt (match_dup 0) (const_int 4096))
5375 @node Constant Attributes
5376 @subsection Constant Attributes
5377 @cindex constant attributes
5379 A special form of @code{define_attr}, where the expression for the
5380 default value is a @code{const} expression, indicates an attribute that
5381 is constant for a given run of the compiler. Constant attributes may be
5382 used to specify which variety of processor is used. For example,
5385 (define_attr "cpu" "m88100,m88110,m88000"
5387 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
5388 (symbol_ref "TARGET_88110") (const_string "m88110")]
5389 (const_string "m88000"))))
5391 (define_attr "memory" "fast,slow"
5393 (if_then_else (symbol_ref "TARGET_FAST_MEM")
5394 (const_string "fast")
5395 (const_string "slow"))))
5398 The routine generated for constant attributes has no parameters as it
5399 does not depend on any particular insn. RTL expressions used to define
5400 the value of a constant attribute may use the @code{symbol_ref} form,
5401 but may not use either the @code{match_operand} form or @code{eq_attr}
5402 forms involving insn attributes.
5407 @subsection Delay Slot Scheduling
5408 @cindex delay slots, defining
5410 The insn attribute mechanism can be used to specify the requirements for
5411 delay slots, if any, on a target machine. An instruction is said to
5412 require a @dfn{delay slot} if some instructions that are physically
5413 after the instruction are executed as if they were located before it.
5414 Classic examples are branch and call instructions, which often execute
5415 the following instruction before the branch or call is performed.
5417 On some machines, conditional branch instructions can optionally
5418 @dfn{annul} instructions in the delay slot. This means that the
5419 instruction will not be executed for certain branch outcomes. Both
5420 instructions that annul if the branch is true and instructions that
5421 annul if the branch is false are supported.
5423 Delay slot scheduling differs from instruction scheduling in that
5424 determining whether an instruction needs a delay slot is dependent only
5425 on the type of instruction being generated, not on data flow between the
5426 instructions. See the next section for a discussion of data-dependent
5427 instruction scheduling.
5429 @findex define_delay
5430 The requirement of an insn needing one or more delay slots is indicated
5431 via the @code{define_delay} expression. It has the following form:
5434 (define_delay @var{test}
5435 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
5436 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
5440 @var{test} is an attribute test that indicates whether this
5441 @code{define_delay} applies to a particular insn. If so, the number of
5442 required delay slots is determined by the length of the vector specified
5443 as the second argument. An insn placed in delay slot @var{n} must
5444 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
5445 attribute test that specifies which insns may be annulled if the branch
5446 is true. Similarly, @var{annul-false-n} specifies which insns in the
5447 delay slot may be annulled if the branch is false. If annulling is not
5448 supported for that delay slot, @code{(nil)} should be coded.
5450 For example, in the common case where branch and call insns require
5451 a single delay slot, which may contain any insn other than a branch or
5452 call, the following would be placed in the @file{md} file:
5455 (define_delay (eq_attr "type" "branch,call")
5456 [(eq_attr "type" "!branch,call") (nil) (nil)])
5459 Multiple @code{define_delay} expressions may be specified. In this
5460 case, each such expression specifies different delay slot requirements
5461 and there must be no insn for which tests in two @code{define_delay}
5462 expressions are both true.
5464 For example, if we have a machine that requires one delay slot for branches
5465 but two for calls, no delay slot can contain a branch or call insn,
5466 and any valid insn in the delay slot for the branch can be annulled if the
5467 branch is true, we might represent this as follows:
5470 (define_delay (eq_attr "type" "branch")
5471 [(eq_attr "type" "!branch,call")
5472 (eq_attr "type" "!branch,call")
5475 (define_delay (eq_attr "type" "call")
5476 [(eq_attr "type" "!branch,call") (nil) (nil)
5477 (eq_attr "type" "!branch,call") (nil) (nil)])
5479 @c the above is *still* too long. --mew 4feb93
5483 @node Processor pipeline description
5484 @subsection Specifying processor pipeline description
5485 @cindex processor pipeline description
5486 @cindex processor functional units
5487 @cindex instruction latency time
5488 @cindex interlock delays
5489 @cindex data dependence delays
5490 @cindex reservation delays
5491 @cindex pipeline hazard recognizer
5492 @cindex automaton based pipeline description
5493 @cindex regular expressions
5494 @cindex deterministic finite state automaton
5495 @cindex automaton based scheduler
5499 To achieve better performance, most modern processors
5500 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
5501 processors) have many @dfn{functional units} on which several
5502 instructions can be executed simultaneously. An instruction starts
5503 execution if its issue conditions are satisfied. If not, the
5504 instruction is stalled until its conditions are satisfied. Such
5505 @dfn{interlock (pipeline) delay} causes interruption of the fetching
5506 of successor instructions (or demands nop instructions, e.g. for some
5509 There are two major kinds of interlock delays in modern processors.
5510 The first one is a data dependence delay determining @dfn{instruction
5511 latency time}. The instruction execution is not started until all
5512 source data have been evaluated by prior instructions (there are more
5513 complex cases when the instruction execution starts even when the data
5514 are not available but will be ready in given time after the
5515 instruction execution start). Taking the data dependence delays into
5516 account is simple. The data dependence (true, output, and
5517 anti-dependence) delay between two instructions is given by a
5518 constant. In most cases this approach is adequate. The second kind
5519 of interlock delays is a reservation delay. The reservation delay
5520 means that two instructions under execution will be in need of shared
5521 processors resources, i.e. buses, internal registers, and/or
5522 functional units, which are reserved for some time. Taking this kind
5523 of delay into account is complex especially for modern @acronym{RISC}
5526 The task of exploiting more processor parallelism is solved by an
5527 instruction scheduler. For a better solution to this problem, the
5528 instruction scheduler has to have an adequate description of the
5529 processor parallelism (or @dfn{pipeline description}). Currently GCC
5530 provides two alternative ways to describe processor parallelism,
5531 both described below. The first method is outlined in the next section;
5532 it was once the only method provided by GCC, and thus is used in a number
5533 of exiting ports. The second, and preferred method, specifies functional
5534 unit reservations for groups of instructions with the aid of @dfn{regular
5535 expressions}. This is called the @dfn{automaton based description}.
5537 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
5538 figure out the possibility of the instruction issue by the processor
5539 on a given simulated processor cycle. The pipeline hazard recognizer is
5540 automatically generated from the processor pipeline description. The
5541 pipeline hazard recognizer generated from the automaton based
5542 description is more sophisticated and based on a deterministic finite
5543 state automaton (@acronym{DFA}) and therefore faster than one
5544 generated from the old description. Furthermore, its speed is not dependent
5545 on processor complexity. The instruction issue is possible if there is
5546 a transition from one automaton state to another one.
5548 You can use either model to describe processor pipeline
5549 characteristics or even mix them. You could use the old description
5550 for some processor submodels and the @acronym{DFA}-based one for other
5551 processor submodels.
5553 In general, using the automaton based description is preferred. Its
5554 model is richer and makes it possible to more accurately describe
5555 pipeline characteristics of processors, which results in improved
5556 code quality (although sometimes only marginally). It will also be
5557 used as an infrastructure to implement sophisticated and practical
5558 instruction scheduling which will try many instruction sequences to
5559 choose the best one.
5563 * Old pipeline description:: Specifying information for insn scheduling.
5564 * Automaton pipeline description:: Describing insn pipeline characteristics.
5565 * Comparison of the two descriptions:: Drawbacks of the old pipeline description
5570 @node Old pipeline description
5571 @subsubsection Specifying Function Units
5572 @cindex old pipeline description
5573 @cindex function units, for scheduling
5575 On most @acronym{RISC} machines, there are instructions whose results
5576 are not available for a specific number of cycles. Common cases are
5577 instructions that load data from memory. On many machines, a pipeline
5578 stall will result if the data is referenced too soon after the load
5581 In addition, many newer microprocessors have multiple function units, usually
5582 one for integer and one for floating point, and often will incur pipeline
5583 stalls when a result that is needed is not yet ready.
5585 The descriptions in this section allow the specification of how much
5586 time must elapse between the execution of an instruction and the time
5587 when its result is used. It also allows specification of when the
5588 execution of an instruction will delay execution of similar instructions
5589 due to function unit conflicts.
5591 For the purposes of the specifications in this section, a machine is
5592 divided into @dfn{function units}, each of which execute a specific
5593 class of instructions in first-in-first-out order. Function units
5594 that accept one instruction each cycle and allow a result to be used
5595 in the succeeding instruction (usually via forwarding) need not be
5596 specified. Classic @acronym{RISC} microprocessors will normally have
5597 a single function unit, which we can call @samp{memory}. The newer
5598 ``superscalar'' processors will often have function units for floating
5599 point operations, usually at least a floating point adder and
5602 @findex define_function_unit
5603 Each usage of a function units by a class of insns is specified with a
5604 @code{define_function_unit} expression, which looks like this:
5607 (define_function_unit @var{name} @var{multiplicity} @var{simultaneity}
5608 @var{test} @var{ready-delay} @var{issue-delay}
5609 [@var{conflict-list}])
5612 @var{name} is a string giving the name of the function unit.
5614 @var{multiplicity} is an integer specifying the number of identical
5615 units in the processor. If more than one unit is specified, they will
5616 be scheduled independently. Only truly independent units should be
5617 counted; a pipelined unit should be specified as a single unit. (The
5618 only common example of a machine that has multiple function units for a
5619 single instruction class that are truly independent and not pipelined
5620 are the two multiply and two increment units of the CDC 6600.)
5622 @var{simultaneity} specifies the maximum number of insns that can be
5623 executing in each instance of the function unit simultaneously or zero
5624 if the unit is pipelined and has no limit.
5626 All @code{define_function_unit} definitions referring to function unit
5627 @var{name} must have the same name and values for @var{multiplicity} and
5630 @var{test} is an attribute test that selects the insns we are describing
5631 in this definition. Note that an insn may use more than one function
5632 unit and a function unit may be specified in more than one
5633 @code{define_function_unit}.
5635 @var{ready-delay} is an integer that specifies the number of cycles
5636 after which the result of the instruction can be used without
5637 introducing any stalls.
5639 @var{issue-delay} is an integer that specifies the number of cycles
5640 after the instruction matching the @var{test} expression begins using
5641 this unit until a subsequent instruction can begin. A cost of @var{N}
5642 indicates an @var{N-1} cycle delay. A subsequent instruction may also
5643 be delayed if an earlier instruction has a longer @var{ready-delay}
5644 value. This blocking effect is computed using the @var{simultaneity},
5645 @var{ready-delay}, @var{issue-delay}, and @var{conflict-list} terms.
5646 For a normal non-pipelined function unit, @var{simultaneity} is one, the
5647 unit is taken to block for the @var{ready-delay} cycles of the executing
5648 insn, and smaller values of @var{issue-delay} are ignored.
5650 @var{conflict-list} is an optional list giving detailed conflict costs
5651 for this unit. If specified, it is a list of condition test expressions
5652 to be applied to insns chosen to execute in @var{name} following the
5653 particular insn matching @var{test} that is already executing in
5654 @var{name}. For each insn in the list, @var{issue-delay} specifies the
5655 conflict cost; for insns not in the list, the cost is zero. If not
5656 specified, @var{conflict-list} defaults to all instructions that use the
5659 Typical uses of this vector are where a floating point function unit can
5660 pipeline either single- or double-precision operations, but not both, or
5661 where a memory unit can pipeline loads, but not stores, etc.
5663 As an example, consider a classic @acronym{RISC} machine where the
5664 result of a load instruction is not available for two cycles (a single
5665 ``delay'' instruction is required) and where only one load instruction
5666 can be executed simultaneously. This would be specified as:
5669 (define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0)
5672 For the case of a floating point function unit that can pipeline either
5673 single or double precision, but not both, the following could be specified:
5676 (define_function_unit
5677 "fp" 1 0 (eq_attr "type" "sp_fp") 4 4 [(eq_attr "type" "dp_fp")])
5678 (define_function_unit
5679 "fp" 1 0 (eq_attr "type" "dp_fp") 4 4 [(eq_attr "type" "sp_fp")])
5682 @strong{Note:} The scheduler attempts to avoid function unit conflicts
5683 and uses all the specifications in the @code{define_function_unit}
5684 expression. It has recently been discovered that these
5685 specifications may not allow modeling of some of the newer
5686 ``superscalar'' processors that have insns using multiple pipelined
5687 units. These insns will cause a potential conflict for the second unit
5688 used during their execution and there is no way of representing that
5689 conflict. Any examples of how function unit conflicts work
5690 in such processors and suggestions for their representation would be
5695 @node Automaton pipeline description
5696 @subsubsection Describing instruction pipeline characteristics
5697 @cindex automaton based pipeline description
5699 This section describes constructions of the automaton based processor
5700 pipeline description. The order of constructions within the machine
5701 description file is not important.
5703 @findex define_automaton
5704 @cindex pipeline hazard recognizer
5705 The following optional construction describes names of automata
5706 generated and used for the pipeline hazards recognition. Sometimes
5707 the generated finite state automaton used by the pipeline hazard
5708 recognizer is large. If we use more than one automaton and bind functional
5709 units to the automata, the total size of the automata is usually
5710 less than the size of the single automaton. If there is no one such
5711 construction, only one finite state automaton is generated.
5714 (define_automaton @var{automata-names})
5717 @var{automata-names} is a string giving names of the automata. The
5718 names are separated by commas. All the automata should have unique names.
5719 The automaton name is used in the constructions @code{define_cpu_unit} and
5720 @code{define_query_cpu_unit}.
5722 @findex define_cpu_unit
5723 @cindex processor functional units
5724 Each processor functional unit used in the description of instruction
5725 reservations should be described by the following construction.
5728 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
5731 @var{unit-names} is a string giving the names of the functional units
5732 separated by commas. Don't use name @samp{nothing}, it is reserved
5735 @var{automaton-name} is a string giving the name of the automaton with
5736 which the unit is bound. The automaton should be described in
5737 construction @code{define_automaton}. You should give
5738 @dfn{automaton-name}, if there is a defined automaton.
5740 The assignment of units to automata are constrained by the uses of the
5741 units in insn reservations. The most important constraint is: if a
5742 unit reservation is present on a particular cycle of an alternative
5743 for an insn reservation, then some unit from the same automaton must
5744 be present on the same cycle for the other alternatives of the insn
5745 reservation. The rest of the constraints are mentioned in the
5746 description of the subsequent constructions.
5748 @findex define_query_cpu_unit
5749 @cindex querying function unit reservations
5750 The following construction describes CPU functional units analogously
5751 to @code{define_cpu_unit}. The reservation of such units can be
5752 queried for an automaton state. The instruction scheduler never
5753 queries reservation of functional units for given automaton state. So
5754 as a rule, you don't need this construction. This construction could
5755 be used for future code generation goals (e.g. to generate
5756 @acronym{VLIW} insn templates).
5759 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
5762 @var{unit-names} is a string giving names of the functional units
5763 separated by commas.
5765 @var{automaton-name} is a string giving the name of the automaton with
5766 which the unit is bound.
5768 @findex define_insn_reservation
5769 @cindex instruction latency time
5770 @cindex regular expressions
5772 The following construction is the major one to describe pipeline
5773 characteristics of an instruction.
5776 (define_insn_reservation @var{insn-name} @var{default_latency}
5777 @var{condition} @var{regexp})
5780 @var{default_latency} is a number giving latency time of the
5781 instruction. There is an important difference between the old
5782 description and the automaton based pipeline description. The latency
5783 time is used for all dependencies when we use the old description. In
5784 the automaton based pipeline description, the given latency time is only
5785 used for true dependencies. The cost of anti-dependencies is always
5786 zero and the cost of output dependencies is the difference between
5787 latency times of the producing and consuming insns (if the difference
5788 is negative, the cost is considered to be zero). You can always
5789 change the default costs for any description by using the target hook
5790 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
5792 @var{insn-name} is a string giving the internal name of the insn. The
5793 internal names are used in constructions @code{define_bypass} and in
5794 the automaton description file generated for debugging. The internal
5795 name has nothing in common with the names in @code{define_insn}. It is a
5796 good practice to use insn classes described in the processor manual.
5798 @var{condition} defines what RTL insns are described by this
5799 construction. You should remember that you will be in trouble if
5800 @var{condition} for two or more different
5801 @code{define_insn_reservation} constructions is TRUE for an insn. In
5802 this case what reservation will be used for the insn is not defined.
5803 Such cases are not checked during generation of the pipeline hazards
5804 recognizer because in general recognizing that two conditions may have
5805 the same value is quite difficult (especially if the conditions
5806 contain @code{symbol_ref}). It is also not checked during the
5807 pipeline hazard recognizer work because it would slow down the
5808 recognizer considerably.
5810 @var{regexp} is a string describing the reservation of the cpu's functional
5811 units by the instruction. The reservations are described by a regular
5812 expression according to the following syntax:
5815 regexp = regexp "," oneof
5818 oneof = oneof "|" allof
5821 allof = allof "+" repeat
5824 repeat = element "*" number
5827 element = cpu_function_unit_name
5836 @samp{,} is used for describing the start of the next cycle in
5840 @samp{|} is used for describing a reservation described by the first
5841 regular expression @strong{or} a reservation described by the second
5842 regular expression @strong{or} etc.
5845 @samp{+} is used for describing a reservation described by the first
5846 regular expression @strong{and} a reservation described by the
5847 second regular expression @strong{and} etc.
5850 @samp{*} is used for convenience and simply means a sequence in which
5851 the regular expression are repeated @var{number} times with cycle
5852 advancing (see @samp{,}).
5855 @samp{cpu_function_unit_name} denotes reservation of the named
5859 @samp{reservation_name} --- see description of construction
5860 @samp{define_reservation}.
5863 @samp{nothing} denotes no unit reservations.
5866 @findex define_reservation
5867 Sometimes unit reservations for different insns contain common parts.
5868 In such case, you can simplify the pipeline description by describing
5869 the common part by the following construction
5872 (define_reservation @var{reservation-name} @var{regexp})
5875 @var{reservation-name} is a string giving name of @var{regexp}.
5876 Functional unit names and reservation names are in the same name
5877 space. So the reservation names should be different from the
5878 functional unit names and can not be the reserved name @samp{nothing}.
5880 @findex define_bypass
5881 @cindex instruction latency time
5883 The following construction is used to describe exceptions in the
5884 latency time for given instruction pair. This is so called bypasses.
5887 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
5891 @var{number} defines when the result generated by the instructions
5892 given in string @var{out_insn_names} will be ready for the
5893 instructions given in string @var{in_insn_names}. The instructions in
5894 the string are separated by commas.
5896 @var{guard} is an optional string giving the name of a C function which
5897 defines an additional guard for the bypass. The function will get the
5898 two insns as parameters. If the function returns zero the bypass will
5899 be ignored for this case. The additional guard is necessary to
5900 recognize complicated bypasses, e.g. when the consumer is only an address
5901 of insn @samp{store} (not a stored value).
5903 @findex exclusion_set
5904 @findex presence_set
5905 @findex final_presence_set
5907 @findex final_absence_set
5910 The following five constructions are usually used to describe
5911 @acronym{VLIW} processors, or more precisely, to describe a placement
5912 of small instructions into @acronym{VLIW} instruction slots. They
5913 can be used for @acronym{RISC} processors, too.
5916 (exclusion_set @var{unit-names} @var{unit-names})
5917 (presence_set @var{unit-names} @var{patterns})
5918 (final_presence_set @var{unit-names} @var{patterns})
5919 (absence_set @var{unit-names} @var{patterns})
5920 (final_absence_set @var{unit-names} @var{patterns})
5923 @var{unit-names} is a string giving names of functional units
5924 separated by commas.
5926 @var{patterns} is a string giving patterns of functional units
5927 separated by comma. Currently pattern is is one unit or units
5928 separated by white-spaces.
5930 The first construction (@samp{exclusion_set}) means that each
5931 functional unit in the first string can not be reserved simultaneously
5932 with a unit whose name is in the second string and vice versa. For
5933 example, the construction is useful for describing processors
5934 (e.g. some SPARC processors) with a fully pipelined floating point
5935 functional unit which can execute simultaneously only single floating
5936 point insns or only double floating point insns.
5938 The second construction (@samp{presence_set}) means that each
5939 functional unit in the first string can not be reserved unless at
5940 least one of pattern of units whose names are in the second string is
5941 reserved. This is an asymmetric relation. For example, it is useful
5942 for description that @acronym{VLIW} @samp{slot1} is reserved after
5943 @samp{slot0} reservation. We could describe it by the following
5947 (presence_set "slot1" "slot0")
5950 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
5951 reservation. In this case we could write
5954 (presence_set "slot1" "slot0 b0")
5957 The third construction (@samp{final_presence_set}) is analogous to
5958 @samp{presence_set}. The difference between them is when checking is
5959 done. When an instruction is issued in given automaton state
5960 reflecting all current and planned unit reservations, the automaton
5961 state is changed. The first state is a source state, the second one
5962 is a result state. Checking for @samp{presence_set} is done on the
5963 source state reservation, checking for @samp{final_presence_set} is
5964 done on the result reservation. This construction is useful to
5965 describe a reservation which is actually two subsequent reservations.
5966 For example, if we use
5969 (presence_set "slot1" "slot0")
5972 the following insn will be never issued (because @samp{slot1} requires
5973 @samp{slot0} which is absent in the source state).
5976 (define_reservation "insn_and_nop" "slot0 + slot1")
5979 but it can be issued if we use analogous @samp{final_presence_set}.
5981 The forth construction (@samp{absence_set}) means that each functional
5982 unit in the first string can be reserved only if each pattern of units
5983 whose names are in the second string is not reserved. This is an
5984 asymmetric relation (actually @samp{exclusion_set} is analogous to
5985 this one but it is symmetric). For example, it is useful for
5986 description that @acronym{VLIW} @samp{slot0} can not be reserved after
5987 @samp{slot1} or @samp{slot2} reservation. We could describe it by the
5988 following construction
5991 (absence_set "slot2" "slot0, slot1")
5994 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
5995 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
5996 this case we could write
5999 (absence_set "slot2" "slot0 b0, slot1 b1")
6002 All functional units mentioned in a set should belong to the same
6005 The last construction (@samp{final_absence_set}) is analogous to
6006 @samp{absence_set} but checking is done on the result (state)
6007 reservation. See comments for @samp{final_presence_set}.
6009 @findex automata_option
6010 @cindex deterministic finite state automaton
6011 @cindex nondeterministic finite state automaton
6012 @cindex finite state automaton minimization
6013 You can control the generator of the pipeline hazard recognizer with
6014 the following construction.
6017 (automata_option @var{options})
6020 @var{options} is a string giving options which affect the generated
6021 code. Currently there are the following options:
6025 @dfn{no-minimization} makes no minimization of the automaton. This is
6026 only worth to do when we are debugging the description and need to
6027 look more accurately at reservations of states.
6030 @dfn{time} means printing additional time statistics about
6031 generation of automata.
6034 @dfn{v} means a generation of the file describing the result automata.
6035 The file has suffix @samp{.dfa} and can be used for the description
6036 verification and debugging.
6039 @dfn{w} means a generation of warning instead of error for
6040 non-critical errors.
6043 @dfn{ndfa} makes nondeterministic finite state automata. This affects
6044 the treatment of operator @samp{|} in the regular expressions. The
6045 usual treatment of the operator is to try the first alternative and,
6046 if the reservation is not possible, the second alternative. The
6047 nondeterministic treatment means trying all alternatives, some of them
6048 may be rejected by reservations in the subsequent insns. You can not
6049 query functional unit reservations in nondeterministic automaton
6053 @dfn{progress} means output of a progress bar showing how many states
6054 were generated so far for automaton being processed. This is useful
6055 during debugging a @acronym{DFA} description. If you see too many
6056 generated states, you could interrupt the generator of the pipeline
6057 hazard recognizer and try to figure out a reason for generation of the
6061 As an example, consider a superscalar @acronym{RISC} machine which can
6062 issue three insns (two integer insns and one floating point insn) on
6063 the cycle but can finish only two insns. To describe this, we define
6064 the following functional units.
6067 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
6068 (define_cpu_unit "port0, port1")
6071 All simple integer insns can be executed in any integer pipeline and
6072 their result is ready in two cycles. The simple integer insns are
6073 issued into the first pipeline unless it is reserved, otherwise they
6074 are issued into the second pipeline. Integer division and
6075 multiplication insns can be executed only in the second integer
6076 pipeline and their results are ready correspondingly in 8 and 4
6077 cycles. The integer division is not pipelined, i.e. the subsequent
6078 integer division insn can not be issued until the current division
6079 insn finished. Floating point insns are fully pipelined and their
6080 results are ready in 3 cycles. Where the result of a floating point
6081 insn is used by an integer insn, an additional delay of one cycle is
6082 incurred. To describe all of this we could specify
6085 (define_cpu_unit "div")
6087 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
6088 "(i0_pipeline | i1_pipeline), (port0 | port1)")
6090 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
6091 "i1_pipeline, nothing*2, (port0 | port1)")
6093 (define_insn_reservation "div" 8 (eq_attr "type" "div")
6094 "i1_pipeline, div*7, div + (port0 | port1)")
6096 (define_insn_reservation "float" 3 (eq_attr "type" "float")
6097 "f_pipeline, nothing, (port0 | port1))
6099 (define_bypass 4 "float" "simple,mult,div")
6102 To simplify the description we could describe the following reservation
6105 (define_reservation "finish" "port0|port1")
6108 and use it in all @code{define_insn_reservation} as in the following
6112 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
6113 "(i0_pipeline | i1_pipeline), finish")
6119 @node Comparison of the two descriptions
6120 @subsubsection Drawbacks of the old pipeline description
6121 @cindex old pipeline description
6122 @cindex automaton based pipeline description
6123 @cindex processor functional units
6124 @cindex interlock delays
6125 @cindex instruction latency time
6126 @cindex pipeline hazard recognizer
6129 The old instruction level parallelism description and the pipeline
6130 hazards recognizer based on it have the following drawbacks in
6131 comparison with the @acronym{DFA}-based ones:
6135 Each functional unit is believed to be reserved at the instruction
6136 execution start. This is a very inaccurate model for modern
6140 An inadequate description of instruction latency times. The latency
6141 time is bound with a functional unit reserved by an instruction not
6142 with the instruction itself. In other words, the description is
6143 oriented to describe at most one unit reservation by each instruction.
6144 It also does not permit to describe special bypasses between
6148 The implementation of the pipeline hazard recognizer interface has
6149 constraints on number of functional units. This is a number of bits
6150 in integer on the host machine.
6153 The interface to the pipeline hazard recognizer is more complex than
6154 one to the automaton based pipeline recognizer.
6157 An unnatural description when you write a unit and a condition which
6158 selects instructions using the unit. Writing all unit reservations
6159 for an instruction (an instruction class) is more natural.
6162 The recognition of the interlock delays has a slow implementation. The GCC
6163 scheduler supports structures which describe the unit reservations.
6164 The more functional units a processor has, the slower its pipeline hazard
6165 recognizer will be. Such an implementation would become even slower when we
6167 reserve functional units not only at the instruction execution start.
6168 In an automaton based pipeline hazard recognizer, speed is not dependent
6169 on processor complexity.
6174 @node Conditional Execution
6175 @section Conditional Execution
6176 @cindex conditional execution
6179 A number of architectures provide for some form of conditional
6180 execution, or predication. The hallmark of this feature is the
6181 ability to nullify most of the instructions in the instruction set.
6182 When the instruction set is large and not entirely symmetric, it
6183 can be quite tedious to describe these forms directly in the
6184 @file{.md} file. An alternative is the @code{define_cond_exec} template.
6186 @findex define_cond_exec
6189 [@var{predicate-pattern}]
6191 "@var{output-template}")
6194 @var{predicate-pattern} is the condition that must be true for the
6195 insn to be executed at runtime and should match a relational operator.
6196 One can use @code{match_operator} to match several relational operators
6197 at once. Any @code{match_operand} operands must have no more than one
6200 @var{condition} is a C expression that must be true for the generated
6203 @findex current_insn_predicate
6204 @var{output-template} is a string similar to the @code{define_insn}
6205 output template (@pxref{Output Template}), except that the @samp{*}
6206 and @samp{@@} special cases do not apply. This is only useful if the
6207 assembly text for the predicate is a simple prefix to the main insn.
6208 In order to handle the general case, there is a global variable
6209 @code{current_insn_predicate} that will contain the entire predicate
6210 if the current insn is predicated, and will otherwise be @code{NULL}.
6212 When @code{define_cond_exec} is used, an implicit reference to
6213 the @code{predicable} instruction attribute is made.
6214 @xref{Insn Attributes}. This attribute must be boolean (i.e.@: have
6215 exactly two elements in its @var{list-of-values}). Further, it must
6216 not be used with complex expressions. That is, the default and all
6217 uses in the insns must be a simple constant, not dependent on the
6218 alternative or anything else.
6220 For each @code{define_insn} for which the @code{predicable}
6221 attribute is true, a new @code{define_insn} pattern will be
6222 generated that matches a predicated version of the instruction.
6226 (define_insn "addsi"
6227 [(set (match_operand:SI 0 "register_operand" "r")
6228 (plus:SI (match_operand:SI 1 "register_operand" "r")
6229 (match_operand:SI 2 "register_operand" "r")))]
6234 [(ne (match_operand:CC 0 "register_operand" "c")
6241 generates a new pattern
6246 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
6247 (set (match_operand:SI 0 "register_operand" "r")
6248 (plus:SI (match_operand:SI 1 "register_operand" "r")
6249 (match_operand:SI 2 "register_operand" "r"))))]
6250 "(@var{test2}) && (@var{test1})"
6251 "(%3) add %2,%1,%0")
6256 @node Constant Definitions
6257 @section Constant Definitions
6258 @cindex constant definitions
6259 @findex define_constants
6261 Using literal constants inside instruction patterns reduces legibility and
6262 can be a maintenance problem.
6264 To overcome this problem, you may use the @code{define_constants}
6265 expression. It contains a vector of name-value pairs. From that
6266 point on, wherever any of the names appears in the MD file, it is as
6267 if the corresponding value had been written instead. You may use
6268 @code{define_constants} multiple times; each appearance adds more
6269 constants to the table. It is an error to redefine a constant with
6272 To come back to the a29k load multiple example, instead of
6276 [(match_parallel 0 "load_multiple_operation"
6277 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
6278 (match_operand:SI 2 "memory_operand" "m"))
6280 (clobber (reg:SI 179))])]
6296 [(match_parallel 0 "load_multiple_operation"
6297 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
6298 (match_operand:SI 2 "memory_operand" "m"))
6300 (clobber (reg:SI R_CR))])]
6305 The constants that are defined with a define_constant are also output
6306 in the insn-codes.h header file as #defines.