3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/dev/vge/if_vge.c,v 1.24 2006/02/14 12:44:56 glebius Exp $
36 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver.
38 * Written by Bill Paul <wpaul@windriver.com>
39 * Senior Networking Software Engineer
44 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that
45 * combines a tri-speed ethernet MAC and PHY, with the following
48 * o Jumbo frame support up to 16K
49 * o Transmit and receive flow control
50 * o IPv4 checksum offload
51 * o VLAN tag insertion and stripping
53 * o 64-bit multicast hash table filter
54 * o 64 entry CAM filter
55 * o 16K RX FIFO and 48K TX FIFO memory
56 * o Interrupt moderation
58 * The VT6122 supports up to four transmit DMA queues. The descriptors
59 * in the transmit ring can address up to 7 data fragments; frames which
60 * span more than 7 data buffers must be coalesced, but in general the
61 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments
62 * long. The receive descriptors address only a single buffer.
64 * There are two peculiar design issues with the VT6122. One is that
65 * receive data buffers must be aligned on a 32-bit boundary. This is
66 * not a problem where the VT6122 is used as a LOM device in x86-based
67 * systems, but on architectures that generate unaligned access traps, we
68 * have to do some copying.
70 * The other issue has to do with the way 64-bit addresses are handled.
71 * The DMA descriptors only allow you to specify 48 bits of addressing
72 * information. The remaining 16 bits are specified using one of the
73 * I/O registers. If you only have a 32-bit system, then this isn't
74 * an issue, but if you have a 64-bit system and more than 4GB of
75 * memory, you must have to make sure your network data buffers reside
76 * in the same 48-bit 'segment.'
78 * Special thanks to Ryan Fu at VIA Networking for providing documentation
79 * and sample NICs for testing.
82 #include "opt_ifpoll.h"
84 #include <sys/param.h>
85 #include <sys/endian.h>
86 #include <sys/systm.h>
87 #include <sys/sockio.h>
89 #include <sys/malloc.h>
90 #include <sys/module.h>
91 #include <sys/kernel.h>
92 #include <sys/socket.h>
93 #include <sys/serialize.h>
97 #include <sys/interrupt.h>
100 #include <net/if_arp.h>
101 #include <net/ethernet.h>
102 #include <net/if_dl.h>
103 #include <net/if_media.h>
104 #include <net/if_poll.h>
105 #include <net/ifq_var.h>
106 #include <net/if_types.h>
107 #include <net/vlan/if_vlan_var.h>
108 #include <net/vlan/if_vlan_ether.h>
112 #include <dev/netif/mii_layer/mii.h>
113 #include <dev/netif/mii_layer/miivar.h>
115 #include <bus/pci/pcireg.h>
116 #include <bus/pci/pcivar.h>
117 #include <bus/pci/pcidevs.h>
119 #include "miibus_if.h"
121 #include <dev/netif/vge/if_vgereg.h>
122 #include <dev/netif/vge/if_vgevar.h>
124 #define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
127 * Various supported device vendors/types and their names.
129 static const struct vge_type vge_devs[] = {
130 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT612X,
131 "VIA Networking Gigabit Ethernet" },
135 static int vge_probe (device_t);
136 static int vge_attach (device_t);
137 static int vge_detach (device_t);
139 static int vge_encap (struct vge_softc *, struct mbuf *, int);
141 static void vge_dma_map_addr (void *, bus_dma_segment_t *, int, int);
142 static void vge_dma_map_rx_desc (void *, bus_dma_segment_t *, int,
144 static void vge_dma_map_tx_desc (void *, bus_dma_segment_t *, int,
146 static int vge_dma_alloc (device_t);
147 static void vge_dma_free (struct vge_softc *);
148 static int vge_newbuf (struct vge_softc *, int, struct mbuf *);
149 static int vge_rx_list_init (struct vge_softc *);
150 static int vge_tx_list_init (struct vge_softc *);
152 static __inline void vge_fixup_rx
155 static void vge_rxeof (struct vge_softc *, int);
156 static void vge_txeof (struct vge_softc *);
157 static void vge_intr (void *);
158 static void vge_tick (struct vge_softc *);
159 static void vge_start (struct ifnet *, struct ifaltq_subque *);
160 static int vge_ioctl (struct ifnet *, u_long, caddr_t,
162 static void vge_init (void *);
163 static void vge_stop (struct vge_softc *);
164 static void vge_watchdog (struct ifnet *);
165 static int vge_suspend (device_t);
166 static int vge_resume (device_t);
167 static void vge_shutdown (device_t);
168 static int vge_ifmedia_upd (struct ifnet *);
169 static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *);
172 static void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *);
174 static void vge_read_eeprom (struct vge_softc *, uint8_t *, int, int, int);
176 static void vge_miipoll_start (struct vge_softc *);
177 static void vge_miipoll_stop (struct vge_softc *);
178 static int vge_miibus_readreg (device_t, int, int);
179 static int vge_miibus_writereg (device_t, int, int, int);
180 static void vge_miibus_statchg (device_t);
182 static void vge_cam_clear (struct vge_softc *);
183 static int vge_cam_set (struct vge_softc *, uint8_t *);
184 static void vge_setmulti (struct vge_softc *);
185 static void vge_reset (struct vge_softc *);
188 static void vge_npoll(struct ifnet *, struct ifpoll_info *);
189 static void vge_npoll_compat(struct ifnet *, void *, int);
190 static void vge_disable_intr(struct vge_softc *);
192 static void vge_enable_intr(struct vge_softc *, uint32_t);
194 #define VGE_PCI_LOIO 0x10
195 #define VGE_PCI_LOMEM 0x14
197 static device_method_t vge_methods[] = {
198 /* Device interface */
199 DEVMETHOD(device_probe, vge_probe),
200 DEVMETHOD(device_attach, vge_attach),
201 DEVMETHOD(device_detach, vge_detach),
202 DEVMETHOD(device_suspend, vge_suspend),
203 DEVMETHOD(device_resume, vge_resume),
204 DEVMETHOD(device_shutdown, vge_shutdown),
207 DEVMETHOD(bus_print_child, bus_generic_print_child),
208 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
211 DEVMETHOD(miibus_readreg, vge_miibus_readreg),
212 DEVMETHOD(miibus_writereg, vge_miibus_writereg),
213 DEVMETHOD(miibus_statchg, vge_miibus_statchg),
218 static driver_t vge_driver = {
221 sizeof(struct vge_softc)
224 static devclass_t vge_devclass;
226 DECLARE_DUMMY_MODULE(if_vge);
227 MODULE_DEPEND(if_vge, miibus, 1, 1, 1);
228 DRIVER_MODULE(if_vge, pci, vge_driver, vge_devclass, NULL, NULL);
229 DRIVER_MODULE(if_vge, cardbus, vge_driver, vge_devclass, NULL, NULL);
230 DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, NULL, NULL);
234 * Read a word of data stored in the EEPROM at address 'addr.'
237 vge_eeprom_getword(struct vge_softc *sc, int addr, uint16_t dest)
243 * Enter EEPROM embedded programming mode. In order to
244 * access the EEPROM at all, we first have to set the
245 * EELOAD bit in the CHIPCFG2 register.
247 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD);
248 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/);
250 /* Select the address of the word we want to read */
251 CSR_WRITE_1(sc, VGE_EEADDR, addr);
253 /* Issue read command */
254 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD);
256 /* Wait for the done bit to be set. */
257 for (i = 0; i < VGE_TIMEOUT; i++) {
258 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE)
261 if (i == VGE_TIMEOUT) {
262 device_printf(sc->vge_dev, "EEPROM read timed out\n");
267 /* Read the result */
268 word = CSR_READ_2(sc, VGE_EERDDAT);
270 /* Turn off EEPROM access mode. */
271 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/);
272 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD);
279 * Read a sequence of words from the EEPROM.
282 vge_read_eeprom(struct vge_softc *sc, uint8_t *dest, int off, int cnt, int swap)
286 uint16_t word = 0, *ptr;
288 for (i = 0; i < cnt; i++) {
289 vge_eeprom_getword(sc, off + i, &word);
290 ptr = (uint16_t *)(dest + (i * 2));
297 for (i = 0; i < ETHER_ADDR_LEN; i++)
298 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i);
303 vge_miipoll_stop(struct vge_softc *sc)
307 CSR_WRITE_1(sc, VGE_MIICMD, 0);
309 for (i = 0; i < VGE_TIMEOUT; i++) {
311 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
314 if (i == VGE_TIMEOUT)
315 if_printf(&sc->arpcom.ac_if, "failed to idle MII autopoll\n");
319 vge_miipoll_start(struct vge_softc *sc)
323 /* First, make sure we're idle. */
324 CSR_WRITE_1(sc, VGE_MIICMD, 0);
325 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL);
327 for (i = 0; i < VGE_TIMEOUT; i++) {
329 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
332 if (i == VGE_TIMEOUT) {
333 if_printf(&sc->arpcom.ac_if, "failed to idle MII autopoll\n");
337 /* Now enable auto poll mode. */
338 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO);
340 /* And make sure it started. */
341 for (i = 0; i < VGE_TIMEOUT; i++) {
343 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0)
346 if (i == VGE_TIMEOUT)
347 if_printf(&sc->arpcom.ac_if, "failed to start MII autopoll\n");
351 vge_miibus_readreg(device_t dev, int phy, int reg)
353 struct vge_softc *sc;
357 sc = device_get_softc(dev);
359 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F))
362 vge_miipoll_stop(sc);
364 /* Specify the register we want to read. */
365 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
367 /* Issue read command. */
368 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD);
370 /* Wait for the read command bit to self-clear. */
371 for (i = 0; i < VGE_TIMEOUT; i++) {
373 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0)
376 if (i == VGE_TIMEOUT)
377 if_printf(&sc->arpcom.ac_if, "MII read timed out\n");
379 rval = CSR_READ_2(sc, VGE_MIIDATA);
381 vge_miipoll_start(sc);
387 vge_miibus_writereg(device_t dev, int phy, int reg, int data)
389 struct vge_softc *sc;
392 sc = device_get_softc(dev);
394 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F))
397 vge_miipoll_stop(sc);
399 /* Specify the register we want to write. */
400 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
402 /* Specify the data we want to write. */
403 CSR_WRITE_2(sc, VGE_MIIDATA, data);
405 /* Issue write command. */
406 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD);
408 /* Wait for the write command bit to self-clear. */
409 for (i = 0; i < VGE_TIMEOUT; i++) {
411 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0)
414 if (i == VGE_TIMEOUT) {
415 if_printf(&sc->arpcom.ac_if, "MII write timed out\n");
419 vge_miipoll_start(sc);
425 vge_cam_clear(struct vge_softc *sc)
430 * Turn off all the mask bits. This tells the chip
431 * that none of the entries in the CAM filter are valid.
432 * desired entries will be enabled as we fill the filter in.
434 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
435 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
436 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE);
437 for (i = 0; i < 8; i++)
438 CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
440 /* Clear the VLAN filter too. */
441 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0);
442 for (i = 0; i < 8; i++)
443 CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
445 CSR_WRITE_1(sc, VGE_CAMADDR, 0);
446 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
447 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
453 vge_cam_set(struct vge_softc *sc, uint8_t *addr)
457 if (sc->vge_camidx == VGE_CAM_MAXADDRS)
460 /* Select the CAM data page. */
461 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
462 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA);
464 /* Set the filter entry we want to update and enable writing. */
465 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx);
467 /* Write the address to the CAM registers */
468 for (i = 0; i < ETHER_ADDR_LEN; i++)
469 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]);
471 /* Issue a write command. */
472 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE);
474 /* Wake for it to clear. */
475 for (i = 0; i < VGE_TIMEOUT; i++) {
477 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0)
480 if (i == VGE_TIMEOUT) {
481 if_printf(&sc->arpcom.ac_if, "setting CAM filter failed\n");
486 /* Select the CAM mask page. */
487 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
488 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
490 /* Set the mask bit that enables this filter. */
491 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8),
492 1<<(sc->vge_camidx & 7));
497 /* Turn off access to CAM. */
498 CSR_WRITE_1(sc, VGE_CAMADDR, 0);
499 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
500 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
506 * Program the multicast filter. We use the 64-entry CAM filter
507 * for perfect filtering. If there's more than 64 multicast addresses,
508 * we use the hash filter insted.
511 vge_setmulti(struct vge_softc *sc)
513 struct ifnet *ifp = &sc->arpcom.ac_if;
515 struct ifmultiaddr *ifma;
516 uint32_t h, hashes[2] = { 0, 0 };
518 /* First, zot all the multicast entries. */
520 CSR_WRITE_4(sc, VGE_MAR0, 0);
521 CSR_WRITE_4(sc, VGE_MAR1, 0);
524 * If the user wants allmulti or promisc mode, enable reception
525 * of all multicast frames.
527 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
528 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF);
529 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF);
533 /* Now program new ones */
534 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
535 if (ifma->ifma_addr->sa_family != AF_LINK)
537 error = vge_cam_set(sc,
538 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
543 /* If there were too many addresses, use the hash filter. */
547 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
548 if (ifma->ifma_addr->sa_family != AF_LINK)
550 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
551 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
553 hashes[0] |= (1 << h);
555 hashes[1] |= (1 << (h - 32));
558 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]);
559 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]);
564 vge_reset(struct vge_softc *sc)
568 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET);
570 for (i = 0; i < VGE_TIMEOUT; i++) {
572 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0)
576 if (i == VGE_TIMEOUT) {
577 if_printf(&sc->arpcom.ac_if, "soft reset timed out");
578 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE);
584 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD);
586 for (i = 0; i < VGE_TIMEOUT; i++) {
588 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0)
591 if (i == VGE_TIMEOUT) {
592 if_printf(&sc->arpcom.ac_if, "EEPROM reload timed out\n");
596 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI);
600 * Probe for a VIA gigabit chip. Check the PCI vendor and device
601 * IDs against our list and return a device name if we find a match.
604 vge_probe(device_t dev)
606 const struct vge_type *t;
609 did = pci_get_device(dev);
610 vid = pci_get_vendor(dev);
611 for (t = vge_devs; t->vge_name != NULL; ++t) {
612 if (vid == t->vge_vid && did == t->vge_did) {
613 device_set_desc(dev, t->vge_name);
621 vge_dma_map_rx_desc(void *arg, bus_dma_segment_t *segs, int nseg,
622 bus_size_t mapsize, int error)
625 struct vge_dmaload_arg *ctx;
626 struct vge_rx_desc *d = NULL;
633 /* Signal error to caller if there's too many segments */
634 if (nseg > ctx->vge_maxsegs) {
635 ctx->vge_maxsegs = 0;
640 * Map the segment array into descriptors.
642 d = &ctx->sc->vge_ldata.vge_rx_list[ctx->vge_idx];
644 /* If this descriptor is still owned by the chip, bail. */
645 if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) {
646 if_printf(&ctx->sc->arpcom.ac_if,
647 "tried to map busy descriptor\n");
648 ctx->vge_maxsegs = 0;
652 d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I);
653 d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr));
654 d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF);
658 ctx->vge_maxsegs = 1;
662 vge_dma_map_tx_desc(void *arg, bus_dma_segment_t *segs, int nseg,
663 bus_size_t mapsize, int error)
665 struct vge_dmaload_arg *ctx;
666 struct vge_tx_desc *d = NULL;
667 struct vge_tx_frag *f;
675 /* Signal error to caller if there's too many segments */
676 if (nseg > ctx->vge_maxsegs) {
677 ctx->vge_maxsegs = 0;
681 /* Map the segment array into descriptors. */
682 d = &ctx->sc->vge_ldata.vge_tx_list[ctx->vge_idx];
684 /* If this descriptor is still owned by the chip, bail. */
685 if (le32toh(d->vge_sts) & VGE_TDSTS_OWN) {
686 ctx->vge_maxsegs = 0;
690 for (i = 0; i < nseg; i++) {
692 f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len));
693 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr));
694 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF);
697 /* Argh. This chip does not autopad short frames */
698 if (ctx->vge_m0->m_pkthdr.len < VGE_MIN_FRAMELEN) {
700 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN -
701 ctx->vge_m0->m_pkthdr.len));
702 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr));
703 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF);
704 ctx->vge_m0->m_pkthdr.len = VGE_MIN_FRAMELEN;
709 * When telling the chip how many segments there are, we
710 * must use nsegs + 1 instead of just nsegs. Darned if I
715 d->vge_sts = ctx->vge_m0->m_pkthdr.len << 16;
716 d->vge_ctl = ctx->vge_flags|(i << 28)|VGE_TD_LS_NORM;
718 if (ctx->vge_m0->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN)
719 d->vge_ctl |= VGE_TDCTL_JUMBO;
721 ctx->vge_maxsegs = nseg;
725 * Map a single buffer address.
729 vge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
734 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
735 *((bus_addr_t *)arg) = segs->ds_addr;
739 vge_dma_alloc(device_t dev)
741 struct vge_softc *sc = device_get_softc(dev);
742 int error, nseg, i, tx_pos = 0, rx_pos = 0;
745 * Allocate the parent bus DMA tag appropriate for PCI.
747 #define VGE_NSEG_NEW 32
748 error = bus_dma_tag_create(NULL, /* parent */
749 1, 0, /* alignment, boundary */
750 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
751 BUS_SPACE_MAXADDR, /* highaddr */
752 NULL, NULL, /* filter, filterarg */
753 MAXBSIZE, VGE_NSEG_NEW, /* maxsize, nsegments */
754 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
755 BUS_DMA_ALLOCNOW, /* flags */
756 &sc->vge_parent_tag);
758 device_printf(dev, "can't create parent dma tag\n");
763 * Allocate map for RX mbufs.
766 error = bus_dma_tag_create(sc->vge_parent_tag, ETHER_ALIGN, 0,
767 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
769 MCLBYTES * nseg, nseg, MCLBYTES,
770 BUS_DMA_ALLOCNOW, &sc->vge_ldata.vge_mtag);
772 device_printf(dev, "could not allocate mbuf dma tag\n");
777 * Allocate map for TX descriptor list.
779 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 0,
780 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
782 VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ,
784 &sc->vge_ldata.vge_tx_list_tag);
786 device_printf(dev, "could not allocate tx list dma tag\n");
790 /* Allocate DMA'able memory for the TX ring */
791 error = bus_dmamem_alloc(sc->vge_ldata.vge_tx_list_tag,
792 (void **)&sc->vge_ldata.vge_tx_list,
793 BUS_DMA_WAITOK | BUS_DMA_ZERO,
794 &sc->vge_ldata.vge_tx_list_map);
796 device_printf(dev, "could not allocate tx list dma memory\n");
800 /* Load the map for the TX ring. */
801 error = bus_dmamap_load(sc->vge_ldata.vge_tx_list_tag,
802 sc->vge_ldata.vge_tx_list_map,
803 sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ,
805 &sc->vge_ldata.vge_tx_list_addr,
808 device_printf(dev, "could not load tx list\n");
809 bus_dmamem_free(sc->vge_ldata.vge_tx_list_tag,
810 sc->vge_ldata.vge_tx_list,
811 sc->vge_ldata.vge_tx_list_map);
812 sc->vge_ldata.vge_tx_list = NULL;
816 /* Create DMA maps for TX buffers */
817 for (i = 0; i < VGE_TX_DESC_CNT; i++) {
818 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0,
819 &sc->vge_ldata.vge_tx_dmamap[i]);
821 device_printf(dev, "can't create DMA map for TX\n");
826 tx_pos = VGE_TX_DESC_CNT;
829 * Allocate map for RX descriptor list.
831 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 0,
832 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
834 VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ,
836 &sc->vge_ldata.vge_rx_list_tag);
838 device_printf(dev, "could not allocate rx list dma tag\n");
842 /* Allocate DMA'able memory for the RX ring */
843 error = bus_dmamem_alloc(sc->vge_ldata.vge_rx_list_tag,
844 (void **)&sc->vge_ldata.vge_rx_list,
845 BUS_DMA_WAITOK | BUS_DMA_ZERO,
846 &sc->vge_ldata.vge_rx_list_map);
848 device_printf(dev, "could not allocate rx list dma memory\n");
852 /* Load the map for the RX ring. */
853 error = bus_dmamap_load(sc->vge_ldata.vge_rx_list_tag,
854 sc->vge_ldata.vge_rx_list_map,
855 sc->vge_ldata.vge_rx_list, VGE_TX_LIST_SZ,
857 &sc->vge_ldata.vge_rx_list_addr,
860 device_printf(dev, "could not load rx list\n");
861 bus_dmamem_free(sc->vge_ldata.vge_rx_list_tag,
862 sc->vge_ldata.vge_rx_list,
863 sc->vge_ldata.vge_rx_list_map);
864 sc->vge_ldata.vge_rx_list = NULL;
868 /* Create DMA maps for RX buffers */
869 for (i = 0; i < VGE_RX_DESC_CNT; i++) {
870 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0,
871 &sc->vge_ldata.vge_rx_dmamap[i]);
873 device_printf(dev, "can't create DMA map for RX\n");
881 for (i = 0; i < tx_pos; ++i) {
882 error = bus_dmamap_destroy(sc->vge_ldata.vge_mtag,
883 sc->vge_ldata.vge_tx_dmamap[i]);
885 for (i = 0; i < rx_pos; ++i) {
886 error = bus_dmamap_destroy(sc->vge_ldata.vge_mtag,
887 sc->vge_ldata.vge_rx_dmamap[i]);
889 bus_dma_tag_destroy(sc->vge_ldata.vge_mtag);
890 sc->vge_ldata.vge_mtag = NULL;
896 vge_dma_free(struct vge_softc *sc)
898 /* Unload and free the RX DMA ring memory and map */
899 if (sc->vge_ldata.vge_rx_list_tag) {
900 bus_dmamap_unload(sc->vge_ldata.vge_rx_list_tag,
901 sc->vge_ldata.vge_rx_list_map);
902 bus_dmamem_free(sc->vge_ldata.vge_rx_list_tag,
903 sc->vge_ldata.vge_rx_list,
904 sc->vge_ldata.vge_rx_list_map);
907 if (sc->vge_ldata.vge_rx_list_tag)
908 bus_dma_tag_destroy(sc->vge_ldata.vge_rx_list_tag);
910 /* Unload and free the TX DMA ring memory and map */
911 if (sc->vge_ldata.vge_tx_list_tag) {
912 bus_dmamap_unload(sc->vge_ldata.vge_tx_list_tag,
913 sc->vge_ldata.vge_tx_list_map);
914 bus_dmamem_free(sc->vge_ldata.vge_tx_list_tag,
915 sc->vge_ldata.vge_tx_list,
916 sc->vge_ldata.vge_tx_list_map);
919 if (sc->vge_ldata.vge_tx_list_tag)
920 bus_dma_tag_destroy(sc->vge_ldata.vge_tx_list_tag);
922 /* Destroy all the RX and TX buffer maps */
923 if (sc->vge_ldata.vge_mtag) {
926 for (i = 0; i < VGE_TX_DESC_CNT; i++) {
927 bus_dmamap_destroy(sc->vge_ldata.vge_mtag,
928 sc->vge_ldata.vge_tx_dmamap[i]);
930 for (i = 0; i < VGE_RX_DESC_CNT; i++) {
931 bus_dmamap_destroy(sc->vge_ldata.vge_mtag,
932 sc->vge_ldata.vge_rx_dmamap[i]);
934 bus_dma_tag_destroy(sc->vge_ldata.vge_mtag);
937 if (sc->vge_parent_tag)
938 bus_dma_tag_destroy(sc->vge_parent_tag);
942 * Attach the interface. Allocate softc structures, do ifmedia
943 * setup and ethernet/BPF attach.
946 vge_attach(device_t dev)
948 uint8_t eaddr[ETHER_ADDR_LEN];
949 struct vge_softc *sc;
953 sc = device_get_softc(dev);
954 ifp = &sc->arpcom.ac_if;
956 /* Initialize if_xname early, so if_printf() can be used */
957 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
960 * Map control/status registers.
962 pci_enable_busmaster(dev);
964 sc->vge_res_rid = VGE_PCI_LOMEM;
965 sc->vge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
966 &sc->vge_res_rid, RF_ACTIVE);
967 if (sc->vge_res == NULL) {
968 device_printf(dev, "couldn't map ports/memory\n");
972 sc->vge_btag = rman_get_bustag(sc->vge_res);
973 sc->vge_bhandle = rman_get_bushandle(sc->vge_res);
975 /* Allocate interrupt */
977 sc->vge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->vge_irq_rid,
978 RF_SHAREABLE | RF_ACTIVE);
979 if (sc->vge_irq == NULL) {
980 device_printf(dev, "couldn't map interrupt\n");
985 /* Reset the adapter. */
989 * Get station address from the EEPROM.
991 vge_read_eeprom(sc, eaddr, VGE_EE_EADDR, 3, 0);
993 /* Allocate DMA related stuffs */
994 error = vge_dma_alloc(dev);
999 error = mii_phy_probe(dev, &sc->vge_miibus, vge_ifmedia_upd,
1002 device_printf(dev, "MII without any phy!\n");
1007 ifp->if_mtu = ETHERMTU;
1008 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1009 ifp->if_init = vge_init;
1010 ifp->if_start = vge_start;
1011 ifp->if_watchdog = vge_watchdog;
1012 ifp->if_ioctl = vge_ioctl;
1013 #ifdef IFPOLL_ENABLE
1014 ifp->if_npoll = vge_npoll;
1016 ifp->if_hwassist = VGE_CSUM_FEATURES;
1017 ifp->if_capabilities = IFCAP_VLAN_MTU |
1019 IFCAP_VLAN_HWTAGGING;
1020 ifp->if_capenable = ifp->if_capabilities;
1021 ifq_set_maxlen(&ifp->if_snd, VGE_IFQ_MAXLEN);
1022 ifq_set_ready(&ifp->if_snd);
1025 * Call MI attach routine.
1027 ether_ifattach(ifp, eaddr, NULL);
1029 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->vge_irq));
1031 #ifdef IFPOLL_ENABLE
1032 ifpoll_compat_setup(&sc->vge_npoll, NULL, NULL, device_get_unit(dev),
1033 ifp->if_serializer);
1036 /* Hook interrupt last to avoid having to lock softc */
1037 error = bus_setup_intr(dev, sc->vge_irq, INTR_MPSAFE, vge_intr, sc,
1038 &sc->vge_intrhand, ifp->if_serializer);
1040 device_printf(dev, "couldn't set up irq\n");
1041 ether_ifdetach(ifp);
1052 * Shutdown hardware and free up resources. This can be called any
1053 * time after the mutex has been initialized. It is called in both
1054 * the error case in attach and the normal detach case so it needs
1055 * to be careful about only freeing resources that have actually been
1059 vge_detach(device_t dev)
1061 struct vge_softc *sc = device_get_softc(dev);
1062 struct ifnet *ifp = &sc->arpcom.ac_if;
1064 /* These should only be active if attach succeeded */
1065 if (device_is_attached(dev)) {
1066 lwkt_serialize_enter(ifp->if_serializer);
1069 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand);
1071 * Force off the IFF_UP flag here, in case someone
1072 * still had a BPF descriptor attached to this
1073 * interface. If they do, ether_ifattach() will cause
1074 * the BPF code to try and clear the promisc mode
1075 * flag, which will bubble down to vge_ioctl(),
1076 * which will try to call vge_init() again. This will
1077 * turn the NIC back on and restart the MII ticker,
1078 * which will panic the system when the kernel tries
1079 * to invoke the vge_tick() function that isn't there
1082 ifp->if_flags &= ~IFF_UP;
1084 lwkt_serialize_exit(ifp->if_serializer);
1086 ether_ifdetach(ifp);
1090 device_delete_child(dev, sc->vge_miibus);
1091 bus_generic_detach(dev);
1094 bus_release_resource(dev, SYS_RES_IRQ, sc->vge_irq_rid,
1099 bus_release_resource(dev, SYS_RES_MEMORY, sc->vge_res_rid,
1108 vge_newbuf(struct vge_softc *sc, int idx, struct mbuf *m)
1110 struct vge_dmaload_arg arg;
1111 struct mbuf *n = NULL;
1115 n = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1120 m->m_data = m->m_ext.ext_buf;
1126 * This is part of an evil trick to deal with non-x86 platforms.
1127 * The VIA chip requires RX buffers to be aligned on 32-bit
1128 * boundaries, but that will hose non-x86 machines. To get around
1129 * this, we leave some empty space at the start of each buffer
1130 * and for non-x86 hosts, we copy the buffer back two bytes
1131 * to achieve word alignment. This is slightly more efficient
1132 * than allocating a new buffer, copying the contents, and
1133 * discarding the old buffer.
1135 m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN;
1136 m_adj(m, VGE_ETHER_ALIGN);
1138 m->m_len = m->m_pkthdr.len = MCLBYTES;
1143 arg.vge_maxsegs = 1;
1146 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag,
1147 sc->vge_ldata.vge_rx_dmamap[idx], m,
1148 vge_dma_map_rx_desc, &arg, BUS_DMA_NOWAIT);
1149 if (error || arg.vge_maxsegs != 1) {
1156 * Note: the manual fails to document the fact that for
1157 * proper opration, the driver needs to replentish the RX
1158 * DMA ring 4 descriptors at a time (rather than one at a
1159 * time, like most chips). We can allocate the new buffers
1160 * but we should not set the OWN bits until we're ready
1161 * to hand back 4 of them in one shot.
1164 #define VGE_RXCHUNK 4
1165 sc->vge_rx_consumed++;
1166 if (sc->vge_rx_consumed == VGE_RXCHUNK) {
1167 for (i = idx; i != idx - sc->vge_rx_consumed; i--) {
1168 sc->vge_ldata.vge_rx_list[i].vge_sts |=
1169 htole32(VGE_RDSTS_OWN);
1171 sc->vge_rx_consumed = 0;
1174 sc->vge_ldata.vge_rx_mbuf[idx] = m;
1176 bus_dmamap_sync(sc->vge_ldata.vge_mtag,
1177 sc->vge_ldata.vge_rx_dmamap[idx], BUS_DMASYNC_PREREAD);
1183 vge_tx_list_init(struct vge_softc *sc)
1185 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ);
1186 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf,
1187 (VGE_TX_DESC_CNT * sizeof(struct mbuf *)));
1189 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag,
1190 sc->vge_ldata.vge_tx_list_map, BUS_DMASYNC_PREWRITE);
1191 sc->vge_ldata.vge_tx_prodidx = 0;
1192 sc->vge_ldata.vge_tx_considx = 0;
1193 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT;
1199 vge_rx_list_init(struct vge_softc *sc)
1203 bzero(sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ);
1204 bzero(&sc->vge_ldata.vge_rx_mbuf,
1205 VGE_RX_DESC_CNT * sizeof(struct mbuf *));
1207 sc->vge_rx_consumed = 0;
1209 for (i = 0; i < VGE_RX_DESC_CNT; i++) {
1210 if (vge_newbuf(sc, i, NULL) == ENOBUFS)
1214 /* Flush the RX descriptors */
1215 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag,
1216 sc->vge_ldata.vge_rx_list_map,
1217 BUS_DMASYNC_PREWRITE);
1219 sc->vge_ldata.vge_rx_prodidx = 0;
1220 sc->vge_rx_consumed = 0;
1221 sc->vge_head = sc->vge_tail = NULL;
1226 static __inline void
1227 vge_fixup_rx(struct mbuf *m)
1229 uint16_t *src, *dst;
1232 src = mtod(m, uint16_t *);
1235 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1238 m->m_data -= ETHER_ALIGN;
1243 * RX handler. We support the reception of jumbo frames that have
1244 * been fragmented across multiple 2K mbuf cluster buffers.
1247 vge_rxeof(struct vge_softc *sc, int count)
1249 struct ifnet *ifp = &sc->arpcom.ac_if;
1251 int i, total_len, lim = 0;
1252 struct vge_rx_desc *cur_rx;
1253 uint32_t rxstat, rxctl;
1255 ASSERT_SERIALIZED(ifp->if_serializer);
1257 i = sc->vge_ldata.vge_rx_prodidx;
1259 /* Invalidate the descriptor memory */
1261 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag,
1262 sc->vge_ldata.vge_rx_list_map, BUS_DMASYNC_POSTREAD);
1264 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) {
1265 #ifdef IFPOLL_ENABLE
1266 if (count >= 0 && count-- == 0)
1270 cur_rx = &sc->vge_ldata.vge_rx_list[i];
1271 m = sc->vge_ldata.vge_rx_mbuf[i];
1272 total_len = VGE_RXBYTES(cur_rx);
1273 rxstat = le32toh(cur_rx->vge_sts);
1274 rxctl = le32toh(cur_rx->vge_ctl);
1276 /* Invalidate the RX mbuf and unload its map */
1277 bus_dmamap_sync(sc->vge_ldata.vge_mtag,
1278 sc->vge_ldata.vge_rx_dmamap[i],
1279 BUS_DMASYNC_POSTWRITE);
1280 bus_dmamap_unload(sc->vge_ldata.vge_mtag,
1281 sc->vge_ldata.vge_rx_dmamap[i]);
1284 * If the 'start of frame' bit is set, this indicates
1285 * either the first fragment in a multi-fragment receive,
1286 * or an intermediate fragment. Either way, we want to
1287 * accumulate the buffers.
1289 if (rxstat & VGE_RXPKT_SOF) {
1290 m->m_len = MCLBYTES - VGE_ETHER_ALIGN;
1291 if (sc->vge_head == NULL) {
1292 sc->vge_head = sc->vge_tail = m;
1294 m->m_flags &= ~M_PKTHDR;
1295 sc->vge_tail->m_next = m;
1298 vge_newbuf(sc, i, NULL);
1304 * Bad/error frames will have the RXOK bit cleared.
1305 * However, there's one error case we want to allow:
1306 * if a VLAN tagged frame arrives and the chip can't
1307 * match it against the CAM filter, it considers this
1308 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit.
1309 * We don't want to drop the frame though: our VLAN
1310 * filtering is done in software.
1312 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) &&
1313 !(rxstat & VGE_RDSTS_CSUMERR)) {
1314 IFNET_STAT_INC(ifp, ierrors, 1);
1316 * If this is part of a multi-fragment packet,
1317 * discard all the pieces.
1319 if (sc->vge_head != NULL) {
1320 m_freem(sc->vge_head);
1321 sc->vge_head = sc->vge_tail = NULL;
1323 vge_newbuf(sc, i, m);
1329 * If allocating a replacement mbuf fails,
1330 * reload the current one.
1332 if (vge_newbuf(sc, i, NULL)) {
1333 IFNET_STAT_INC(ifp, ierrors, 1);
1334 if (sc->vge_head != NULL) {
1335 m_freem(sc->vge_head);
1336 sc->vge_head = sc->vge_tail = NULL;
1338 vge_newbuf(sc, i, m);
1345 if (sc->vge_head != NULL) {
1346 m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN);
1348 * Special case: if there's 4 bytes or less
1349 * in this buffer, the mbuf can be discarded:
1350 * the last 4 bytes is the CRC, which we don't
1351 * care about anyway.
1353 if (m->m_len <= ETHER_CRC_LEN) {
1354 sc->vge_tail->m_len -=
1355 (ETHER_CRC_LEN - m->m_len);
1358 m->m_len -= ETHER_CRC_LEN;
1359 m->m_flags &= ~M_PKTHDR;
1360 sc->vge_tail->m_next = m;
1363 sc->vge_head = sc->vge_tail = NULL;
1364 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1366 m->m_pkthdr.len = m->m_len =
1367 (total_len - ETHER_CRC_LEN);
1373 IFNET_STAT_INC(ifp, ipackets, 1);
1374 m->m_pkthdr.rcvif = ifp;
1376 /* Do RX checksumming if enabled */
1377 if (ifp->if_capenable & IFCAP_RXCSUM) {
1378 /* Check IP header checksum */
1379 if (rxctl & VGE_RDCTL_IPPKT)
1380 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1381 if (rxctl & VGE_RDCTL_IPCSUMOK)
1382 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1384 /* Check TCP/UDP checksum */
1385 if (rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT) &&
1386 rxctl & VGE_RDCTL_PROTOCSUMOK) {
1387 m->m_pkthdr.csum_flags |=
1388 CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
1389 CSUM_FRAG_NOT_CHECKED;
1390 m->m_pkthdr.csum_data = 0xffff;
1394 if (rxstat & VGE_RDSTS_VTAG) {
1395 m->m_flags |= M_VLANTAG;
1396 m->m_pkthdr.ether_vlantag =
1397 ntohs((rxctl & VGE_RDCTL_VLANID));
1399 ifp->if_input(ifp, m);
1402 if (lim == VGE_RX_DESC_CNT)
1406 /* Flush the RX DMA ring */
1407 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag,
1408 sc->vge_ldata.vge_rx_list_map,
1409 BUS_DMASYNC_PREWRITE);
1411 sc->vge_ldata.vge_rx_prodidx = i;
1412 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim);
1416 vge_txeof(struct vge_softc *sc)
1418 struct ifnet *ifp = &sc->arpcom.ac_if;
1422 idx = sc->vge_ldata.vge_tx_considx;
1424 /* Invalidate the TX descriptor list */
1426 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag,
1427 sc->vge_ldata.vge_tx_list_map, BUS_DMASYNC_POSTREAD);
1429 while (idx != sc->vge_ldata.vge_tx_prodidx) {
1431 txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts);
1432 if (txstat & VGE_TDSTS_OWN)
1435 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]);
1436 sc->vge_ldata.vge_tx_mbuf[idx] = NULL;
1437 bus_dmamap_unload(sc->vge_ldata.vge_mtag,
1438 sc->vge_ldata.vge_tx_dmamap[idx]);
1439 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL))
1440 IFNET_STAT_INC(ifp, collisions, 1);
1441 if (txstat & VGE_TDSTS_TXERR)
1442 IFNET_STAT_INC(ifp, oerrors, 1);
1444 IFNET_STAT_INC(ifp, opackets, 1);
1446 sc->vge_ldata.vge_tx_free++;
1447 VGE_TX_DESC_INC(idx);
1450 /* No changes made to the TX ring, so no flush needed */
1451 if (idx != sc->vge_ldata.vge_tx_considx) {
1452 sc->vge_ldata.vge_tx_considx = idx;
1453 ifq_clr_oactive(&ifp->if_snd);
1458 * If not all descriptors have been released reaped yet,
1459 * reload the timer so that we will eventually get another
1460 * interrupt that will cause us to re-enter this routine.
1461 * This is done in case the transmitter has gone idle.
1463 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT)
1464 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE);
1468 vge_tick(struct vge_softc *sc)
1470 struct ifnet *ifp = &sc->arpcom.ac_if;
1471 struct mii_data *mii;
1473 mii = device_get_softc(sc->vge_miibus);
1477 if (!(mii->mii_media_status & IFM_ACTIVE))
1480 if (mii->mii_media_status & IFM_ACTIVE &&
1481 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1483 if (!ifq_is_empty(&ifp->if_snd))
1489 #ifdef IFPOLL_ENABLE
1492 vge_npoll_compat(struct ifnet *ifp, void *arg __unused, int count)
1494 struct vge_softc *sc = ifp->if_softc;
1496 ASSERT_SERIALIZED(ifp->if_serializer);
1498 vge_rxeof(sc, count);
1501 if (!ifq_is_empty(&ifp->if_snd))
1504 /* XXX copy & paste from vge_intr */
1505 if (sc->vge_npoll.ifpc_stcount-- == 0) {
1508 sc->vge_npoll.ifpc_stcount = sc->vge_npoll.ifpc_stfrac;
1510 status = CSR_READ_4(sc, VGE_ISR);
1511 if (status == 0xffffffff)
1515 CSR_WRITE_4(sc, VGE_ISR, status);
1517 if (status & (VGE_ISR_TXDMA_STALL |
1518 VGE_ISR_RXDMA_STALL))
1521 if (status & (VGE_ISR_RXOFLOW | VGE_ISR_RXNODESC)) {
1522 IFNET_STAT_INC(ifp, ierrors, 1);
1523 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
1524 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
1530 vge_npoll(struct ifnet *ifp, struct ifpoll_info *info)
1532 struct vge_softc *sc = ifp->if_softc;
1534 ASSERT_SERIALIZED(ifp->if_serializer);
1537 int cpuid = sc->vge_npoll.ifpc_cpuid;
1539 info->ifpi_rx[cpuid].poll_func = vge_npoll_compat;
1540 info->ifpi_rx[cpuid].arg = NULL;
1541 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
1543 if (ifp->if_flags & IFF_RUNNING)
1544 vge_disable_intr(sc);
1545 ifq_set_cpuid(&ifp->if_snd, cpuid);
1547 if (ifp->if_flags & IFF_RUNNING)
1548 vge_enable_intr(sc, 0xffffffff);
1549 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->vge_irq));
1553 #endif /* IFPOLL_ENABLE */
1558 struct vge_softc *sc = arg;
1559 struct ifnet *ifp = &sc->arpcom.ac_if;
1562 if (sc->suspended || !(ifp->if_flags & IFF_UP))
1565 /* Disable interrupts */
1566 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
1569 status = CSR_READ_4(sc, VGE_ISR);
1570 /* If the card has gone away the read returns 0xffff. */
1571 if (status == 0xFFFFFFFF)
1575 CSR_WRITE_4(sc, VGE_ISR, status);
1577 if ((status & VGE_INTRS) == 0)
1580 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO))
1583 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) {
1585 IFNET_STAT_INC(ifp, ierrors, 1);
1586 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
1587 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
1590 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0))
1593 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL))
1596 if (status & VGE_ISR_LINKSTS)
1600 /* Re-enable interrupts */
1601 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
1603 if (!ifq_is_empty(&ifp->if_snd))
1608 vge_encap(struct vge_softc *sc, struct mbuf *m_head, int idx)
1610 struct vge_dmaload_arg arg;
1616 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1617 arg.vge_flags |= VGE_TDCTL_IPCSUM;
1618 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
1619 arg.vge_flags |= VGE_TDCTL_TCPCSUM;
1620 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
1621 arg.vge_flags |= VGE_TDCTL_UDPCSUM;
1625 arg.vge_m0 = m_head;
1626 arg.vge_maxsegs = VGE_TX_FRAGS;
1628 map = sc->vge_ldata.vge_tx_dmamap[idx];
1629 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, m_head,
1630 vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT);
1631 if (error && error != EFBIG) {
1632 if_printf(&sc->arpcom.ac_if, "can't map mbuf (error %d)\n",
1637 /* Too many segments to map, coalesce into a single mbuf */
1638 if (error || arg.vge_maxsegs == 0) {
1641 m_new = m_defrag(m_head, MB_DONTWAIT);
1642 if (m_new == NULL) {
1650 arg.vge_m0 = m_head;
1652 arg.vge_maxsegs = 1;
1654 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map,
1655 m_head, vge_dma_map_tx_desc, &arg,
1658 if_printf(&sc->arpcom.ac_if,
1659 "can't map mbuf (error %d)\n", error);
1664 sc->vge_ldata.vge_tx_mbuf[idx] = m_head;
1665 sc->vge_ldata.vge_tx_free--;
1668 * Set up hardware VLAN tagging.
1670 if (m_head->m_flags & M_VLANTAG) {
1671 sc->vge_ldata.vge_tx_list[idx].vge_ctl |=
1672 htole32(htons(m_head->m_pkthdr.ether_vlantag) |
1676 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN);
1685 * Main transmit routine.
1689 vge_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1691 struct vge_softc *sc = ifp->if_softc;
1692 struct mbuf *m_head = NULL;
1695 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1696 ASSERT_SERIALIZED(ifp->if_serializer);
1698 if (!sc->vge_link) {
1699 ifq_purge(&ifp->if_snd);
1703 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
1706 idx = sc->vge_ldata.vge_tx_prodidx;
1710 pidx = VGE_TX_DESC_CNT - 1;
1712 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) {
1713 if (sc->vge_ldata.vge_tx_free <= 2) {
1714 ifq_set_oactive(&ifp->if_snd);
1718 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1722 if (vge_encap(sc, m_head, idx)) {
1723 /* If vge_encap() failed, it will free m_head for us */
1724 ifq_set_oactive(&ifp->if_snd);
1728 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |=
1729 htole16(VGE_TXDESC_Q);
1732 VGE_TX_DESC_INC(idx);
1735 * If there's a BPF listener, bounce a copy of this frame
1738 ETHER_BPF_MTAP(ifp, m_head);
1741 if (idx == sc->vge_ldata.vge_tx_prodidx)
1744 /* Flush the TX descriptors */
1745 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag,
1746 sc->vge_ldata.vge_tx_list_map,
1747 BUS_DMASYNC_PREWRITE);
1749 /* Issue a transmit command. */
1750 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0);
1752 sc->vge_ldata.vge_tx_prodidx = idx;
1755 * Use the countdown timer for interrupt moderation.
1756 * 'TX done' interrupts are disabled. Instead, we reset the
1757 * countdown timer, which will begin counting until it hits
1758 * the value in the SSTIMER register, and then trigger an
1759 * interrupt. Each time we set the TIMER0_ENABLE bit, the
1760 * the timer count is reloaded. Only when the transmitter
1761 * is idle will the timer hit 0 and an interrupt fire.
1763 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE);
1766 * Set a timeout in case the chip goes out to lunch.
1774 struct vge_softc *sc = xsc;
1775 struct ifnet *ifp = &sc->arpcom.ac_if;
1776 struct mii_data *mii;
1779 ASSERT_SERIALIZED(ifp->if_serializer);
1781 mii = device_get_softc(sc->vge_miibus);
1784 * Cancel pending I/O and free all RX/TX buffers.
1790 * Initialize the RX and TX descriptors and mbufs.
1792 vge_rx_list_init(sc);
1793 vge_tx_list_init(sc);
1795 /* Set our station address */
1796 for (i = 0; i < ETHER_ADDR_LEN; i++)
1797 CSR_WRITE_1(sc, VGE_PAR0 + i, IF_LLADDR(ifp)[i]);
1800 * Set receive FIFO threshold. Also allow transmission and
1801 * reception of VLAN tagged frames.
1803 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT);
1804 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2);
1806 /* Set DMA burst length */
1807 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN);
1808 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128);
1810 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK);
1812 /* Set collision backoff algorithm */
1813 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM|
1814 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT);
1815 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET);
1817 /* Disable LPSEL field in priority resolution */
1818 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS);
1821 * Load the addresses of the DMA queues into the chip.
1822 * Note that we only use one transmit queue.
1824 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0,
1825 VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr));
1826 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1);
1828 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO,
1829 VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr));
1830 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1);
1831 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT);
1833 /* Enable and wake up the RX descriptor queue */
1834 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
1835 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
1837 /* Enable the TX descriptor queue */
1838 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0);
1840 /* Set up the receive filter -- allow large frames for VLANs. */
1841 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT);
1843 /* If we want promiscuous mode, set the allframes bit. */
1844 if (ifp->if_flags & IFF_PROMISC)
1845 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC);
1847 /* Set capture broadcast bit to capture broadcast frames. */
1848 if (ifp->if_flags & IFF_BROADCAST)
1849 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST);
1851 /* Set multicast bit to capture multicast frames. */
1852 if (ifp->if_flags & IFF_MULTICAST)
1853 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST);
1855 /* Init the cam filter. */
1858 /* Init the multicast filter. */
1861 /* Enable flow control */
1863 CSR_WRITE_1(sc, VGE_CRS2, 0x8B);
1865 /* Enable jumbo frame reception (if desired) */
1867 /* Start the MAC. */
1868 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP);
1869 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL);
1870 CSR_WRITE_1(sc, VGE_CRS0,
1871 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START);
1874 * Configure one-shot timer for microsecond
1875 * resulution and load it for 500 usecs.
1877 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES);
1878 CSR_WRITE_2(sc, VGE_SSTIMER, 400);
1881 * Configure interrupt moderation for receive. Enable
1882 * the holdoff counter and load it, and set the RX
1883 * suppression count to the number of descriptors we
1884 * want to allow before triggering an interrupt.
1885 * The holdoff timer is in units of 20 usecs.
1889 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE);
1890 /* Select the interrupt holdoff timer page. */
1891 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
1892 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF);
1893 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */
1895 /* Enable use of the holdoff timer. */
1896 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF);
1897 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD);
1899 /* Select the RX suppression threshold page. */
1900 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
1901 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR);
1902 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */
1904 /* Restore the page select bits. */
1905 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
1906 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
1909 #ifdef IFPOLL_ENABLE
1910 /* Disable intr if polling(4) is enabled */
1911 if (ifp->if_flags & IFF_NPOLLING)
1912 vge_disable_intr(sc);
1915 vge_enable_intr(sc, 0);
1919 ifp->if_flags |= IFF_RUNNING;
1920 ifq_clr_oactive(&ifp->if_snd);
1922 sc->vge_if_flags = 0;
1927 * Set media options.
1930 vge_ifmedia_upd(struct ifnet *ifp)
1932 struct vge_softc *sc = ifp->if_softc;
1933 struct mii_data *mii = device_get_softc(sc->vge_miibus);
1941 * Report current media status.
1944 vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1946 struct vge_softc *sc = ifp->if_softc;
1947 struct mii_data *mii = device_get_softc(sc->vge_miibus);
1950 ifmr->ifm_active = mii->mii_media_active;
1951 ifmr->ifm_status = mii->mii_media_status;
1955 vge_miibus_statchg(device_t dev)
1957 struct vge_softc *sc;
1958 struct mii_data *mii;
1959 struct ifmedia_entry *ife;
1961 sc = device_get_softc(dev);
1962 mii = device_get_softc(sc->vge_miibus);
1963 ife = mii->mii_media.ifm_cur;
1966 * If the user manually selects a media mode, we need to turn
1967 * on the forced MAC mode bit in the DIAGCTL register. If the
1968 * user happens to choose a full duplex mode, we also need to
1969 * set the 'force full duplex' bit. This applies only to
1970 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC
1971 * mode is disabled, and in 1000baseT mode, full duplex is
1972 * always implied, so we turn on the forced mode bit but leave
1973 * the FDX bit cleared.
1976 switch (IFM_SUBTYPE(ife->ifm_media)) {
1978 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
1979 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
1982 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
1983 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
1987 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
1988 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX)
1989 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
1991 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
1994 device_printf(dev, "unknown media type: %x\n",
1995 IFM_SUBTYPE(ife->ifm_media));
2001 vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2003 struct vge_softc *sc = ifp->if_softc;
2004 struct ifreq *ifr = (struct ifreq *)data;
2005 struct mii_data *mii;
2010 if (ifr->ifr_mtu > VGE_JUMBO_MTU)
2012 ifp->if_mtu = ifr->ifr_mtu;
2015 if (ifp->if_flags & IFF_UP) {
2016 if ((ifp->if_flags & IFF_RUNNING) &&
2017 (ifp->if_flags & IFF_PROMISC) &&
2018 !(sc->vge_if_flags & IFF_PROMISC)) {
2019 CSR_SETBIT_1(sc, VGE_RXCTL,
2020 VGE_RXCTL_RX_PROMISC);
2022 } else if ((ifp->if_flags & IFF_RUNNING) &&
2023 !(ifp->if_flags & IFF_PROMISC) &&
2024 (sc->vge_if_flags & IFF_PROMISC)) {
2025 CSR_CLRBIT_1(sc, VGE_RXCTL,
2026 VGE_RXCTL_RX_PROMISC);
2032 if (ifp->if_flags & IFF_RUNNING)
2035 sc->vge_if_flags = ifp->if_flags;
2043 mii = device_get_softc(sc->vge_miibus);
2044 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2048 uint32_t mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2050 if (mask & IFCAP_HWCSUM) {
2051 ifp->if_capenable |= ifr->ifr_reqcap & (IFCAP_HWCSUM);
2052 if (ifp->if_capenable & IFCAP_TXCSUM)
2053 ifp->if_hwassist = VGE_CSUM_FEATURES;
2055 ifp->if_hwassist = 0;
2056 if (ifp->if_flags & IFF_RUNNING)
2062 error = ether_ioctl(ifp, command, data);
2069 vge_watchdog(struct ifnet *ifp)
2071 struct vge_softc *sc = ifp->if_softc;
2073 if_printf(ifp, "watchdog timeout\n");
2074 IFNET_STAT_INC(ifp, oerrors, 1);
2083 * Stop the adapter and free any mbufs allocated to the
2087 vge_stop(struct vge_softc *sc)
2089 struct ifnet *ifp = &sc->arpcom.ac_if;
2092 ASSERT_SERIALIZED(ifp->if_serializer);
2096 ifp->if_flags &= ~IFF_RUNNING;
2097 ifq_clr_oactive(&ifp->if_snd);
2099 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
2100 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP);
2101 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF);
2102 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF);
2103 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF);
2104 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0);
2106 if (sc->vge_head != NULL) {
2107 m_freem(sc->vge_head);
2108 sc->vge_head = sc->vge_tail = NULL;
2111 /* Free the TX list buffers. */
2112 for (i = 0; i < VGE_TX_DESC_CNT; i++) {
2113 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) {
2114 bus_dmamap_unload(sc->vge_ldata.vge_mtag,
2115 sc->vge_ldata.vge_tx_dmamap[i]);
2116 m_freem(sc->vge_ldata.vge_tx_mbuf[i]);
2117 sc->vge_ldata.vge_tx_mbuf[i] = NULL;
2121 /* Free the RX list buffers. */
2122 for (i = 0; i < VGE_RX_DESC_CNT; i++) {
2123 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) {
2124 bus_dmamap_unload(sc->vge_ldata.vge_mtag,
2125 sc->vge_ldata.vge_rx_dmamap[i]);
2126 m_freem(sc->vge_ldata.vge_rx_mbuf[i]);
2127 sc->vge_ldata.vge_rx_mbuf[i] = NULL;
2133 * Device suspend routine. Stop the interface and save some PCI
2134 * settings in case the BIOS doesn't restore them properly on
2138 vge_suspend(device_t dev)
2140 struct vge_softc *sc = device_get_softc(dev);
2141 struct ifnet *ifp = &sc->arpcom.ac_if;
2143 lwkt_serialize_enter(ifp->if_serializer);
2146 lwkt_serialize_exit(ifp->if_serializer);
2152 * Device resume routine. Restore some PCI settings in case the BIOS
2153 * doesn't, re-enable busmastering, and restart the interface if
2157 vge_resume(device_t dev)
2159 struct vge_softc *sc = device_get_softc(dev);
2160 struct ifnet *ifp = &sc->arpcom.ac_if;
2162 /* reenable busmastering */
2163 pci_enable_busmaster(dev);
2164 pci_enable_io(dev, SYS_RES_MEMORY);
2166 lwkt_serialize_enter(ifp->if_serializer);
2167 /* reinitialize interface if necessary */
2168 if (ifp->if_flags & IFF_UP)
2172 lwkt_serialize_exit(ifp->if_serializer);
2178 * Stop all chip I/O so that the kernel's probe routines don't
2179 * get confused by errant DMAs when rebooting.
2182 vge_shutdown(device_t dev)
2184 struct vge_softc *sc = device_get_softc(dev);
2185 struct ifnet *ifp = &sc->arpcom.ac_if;
2187 lwkt_serialize_enter(ifp->if_serializer);
2189 lwkt_serialize_exit(ifp->if_serializer);
2193 vge_enable_intr(struct vge_softc *sc, uint32_t isr)
2195 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS);
2196 CSR_WRITE_4(sc, VGE_ISR, isr);
2197 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
2200 #ifdef IFPOLL_ENABLE
2203 vge_disable_intr(struct vge_softc *sc)
2205 CSR_WRITE_4(sc, VGE_IMR, 0);
2206 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
2207 sc->vge_npoll.ifpc_stcount = 0;
2210 #endif /* IFPOLL_ENABLE */