1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <drm/i915_drm.h>
32 #include "intel_drv.h"
33 #include "intel_ringbuffer.h"
34 #include <linux/workqueue.h>
36 extern struct drm_i915_private *i915_mch_dev;
38 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
40 #define BEGIN_LP_RING(n) \
41 intel_ring_begin(LP_RING(dev_priv), (n))
44 intel_ring_emit(LP_RING(dev_priv), x)
46 #define ADVANCE_LP_RING() \
47 intel_ring_advance(LP_RING(dev_priv))
50 * Lock test for when it's just for synchronization of ring access.
52 * In that case, we don't need to do it when GEM is initialized as nobody else
53 * has access to the ring.
55 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
56 if (LP_RING(dev->dev_private)->obj == NULL) \
57 LOCK_TEST_WITH_RETURN(dev, file); \
61 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
63 if (I915_NEED_GFX_HWS(dev_priv->dev))
64 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
66 return intel_read_status_page(LP_RING(dev_priv), reg);
69 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
70 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
71 #define I915_BREADCRUMB_INDEX 0x21
73 void i915_update_dri1_breadcrumb(struct drm_device *dev)
76 * The dri breadcrumb update races against the drm master disappearing.
77 * Instead of trying to fix this (this is by far not the only ums issue)
78 * just don't do the update in kms mode.
80 if (drm_core_check_feature(dev, DRIVER_MODESET))
83 /* XXX: don't do it at all actually */
87 static void i915_write_hws_pga(struct drm_device *dev)
89 drm_i915_private_t *dev_priv = dev->dev_private;
92 addr = dev_priv->status_page_dmah->busaddr;
93 if (INTEL_INFO(dev)->gen >= 4)
94 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
95 I915_WRITE(HWS_PGA, addr);
99 * Frees the hardware status page, whether it's a physical address or a virtual
100 * address set up by the X Server.
102 static void i915_free_hws(struct drm_device *dev)
104 drm_i915_private_t *dev_priv = dev->dev_private;
105 struct intel_ring_buffer *ring = LP_RING(dev_priv);
107 if (dev_priv->status_page_dmah) {
108 drm_pci_free(dev, dev_priv->status_page_dmah);
109 dev_priv->status_page_dmah = NULL;
112 if (ring->status_page.gfx_addr) {
113 ring->status_page.gfx_addr = 0;
114 #if 0 /* We don't care about dri1 */
115 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
119 /* Need to rewrite hardware status page */
120 I915_WRITE(HWS_PGA, 0x1ffff000);
123 void i915_kernel_lost_context(struct drm_device * dev)
125 drm_i915_private_t *dev_priv = dev->dev_private;
126 struct intel_ring_buffer *ring = LP_RING(dev_priv);
129 * We should never lose context on the ring with modesetting
130 * as we don't expose it to userspace
132 if (drm_core_check_feature(dev, DRIVER_MODESET))
135 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
136 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
137 ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
139 ring->space += ring->size;
144 if (!dev->primary->master)
148 if (ring->head == ring->tail && dev_priv->sarea_priv)
149 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
152 static int i915_dma_cleanup(struct drm_device * dev)
154 drm_i915_private_t *dev_priv = dev->dev_private;
158 /* Make sure interrupts are disabled here because the uninstall ioctl
159 * may not have been called from userspace and after dev_private
160 * is freed, it's too late.
162 if (dev->irq_enabled)
163 drm_irq_uninstall(dev);
165 mutex_lock(&dev->struct_mutex);
166 for (i = 0; i < I915_NUM_RINGS; i++)
167 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
168 mutex_unlock(&dev->struct_mutex);
170 /* Clear the HWS virtual address at teardown */
171 if (I915_NEED_GFX_HWS(dev))
177 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
179 drm_i915_private_t *dev_priv = dev->dev_private;
182 dev_priv->sarea = drm_getsarea(dev);
183 if (!dev_priv->sarea) {
184 DRM_ERROR("can not find sarea!\n");
185 i915_dma_cleanup(dev);
189 dev_priv->sarea_priv = (drm_i915_sarea_t *)
190 ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
192 if (init->ring_size != 0) {
193 if (LP_RING(dev_priv)->obj != NULL) {
194 i915_dma_cleanup(dev);
195 DRM_ERROR("Client tried to initialize ringbuffer in "
200 ret = intel_render_ring_init_dri(dev,
204 i915_dma_cleanup(dev);
209 dev_priv->dri1.cpp = init->cpp;
210 dev_priv->dri1.back_offset = init->back_offset;
211 dev_priv->dri1.front_offset = init->front_offset;
212 dev_priv->dri1.current_page = 0;
213 dev_priv->sarea_priv->pf_current_page = 0;
216 /* Allow hardware batchbuffers unless told otherwise.
218 dev_priv->dri1.allow_batchbuffer = 1;
223 static int i915_dma_resume(struct drm_device * dev)
225 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
226 struct intel_ring_buffer *ring = LP_RING(dev_priv);
228 DRM_DEBUG_DRIVER("%s\n", __func__);
230 if (ring->virtual_start == NULL) {
231 DRM_ERROR("can not ioremap virtual address for"
236 /* Program Hardware Status Page */
237 if (!ring->status_page.page_addr) {
238 DRM_ERROR("Can not find hardware status page\n");
241 DRM_DEBUG_DRIVER("hw status page @ %p\n",
242 ring->status_page.page_addr);
243 if (ring->status_page.gfx_addr != 0)
244 intel_ring_setup_status_page(ring);
246 i915_write_hws_pga(dev);
248 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
253 static int i915_dma_init(struct drm_device *dev, void *data,
254 struct drm_file *file_priv)
256 drm_i915_init_t *init = data;
259 if (drm_core_check_feature(dev, DRIVER_MODESET))
262 switch (init->func) {
264 retcode = i915_initialize(dev, init);
266 case I915_CLEANUP_DMA:
267 retcode = i915_dma_cleanup(dev);
269 case I915_RESUME_DMA:
270 retcode = i915_dma_resume(dev);
280 /* Implement basically the same security restrictions as hardware does
281 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
283 * Most of the calculations below involve calculating the size of a
284 * particular instruction. It's important to get the size right as
285 * that tells us where the next instruction to check is. Any illegal
286 * instruction detected will be given a size of zero, which is a
287 * signal to abort the rest of the buffer.
289 static int validate_cmd(int cmd)
291 switch (((cmd >> 29) & 0x7)) {
293 switch ((cmd >> 23) & 0x3f) {
295 return 1; /* MI_NOOP */
297 return 1; /* MI_FLUSH */
299 return 0; /* disallow everything else */
303 return 0; /* reserved */
305 return (cmd & 0xff) + 2; /* 2d commands */
307 if (((cmd >> 24) & 0x1f) <= 0x18)
310 switch ((cmd >> 24) & 0x1f) {
314 switch ((cmd >> 16) & 0xff) {
316 return (cmd & 0x1f) + 2;
318 return (cmd & 0xf) + 2;
320 return (cmd & 0xffff) + 2;
324 return (cmd & 0xffff) + 1;
328 if ((cmd & (1 << 23)) == 0) /* inline vertices */
329 return (cmd & 0x1ffff) + 2;
330 else if (cmd & (1 << 17)) /* indirect random */
331 if ((cmd & 0xffff) == 0)
332 return 0; /* unknown length, too hard */
334 return (((cmd & 0xffff) + 1) / 2) + 1;
336 return 2; /* indirect sequential */
347 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
349 drm_i915_private_t *dev_priv = dev->dev_private;
352 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
355 for (i = 0; i < dwords;) {
356 int sz = validate_cmd(buffer[i]);
357 if (sz == 0 || i + sz > dwords)
362 ret = BEGIN_LP_RING((dwords+1)&~1);
366 for (i = 0; i < dwords; i++)
377 i915_emit_box(struct drm_device *dev,
378 struct drm_clip_rect *box,
381 struct drm_i915_private *dev_priv = dev->dev_private;
384 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
385 box->y2 <= 0 || box->x2 <= 0) {
386 DRM_ERROR("Bad box %d,%d..%d,%d\n",
387 box->x1, box->y1, box->x2, box->y2);
391 if (INTEL_INFO(dev)->gen >= 4) {
392 ret = BEGIN_LP_RING(4);
396 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
397 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
398 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
401 ret = BEGIN_LP_RING(6);
405 OUT_RING(GFX_OP_DRAWRECT_INFO);
407 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
408 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
417 /* XXX: Emitting the counter should really be moved to part of the IRQ
418 * emit. For now, do it in both places:
421 static void i915_emit_breadcrumb(struct drm_device *dev)
423 drm_i915_private_t *dev_priv = dev->dev_private;
425 dev_priv->dri1.counter++;
426 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
427 dev_priv->dri1.counter = 0;
428 if (dev_priv->sarea_priv)
429 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
431 if (BEGIN_LP_RING(4) == 0) {
432 OUT_RING(MI_STORE_DWORD_INDEX);
433 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
434 OUT_RING(dev_priv->dri1.counter);
440 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
441 drm_i915_cmdbuffer_t *cmd,
442 struct drm_clip_rect *cliprects,
445 int nbox = cmd->num_cliprects;
446 int i = 0, count, ret;
449 DRM_ERROR("alignment");
453 i915_kernel_lost_context(dev);
455 count = nbox ? nbox : 1;
457 for (i = 0; i < count; i++) {
459 ret = i915_emit_box(dev, &cliprects[i],
465 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
470 i915_emit_breadcrumb(dev);
474 static int i915_dispatch_batchbuffer(struct drm_device * dev,
475 drm_i915_batchbuffer_t * batch,
476 struct drm_clip_rect *cliprects)
478 struct drm_i915_private *dev_priv = dev->dev_private;
479 int nbox = batch->num_cliprects;
482 if ((batch->start | batch->used) & 0x7) {
483 DRM_ERROR("alignment");
487 i915_kernel_lost_context(dev);
489 count = nbox ? nbox : 1;
490 for (i = 0; i < count; i++) {
492 ret = i915_emit_box(dev, &cliprects[i],
493 batch->DR1, batch->DR4);
498 if (!IS_I830(dev) && !IS_845G(dev)) {
499 ret = BEGIN_LP_RING(2);
503 if (INTEL_INFO(dev)->gen >= 4) {
504 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
505 OUT_RING(batch->start);
507 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
508 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
511 ret = BEGIN_LP_RING(4);
515 OUT_RING(MI_BATCH_BUFFER);
516 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
517 OUT_RING(batch->start + batch->used - 4);
524 if (IS_G4X(dev) || IS_GEN5(dev)) {
525 if (BEGIN_LP_RING(2) == 0) {
526 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
532 i915_emit_breadcrumb(dev);
536 static int i915_dispatch_flip(struct drm_device * dev)
538 drm_i915_private_t *dev_priv = dev->dev_private;
541 if (!dev_priv->sarea_priv)
544 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
546 dev_priv->dri1.current_page,
547 dev_priv->sarea_priv->pf_current_page);
549 i915_kernel_lost_context(dev);
551 ret = BEGIN_LP_RING(10);
555 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
558 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
560 if (dev_priv->dri1.current_page == 0) {
561 OUT_RING(dev_priv->dri1.back_offset);
562 dev_priv->dri1.current_page = 1;
564 OUT_RING(dev_priv->dri1.front_offset);
565 dev_priv->dri1.current_page = 0;
569 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
574 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
576 if (BEGIN_LP_RING(4) == 0) {
577 OUT_RING(MI_STORE_DWORD_INDEX);
578 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
579 OUT_RING(dev_priv->dri1.counter);
584 dev_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
588 static int i915_quiescent(struct drm_device *dev)
590 i915_kernel_lost_context(dev);
591 return intel_ring_idle(LP_RING(dev->dev_private));
594 static int i915_flush_ioctl(struct drm_device *dev, void *data,
595 struct drm_file *file_priv)
599 if (drm_core_check_feature(dev, DRIVER_MODESET))
602 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
604 mutex_lock(&dev->struct_mutex);
605 ret = i915_quiescent(dev);
606 mutex_unlock(&dev->struct_mutex);
611 static int i915_batchbuffer(struct drm_device *dev, void *data,
612 struct drm_file *file_priv)
614 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
615 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
616 drm_i915_batchbuffer_t *batch = data;
618 struct drm_clip_rect *cliprects = NULL;
620 if (drm_core_check_feature(dev, DRIVER_MODESET))
623 if (!dev_priv->dri1.allow_batchbuffer) {
624 DRM_ERROR("Batchbuffer ioctl disabled\n");
628 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
629 batch->start, batch->used, batch->num_cliprects);
631 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
633 if (batch->num_cliprects < 0)
636 if (batch->num_cliprects) {
637 cliprects = kmalloc(batch->num_cliprects *
638 sizeof(struct drm_clip_rect), M_DRM,
640 if (cliprects == NULL)
643 ret = copy_from_user(cliprects, batch->cliprects,
644 batch->num_cliprects *
645 sizeof(struct drm_clip_rect));
652 mutex_lock(&dev->struct_mutex);
653 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
654 mutex_unlock(&dev->struct_mutex);
657 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
664 static int i915_cmdbuffer(struct drm_device *dev, void *data,
665 struct drm_file *file_priv)
667 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
668 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
669 drm_i915_cmdbuffer_t *cmdbuf = data;
670 struct drm_clip_rect *cliprects = NULL;
674 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
675 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
677 if (drm_core_check_feature(dev, DRIVER_MODESET))
680 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
682 if (cmdbuf->num_cliprects < 0)
685 batch_data = kmalloc(cmdbuf->sz, M_DRM, M_WAITOK);
686 if (batch_data == NULL)
689 ret = -copyin(cmdbuf->buf, batch_data, cmdbuf->sz);
692 goto fail_batch_free;
695 if (cmdbuf->num_cliprects) {
696 cliprects = kmalloc(cmdbuf->num_cliprects *
697 sizeof(struct drm_clip_rect), M_DRM,
699 if (cliprects == NULL) {
701 goto fail_batch_free;
704 ret = copy_from_user(cliprects, cmdbuf->cliprects,
705 cmdbuf->num_cliprects *
706 sizeof(struct drm_clip_rect));
713 mutex_lock(&dev->struct_mutex);
714 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
715 mutex_unlock(&dev->struct_mutex);
717 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
722 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
725 drm_free(cliprects, M_DRM);
727 drm_free(batch_data, M_DRM);
731 static int i915_emit_irq(struct drm_device * dev)
733 drm_i915_private_t *dev_priv = dev->dev_private;
735 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
738 i915_kernel_lost_context(dev);
740 DRM_DEBUG_DRIVER("\n");
742 dev_priv->dri1.counter++;
743 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
744 dev_priv->dri1.counter = 1;
745 if (dev_priv->sarea_priv)
746 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
748 if (BEGIN_LP_RING(4) == 0) {
749 OUT_RING(MI_STORE_DWORD_INDEX);
750 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
751 OUT_RING(dev_priv->dri1.counter);
752 OUT_RING(MI_USER_INTERRUPT);
756 return dev_priv->dri1.counter;
759 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
761 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
763 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
766 struct intel_ring_buffer *ring = LP_RING(dev_priv);
768 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
769 READ_BREADCRUMB(dev_priv));
772 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
773 if (master_priv->sarea_priv)
774 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
778 if (master_priv->sarea_priv)
779 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
781 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
782 if (dev_priv->sarea_priv) {
783 dev_priv->sarea_priv->last_dispatch =
784 READ_BREADCRUMB(dev_priv);
789 if (dev_priv->sarea_priv)
790 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
793 if (ring->irq_get(ring)) {
794 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
795 READ_BREADCRUMB(dev_priv) >= irq_nr);
797 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
801 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
802 READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
808 /* Needs the lock as it touches the ring.
810 static int i915_irq_emit(struct drm_device *dev, void *data,
811 struct drm_file *file_priv)
813 drm_i915_private_t *dev_priv = dev->dev_private;
814 drm_i915_irq_emit_t *emit = data;
817 if (drm_core_check_feature(dev, DRIVER_MODESET))
820 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
821 DRM_ERROR("called with no initialization\n");
825 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
827 mutex_lock(&dev->struct_mutex);
828 result = i915_emit_irq(dev);
829 mutex_unlock(&dev->struct_mutex);
831 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
832 DRM_ERROR("copy_to_user\n");
839 /* Doesn't need the hardware lock.
841 static int i915_irq_wait(struct drm_device *dev, void *data,
842 struct drm_file *file_priv)
844 drm_i915_private_t *dev_priv = dev->dev_private;
845 drm_i915_irq_wait_t *irqwait = data;
847 if (drm_core_check_feature(dev, DRIVER_MODESET))
851 DRM_ERROR("called with no initialization\n");
855 return i915_wait_irq(dev, irqwait->irq_seq);
858 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
859 struct drm_file *file_priv)
861 drm_i915_private_t *dev_priv = dev->dev_private;
862 drm_i915_vblank_pipe_t *pipe = data;
864 if (drm_core_check_feature(dev, DRIVER_MODESET))
868 DRM_ERROR("called with no initialization\n");
872 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
878 * Schedule buffer swap at given vertical blank.
880 static int i915_vblank_swap(struct drm_device *dev, void *data,
881 struct drm_file *file_priv)
883 /* The delayed swap mechanism was fundamentally racy, and has been
884 * removed. The model was that the client requested a delayed flip/swap
885 * from the kernel, then waited for vblank before continuing to perform
886 * rendering. The problem was that the kernel might wake the client
887 * up before it dispatched the vblank swap (since the lock has to be
888 * held while touching the ringbuffer), in which case the client would
889 * clear and start the next frame before the swap occurred, and
890 * flicker would occur in addition to likely missing the vblank.
892 * In the absence of this ioctl, userland falls back to a correct path
893 * of waiting for a vblank, then dispatching the swap on its own.
894 * Context switching to userland and back is plenty fast enough for
895 * meeting the requirements of vblank swapping.
900 static int i915_flip_bufs(struct drm_device *dev, void *data,
901 struct drm_file *file_priv)
905 if (drm_core_check_feature(dev, DRIVER_MODESET))
908 DRM_DEBUG_DRIVER("%s\n", __func__);
910 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
912 mutex_lock(&dev->struct_mutex);
913 ret = i915_dispatch_flip(dev);
914 mutex_unlock(&dev->struct_mutex);
919 static int i915_getparam(struct drm_device *dev, void *data,
920 struct drm_file *file_priv)
922 drm_i915_private_t *dev_priv = dev->dev_private;
923 drm_i915_getparam_t *param = data;
927 DRM_ERROR("called with no initialization\n");
931 switch (param->param) {
932 case I915_PARAM_IRQ_ACTIVE:
933 value = dev->irq_enabled ? 1 : 0;
935 case I915_PARAM_ALLOW_BATCHBUFFER:
936 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
938 case I915_PARAM_LAST_DISPATCH:
939 value = READ_BREADCRUMB(dev_priv);
941 case I915_PARAM_CHIPSET_ID:
942 value = dev->pci_device;
944 case I915_PARAM_HAS_GEM:
947 case I915_PARAM_NUM_FENCES_AVAIL:
948 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
950 case I915_PARAM_HAS_OVERLAY:
951 value = dev_priv->overlay ? 1 : 0;
953 case I915_PARAM_HAS_PAGEFLIPPING:
956 case I915_PARAM_HAS_EXECBUF2:
960 case I915_PARAM_HAS_BSD:
961 value = intel_ring_initialized(&dev_priv->ring[VCS]);
963 case I915_PARAM_HAS_BLT:
964 value = intel_ring_initialized(&dev_priv->ring[BCS]);
966 case I915_PARAM_HAS_RELAXED_FENCING:
969 case I915_PARAM_HAS_COHERENT_RINGS:
972 case I915_PARAM_HAS_EXEC_CONSTANTS:
973 value = INTEL_INFO(dev)->gen >= 4;
975 case I915_PARAM_HAS_RELAXED_DELTA:
978 case I915_PARAM_HAS_GEN7_SOL_RESET:
981 case I915_PARAM_HAS_LLC:
982 value = HAS_LLC(dev);
984 case I915_PARAM_HAS_ALIASING_PPGTT:
985 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
987 case I915_PARAM_HAS_WAIT_TIMEOUT:
990 case I915_PARAM_HAS_SEMAPHORES:
991 value = i915_semaphore_is_enabled(dev);
993 case I915_PARAM_HAS_PINNED_BATCHES:
996 case I915_PARAM_HAS_EXEC_NO_RELOC:
999 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
1003 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
1008 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1009 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1016 static int i915_setparam(struct drm_device *dev, void *data,
1017 struct drm_file *file_priv)
1019 drm_i915_private_t *dev_priv = dev->dev_private;
1020 drm_i915_setparam_t *param = data;
1023 DRM_ERROR("called with no initialization\n");
1027 switch (param->param) {
1028 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1030 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1032 case I915_SETPARAM_ALLOW_BATCHBUFFER:
1033 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1035 case I915_SETPARAM_NUM_USED_FENCES:
1036 if (param->value > dev_priv->num_fence_regs ||
1039 /* Userspace can use first N regs */
1040 dev_priv->fence_reg_start = param->value;
1043 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1051 static int i915_set_status_page(struct drm_device *dev, void *data,
1052 struct drm_file *file_priv)
1054 #if 0 /* We don't care about dri1 */
1055 drm_i915_private_t *dev_priv = dev->dev_private;
1056 drm_i915_hws_addr_t *hws = data;
1057 struct intel_ring_buffer *ring;
1059 if (drm_core_check_feature(dev, DRIVER_MODESET))
1062 if (!I915_NEED_GFX_HWS(dev))
1066 DRM_ERROR("called with no initialization\n");
1070 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1071 WARN(1, "tried to set status page when mode setting active\n");
1075 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1077 ring = LP_RING(dev_priv);
1078 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1080 dev_priv->dri1.gfx_hws_cpu_addr =
1081 ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096);
1082 if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1083 i915_dma_cleanup(dev);
1084 ring->status_page.gfx_addr = 0;
1085 DRM_ERROR("can not ioremap virtual address for"
1086 " G33 hw status page\n");
1090 memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1091 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1093 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1094 ring->status_page.gfx_addr);
1095 DRM_DEBUG_DRIVER("load hws at %p\n",
1096 ring->status_page.page_addr);
1102 static int i915_get_bridge_dev(struct drm_device *dev)
1104 struct drm_i915_private *dev_priv = dev->dev_private;
1105 static struct pci_dev i915_bridge_dev;
1107 i915_bridge_dev.dev = pci_find_dbsf(0, 0, 0, 0);
1108 if (!i915_bridge_dev.dev) {
1109 DRM_ERROR("bridge device not found\n");
1113 dev_priv->bridge_dev = &i915_bridge_dev;
1117 #define MCHBAR_I915 0x44
1118 #define MCHBAR_I965 0x48
1119 #define MCHBAR_SIZE (4*4096)
1121 #define DEVEN_REG 0x54
1122 #define DEVEN_MCHBAR_EN (1 << 28)
1124 /* Allocate space for the MCH regs if needed, return nonzero on error */
1126 intel_alloc_mchbar_resource(struct drm_device *dev)
1128 drm_i915_private_t *dev_priv = dev->dev_private;
1129 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1131 u32 temp_lo, temp_hi = 0;
1134 if (INTEL_INFO(dev)->gen >= 4)
1135 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1136 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1137 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1139 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1142 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1146 /* Get some space for it */
1147 vga = device_get_parent(dev->dev);
1148 dev_priv->mch_res_rid = 0x100;
1149 dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1150 dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1151 MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
1152 if (dev_priv->mch_res == NULL) {
1153 DRM_ERROR("failed mchbar resource alloc\n");
1157 if (INTEL_INFO(dev)->gen >= 4)
1158 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1159 upper_32_bits(rman_get_start(dev_priv->mch_res)));
1161 pci_write_config_dword(dev_priv->bridge_dev, reg,
1162 lower_32_bits(rman_get_start(dev_priv->mch_res)));
1166 /* Setup MCHBAR if possible, return true if we should disable it again */
1168 intel_setup_mchbar(struct drm_device *dev)
1170 drm_i915_private_t *dev_priv = dev->dev_private;
1171 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1175 dev_priv->mchbar_need_disable = false;
1177 if (IS_I915G(dev) || IS_I915GM(dev)) {
1178 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1179 enabled = (temp & DEVEN_MCHBAR_EN) != 0;
1181 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1185 /* If it's already enabled, don't have to do anything */
1189 if (intel_alloc_mchbar_resource(dev))
1192 dev_priv->mchbar_need_disable = true;
1194 /* Space is allocated or reserved, so enable it. */
1195 if (IS_I915G(dev) || IS_I915GM(dev)) {
1196 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1197 temp | DEVEN_MCHBAR_EN);
1199 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1200 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1205 intel_teardown_mchbar(struct drm_device *dev)
1207 drm_i915_private_t *dev_priv = dev->dev_private;
1208 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1212 if (dev_priv->mchbar_need_disable) {
1213 if (IS_I915G(dev) || IS_I915GM(dev)) {
1214 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1215 temp &= ~DEVEN_MCHBAR_EN;
1216 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1218 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1220 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1224 if (dev_priv->mch_res != NULL) {
1225 vga = device_get_parent(dev->dev);
1226 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
1227 SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1228 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
1229 SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1230 dev_priv->mch_res = NULL;
1234 static int i915_load_modeset_init(struct drm_device *dev)
1236 struct drm_i915_private *dev_priv = dev->dev_private;
1239 ret = intel_parse_bios(dev);
1241 DRM_INFO("failed to find VBIOS tables\n");
1244 /* If we have > 1 VGA cards, then we need to arbitrate access
1245 * to the common VGA resources.
1247 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1248 * then we do not take part in VGA arbitration and the
1249 * vga_client_register() fails with -ENODEV.
1251 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1252 if (ret && ret != -ENODEV)
1255 intel_register_dsm_handler();
1257 ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops);
1259 goto cleanup_vga_client;
1261 /* Initialise stolen first so that we may reserve preallocated
1262 * objects for the BIOS to KMS transition.
1264 ret = i915_gem_init_stolen(dev);
1266 goto cleanup_vga_switcheroo;
1269 ret = drm_irq_install(dev);
1271 goto cleanup_gem_stolen;
1273 /* Important: The output setup functions called by modeset_init need
1274 * working irqs for e.g. gmbus and dp aux transfers. */
1275 intel_modeset_init(dev);
1277 ret = i915_gem_init(dev);
1282 INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
1285 intel_modeset_gem_init(dev);
1287 /* Always safe in the mode setting case. */
1288 /* FIXME: do pre/post-mode set stuff in core KMS code */
1289 dev->vblank_disable_allowed = 1;
1291 ret = intel_fbdev_init(dev);
1295 /* Only enable hotplug handling once the fbdev is fully set up. */
1296 intel_hpd_init(dev);
1299 * Some ports require correctly set-up hpd registers for detection to
1300 * work properly (leading to ghost connected connector status), e.g. VGA
1301 * on gm45. Hence we can only set up the initial fbdev config after hpd
1302 * irqs are fully enabled. Now we should scan for the initial config
1303 * only once hotplug handling is enabled, but due to screwed-up locking
1304 * around kms/fbdev init we can't protect the fdbev initial config
1305 * scanning against hotplug events. Hence do this first and ignore the
1306 * tiny window where we will loose hotplug notifactions.
1308 intel_fbdev_initial_config(dev);
1310 /* Only enable hotplug handling once the fbdev is fully set up. */
1311 dev_priv->enable_hotplug_processing = true;
1313 drm_kms_helper_poll_init(dev);
1315 /* We're off and running w/KMS */
1316 dev_priv->mm.suspended = 0;
1321 mutex_lock(&dev->struct_mutex);
1322 i915_gem_cleanup_ringbuffer(dev);
1323 mutex_unlock(&dev->struct_mutex);
1324 i915_gem_cleanup_aliasing_ppgtt(dev);
1326 drm_irq_uninstall(dev);
1329 i915_gem_cleanup_stolen(dev);
1330 cleanup_vga_switcheroo:
1331 vga_switcheroo_unregister_client(dev->pdev);
1333 vga_client_register(dev->pdev, NULL, NULL, NULL);
1340 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1342 struct apertures_struct *ap;
1343 struct pci_dev *pdev = dev_priv->dev->pdev;
1346 ap = alloc_apertures(1);
1350 ap->ranges[0].base = dev_priv->gtt.mappable_base;
1351 ap->ranges[0].size = dev_priv->gtt.mappable_end - dev_priv->gtt.start;
1354 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1356 remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1363 * i915_driver_load - setup chip and create an initial config
1365 * @flags: startup flags
1367 * The driver load routine has to do several things:
1368 * - drive output discovery via intel_modeset_init()
1369 * - initialize the memory manager
1370 * - allocate initial config memory
1371 * - setup the DRM framebuffer with the allocated memory
1373 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376 unsigned long base, size;
1377 int ret = 0, mmio_bar;
1378 static struct pci_dev i915_pdev;
1380 /* XXX: struct pci_dev */
1381 i915_pdev.dev = dev->dev;
1382 dev->pdev = &i915_pdev;
1384 /* i915 has 4 more counters */
1386 dev->types[6] = _DRM_STAT_IRQ;
1387 dev->types[7] = _DRM_STAT_PRIMARY;
1388 dev->types[8] = _DRM_STAT_SECONDARY;
1389 dev->types[9] = _DRM_STAT_DMA;
1391 dev_priv = kmalloc(sizeof(drm_i915_private_t), M_DRM,
1393 if (dev_priv == NULL)
1396 dev->dev_private = (void *)dev_priv;
1397 dev_priv->dev = dev;
1398 dev_priv->info = i915_get_device_id(dev->pci_device);
1400 if (i915_get_bridge_dev(dev)) {
1405 ret = i915_gem_gtt_init(dev);
1410 if (drm_core_check_feature(dev, DRIVER_MODESET))
1411 i915_kick_out_firmware_fb(dev_priv);
1413 pci_set_master(dev->pdev);
1415 /* overlay on gen2 is broken and can't address above 1G */
1417 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1419 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1420 * using 32bit addressing, overwriting memory if HWS is located
1423 * The documentation also mentions an issue with undefined
1424 * behaviour if any general state is accessed within a page above 4GB,
1425 * which also needs to be handled carefully.
1427 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1428 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1431 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1432 /* Before gen4, the registers and the GTT are behind different BARs.
1433 * However, from gen4 onwards, the registers and the GTT are shared
1434 * in the same BAR, so we want to restrict this ioremap from
1435 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1436 * the register BAR remains the same size for all the earlier
1437 * generations up to Ironlake.
1441 mmio_size = 512*1024;
1443 mmio_size = 2*1024*1024;
1445 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1446 if (!dev_priv->regs) {
1447 DRM_ERROR("failed to map registers\n");
1452 aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1454 dev_priv->gtt.mappable =
1455 io_mapping_create_wc(dev_priv->gtt.mappable_base,
1457 if (dev_priv->gtt.mappable == NULL) {
1462 i915_mtrr_setup(dev_priv, dev_priv->gtt.mappable_base,
1466 base = drm_get_resource_start(dev, mmio_bar);
1467 size = drm_get_resource_len(dev, mmio_bar);
1469 ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1470 _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1472 /* The i915 workqueue is primarily used for batched retirement of
1473 * requests (and thus managing bo) once the task has been completed
1474 * by the GPU. i915_gem_retire_requests() is called directly when we
1475 * need high-priority retirement, such as waiting for an explicit
1478 * It is also used for periodic low-priority events, such as
1479 * idle-timers and recording error state.
1481 * All tasks on the workqueue are expected to acquire the dev mutex
1482 * so there is no point in running more than one instance of the
1483 * workqueue at any time. Use an ordered one.
1485 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1486 if (dev_priv->wq == NULL) {
1487 DRM_ERROR("Failed to create our workqueue.\n");
1492 /* This must be called before any calls to HAS_PCH_* */
1493 intel_detect_pch(dev);
1495 intel_irq_init(dev);
1498 /* Try to make sure MCHBAR is enabled before poking at it */
1499 intel_setup_mchbar(dev);
1500 intel_setup_gmbus(dev);
1501 intel_opregion_setup(dev);
1503 intel_setup_bios(dev);
1507 /* On the 945G/GM, the chipset reports the MSI capability on the
1508 * integrated graphics even though the support isn't actually there
1509 * according to the published specs. It doesn't appear to function
1510 * correctly in testing on 945G.
1511 * This may be a side effect of MSI having been made available for PEG
1512 * and the registers being closely associated.
1514 * According to chipset errata, on the 965GM, MSI interrupts may
1515 * be lost or delayed, but we use them anyways to avoid
1516 * stuck interrupts on some machines.
1519 if (!IS_I945G(dev) && !IS_I945GM(dev))
1520 pci_enable_msi(dev->pdev);
1523 lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
1524 lockinit(&dev_priv->gpu_error.lock, "915err", 0, LK_CANRECURSE);
1525 spin_init(&dev_priv->rps.lock, "i915initrps");
1526 lockinit(&dev_priv->dpio_lock, "i915dpio", 0, LK_CANRECURSE);
1528 lockinit(&dev_priv->rps.hw_lock, "i915 rps.hw_lock", 0, LK_CANRECURSE);
1529 lockinit(&dev_priv->modeset_restore_lock, "i915mrl", 0, LK_CANRECURSE);
1531 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1532 dev_priv->num_pipe = 3;
1533 else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1534 dev_priv->num_pipe = 2;
1536 dev_priv->num_pipe = 1;
1538 ret = drm_vblank_init(dev, dev_priv->num_pipe);
1540 goto out_gem_unload;
1542 /* Start out suspended */
1543 dev_priv->mm.suspended = 1;
1545 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1546 ret = i915_load_modeset_init(dev);
1548 DRM_ERROR("failed to init modeset\n");
1549 goto out_gem_unload;
1554 i915_setup_sysfs(dev);
1557 /* Must be done after probing outputs */
1558 intel_opregion_init(dev);
1560 acpi_video_register();
1564 intel_gpu_ips_init(dev_priv);
1570 intel_teardown_gmbus(dev);
1571 intel_teardown_mchbar(dev);
1572 destroy_workqueue(dev_priv->wq);
1580 int i915_driver_unload(struct drm_device *dev)
1582 struct drm_i915_private *dev_priv = dev->dev_private;
1585 intel_gpu_ips_teardown();
1588 i915_teardown_sysfs(dev);
1590 if (dev_priv->mm.inactive_shrinker.shrink)
1591 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1594 mutex_lock(&dev->struct_mutex);
1595 ret = i915_gpu_idle(dev);
1597 DRM_ERROR("failed to idle hardware: %d\n", ret);
1598 i915_gem_retire_requests(dev);
1599 mutex_unlock(&dev->struct_mutex);
1601 /* Cancel the retire work handler, which should be idle now. */
1602 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
1605 io_mapping_free(dev_priv->gtt.mappable);
1606 if (dev_priv->mm.gtt_mtrr >= 0) {
1607 mtrr_del(dev_priv->mm.gtt_mtrr,
1608 dev_priv->gtt.mappable_base,
1609 dev_priv->mm.gtt->gtt_mappable_entries * PAGE_SIZE);
1610 dev_priv->mm.gtt_mtrr = -1;
1613 acpi_video_unregister();
1616 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1617 intel_fbdev_fini(dev);
1618 intel_modeset_cleanup(dev);
1620 cancel_work_sync(&dev_priv->console_resume_work);
1624 * free the memory space allocated for the child device
1625 * config parsed from VBT
1627 if (dev_priv->child_dev && dev_priv->child_dev_num) {
1628 kfree(dev_priv->child_dev);
1629 dev_priv->child_dev = NULL;
1630 dev_priv->child_dev_num = 0;
1635 /* Free error state after interrupts are fully disabled. */
1636 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1637 cancel_work_sync(&dev_priv->gpu_error.work);
1638 i915_destroy_error_state(dev);
1640 intel_opregion_fini(dev);
1642 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1643 /* Flush any outstanding unpin_work. */
1644 flush_workqueue(dev_priv->wq);
1646 mutex_lock(&dev->struct_mutex);
1647 i915_gem_free_all_phys_object(dev);
1648 i915_gem_cleanup_ringbuffer(dev);
1649 i915_gem_context_fini(dev);
1650 mutex_unlock(&dev->struct_mutex);
1651 i915_gem_cleanup_aliasing_ppgtt(dev);
1653 i915_gem_cleanup_stolen(dev);
1656 if (!I915_NEED_GFX_HWS(dev))
1661 if (dev_priv->regs != NULL)
1662 pci_iounmap(dev->pdev, dev_priv->regs);
1665 intel_teardown_gmbus(dev);
1666 intel_teardown_mchbar(dev);
1668 bus_generic_detach(dev->dev);
1669 drm_rmmap(dev, dev_priv->mmio_map);
1670 intel_teardown_gmbus(dev);
1672 destroy_workqueue(dev_priv->wq);
1673 pm_qos_remove_request(&dev_priv->pm_qos);
1675 pci_dev_put(dev_priv->bridge_dev);
1676 drm_free(dev->dev_private, M_DRM);
1681 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1683 struct drm_i915_file_private *file_priv;
1685 DRM_DEBUG_DRIVER("\n");
1686 file_priv = kmalloc(sizeof(*file_priv), M_DRM, M_WAITOK | M_ZERO);
1690 file->driver_priv = file_priv;
1692 spin_init(&file_priv->mm.lock, "i915_priv");
1693 INIT_LIST_HEAD(&file_priv->mm.request_list);
1695 idr_init(&file_priv->context_idr);
1701 * i915_driver_lastclose - clean up after all DRM clients have exited
1704 * Take care of cleaning up after all DRM clients have exited. In the
1705 * mode setting case, we want to restore the kernel's initial mode (just
1706 * in case the last client left us in a bad state).
1708 * Additionally, in the non-mode setting case, we'll tear down the GTT
1709 * and DMA structures, since the kernel won't be using them, and clea
1712 void i915_driver_lastclose(struct drm_device * dev)
1714 drm_i915_private_t *dev_priv = dev->dev_private;
1716 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1720 drm_fb_helper_restore();
1721 vga_switcheroo_process_delayed_switch();
1725 i915_gem_lastclose(dev);
1726 i915_dma_cleanup(dev);
1729 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1731 i915_gem_context_close(dev, file_priv);
1732 i915_gem_release(dev, file_priv);
1735 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1737 struct drm_i915_file_private *file_priv = file->driver_priv;
1742 struct drm_ioctl_desc i915_ioctls[] = {
1743 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1744 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1745 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1746 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1747 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1748 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1749 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
1750 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1751 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1752 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1753 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1754 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1755 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1756 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1757 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
1758 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1759 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1760 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1761 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1762 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
1763 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1764 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1765 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1766 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED),
1767 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED),
1768 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1769 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1770 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1771 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
1772 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1773 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1774 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
1775 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1776 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1777 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1778 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
1779 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
1780 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1781 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1782 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1783 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1784 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1785 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1786 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1787 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED),
1788 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED),
1789 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED),
1790 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED),
1793 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1796 * This is really ugly: Because old userspace abused the linux agp interface to
1797 * manage the gtt, we need to claim that all intel devices are agp. For
1798 * otherwise the drm core refuses to initialize the agp support code.
1800 int i915_driver_device_is_agp(struct drm_device * dev)