2 * Copyright (c) 2000 Doug Rabson
3 * Copyright (c) 2000 Ruslan Ermilov
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/agp/agp_i810.c,v 1.43 2007/11/12 21:51:36 jhb Exp $
31 * Fixes for 830/845G support: David Dawes <dawes@xfree86.org>
32 * 852GM/855GM/865G support added by David Dawes <dawes@xfree86.org>
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/malloc.h>
38 #include <sys/kernel.h>
43 #include <bus/pci/pcivar.h>
44 #include <bus/pci/pcireg.h>
49 #include <vm/vm_object.h>
50 #include <vm/vm_page.h>
51 #include <vm/vm_pageout.h>
54 #include <machine/md_var.h>
56 #define bus_read_1(r, o) \
57 bus_space_read_1((r)->r_bustag, (r)->r_bushandle, (o))
58 #define bus_read_4(r, o) \
59 bus_space_read_4((r)->r_bustag, (r)->r_bushandle, (o))
60 #define bus_write_4(r, o, v) \
61 bus_space_write_4((r)->r_bustag, (r)->r_bushandle, (o), (v))
63 MALLOC_DECLARE(M_AGP);
66 CHIP_I810, /* i810/i815 */
67 CHIP_I830, /* 830M/845G */
68 CHIP_I855, /* 852GM/855GM/865G */
69 CHIP_I915, /* 915G/915GM */
71 CHIP_G33, /* G33/Q33/Q35 */
72 CHIP_IGD, /* G33 like IGD */
73 CHIP_G4X, /* G45/Q45 */
76 /* The i810 through i855 have the registers at BAR 1, and the GATT gets
77 * allocated by us. The i915 has registers in BAR 0 and the GATT is at the
78 * start of the stolen memory, and should only be accessed by the OS through
79 * BAR 3. The G965 has registers and GATT in the same BAR (0) -- first 512KB
80 * is registers, second 512KB is GATT.
82 static struct resource_spec agp_i810_res_spec[] = {
83 { SYS_RES_MEMORY, AGP_I810_MMADR, RF_ACTIVE | RF_SHAREABLE },
87 static struct resource_spec agp_i915_res_spec[] = {
88 { SYS_RES_MEMORY, AGP_I915_MMADR, RF_ACTIVE | RF_SHAREABLE },
89 { SYS_RES_MEMORY, AGP_I915_GTTADR, RF_ACTIVE | RF_SHAREABLE },
93 static struct resource_spec agp_i965_res_spec[] = {
94 { SYS_RES_MEMORY, AGP_I965_GTTMMADR, RF_ACTIVE | RF_SHAREABLE },
98 struct agp_i810_softc {
100 u_int32_t initial_aperture; /* aperture size at startup */
101 struct agp_gatt *gatt;
102 int chiptype; /* i810-like or i830 */
103 u_int32_t dcache_size; /* i810 only */
104 u_int32_t stolen; /* number of i830/845 gtt entries for stolen memory */
105 device_t bdev; /* bridge device */
107 void *argb_cursor; /* contigmalloc area for ARGB cursor */
109 struct resource_spec * sc_res_spec;
110 struct resource *sc_res[2];
113 /* For adding new devices, devid is the id of the graphics controller
114 * (pci:0:2:0, for example). The placeholder (usually at pci:0:2:1) for the
115 * second head should never be added. The bridge_offset is the offset to
116 * subtract from devid to get the id of the hostb that the device is on.
118 static const struct agp_i810_match {
123 } agp_i810_matches[] = {
124 {0x71218086, CHIP_I810, 0x00010000,
125 "Intel 82810 (i810 GMCH) SVGA controller"},
126 {0x71238086, CHIP_I810, 0x00010000,
127 "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller"},
128 {0x71258086, CHIP_I810, 0x00010000,
129 "Intel 82810E (i810E GMCH) SVGA controller"},
130 {0x11328086, CHIP_I810, 0x00020000,
131 "Intel 82815 (i815 GMCH) SVGA controller"},
132 {0x35778086, CHIP_I830, 0x00020000,
133 "Intel 82830M (830M GMCH) SVGA controller"},
134 {0x25628086, CHIP_I830, 0x00020000,
135 "Intel 82845M (845M GMCH) SVGA controller"},
136 {0x35828086, CHIP_I855, 0x00020000,
137 "Intel 82852/855GM SVGA controller"},
138 {0x25728086, CHIP_I855, 0x00020000,
139 "Intel 82865G (865G GMCH) SVGA controller"},
140 {0x25828086, CHIP_I915, 0x00020000,
141 "Intel 82915G (915G GMCH) SVGA controller"},
142 {0x258A8086, CHIP_I915, 0x00020000,
143 "Intel E7221 SVGA controller"},
144 {0x25928086, CHIP_I915, 0x00020000,
145 "Intel 82915GM (915GM GMCH) SVGA controller"},
146 {0x27728086, CHIP_I915, 0x00020000,
147 "Intel 82945G (945G GMCH) SVGA controller"},
148 {0x27A28086, CHIP_I915, 0x00020000,
149 "Intel 82945GM (945GM GMCH) SVGA controller"},
150 {0x27AE8086, CHIP_I915, 0x00020000,
151 "Intel 945GME SVGA controller"},
152 {0x29728086, CHIP_I965, 0x00020000,
153 "Intel 946GZ SVGA controller"},
154 {0x29828086, CHIP_I965, 0x00020000,
155 "Intel G965 SVGA controller"},
156 {0x29928086, CHIP_I965, 0x00020000,
157 "Intel Q965 SVGA controller"},
158 {0x29A28086, CHIP_I965, 0x00020000,
159 "Intel G965 SVGA controller"},
160 {0x29B28086, CHIP_G33, 0x00020000,
161 "Intel Q35 SVGA controller"},
162 {0x29C28086, CHIP_G33, 0x00020000,
163 "Intel G33 SVGA controller"},
164 {0x29D28086, CHIP_G33, 0x00020000,
165 "Intel Q33 SVGA controller"},
166 {0x2A028086, CHIP_I965, 0x00020000,
167 "Intel GM965 SVGA controller"},
168 {0x2A128086, CHIP_I965, 0x00020000,
169 "Intel GME965 SVGA controller"},
170 {0x2A428086, CHIP_G4X, 0x00020000,
171 "Intel GM45 SVGA controller"},
172 {0x2E028086, CHIP_G4X, 0x00020000,
173 "Intel 4 Series SVGA controller"},
174 {0x2E128086, CHIP_G4X, 0x00020000,
175 "Intel Q45 SVGA controller"},
176 {0x2E228086, CHIP_G4X, 0x00020000,
177 "Intel G45 SVGA controller"},
178 {0x2E328086, CHIP_G4X, 0x00020000,
179 "Intel G41 SVGA controller"},
180 {0xA0018086, CHIP_IGD, 0x00010000,
181 "Intel IGD SVGA controller"},
182 {0xA0118086, CHIP_IGD, 0x00010000,
183 "Intel IGD SVGA controller"},
187 static const struct agp_i810_match*
188 agp_i810_match(device_t dev)
192 if (pci_get_class(dev) != PCIC_DISPLAY
193 || pci_get_subclass(dev) != PCIS_DISPLAY_VGA)
196 devid = pci_get_devid(dev);
197 for (i = 0; agp_i810_matches[i].devid != 0; i++) {
198 if (agp_i810_matches[i].devid == devid)
201 if (agp_i810_matches[i].devid == 0)
204 return &agp_i810_matches[i];
208 * Find bridge device.
211 agp_i810_find_bridge(device_t dev)
213 device_t *children, child;
216 const struct agp_i810_match *match;
218 match = agp_i810_match(dev);
219 devid = match->devid - match->bridge_offset;
221 if (device_get_children(device_get_parent(device_get_parent(dev)),
222 &children, &nchildren))
225 for (i = 0; i < nchildren; i++) {
228 if (pci_get_devid(child) == devid) {
229 kfree(children, M_TEMP);
233 kfree(children, M_TEMP);
238 agp_i810_identify(driver_t *driver, device_t parent)
241 if (device_find_child(parent, "agp", -1) == NULL &&
242 agp_i810_match(parent))
243 device_add_child(parent, "agp", -1);
247 agp_i810_probe(device_t dev)
250 const struct agp_i810_match *match;
254 if (resource_disabled("agp", device_get_unit(dev)))
256 match = agp_i810_match(dev);
260 bdev = agp_i810_find_bridge(dev);
263 kprintf("I810: can't find bridge device\n");
268 * checking whether internal graphics device has been activated.
270 switch (match->chiptype) {
272 smram = pci_read_config(bdev, AGP_I810_SMRAM, 1);
273 if ((smram & AGP_I810_SMRAM_GMS) ==
274 AGP_I810_SMRAM_GMS_DISABLED) {
276 kprintf("I810: disabled, not probing\n");
282 gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1);
283 if ((gcc1 & AGP_I830_GCC1_DEV2) ==
284 AGP_I830_GCC1_DEV2_DISABLED) {
286 kprintf("I830: disabled, not probing\n");
295 deven = pci_read_config(bdev, AGP_I915_DEVEN, 4);
296 if ((deven & AGP_I915_DEVEN_D2F0) ==
297 AGP_I915_DEVEN_D2F0_DISABLED) {
299 kprintf("I915: disabled, not probing\n");
306 if (match->devid == 0x35828086) {
307 switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) {
310 "Intel 82855GME (855GME GMCH) SVGA controller");
314 "Intel 82855GM (855GM GMCH) SVGA controller");
318 "Intel 82852GME (852GME GMCH) SVGA controller");
322 "Intel 82852GM (852GM GMCH) SVGA controller");
326 "Intel 8285xM (85xGM GMCH) SVGA controller");
330 device_set_desc(dev, match->name);
333 return BUS_PROBE_DEFAULT;
337 agp_i810_dump_regs(device_t dev)
339 struct agp_i810_softc *sc = device_get_softc(dev);
341 device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
342 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
344 switch (sc->chiptype) {
346 device_printf(dev, "AGP_I810_MISCC: 0x%04x\n",
347 pci_read_config(sc->bdev, AGP_I810_MISCC, 2));
350 device_printf(dev, "AGP_I830_GCC1: 0x%02x\n",
351 pci_read_config(sc->bdev, AGP_I830_GCC1, 1));
354 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
355 pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
362 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
363 pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
364 device_printf(dev, "AGP_I915_MSAC: 0x%02x\n",
365 pci_read_config(sc->bdev, AGP_I915_MSAC, 1));
368 device_printf(dev, "Aperture resource size: %d bytes\n",
369 AGP_GET_APERTURE(dev));
373 agp_i810_attach(device_t dev)
375 struct agp_i810_softc *sc = device_get_softc(dev);
376 struct agp_gatt *gatt;
377 const struct agp_i810_match *match;
380 sc->bdev = agp_i810_find_bridge(dev);
384 match = agp_i810_match(dev);
385 sc->chiptype = match->chiptype;
387 switch (sc->chiptype) {
391 sc->sc_res_spec = agp_i810_res_spec;
392 agp_set_aperture_resource(dev, AGP_APBASE);
397 sc->sc_res_spec = agp_i915_res_spec;
398 agp_set_aperture_resource(dev, AGP_I915_GMADR);
402 sc->sc_res_spec = agp_i965_res_spec;
403 agp_set_aperture_resource(dev, AGP_I915_GMADR);
407 error = agp_generic_attach(dev);
411 if (sc->chiptype != CHIP_I965 && sc->chiptype != CHIP_G33 &&
412 sc->chiptype != CHIP_IGD && sc->chiptype != CHIP_G4X &&
413 ptoa((vm_paddr_t)Maxmem) > 0xfffffffful)
415 device_printf(dev, "agp_i810.c does not support physical "
416 "memory above 4GB.\n");
420 if (bus_alloc_resources(dev, sc->sc_res_spec, sc->sc_res)) {
421 agp_generic_detach(dev);
425 sc->initial_aperture = AGP_GET_APERTURE(dev);
426 if (sc->initial_aperture == 0) {
427 device_printf(dev, "bad initial aperture size, disabling\n");
431 gatt = kmalloc( sizeof(struct agp_gatt), M_AGP, M_INTWAIT);
434 gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT;
436 if ( sc->chiptype == CHIP_I810 ) {
437 /* Some i810s have on-chip memory called dcache */
438 if (bus_read_1(sc->sc_res[0], AGP_I810_DRT) &
439 AGP_I810_DRT_POPULATED)
440 sc->dcache_size = 4 * 1024 * 1024;
444 /* According to the specs the gatt on the i810 must be 64k */
445 gatt->ag_virtual = contigmalloc( 64 * 1024, M_AGP, 0,
446 0, ~0, PAGE_SIZE, 0);
447 if (!gatt->ag_virtual) {
449 device_printf(dev, "contiguous allocation failed\n");
450 bus_release_resources(dev, sc->sc_res_spec,
453 agp_generic_detach(dev);
456 bzero(gatt->ag_virtual, gatt->ag_entries * sizeof(u_int32_t));
458 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual);
460 /* Install the GATT. */
461 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
462 gatt->ag_physical | 1);
463 } else if ( sc->chiptype == CHIP_I830 ) {
464 /* The i830 automatically initializes the 128k gatt on boot. */
465 unsigned int gcc1, pgtblctl;
467 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1);
468 switch (gcc1 & AGP_I830_GCC1_GMS) {
469 case AGP_I830_GCC1_GMS_STOLEN_512:
470 sc->stolen = (512 - 132) * 1024 / 4096;
472 case AGP_I830_GCC1_GMS_STOLEN_1024:
473 sc->stolen = (1024 - 132) * 1024 / 4096;
475 case AGP_I830_GCC1_GMS_STOLEN_8192:
476 sc->stolen = (8192 - 132) * 1024 / 4096;
480 device_printf(dev, "unknown memory configuration, disabling\n");
481 bus_release_resources(dev, sc->sc_res_spec,
484 agp_generic_detach(dev);
487 if (sc->stolen > 0) {
488 device_printf(dev, "detected %dk stolen memory\n",
491 device_printf(dev, "aperture size is %dM\n",
492 sc->initial_aperture / 1024 / 1024);
494 /* GATT address is already in there, make sure it's enabled */
495 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
497 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
499 gatt->ag_physical = pgtblctl & ~1;
500 } else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915 ||
501 sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 ||
502 sc->chiptype == CHIP_IGD || sc->chiptype == CHIP_G4X) {
503 unsigned int gcc1, pgtblctl, stolen, gtt_size;
505 /* Stolen memory is set up at the beginning of the aperture by
506 * the BIOS, consisting of the GATT followed by 4kb for the
509 switch (sc->chiptype) {
517 switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) &
518 AGP_I810_PGTBL_SIZE_MASK) {
519 case AGP_I810_PGTBL_SIZE_128KB:
522 case AGP_I810_PGTBL_SIZE_256KB:
525 case AGP_I810_PGTBL_SIZE_512KB:
528 case AGP_I965_PGTBL_SIZE_1MB:
531 case AGP_I965_PGTBL_SIZE_2MB:
534 case AGP_I965_PGTBL_SIZE_1_5MB:
535 gtt_size = 1024 + 512;
538 device_printf(dev, "Bad PGTBL size\n");
539 bus_release_resources(dev, sc->sc_res_spec,
542 agp_generic_detach(dev);
547 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 2);
548 switch (gcc1 & AGP_G33_MGGC_GGMS_MASK) {
549 case AGP_G33_MGGC_GGMS_SIZE_1M:
552 case AGP_G33_MGGC_GGMS_SIZE_2M:
556 device_printf(dev, "Bad PGTBL size\n");
557 bus_release_resources(dev, sc->sc_res_spec,
560 agp_generic_detach(dev);
569 device_printf(dev, "Bad chiptype\n");
570 bus_release_resources(dev, sc->sc_res_spec,
573 agp_generic_detach(dev);
577 /* GCC1 is called MGGC on i915+ */
578 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1);
579 switch (gcc1 & AGP_I855_GCC1_GMS) {
580 case AGP_I855_GCC1_GMS_STOLEN_1M:
583 case AGP_I855_GCC1_GMS_STOLEN_4M:
586 case AGP_I855_GCC1_GMS_STOLEN_8M:
589 case AGP_I855_GCC1_GMS_STOLEN_16M:
592 case AGP_I855_GCC1_GMS_STOLEN_32M:
595 case AGP_I915_GCC1_GMS_STOLEN_48M:
596 if (sc->chiptype == CHIP_I915 ||
597 sc->chiptype == CHIP_I965 ||
598 sc->chiptype == CHIP_G33 ||
599 sc->chiptype == CHIP_IGD ||
600 sc->chiptype == CHIP_G4X) {
606 case AGP_I915_GCC1_GMS_STOLEN_64M:
607 if (sc->chiptype == CHIP_I915 ||
608 sc->chiptype == CHIP_I965 ||
609 sc->chiptype == CHIP_G33 ||
610 sc->chiptype == CHIP_IGD ||
611 sc->chiptype == CHIP_G4X) {
617 case AGP_G33_GCC1_GMS_STOLEN_128M:
618 if (sc->chiptype == CHIP_I965 ||
619 sc->chiptype == CHIP_G33 ||
620 sc->chiptype == CHIP_IGD ||
621 sc->chiptype == CHIP_G4X) {
627 case AGP_G33_GCC1_GMS_STOLEN_256M:
628 if (sc->chiptype == CHIP_I965 ||
629 sc->chiptype == CHIP_G33 ||
630 sc->chiptype == CHIP_IGD ||
631 sc->chiptype == CHIP_G4X) {
637 case AGP_G4X_GCC1_GMS_STOLEN_96M:
638 if (sc->chiptype == CHIP_I965 ||
639 sc->chiptype == CHIP_G4X) {
645 case AGP_G4X_GCC1_GMS_STOLEN_160M:
646 if (sc->chiptype == CHIP_I965 ||
647 sc->chiptype == CHIP_G4X) {
653 case AGP_G4X_GCC1_GMS_STOLEN_224M:
654 if (sc->chiptype == CHIP_I965 ||
655 sc->chiptype == CHIP_G4X) {
661 case AGP_G4X_GCC1_GMS_STOLEN_352M:
662 if (sc->chiptype == CHIP_I965 ||
663 sc->chiptype == CHIP_G4X) {
670 device_printf(dev, "unknown memory configuration, "
672 bus_release_resources(dev, sc->sc_res_spec,
675 agp_generic_detach(dev);
681 sc->stolen = (stolen - gtt_size) * 1024 / 4096;
683 device_printf(dev, "detected %dk stolen memory\n", sc->stolen * 4);
684 device_printf(dev, "aperture size is %dM\n", sc->initial_aperture / 1024 / 1024);
686 /* GATT address is already in there, make sure it's enabled */
687 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
689 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
691 gatt->ag_physical = pgtblctl & ~1;
695 agp_i810_dump_regs(dev);
701 agp_i810_detach(device_t dev)
703 struct agp_i810_softc *sc = device_get_softc(dev);
707 /* Clear the GATT base. */
708 if ( sc->chiptype == CHIP_I810 ) {
709 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 0);
711 unsigned int pgtblctl;
712 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
714 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
717 /* Put the aperture back the way it started. */
718 AGP_SET_APERTURE(dev, sc->initial_aperture);
720 if ( sc->chiptype == CHIP_I810 ) {
721 contigfree(sc->gatt->ag_virtual, 64 * 1024, M_AGP);
723 kfree(sc->gatt, M_AGP);
725 bus_release_resources(dev, sc->sc_res_spec, sc->sc_res);
732 agp_i810_resume(device_t dev)
734 struct agp_i810_softc *sc;
735 sc = device_get_softc(dev);
737 AGP_SET_APERTURE(dev, sc->initial_aperture);
739 /* Install the GATT. */
740 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
741 sc->gatt->ag_physical | 1);
743 return (bus_generic_resume(dev));
747 * Sets the PCI resource size of the aperture on i830-class and below chipsets,
748 * while returning failure on later chipsets when an actual change is
751 * This whole function is likely bogus, as the kernel would probably need to
752 * reconfigure the placement of the AGP aperture if a larger size is requested,
753 * which doesn't happen currently.
756 agp_i810_set_aperture(device_t dev, u_int32_t aperture)
758 struct agp_i810_softc *sc = device_get_softc(dev);
759 u_int16_t miscc, gcc1;
761 switch (sc->chiptype) {
764 * Double check for sanity.
766 if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) {
767 device_printf(dev, "bad aperture size %d\n", aperture);
771 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
772 miscc &= ~AGP_I810_MISCC_WINSIZE;
773 if (aperture == 32 * 1024 * 1024)
774 miscc |= AGP_I810_MISCC_WINSIZE_32;
776 miscc |= AGP_I810_MISCC_WINSIZE_64;
778 pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2);
781 if (aperture != 64 * 1024 * 1024 &&
782 aperture != 128 * 1024 * 1024) {
783 device_printf(dev, "bad aperture size %d\n", aperture);
786 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
787 gcc1 &= ~AGP_I830_GCC1_GMASIZE;
788 if (aperture == 64 * 1024 * 1024)
789 gcc1 |= AGP_I830_GCC1_GMASIZE_64;
791 gcc1 |= AGP_I830_GCC1_GMASIZE_128;
793 pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2);
801 return agp_generic_set_aperture(dev, aperture);
808 * Writes a GTT entry mapping the page at the given offset from the beginning
809 * of the aperture to the given physical address.
812 agp_i810_write_gtt_entry(device_t dev, int offset, vm_offset_t physical,
815 struct agp_i810_softc *sc = device_get_softc(dev);
818 pte = (u_int32_t)physical | 1;
819 if (sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 ||
820 sc->chiptype == CHIP_IGD || sc->chiptype == CHIP_G4X) {
821 pte |= (physical & 0x0000000f00000000ull) >> 28;
823 /* If we do actually have memory above 4GB on an older system,
824 * crash cleanly rather than scribble on system memory,
825 * so we know we need to fix it.
827 KASSERT((pte & 0x0000000f00000000ull) == 0,
828 (">4GB physical address in agp"));
831 switch (sc->chiptype) {
835 bus_write_4(sc->sc_res[0],
836 AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, pte);
841 bus_write_4(sc->sc_res[1],
842 (offset >> AGP_PAGE_SHIFT) * 4, pte);
845 bus_write_4(sc->sc_res[0],
846 (offset >> AGP_PAGE_SHIFT) * 4 + (512 * 1024), pte);
849 bus_write_4(sc->sc_res[0],
850 (offset >> AGP_PAGE_SHIFT) * 4 + (2 * 1024 * 1024), pte);
856 agp_i810_bind_page(device_t dev, int offset, vm_offset_t physical)
858 struct agp_i810_softc *sc = device_get_softc(dev);
860 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) {
861 device_printf(dev, "failed: offset is 0x%08x, shift is %d, entries is %d\n", offset, AGP_PAGE_SHIFT, sc->gatt->ag_entries);
865 if ( sc->chiptype != CHIP_I810 ) {
866 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
867 device_printf(dev, "trying to bind into stolen memory");
872 agp_i810_write_gtt_entry(dev, offset, physical, 1);
878 agp_i810_unbind_page(device_t dev, int offset)
880 struct agp_i810_softc *sc = device_get_softc(dev);
882 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
885 if ( sc->chiptype != CHIP_I810 ) {
886 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
887 device_printf(dev, "trying to unbind from stolen memory");
892 agp_i810_write_gtt_entry(dev, offset, 0, 0);
898 * Writing via memory mapped registers already flushes all TLBs.
901 agp_i810_flush_tlb(device_t dev)
906 agp_i810_enable(device_t dev, u_int32_t mode)
912 static struct agp_memory *
913 agp_i810_alloc_memory(device_t dev, int type, vm_size_t size)
915 struct agp_i810_softc *sc = device_get_softc(dev);
916 struct agp_memory *mem;
918 if ((size & (AGP_PAGE_SIZE - 1)) != 0)
921 if (sc->agp.as_allocated + size > sc->agp.as_maxmem)
926 * Mapping local DRAM into GATT.
928 if ( sc->chiptype != CHIP_I810 )
930 if (size != sc->dcache_size)
932 } else if (type == 2) {
934 * Type 2 is the contiguous physical memory type, that hands
935 * back a physical address. This is used for cursors on i810.
936 * Hand back as many single pages with physical as the user
937 * wants, but only allow one larger allocation (ARGB cursor)
940 if (size != AGP_PAGE_SIZE) {
941 if (sc->argb_cursor != NULL)
944 /* Allocate memory for ARGB cursor, if we can. */
945 sc->argb_cursor = contigmalloc(size, M_AGP,
946 0, 0, ~0, PAGE_SIZE, 0);
947 if (sc->argb_cursor == NULL)
952 mem = kmalloc(sizeof *mem, M_AGP, M_INTWAIT);
953 mem->am_id = sc->agp.as_nextid++;
956 if (type != 1 && (type != 2 || size == AGP_PAGE_SIZE))
957 mem->am_obj = vm_object_allocate(OBJT_DEFAULT,
958 atop(round_page(size)));
963 if (size == AGP_PAGE_SIZE) {
965 * Allocate and wire down the page now so that we can
966 * get its physical address.
970 m = vm_page_grab(mem->am_obj, 0, VM_ALLOC_NORMAL |
974 mem->am_physical = VM_PAGE_TO_PHYS(m);
977 /* Our allocation is already nicely wired down for us.
978 * Just grab the physical address.
980 mem->am_physical = vtophys(sc->argb_cursor);
983 mem->am_physical = 0;
987 mem->am_is_bound = 0;
988 TAILQ_INSERT_TAIL(&sc->agp.as_memory, mem, am_link);
989 sc->agp.as_allocated += size;
995 agp_i810_free_memory(device_t dev, struct agp_memory *mem)
997 struct agp_i810_softc *sc = device_get_softc(dev);
999 if (mem->am_is_bound)
1002 if (mem->am_type == 2) {
1003 if (mem->am_size == AGP_PAGE_SIZE) {
1005 * Unwire the page which we wired in alloc_memory.
1009 vm_object_hold(mem->am_obj);
1010 m = vm_page_lookup_busy_wait(mem->am_obj, 0,
1012 vm_object_drop(mem->am_obj);
1013 vm_page_unwire(m, 0);
1016 contigfree(sc->argb_cursor, mem->am_size, M_AGP);
1017 sc->argb_cursor = NULL;
1021 sc->agp.as_allocated -= mem->am_size;
1022 TAILQ_REMOVE(&sc->agp.as_memory, mem, am_link);
1024 vm_object_deallocate(mem->am_obj);
1030 agp_i810_bind_memory(device_t dev, struct agp_memory *mem,
1033 struct agp_i810_softc *sc = device_get_softc(dev);
1036 /* Do some sanity checks first. */
1037 if (offset < 0 || (offset & (AGP_PAGE_SIZE - 1)) != 0 ||
1038 offset + mem->am_size > AGP_GET_APERTURE(dev)) {
1039 device_printf(dev, "binding memory at bad offset %#x\n",
1044 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1045 lockmgr(&sc->agp.as_lock, LK_EXCLUSIVE);
1046 if (mem->am_is_bound) {
1047 lockmgr(&sc->agp.as_lock, LK_RELEASE);
1050 /* The memory's already wired down, just stick it in the GTT. */
1051 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1052 agp_i810_write_gtt_entry(dev, offset + i,
1053 mem->am_physical + i, 1);
1056 mem->am_offset = offset;
1057 mem->am_is_bound = 1;
1058 lockmgr(&sc->agp.as_lock, LK_RELEASE);
1062 if (mem->am_type != 1)
1063 return agp_generic_bind_memory(dev, mem, offset);
1065 if ( sc->chiptype != CHIP_I810 )
1068 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1069 bus_write_4(sc->sc_res[0],
1070 AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, i | 3);
1077 agp_i810_unbind_memory(device_t dev, struct agp_memory *mem)
1079 struct agp_i810_softc *sc = device_get_softc(dev);
1082 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1083 lockmgr(&sc->agp.as_lock, LK_EXCLUSIVE);
1084 if (!mem->am_is_bound) {
1085 lockmgr(&sc->agp.as_lock, LK_RELEASE);
1089 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1090 agp_i810_write_gtt_entry(dev, mem->am_offset + i,
1094 mem->am_is_bound = 0;
1095 lockmgr(&sc->agp.as_lock, LK_RELEASE);
1099 if (mem->am_type != 1)
1100 return agp_generic_unbind_memory(dev, mem);
1102 if ( sc->chiptype != CHIP_I810 )
1105 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1106 bus_write_4(sc->sc_res[0],
1107 AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, 0);
1113 static device_method_t agp_i810_methods[] = {
1114 /* Device interface */
1115 DEVMETHOD(device_identify, agp_i810_identify),
1116 DEVMETHOD(device_probe, agp_i810_probe),
1117 DEVMETHOD(device_attach, agp_i810_attach),
1118 DEVMETHOD(device_detach, agp_i810_detach),
1119 DEVMETHOD(device_suspend, bus_generic_suspend),
1120 DEVMETHOD(device_resume, agp_i810_resume),
1123 DEVMETHOD(agp_get_aperture, agp_generic_get_aperture),
1124 DEVMETHOD(agp_set_aperture, agp_i810_set_aperture),
1125 DEVMETHOD(agp_bind_page, agp_i810_bind_page),
1126 DEVMETHOD(agp_unbind_page, agp_i810_unbind_page),
1127 DEVMETHOD(agp_flush_tlb, agp_i810_flush_tlb),
1128 DEVMETHOD(agp_enable, agp_i810_enable),
1129 DEVMETHOD(agp_alloc_memory, agp_i810_alloc_memory),
1130 DEVMETHOD(agp_free_memory, agp_i810_free_memory),
1131 DEVMETHOD(agp_bind_memory, agp_i810_bind_memory),
1132 DEVMETHOD(agp_unbind_memory, agp_i810_unbind_memory),
1137 static driver_t agp_i810_driver = {
1140 sizeof(struct agp_i810_softc),
1143 static devclass_t agp_devclass;
1145 DRIVER_MODULE(agp_i810, vgapci, agp_i810_driver, agp_devclass, NULL, NULL);
1146 MODULE_DEPEND(agp_i810, agp, 1, 1, 1);
1147 MODULE_DEPEND(agp_i810, pci, 1, 1, 1);