sys/dev/drm/i915/intel_crt.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/i2c.h>
  29 #include <drm/drmP.h>
  30 #include <drm/drm_crtc.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/drm_edid.h>
  33 #include "intel_drv.h"
  34 #include <drm/i915_drm.h>
  35 #include "i915_drv.h"
  36
  37 /* Here's the desired hotplug mode */
  38 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  39                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  40                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  41                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  42                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  43                            ADPA_CRT_HOTPLUG_ENABLE)
  44
  45 struct intel_crt {
  46         struct intel_encoder base;
  47         /* DPMS state is stored in the connector, which we need in the
  48          * encoder's enable/disable callbacks */
  49         struct intel_connector *connector;
  50         bool force_hotplug_required;
  51         u32 adpa_reg;
  52 };
  53
  54 static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  55 {
  56         return container_of(intel_attached_encoder(connector),
  57                             struct intel_crt, base);
  58 }
  59
  60 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  61 {
  62         return container_of(encoder, struct intel_crt, base);
  63 }
  64
  65 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  66                                    enum i915_pipe *pipe)
  67 {
  68         struct drm_device *dev = encoder->base.dev;
  69         struct drm_i915_private *dev_priv = dev->dev_private;
  70         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  71         u32 tmp;
  72
  73         tmp = I915_READ(crt->adpa_reg);
  74
  75         if (!(tmp & ADPA_DAC_ENABLE))
  76                 return false;
  77
  78         if (HAS_PCH_CPT(dev))
  79                 *pipe = PORT_TO_PIPE_CPT(tmp);
  80         else
  81                 *pipe = PORT_TO_PIPE(tmp);
  82
  83         return true;
  84 }
  85
  86 static void intel_crt_get_config(struct intel_encoder *encoder,
  87                                  struct intel_crtc_config *pipe_config)
  88 {
  89         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  90         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  91         u32 tmp, flags = 0;
  92
  93         tmp = I915_READ(crt->adpa_reg);
  94
  95         if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
  96                 flags |= DRM_MODE_FLAG_PHSYNC;
  97         else
  98                 flags |= DRM_MODE_FLAG_NHSYNC;
  99
 100         if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
 101                 flags |= DRM_MODE_FLAG_PVSYNC;
 102         else
 103                 flags |= DRM_MODE_FLAG_NVSYNC;
 104
 105         pipe_config->adjusted_mode.flags |= flags;
 106 }
 107
 108 /* Note: The caller is required to filter out dpms modes not supported by the
 109  * platform. */
 110 static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
 111 {
 112         struct drm_device *dev = encoder->base.dev;
 113         struct drm_i915_private *dev_priv = dev->dev_private;
 114         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 115         u32 temp;
 116
 117         temp = I915_READ(crt->adpa_reg);
 118         temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
 119         temp &= ~ADPA_DAC_ENABLE;
 120
 121         switch (mode) {
 122         case DRM_MODE_DPMS_ON:
 123                 temp |= ADPA_DAC_ENABLE;
 124                 break;
 125         case DRM_MODE_DPMS_STANDBY:
 126                 temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
 127                 break;
 128         case DRM_MODE_DPMS_SUSPEND:
 129                 temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
 130                 break;
 131         case DRM_MODE_DPMS_OFF:
 132                 temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
 133                 break;
 134         }
 135
 136         I915_WRITE(crt->adpa_reg, temp);
 137 }
 138
 139 static void intel_disable_crt(struct intel_encoder *encoder)
 140 {
 141         intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
 142 }
 143
 144 static void intel_enable_crt(struct intel_encoder *encoder)
 145 {
 146         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 147
 148         intel_crt_set_dpms(encoder, crt->connector->base.dpms);
 149 }
 150
 151 /* Special dpms function to support cloning between dvo/sdvo/crt. */
 152 static void intel_crt_dpms(struct drm_connector *connector, int mode)
 153 {
 154         struct drm_device *dev = connector->dev;
 155         struct intel_encoder *encoder = intel_attached_encoder(connector);
 156         struct drm_crtc *crtc;
 157         int old_dpms;
 158
 159         /* PCH platforms and VLV only support on/off. */
 160         if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON)
 161                 mode = DRM_MODE_DPMS_OFF;
 162
 163         if (mode == connector->dpms)
 164                 return;
 165
 166         old_dpms = connector->dpms;
 167         connector->dpms = mode;
 168
 169         /* Only need to change hw state when actually enabled */
 170         crtc = encoder->base.crtc;
 171         if (!crtc) {
 172                 encoder->connectors_active = false;
 173                 return;
 174         }
 175
 176         /* We need the pipe to run for anything but OFF. */
 177         if (mode == DRM_MODE_DPMS_OFF)
 178                 encoder->connectors_active = false;
 179         else
 180                 encoder->connectors_active = true;
 181
 182         /* We call connector dpms manually below in case pipe dpms doesn't
 183          * change due to cloning. */
 184         if (mode < old_dpms) {
 185                 /* From off to on, enable the pipe first. */
 186                 intel_crtc_update_dpms(crtc);
 187
 188                 intel_crt_set_dpms(encoder, mode);
 189         } else {
 190                 intel_crt_set_dpms(encoder, mode);
 191
 192                 intel_crtc_update_dpms(crtc);
 193         }
 194
 195         intel_modeset_check_state(connector->dev);
 196 }
 197
 198 static int intel_crt_mode_valid(struct drm_connector *connector,
 199                                 struct drm_display_mode *mode)
 200 {
 201         struct drm_device *dev = connector->dev;
 202
 203         int max_clock = 0;
 204         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 205                 return MODE_NO_DBLESCAN;
 206
 207         if (mode->clock < 25000)
 208                 return MODE_CLOCK_LOW;
 209
 210         if (IS_GEN2(dev))
 211                 max_clock = 350000;
 212         else
 213                 max_clock = 400000;
 214         if (mode->clock > max_clock)
 215                 return MODE_CLOCK_HIGH;
 216
 217         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
 218         if (HAS_PCH_LPT(dev) &&
 219             (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
 220                 return MODE_CLOCK_HIGH;
 221
 222         return MODE_OK;
 223 }
 224
 225 static bool intel_crt_compute_config(struct intel_encoder *encoder,
 226                                      struct intel_crtc_config *pipe_config)
 227 {
 228         struct drm_device *dev = encoder->base.dev;
 229
 230         if (HAS_PCH_SPLIT(dev))
 231                 pipe_config->has_pch_encoder = true;
 232
 233         /* LPT FDI RX only supports 8bpc. */
 234         if (HAS_PCH_LPT(dev))
 235                 pipe_config->pipe_bpp = 24;
 236
 237         return true;
 238 }
 239
 240 static void intel_crt_mode_set(struct drm_encoder *encoder,
 241                                struct drm_display_mode *mode,
 242                                struct drm_display_mode *adjusted_mode)
 243 {
 244
 245         struct drm_device *dev = encoder->dev;
 246         struct drm_crtc *crtc = encoder->crtc;
 247         struct intel_crt *crt =
 248                 intel_encoder_to_crt(to_intel_encoder(encoder));
 249         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 250         struct drm_i915_private *dev_priv = dev->dev_private;
 251         u32 adpa;
 252
 253         if (HAS_PCH_SPLIT(dev))
 254                 adpa = ADPA_HOTPLUG_BITS;
 255         else
 256                 adpa = 0;
 257
 258         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 259                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
 260         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 261                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
 262
 263         /* For CPT allow 3 pipe config, for others just use A or B */
 264         if (HAS_PCH_LPT(dev))
 265                 ; /* Those bits don't exist here */
 266         else if (HAS_PCH_CPT(dev))
 267                 adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
 268         else if (intel_crtc->pipe == 0)
 269                 adpa |= ADPA_PIPE_A_SELECT;
 270         else
 271                 adpa |= ADPA_PIPE_B_SELECT;
 272
 273         if (!HAS_PCH_SPLIT(dev))
 274                 I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
 275
 276         I915_WRITE(crt->adpa_reg, adpa);
 277 }
 278
 279 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
 280 {
 281         struct drm_device *dev = connector->dev;
 282         struct intel_crt *crt = intel_attached_crt(connector);
 283         struct drm_i915_private *dev_priv = dev->dev_private;
 284         u32 adpa;
 285         bool ret;
 286
 287         /* The first time through, trigger an explicit detection cycle */
 288         if (crt->force_hotplug_required) {
 289                 bool turn_off_dac = HAS_PCH_SPLIT(dev);
 290                 u32 save_adpa;
 291
 292                 crt->force_hotplug_required = 0;
 293
 294                 save_adpa = adpa = I915_READ(crt->adpa_reg);
 295                 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 296
 297                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 298                 if (turn_off_dac)
 299                         adpa &= ~ADPA_DAC_ENABLE;
 300
 301                 I915_WRITE(crt->adpa_reg, adpa);
 302
 303                 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
 304                              1000))
 305                         DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 306
 307                 if (turn_off_dac) {
 308                         I915_WRITE(crt->adpa_reg, save_adpa);
 309                         POSTING_READ(crt->adpa_reg);
 310                 }
 311         }
 312
 313         /* Check the status to see if both blue and green are on now */
 314         adpa = I915_READ(crt->adpa_reg);
 315         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 316                 ret = true;
 317         else
 318                 ret = false;
 319         DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
 320
 321         return ret;
 322 }
 323
 324 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
 325 {
 326         struct drm_device *dev = connector->dev;
 327         struct intel_crt *crt = intel_attached_crt(connector);
 328         struct drm_i915_private *dev_priv = dev->dev_private;
 329         u32 adpa;
 330         bool ret;
 331         u32 save_adpa;
 332
 333         save_adpa = adpa = I915_READ(crt->adpa_reg);
 334         DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 335
 336         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 337
 338         I915_WRITE(crt->adpa_reg, adpa);
 339
 340         if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
 341                      1000)) {
 342                 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 343                 I915_WRITE(crt->adpa_reg, save_adpa);
 344         }
 345
 346         /* Check the status to see if both blue and green are on now */
 347         adpa = I915_READ(crt->adpa_reg);
 348         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 349                 ret = true;
 350         else
 351                 ret = false;
 352
 353         DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
 354
 355         /* FIXME: debug force function and remove */
 356         ret = true;
 357
 358         return ret;
 359 }
 360
 361 /**
 362  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
 363  *
 364  * Not for i915G/i915GM
 365  *
 366  * \return true if CRT is connected.
 367  * \return false if CRT is disconnected.
 368  */
 369 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 370 {
 371         struct drm_device *dev = connector->dev;
 372         struct drm_i915_private *dev_priv = dev->dev_private;
 373         u32 hotplug_en, orig, stat;
 374         bool ret = false;
 375         int i, tries = 0;
 376
 377         if (HAS_PCH_SPLIT(dev))
 378                 return intel_ironlake_crt_detect_hotplug(connector);
 379
 380         if (IS_VALLEYVIEW(dev))
 381                 return valleyview_crt_detect_hotplug(connector);
 382
 383         /*
 384          * On 4 series desktop, CRT detect sequence need to be done twice
 385          * to get a reliable result.
 386          */
 387
 388         if (IS_G4X(dev) && !IS_GM45(dev))
 389                 tries = 2;
 390         else
 391                 tries = 1;
 392         hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
 393         hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
 394
 395         for (i = 0; i < tries ; i++) {
 396                 /* turn on the FORCE_DETECT */
 397                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
 398                 /* wait for FORCE_DETECT to go off */
 399                 if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
 400                               CRT_HOTPLUG_FORCE_DETECT) == 0,
 401                              1000))
 402                         DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
 403         }
 404
 405         stat = I915_READ(PORT_HOTPLUG_STAT);
 406         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
 407                 ret = true;
 408
 409         /* clear the interrupt we just generated, if any */
 410         I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
 411
 412         /* and put the bits back */
 413         I915_WRITE(PORT_HOTPLUG_EN, orig);
 414
 415         return ret;
 416 }
 417
 418 static struct edid *intel_crt_get_edid(struct drm_connector *connector,
 419                                 struct device *i2c)
 420 {
 421         struct edid *edid;
 422
 423         edid = drm_get_edid(connector, i2c);
 424
 425         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
 426                 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
 427                 intel_gmbus_force_bit(i2c, true);
 428                 edid = drm_get_edid(connector, i2c);
 429                 intel_gmbus_force_bit(i2c, false);
 430         }
 431
 432         return edid;
 433 }
 434
 435 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
 436 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
 437                                 struct device *adapter)
 438 {
 439         struct edid *edid;
 440         int ret;
 441
 442         edid = intel_crt_get_edid(connector, adapter);
 443         if (!edid)
 444                 return 0;
 445
 446         ret = intel_connector_update_modes(connector, edid);
 447         kfree(edid);
 448
 449         return ret;
 450 }
 451
 452 static bool intel_crt_detect_ddc(struct drm_connector *connector)
 453 {
 454         struct intel_crt *crt = intel_attached_crt(connector);
 455         struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
 456         struct edid *edid;
 457         struct device *i2c;
 458
 459         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
 460
 461         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 462         edid = intel_crt_get_edid(connector, i2c);
 463
 464         if (edid) {
 465                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
 466
 467                 /*
 468                  * This may be a DVI-I connector with a shared DDC
 469                  * link between analog and digital outputs, so we
 470                  * have to check the EDID input spec of the attached device.
 471                  */
 472                 if (!is_digital) {
 473                         DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
 474                         return true;
 475                 }
 476
 477                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
 478         } else {
 479                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
 480         }
 481
 482         kfree(edid);
 483
 484         return false;
 485 }
 486
 487 static enum drm_connector_status
 488 intel_crt_load_detect(struct intel_crt *crt)
 489 {
 490         struct drm_device *dev = crt->base.base.dev;
 491         struct drm_i915_private *dev_priv = dev->dev_private;
 492         uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
 493         uint32_t save_bclrpat;
 494         uint32_t save_vtotal;
 495         uint32_t vtotal, vactive;
 496         uint32_t vsample;
 497         uint32_t vblank, vblank_start, vblank_end;
 498         uint32_t dsl;
 499         uint32_t bclrpat_reg;
 500         uint32_t vtotal_reg;
 501         uint32_t vblank_reg;
 502         uint32_t vsync_reg;
 503         uint32_t pipeconf_reg;
 504         uint32_t pipe_dsl_reg;
 505         uint8_t st00;
 506         enum drm_connector_status status;
 507
 508         DRM_DEBUG_KMS("starting load-detect on CRT\n");
 509
 510         bclrpat_reg = BCLRPAT(pipe);
 511         vtotal_reg = VTOTAL(pipe);
 512         vblank_reg = VBLANK(pipe);
 513         vsync_reg = VSYNC(pipe);
 514         pipeconf_reg = PIPECONF(pipe);
 515         pipe_dsl_reg = PIPEDSL(pipe);
 516
 517         save_bclrpat = I915_READ(bclrpat_reg);
 518         save_vtotal = I915_READ(vtotal_reg);
 519         vblank = I915_READ(vblank_reg);
 520
 521         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
 522         vactive = (save_vtotal & 0x7ff) + 1;
 523
 524         vblank_start = (vblank & 0xfff) + 1;
 525         vblank_end = ((vblank >> 16) & 0xfff) + 1;
 526
 527         /* Set the border color to purple. */
 528         I915_WRITE(bclrpat_reg, 0x500050);
 529
 530         if (!IS_GEN2(dev)) {
 531                 uint32_t pipeconf = I915_READ(pipeconf_reg);
 532                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
 533                 POSTING_READ(pipeconf_reg);
 534                 /* Wait for next Vblank to substitue
 535                  * border color for Color info */
 536                 intel_wait_for_vblank(dev, pipe);
 537                 st00 = I915_READ8(VGA_MSR_WRITE);
 538                 status = ((st00 & (1 << 4)) != 0) ?
 539                         connector_status_connected :
 540                         connector_status_disconnected;
 541
 542                 I915_WRITE(pipeconf_reg, pipeconf);
 543         } else {
 544                 bool restore_vblank = false;
 545                 int count, detect;
 546
 547                 /*
 548                 * If there isn't any border, add some.
 549                 * Yes, this will flicker
 550                 */
 551                 if (vblank_start <= vactive && vblank_end >= vtotal) {
 552                         uint32_t vsync = I915_READ(vsync_reg);
 553                         uint32_t vsync_start = (vsync & 0xffff) + 1;
 554
 555                         vblank_start = vsync_start;
 556                         I915_WRITE(vblank_reg,
 557                                    (vblank_start - 1) |
 558                                    ((vblank_end - 1) << 16));
 559                         restore_vblank = true;
 560                 }
 561                 /* sample in the vertical border, selecting the larger one */
 562                 if (vblank_start - vactive >= vtotal - vblank_end)
 563                         vsample = (vblank_start + vactive) >> 1;
 564                 else
 565                         vsample = (vtotal + vblank_end) >> 1;
 566
 567                 /*
 568                  * Wait for the border to be displayed
 569                  */
 570                 while (I915_READ(pipe_dsl_reg) >= vactive)
 571                         ;
 572                 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
 573                         ;
 574                 /*
 575                  * Watch ST00 for an entire scanline
 576                  */
 577                 detect = 0;
 578                 count = 0;
 579                 do {
 580                         count++;
 581                         /* Read the ST00 VGA status register */
 582                         st00 = I915_READ8(VGA_MSR_WRITE);
 583                         if (st00 & (1 << 4))
 584                                 detect++;
 585                 } while ((I915_READ(pipe_dsl_reg) == dsl));
 586
 587                 /* restore vblank if necessary */
 588                 if (restore_vblank)
 589                         I915_WRITE(vblank_reg, vblank);
 590                 /*
 591                  * If more than 3/4 of the scanline detected a monitor,
 592                  * then it is assumed to be present. This works even on i830,
 593                  * where there isn't any way to force the border color across
 594                  * the screen
 595                  */
 596                 status = detect * 4 > count * 3 ?
 597                          connector_status_connected :
 598                          connector_status_disconnected;
 599         }
 600
 601         /* Restore previous settings */
 602         I915_WRITE(bclrpat_reg, save_bclrpat);
 603
 604         return status;
 605 }
 606
 607 static enum drm_connector_status
 608 intel_crt_detect(struct drm_connector *connector, bool force)
 609 {
 610         struct drm_device *dev = connector->dev;
 611         struct intel_crt *crt = intel_attached_crt(connector);
 612         enum drm_connector_status status;
 613         struct intel_load_detect_pipe tmp;
 614
 615         if (I915_HAS_HOTPLUG(dev)) {
 616                 /* We can not rely on the HPD pin always being correctly wired
 617                  * up, for example many KVM do not pass it through, and so
 618                  * only trust an assertion that the monitor is connected.
 619                  */
 620                 if (intel_crt_detect_hotplug(connector)) {
 621                         DRM_DEBUG_KMS("CRT detected via hotplug\n");
 622                         return connector_status_connected;
 623                 } else
 624                         DRM_DEBUG_KMS("CRT not detected via hotplug\n");
 625         }
 626
 627         if (intel_crt_detect_ddc(connector))
 628                 return connector_status_connected;
 629
 630         /* Load detection is broken on HPD capable machines. Whoever wants a
 631          * broken monitor (without edid) to work behind a broken kvm (that fails
 632          * to have the right resistors for HP detection) needs to fix this up.
 633          * For now just bail out. */
 634         if (I915_HAS_HOTPLUG(dev))
 635                 return connector_status_disconnected;
 636
 637         if (!force)
 638                 return connector->status;
 639
 640         /* for pre-945g platforms use load detect */
 641         if (intel_get_load_detect_pipe(connector, NULL, &tmp)) {
 642                 if (intel_crt_detect_ddc(connector))
 643                         status = connector_status_connected;
 644                 else
 645                         status = intel_crt_load_detect(crt);
 646                 intel_release_load_detect_pipe(connector, &tmp);
 647         } else
 648                 status = connector_status_unknown;
 649
 650         return status;
 651 }
 652
 653 static void intel_crt_destroy(struct drm_connector *connector)
 654 {
 655         drm_sysfs_connector_remove(connector);
 656         drm_connector_cleanup(connector);
 657         kfree(connector);
 658 }
 659
 660 static int intel_crt_get_modes(struct drm_connector *connector)
 661 {
 662         struct drm_device *dev = connector->dev;
 663         struct drm_i915_private *dev_priv = dev->dev_private;
 664         int ret;
 665         struct device *i2c;
 666
 667         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 668         ret = intel_crt_ddc_get_modes(connector, i2c);
 669         if (ret || !IS_G4X(dev))
 670                 return ret;
 671
 672         /* Try to probe digital port for output in DVI-I -> VGA mode. */
 673         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
 674         return intel_crt_ddc_get_modes(connector, i2c);
 675 }
 676
 677 static int intel_crt_set_property(struct drm_connector *connector,
 678                                   struct drm_property *property,
 679                                   uint64_t value)
 680 {
 681         return 0;
 682 }
 683
 684 static void intel_crt_reset(struct drm_connector *connector)
 685 {
 686         struct drm_device *dev = connector->dev;
 687         struct drm_i915_private *dev_priv = dev->dev_private;
 688         struct intel_crt *crt = intel_attached_crt(connector);
 689
 690         if (HAS_PCH_SPLIT(dev)) {
 691                 u32 adpa;
 692
 693                 adpa = I915_READ(crt->adpa_reg);
 694                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
 695                 adpa |= ADPA_HOTPLUG_BITS;
 696                 I915_WRITE(crt->adpa_reg, adpa);
 697                 POSTING_READ(crt->adpa_reg);
 698
 699                 DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
 700                 crt->force_hotplug_required = 1;
 701         }
 702
 703 }
 704
 705 /*
 706  * Routines for controlling stuff on the analog port
 707  */
 708
 709 static const struct drm_encoder_helper_funcs crt_encoder_funcs = {
 710         .mode_set = intel_crt_mode_set,
 711 };
 712
 713 static const struct drm_connector_funcs intel_crt_connector_funcs = {
 714         .reset = intel_crt_reset,
 715         .dpms = intel_crt_dpms,
 716         .detect = intel_crt_detect,
 717         .fill_modes = drm_helper_probe_single_connector_modes,
 718         .destroy = intel_crt_destroy,
 719         .set_property = intel_crt_set_property,
 720 };
 721
 722 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
 723         .mode_valid = intel_crt_mode_valid,
 724         .get_modes = intel_crt_get_modes,
 725         .best_encoder = intel_best_encoder,
 726 };
 727
 728 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
 729         .destroy = intel_encoder_destroy,
 730 };
 731
 732 static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id)
 733 {
 734         DRM_INFO("Skipping CRT initialization for %s\n", id->ident);
 735         return 1;
 736 }
 737
 738 static const struct dmi_system_id intel_no_crt[] = {
 739         {
 740                 .callback = intel_no_crt_dmi_callback,
 741                 .ident = "ACER ZGB",
 742                 .matches = {
 743                         DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
 744                         DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
 745                 },
 746         },
 747         { }
 748 };
 749
 750 void intel_crt_init(struct drm_device *dev)
 751 {
 752         struct drm_connector *connector;
 753         struct intel_crt *crt;
 754         struct intel_connector *intel_connector;
 755         struct drm_i915_private *dev_priv = dev->dev_private;
 756
 757         /* Skip machines without VGA that falsely report hotplug events */
 758         if (dmi_check_system(intel_no_crt))
 759                 return;
 760
 761         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
 762         if (!crt)
 763                 return;
 764
 765         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
 766         if (!intel_connector) {
 767                 kfree(crt);
 768                 return;
 769         }
 770
 771         connector = &intel_connector->base;
 772         crt->connector = intel_connector;
 773         drm_connector_init(dev, &intel_connector->base,
 774                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
 775
 776         drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
 777                          DRM_MODE_ENCODER_DAC);
 778
 779         intel_connector_attach_encoder(intel_connector, &crt->base);
 780
 781         crt->base.type = INTEL_OUTPUT_ANALOG;
 782         crt->base.cloneable = true;
 783         if (IS_I830(dev))
 784                 crt->base.crtc_mask = (1 << 0);
 785         else
 786                 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 787
 788         if (IS_GEN2(dev))
 789                 connector->interlace_allowed = 0;
 790         else
 791                 connector->interlace_allowed = 1;
 792         connector->doublescan_allowed = 0;
 793
 794         if (HAS_PCH_SPLIT(dev))
 795                 crt->adpa_reg = PCH_ADPA;
 796         else if (IS_VALLEYVIEW(dev))
 797                 crt->adpa_reg = VLV_ADPA;
 798         else
 799                 crt->adpa_reg = ADPA;
 800
 801         crt->base.compute_config = intel_crt_compute_config;
 802         crt->base.disable = intel_disable_crt;
 803         crt->base.enable = intel_enable_crt;
 804         crt->base.get_config = intel_crt_get_config;
 805         if (I915_HAS_HOTPLUG(dev))
 806                 crt->base.hpd_pin = HPD_CRT;
 807         if (HAS_DDI(dev))
 808                 crt->base.get_hw_state = intel_ddi_get_hw_state;
 809         else
 810                 crt->base.get_hw_state = intel_crt_get_hw_state;
 811         intel_connector->get_hw_state = intel_connector_get_hw_state;
 812
 813         drm_encoder_helper_add(&crt->base.base, &crt_encoder_funcs);
 814         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
 815
 816         drm_sysfs_connector_add(connector);
 817
 818         if (!I915_HAS_HOTPLUG(dev))
 819                 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
 820
 821         /*
 822          * Configure the automatic hotplug detection stuff
 823          */
 824         crt->force_hotplug_required = 0;
 825
 826         /*
 827          * TODO: find a proper way to discover whether we need to set the the
 828          * polarity and link reversal bits or not, instead of relying on the
 829          * BIOS.
 830          */
 831         if (HAS_PCH_LPT(dev)) {
 832                 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
 833                                  FDI_RX_LINK_REVERSAL_OVERRIDE;
 834
 835                 dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config;
 836         }
 837 }