2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/ale/if_ale.c,v 1.3 2008/12/03 09:01:12 yongari Exp $
30 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */
32 #include <sys/param.h>
33 #include <sys/endian.h>
34 #include <sys/kernel.h>
36 #include <sys/interrupt.h>
37 #include <sys/malloc.h>
40 #include <sys/serialize.h>
41 #include <sys/socket.h>
42 #include <sys/sockio.h>
43 #include <sys/sysctl.h>
45 #include <net/ethernet.h>
48 #include <net/if_arp.h>
49 #include <net/if_dl.h>
50 #include <net/if_llc.h>
51 #include <net/if_media.h>
52 #include <net/ifq_var.h>
53 #include <net/vlan/if_vlan_var.h>
54 #include <net/vlan/if_vlan_ether.h>
56 #include <netinet/ip.h>
58 #include <dev/netif/mii_layer/mii.h>
59 #include <dev/netif/mii_layer/miivar.h>
61 #include <bus/pci/pcireg.h>
62 #include <bus/pci/pcivar.h>
63 #include <bus/pci/pcidevs.h>
65 #include <dev/netif/ale/if_alereg.h>
66 #include <dev/netif/ale/if_alevar.h>
68 /* "device miibus" required. See GENERIC if you get errors here. */
69 #include "miibus_if.h"
71 /* For more information about Tx checksum offload issues see ale_encap(). */
72 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
74 struct ale_dmamap_ctx {
76 bus_dma_segment_t *segs;
79 static int ale_probe(device_t);
80 static int ale_attach(device_t);
81 static int ale_detach(device_t);
82 static int ale_shutdown(device_t);
83 static int ale_suspend(device_t);
84 static int ale_resume(device_t);
86 static int ale_miibus_readreg(device_t, int, int);
87 static int ale_miibus_writereg(device_t, int, int, int);
88 static void ale_miibus_statchg(device_t);
90 static void ale_init(void *);
91 static void ale_start(struct ifnet *);
92 static int ale_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
93 static void ale_watchdog(struct ifnet *);
94 static int ale_mediachange(struct ifnet *);
95 static void ale_mediastatus(struct ifnet *, struct ifmediareq *);
97 static void ale_intr(void *);
98 static int ale_rxeof(struct ale_softc *sc);
99 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **,
100 uint32_t, uint32_t *);
101 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t);
102 static void ale_txeof(struct ale_softc *);
104 static int ale_dma_alloc(struct ale_softc *);
105 static void ale_dma_free(struct ale_softc *);
106 static int ale_check_boundary(struct ale_softc *);
107 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int);
108 static void ale_dmamap_buf_cb(void *, bus_dma_segment_t *, int,
110 static int ale_encap(struct ale_softc *, struct mbuf **);
111 static void ale_init_rx_pages(struct ale_softc *);
112 static void ale_init_tx_ring(struct ale_softc *);
114 static void ale_stop(struct ale_softc *);
115 static void ale_tick(void *);
116 static void ale_get_macaddr(struct ale_softc *);
117 static void ale_mac_config(struct ale_softc *);
118 static void ale_phy_reset(struct ale_softc *);
119 static void ale_reset(struct ale_softc *);
120 static void ale_rxfilter(struct ale_softc *);
121 static void ale_rxvlan(struct ale_softc *);
122 static void ale_stats_clear(struct ale_softc *);
123 static void ale_stats_update(struct ale_softc *);
124 static void ale_stop_mac(struct ale_softc *);
126 static void ale_setlinkspeed(struct ale_softc *);
127 static void ale_setwol(struct ale_softc *);
130 static void ale_sysctl_node(struct ale_softc *);
131 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS);
134 * Devices supported by this driver.
136 static struct ale_dev {
137 uint16_t ale_vendorid;
138 uint16_t ale_deviceid;
139 const char *ale_name;
141 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX,
142 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" },
145 static device_method_t ale_methods[] = {
146 /* Device interface. */
147 DEVMETHOD(device_probe, ale_probe),
148 DEVMETHOD(device_attach, ale_attach),
149 DEVMETHOD(device_detach, ale_detach),
150 DEVMETHOD(device_shutdown, ale_shutdown),
151 DEVMETHOD(device_suspend, ale_suspend),
152 DEVMETHOD(device_resume, ale_resume),
155 DEVMETHOD(bus_print_child, bus_generic_print_child),
156 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
159 DEVMETHOD(miibus_readreg, ale_miibus_readreg),
160 DEVMETHOD(miibus_writereg, ale_miibus_writereg),
161 DEVMETHOD(miibus_statchg, ale_miibus_statchg),
166 static driver_t ale_driver = {
169 sizeof(struct ale_softc)
172 static devclass_t ale_devclass;
174 DECLARE_DUMMY_MODULE(if_ale);
175 MODULE_VERSION(if_ale, 1);
176 MODULE_DEPEND(if_ale, miibus, 1, 1, 1);
177 DRIVER_MODULE(if_ale, pci, ale_driver, ale_devclass, NULL, NULL);
178 DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, NULL, NULL);
181 ale_miibus_readreg(device_t dev, int phy, int reg)
183 struct ale_softc *sc;
187 sc = device_get_softc(dev);
189 if (phy != sc->ale_phyaddr)
192 if (sc->ale_flags & ALE_FLAG_FASTETHER) {
193 if (reg == MII_100T2CR || reg == MII_100T2SR ||
198 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
199 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
200 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
202 v = CSR_READ_4(sc, ALE_MDIO);
203 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
208 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg);
212 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
216 ale_miibus_writereg(device_t dev, int phy, int reg, int val)
218 struct ale_softc *sc;
222 sc = device_get_softc(dev);
224 if (phy != sc->ale_phyaddr)
227 if (sc->ale_flags & ALE_FLAG_FASTETHER) {
228 if (reg == MII_100T2CR || reg == MII_100T2SR ||
233 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
234 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
235 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
236 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
238 v = CSR_READ_4(sc, ALE_MDIO);
239 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
244 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg);
250 ale_miibus_statchg(device_t dev)
252 struct ale_softc *sc = device_get_softc(dev);
253 struct ifnet *ifp = &sc->arpcom.ac_if;
254 struct mii_data *mii;
257 ASSERT_SERIALIZED(ifp->if_serializer);
259 if ((ifp->if_flags & IFF_RUNNING) == 0)
262 mii = device_get_softc(sc->ale_miibus);
264 sc->ale_flags &= ~ALE_FLAG_LINK;
265 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
266 (IFM_ACTIVE | IFM_AVALID)) {
267 switch (IFM_SUBTYPE(mii->mii_media_active)) {
270 sc->ale_flags |= ALE_FLAG_LINK;
274 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
275 sc->ale_flags |= ALE_FLAG_LINK;
283 /* Stop Rx/Tx MACs. */
286 /* Program MACs with resolved speed/duplex/flow-control. */
287 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) {
289 /* Reenable Tx/Rx MACs. */
290 reg = CSR_READ_4(sc, ALE_MAC_CFG);
291 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
292 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
297 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
299 struct ale_softc *sc = ifp->if_softc;
300 struct mii_data *mii = device_get_softc(sc->ale_miibus);
302 ASSERT_SERIALIZED(ifp->if_serializer);
305 ifmr->ifm_status = mii->mii_media_status;
306 ifmr->ifm_active = mii->mii_media_active;
310 ale_mediachange(struct ifnet *ifp)
312 struct ale_softc *sc = ifp->if_softc;
313 struct mii_data *mii = device_get_softc(sc->ale_miibus);
316 ASSERT_SERIALIZED(ifp->if_serializer);
318 if (mii->mii_instance != 0) {
319 struct mii_softc *miisc;
321 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
322 mii_phy_reset(miisc);
324 error = mii_mediachg(mii);
330 ale_probe(device_t dev)
334 uint16_t vendor, devid;
336 vendor = pci_get_vendor(dev);
337 devid = pci_get_device(dev);
339 for (i = 0; i < NELEM(ale_devs); i++) {
340 if (vendor == sp->ale_vendorid &&
341 devid == sp->ale_deviceid) {
342 device_set_desc(dev, sp->ale_name);
352 ale_get_macaddr(struct ale_softc *sc)
357 reg = CSR_READ_4(sc, ALE_SPI_CTRL);
358 if ((reg & SPI_VPD_ENB) != 0) {
360 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);
363 vpdc = pci_get_vpdcap_ptr(sc->ale_dev);
366 * PCI VPD capability found, let TWSI reload EEPROM.
367 * This will set ethernet address of controller.
369 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
370 TWSI_CTRL_SW_LD_START);
371 for (i = 100; i > 0; i--) {
373 reg = CSR_READ_4(sc, ALE_TWSI_CTRL);
374 if ((reg & TWSI_CTRL_SW_LD_START) == 0)
378 device_printf(sc->ale_dev,
379 "reloading EEPROM timeout!\n");
382 device_printf(sc->ale_dev,
383 "PCI VPD capability not found!\n");
386 ea[0] = CSR_READ_4(sc, ALE_PAR0);
387 ea[1] = CSR_READ_4(sc, ALE_PAR1);
388 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF;
389 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF;
390 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF;
391 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF;
392 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF;
393 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF;
397 ale_phy_reset(struct ale_softc *sc)
399 /* Reset magic from Linux. */
400 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
401 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
402 GPHY_CTRL_PHY_PLL_ON);
404 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
405 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE |
406 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON);
409 #define ATPHY_DBG_ADDR 0x1D
410 #define ATPHY_DBG_DATA 0x1E
412 /* Enable hibernation mode. */
413 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
414 ATPHY_DBG_ADDR, 0x0B);
415 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
416 ATPHY_DBG_DATA, 0xBC00);
417 /* Set Class A/B for all modes. */
418 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
419 ATPHY_DBG_ADDR, 0x00);
420 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
421 ATPHY_DBG_DATA, 0x02EF);
422 /* Enable 10BT power saving. */
423 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
424 ATPHY_DBG_ADDR, 0x12);
425 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
426 ATPHY_DBG_DATA, 0x4C04);
427 /* Adjust 1000T power. */
428 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
429 ATPHY_DBG_ADDR, 0x04);
430 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
431 ATPHY_DBG_ADDR, 0x8BBB);
432 /* 10BT center tap voltage. */
433 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
434 ATPHY_DBG_ADDR, 0x05);
435 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
436 ATPHY_DBG_ADDR, 0x2C46);
438 #undef ATPHY_DBG_ADDR
439 #undef ATPHY_DBG_DATA
444 ale_attach(device_t dev)
446 struct ale_softc *sc = device_get_softc(dev);
447 struct ifnet *ifp = &sc->arpcom.ac_if;
449 uint32_t rxf_len, txf_len;
452 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
455 callout_init(&sc->ale_tick_ch);
458 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
461 irq = pci_read_config(dev, PCIR_INTLINE, 4);
462 mem = pci_read_config(dev, ALE_PCIR_BAR, 4);
464 device_printf(dev, "chip is in D%d power mode "
465 "-- setting to D0\n", pci_get_powerstate(dev));
467 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
469 pci_write_config(dev, PCIR_INTLINE, irq, 4);
470 pci_write_config(dev, ALE_PCIR_BAR, mem, 4);
472 #endif /* !BURN_BRIDGE */
474 /* Enable bus mastering */
475 pci_enable_busmaster(dev);
478 * Allocate memory mapped IO
480 sc->ale_mem_rid = ALE_PCIR_BAR;
481 sc->ale_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
482 &sc->ale_mem_rid, RF_ACTIVE);
483 if (sc->ale_mem_res == NULL) {
484 device_printf(dev, "can't allocate IO memory\n");
487 sc->ale_mem_bt = rman_get_bustag(sc->ale_mem_res);
488 sc->ale_mem_bh = rman_get_bushandle(sc->ale_mem_res);
494 sc->ale_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
496 RF_SHAREABLE | RF_ACTIVE);
497 if (sc->ale_irq_res == NULL) {
498 device_printf(dev, "can't allocate irq\n");
503 /* Set PHY address. */
504 sc->ale_phyaddr = ALE_PHY_ADDR;
509 /* Reset the ethernet controller. */
512 /* Get PCI and chip id/revision. */
513 sc->ale_rev = pci_get_revid(dev);
514 if (sc->ale_rev >= 0xF0) {
515 /* L2E Rev. B. AR8114 */
516 sc->ale_flags |= ALE_FLAG_FASTETHER;
518 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) {
520 sc->ale_flags |= ALE_FLAG_JUMBO;
522 /* L2E Rev. A. AR8113 */
523 sc->ale_flags |= ALE_FLAG_FASTETHER;
528 * All known controllers seems to require 4 bytes alignment
529 * of Tx buffers to make Tx checksum offload with custom
530 * checksum generation method work.
532 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG;
535 * All known controllers seems to have issues on Rx checksum
536 * offload for fragmented IP datagrams.
538 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG;
541 * Don't use Tx CMB. It is known to cause RRS update failure
542 * under certain circumstances. Typical phenomenon of the
543 * issue would be unexpected sequence number encountered in
546 sc->ale_flags |= ALE_FLAG_TXCMB_BUG;
547 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >>
548 MASTER_CHIP_REV_SHIFT;
550 device_printf(dev, "PCI device revision : 0x%04x\n",
552 device_printf(dev, "Chip id/revision : 0x%04x\n",
557 * Uninitialized hardware returns an invalid chip id/revision
558 * as well as 0xFFFFFFFF for Tx/Rx fifo length.
560 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN);
561 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
562 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF ||
563 rxf_len == 0xFFFFFFF) {
564 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO "
565 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev,
570 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len);
572 /* Get DMA parameters from PCIe device control register. */
573 pcie_ptr = pci_get_pciecap_ptr(dev);
577 sc->ale_flags |= ALE_FLAG_PCIE;
578 devctl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
579 /* Max read request size. */
580 sc->ale_dma_rd_burst = ((devctl >> 12) & 0x07) <<
581 DMA_CFG_RD_BURST_SHIFT;
582 /* Max payload size. */
583 sc->ale_dma_wr_burst = ((devctl >> 5) & 0x07) <<
584 DMA_CFG_WR_BURST_SHIFT;
586 device_printf(dev, "Read request size : %d bytes.\n",
587 128 << ((devctl >> 12) & 0x07));
588 device_printf(dev, "TLP payload size : %d bytes.\n",
589 128 << ((devctl >> 5) & 0x07));
592 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128;
593 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128;
596 /* Create device sysctl node. */
599 if ((error = ale_dma_alloc(sc) != 0))
602 /* Load station address. */
606 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
607 ifp->if_ioctl = ale_ioctl;
608 ifp->if_start = ale_start;
609 ifp->if_init = ale_init;
610 ifp->if_watchdog = ale_watchdog;
611 ifq_set_maxlen(&ifp->if_snd, ALE_TX_RING_CNT - 1);
612 ifq_set_ready(&ifp->if_snd);
614 ifp->if_capabilities = IFCAP_RXCSUM |
616 IFCAP_VLAN_HWTAGGING;
618 ifp->if_capabilities |= IFCAP_TXCSUM;
619 ifp->if_hwassist = ALE_CSUM_FEATURES;
621 ifp->if_capenable = ifp->if_capabilities;
623 /* Set up MII bus. */
624 if ((error = mii_phy_probe(dev, &sc->ale_miibus, ale_mediachange,
625 ale_mediastatus)) != 0) {
626 device_printf(dev, "no PHY found!\n");
630 ether_ifattach(ifp, sc->ale_eaddr, NULL);
632 /* Tell the upper layer(s) we support long frames. */
633 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
635 error = bus_setup_intr(dev, sc->ale_irq_res, INTR_MPSAFE, ale_intr, sc,
636 &sc->ale_irq_handle, ifp->if_serializer);
638 device_printf(dev, "could not set up interrupt handler.\n");
643 ifp->if_cpuid = rman_get_cpuid(sc->ale_irq_res);
644 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
652 ale_detach(device_t dev)
654 struct ale_softc *sc = device_get_softc(dev);
656 if (device_is_attached(dev)) {
657 struct ifnet *ifp = &sc->arpcom.ac_if;
659 lwkt_serialize_enter(ifp->if_serializer);
660 sc->ale_flags |= ALE_FLAG_DETACH;
662 bus_teardown_intr(dev, sc->ale_irq_res, sc->ale_irq_handle);
663 lwkt_serialize_exit(ifp->if_serializer);
668 if (sc->ale_sysctl_tree != NULL)
669 sysctl_ctx_free(&sc->ale_sysctl_ctx);
671 if (sc->ale_miibus != NULL)
672 device_delete_child(dev, sc->ale_miibus);
673 bus_generic_detach(dev);
675 if (sc->ale_irq_res != NULL) {
676 bus_release_resource(dev, SYS_RES_IRQ, sc->ale_irq_rid,
679 if (sc->ale_mem_res != NULL) {
680 bus_release_resource(dev, SYS_RES_MEMORY, sc->ale_mem_rid,
689 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
690 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
691 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
692 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
695 ale_sysctl_node(struct ale_softc *sc)
697 struct sysctl_ctx_list *ctx;
698 struct sysctl_oid_list *child, *parent;
699 struct sysctl_oid *tree;
700 struct ale_hw_stats *stats;
703 sysctl_ctx_init(&sc->ale_sysctl_ctx);
704 sc->ale_sysctl_tree = SYSCTL_ADD_NODE(&sc->ale_sysctl_ctx,
705 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
706 device_get_nameunit(sc->ale_dev),
708 if (sc->ale_sysctl_tree == NULL) {
709 device_printf(sc->ale_dev, "can't add sysctl node\n");
713 stats = &sc->ale_stats;
714 ctx = &sc->ale_sysctl_ctx;
715 child = SYSCTL_CHILDREN(sc->ale_sysctl_tree);
717 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod",
718 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0,
719 sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation");
720 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod",
721 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0,
722 sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation");
725 * Pull in device tunables.
727 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
728 error = resource_int_value(device_get_name(sc->ale_dev),
729 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod);
731 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN ||
732 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) {
733 device_printf(sc->ale_dev, "int_rx_mod value out of "
734 "range; using default: %d\n",
735 ALE_IM_RX_TIMER_DEFAULT);
736 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
740 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
741 error = resource_int_value(device_get_name(sc->ale_dev),
742 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod);
744 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN ||
745 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) {
746 device_printf(sc->ale_dev, "int_tx_mod value out of "
747 "range; using default: %d\n",
748 ALE_IM_TX_TIMER_DEFAULT);
749 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
753 /* Misc statistics. */
754 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq",
755 &stats->reset_brk_seq,
756 "Controller resets due to broken Rx sequnce number");
758 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
759 NULL, "ATE statistics");
760 parent = SYSCTL_CHILDREN(tree);
763 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
764 NULL, "Rx MAC statistics");
765 child = SYSCTL_CHILDREN(tree);
766 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
767 &stats->rx_frames, "Good frames");
768 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
769 &stats->rx_bcast_frames, "Good broadcast frames");
770 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
771 &stats->rx_mcast_frames, "Good multicast frames");
772 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
773 &stats->rx_pause_frames, "Pause control frames");
774 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
775 &stats->rx_control_frames, "Control frames");
776 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
777 &stats->rx_crcerrs, "CRC errors");
778 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
779 &stats->rx_lenerrs, "Frames with length mismatched");
780 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
781 &stats->rx_bytes, "Good octets");
782 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
783 &stats->rx_bcast_bytes, "Good broadcast octets");
784 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
785 &stats->rx_mcast_bytes, "Good multicast octets");
786 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts",
787 &stats->rx_runts, "Too short frames");
788 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments",
789 &stats->rx_fragments, "Fragmented frames");
790 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
791 &stats->rx_pkts_64, "64 bytes frames");
792 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
793 &stats->rx_pkts_65_127, "65 to 127 bytes frames");
794 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
795 &stats->rx_pkts_128_255, "128 to 255 bytes frames");
796 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
797 &stats->rx_pkts_256_511, "256 to 511 bytes frames");
798 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
799 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames");
800 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
801 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames");
802 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
803 &stats->rx_pkts_1519_max, "1519 to max frames");
804 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
805 &stats->rx_pkts_truncated, "Truncated frames due to MTU size");
806 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
807 &stats->rx_fifo_oflows, "FIFO overflows");
808 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs",
809 &stats->rx_rrs_errs, "Return status write-back errors");
810 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
811 &stats->rx_alignerrs, "Alignment errors");
812 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered",
813 &stats->rx_pkts_filtered,
814 "Frames dropped due to address filtering");
817 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
818 NULL, "Tx MAC statistics");
819 child = SYSCTL_CHILDREN(tree);
820 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
821 &stats->tx_frames, "Good frames");
822 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
823 &stats->tx_bcast_frames, "Good broadcast frames");
824 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
825 &stats->tx_mcast_frames, "Good multicast frames");
826 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
827 &stats->tx_pause_frames, "Pause control frames");
828 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
829 &stats->tx_control_frames, "Control frames");
830 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
831 &stats->tx_excess_defer, "Frames with excessive derferrals");
832 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers",
833 &stats->tx_excess_defer, "Frames with derferrals");
834 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
835 &stats->tx_bytes, "Good octets");
836 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
837 &stats->tx_bcast_bytes, "Good broadcast octets");
838 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
839 &stats->tx_mcast_bytes, "Good multicast octets");
840 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
841 &stats->tx_pkts_64, "64 bytes frames");
842 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
843 &stats->tx_pkts_65_127, "65 to 127 bytes frames");
844 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
845 &stats->tx_pkts_128_255, "128 to 255 bytes frames");
846 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
847 &stats->tx_pkts_256_511, "256 to 511 bytes frames");
848 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
849 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames");
850 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
851 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames");
852 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
853 &stats->tx_pkts_1519_max, "1519 to max frames");
854 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
855 &stats->tx_single_colls, "Single collisions");
856 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
857 &stats->tx_multi_colls, "Multiple collisions");
858 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
859 &stats->tx_late_colls, "Late collisions");
860 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls",
861 &stats->tx_excess_colls, "Excessive collisions");
862 ALE_SYSCTL_STAT_ADD32(ctx, child, "abort",
863 &stats->tx_abort, "Aborted frames due to Excessive collisions");
864 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns",
865 &stats->tx_underrun, "FIFO underruns");
866 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns",
867 &stats->tx_desc_underrun, "Descriptor write-back errors");
868 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
869 &stats->tx_lenerrs, "Frames with length mismatched");
870 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
871 &stats->tx_pkts_truncated, "Truncated frames due to MTU size");
874 #undef ALE_SYSCTL_STAT_ADD32
875 #undef ALE_SYSCTL_STAT_ADD64
877 struct ale_dmamap_arg {
878 bus_addr_t ale_busaddr;
882 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
884 struct ale_dmamap_arg *ctx;
889 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
891 ctx = (struct ale_dmamap_arg *)arg;
892 ctx->ale_busaddr = segs[0].ds_addr;
896 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register
897 * which specifies high address region of DMA blocks. Therefore these
898 * blocks should have the same high address of given 4GB address
899 * space(i.e. crossing 4GB boundary is not allowed).
902 ale_check_boundary(struct ale_softc *sc)
904 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end;
905 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end;
907 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr +
909 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr +
911 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ;
912 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ;
913 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ;
914 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ;
916 if ((ALE_ADDR_HI(tx_ring_end) !=
917 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) ||
918 (ALE_ADDR_HI(rx_page_end[0]) !=
919 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) ||
920 (ALE_ADDR_HI(rx_page_end[1]) !=
921 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) ||
922 (ALE_ADDR_HI(tx_cmb_end) !=
923 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) ||
924 (ALE_ADDR_HI(rx_cmb_end[0]) !=
925 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) ||
926 (ALE_ADDR_HI(rx_cmb_end[1]) !=
927 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr)))
930 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) ||
931 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) ||
932 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) ||
933 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) ||
934 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end)))
941 ale_dma_alloc(struct ale_softc *sc)
943 struct ale_txdesc *txd;
945 struct ale_dmamap_arg ctx;
946 int error, guard_size, i;
948 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0)
949 guard_size = ALE_JUMBO_FRAMELEN;
951 guard_size = ALE_MAX_FRAMELEN;
952 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ,
954 lowaddr = BUS_SPACE_MAXADDR;
956 /* Create parent DMA tag. */
957 error = bus_dma_tag_create(
959 1, 0, /* alignment, boundary */
960 lowaddr, /* lowaddr */
961 BUS_SPACE_MAXADDR, /* highaddr */
962 NULL, NULL, /* filter, filterarg */
963 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
965 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
967 &sc->ale_cdata.ale_parent_tag);
969 device_printf(sc->ale_dev,
970 "could not create parent DMA tag.\n");
974 /* Create DMA tag for Tx descriptor ring. */
975 error = bus_dma_tag_create(
976 sc->ale_cdata.ale_parent_tag, /* parent */
977 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */
978 BUS_SPACE_MAXADDR, /* lowaddr */
979 BUS_SPACE_MAXADDR, /* highaddr */
980 NULL, NULL, /* filter, filterarg */
981 ALE_TX_RING_SZ, /* maxsize */
983 ALE_TX_RING_SZ, /* maxsegsize */
985 &sc->ale_cdata.ale_tx_ring_tag);
987 device_printf(sc->ale_dev,
988 "could not create Tx ring DMA tag.\n");
992 /* Create DMA tag for Rx pages. */
993 for (i = 0; i < ALE_RX_PAGES; i++) {
994 error = bus_dma_tag_create(
995 sc->ale_cdata.ale_parent_tag, /* parent */
996 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */
997 BUS_SPACE_MAXADDR, /* lowaddr */
998 BUS_SPACE_MAXADDR, /* highaddr */
999 NULL, NULL, /* filter, filterarg */
1000 sc->ale_pagesize, /* maxsize */
1002 sc->ale_pagesize, /* maxsegsize */
1004 &sc->ale_cdata.ale_rx_page[i].page_tag);
1006 device_printf(sc->ale_dev,
1007 "could not create Rx page %d DMA tag.\n", i);
1012 /* Create DMA tag for Tx coalescing message block. */
1013 error = bus_dma_tag_create(
1014 sc->ale_cdata.ale_parent_tag, /* parent */
1015 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1016 BUS_SPACE_MAXADDR, /* lowaddr */
1017 BUS_SPACE_MAXADDR, /* highaddr */
1018 NULL, NULL, /* filter, filterarg */
1019 ALE_TX_CMB_SZ, /* maxsize */
1021 ALE_TX_CMB_SZ, /* maxsegsize */
1023 &sc->ale_cdata.ale_tx_cmb_tag);
1025 device_printf(sc->ale_dev,
1026 "could not create Tx CMB DMA tag.\n");
1030 /* Create DMA tag for Rx coalescing message block. */
1031 for (i = 0; i < ALE_RX_PAGES; i++) {
1032 error = bus_dma_tag_create(
1033 sc->ale_cdata.ale_parent_tag, /* parent */
1034 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1035 BUS_SPACE_MAXADDR, /* lowaddr */
1036 BUS_SPACE_MAXADDR, /* highaddr */
1037 NULL, NULL, /* filter, filterarg */
1038 ALE_RX_CMB_SZ, /* maxsize */
1040 ALE_RX_CMB_SZ, /* maxsegsize */
1042 &sc->ale_cdata.ale_rx_page[i].cmb_tag);
1044 device_printf(sc->ale_dev,
1045 "could not create Rx page %d CMB DMA tag.\n", i);
1050 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1051 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag,
1052 (void **)&sc->ale_cdata.ale_tx_ring,
1053 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1054 &sc->ale_cdata.ale_tx_ring_map);
1056 device_printf(sc->ale_dev,
1057 "could not allocate DMA'able memory for Tx ring.\n");
1060 ctx.ale_busaddr = 0;
1061 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag,
1062 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring,
1063 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0);
1064 if (error != 0 || ctx.ale_busaddr == 0) {
1065 device_printf(sc->ale_dev,
1066 "could not load DMA'able memory for Tx ring.\n");
1069 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr;
1072 for (i = 0; i < ALE_RX_PAGES; i++) {
1073 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag,
1074 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr,
1075 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1076 &sc->ale_cdata.ale_rx_page[i].page_map);
1078 device_printf(sc->ale_dev,
1079 "could not allocate DMA'able memory for "
1080 "Rx page %d.\n", i);
1083 ctx.ale_busaddr = 0;
1084 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag,
1085 sc->ale_cdata.ale_rx_page[i].page_map,
1086 sc->ale_cdata.ale_rx_page[i].page_addr,
1087 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0);
1088 if (error != 0 || ctx.ale_busaddr == 0) {
1089 device_printf(sc->ale_dev,
1090 "could not load DMA'able memory for "
1091 "Rx page %d.\n", i);
1094 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr;
1098 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag,
1099 (void **)&sc->ale_cdata.ale_tx_cmb,
1100 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1101 &sc->ale_cdata.ale_tx_cmb_map);
1103 device_printf(sc->ale_dev,
1104 "could not allocate DMA'able memory for Tx CMB.\n");
1107 ctx.ale_busaddr = 0;
1108 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag,
1109 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb,
1110 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1111 if (error != 0 || ctx.ale_busaddr == 0) {
1112 device_printf(sc->ale_dev,
1113 "could not load DMA'able memory for Tx CMB.\n");
1116 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr;
1119 for (i = 0; i < ALE_RX_PAGES; i++) {
1120 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1121 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr,
1122 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1123 &sc->ale_cdata.ale_rx_page[i].cmb_map);
1125 device_printf(sc->ale_dev, "could not allocate "
1126 "DMA'able memory for Rx page %d CMB.\n", i);
1129 ctx.ale_busaddr = 0;
1130 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1131 sc->ale_cdata.ale_rx_page[i].cmb_map,
1132 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1133 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1134 if (error != 0 || ctx.ale_busaddr == 0) {
1135 device_printf(sc->ale_dev, "could not load DMA'able "
1136 "memory for Rx page %d CMB.\n", i);
1139 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr;
1143 * Tx descriptors/RXF0/CMB DMA blocks share the same
1144 * high address region of 64bit DMA address space.
1146 if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1147 (error = ale_check_boundary(sc)) != 0) {
1148 device_printf(sc->ale_dev, "4GB boundary crossed, "
1149 "switching to 32bit DMA addressing mode.\n");
1152 * Limit max allowable DMA address space to 32bit
1155 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1160 * Create Tx buffer parent tag.
1161 * AR81xx allows 64bit DMA addressing of Tx buffers so it
1162 * needs separate parent DMA tag as parent DMA address space
1163 * could be restricted to be within 32bit address space by
1164 * 4GB boundary crossing.
1166 error = bus_dma_tag_create(
1168 1, 0, /* alignment, boundary */
1169 BUS_SPACE_MAXADDR, /* lowaddr */
1170 BUS_SPACE_MAXADDR, /* highaddr */
1171 NULL, NULL, /* filter, filterarg */
1172 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1174 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1176 &sc->ale_cdata.ale_buffer_tag);
1178 device_printf(sc->ale_dev,
1179 "could not create parent buffer DMA tag.\n");
1183 /* Create DMA tag for Tx buffers. */
1184 error = bus_dma_tag_create(
1185 sc->ale_cdata.ale_buffer_tag, /* parent */
1186 1, 0, /* alignment, boundary */
1187 BUS_SPACE_MAXADDR, /* lowaddr */
1188 BUS_SPACE_MAXADDR, /* highaddr */
1189 NULL, NULL, /* filter, filterarg */
1190 ALE_TSO_MAXSIZE, /* maxsize */
1191 ALE_MAXTXSEGS, /* nsegments */
1192 ALE_TSO_MAXSEGSIZE, /* maxsegsize */
1194 &sc->ale_cdata.ale_tx_tag);
1196 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n");
1200 /* Create DMA maps for Tx buffers. */
1201 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1202 txd = &sc->ale_cdata.ale_txdesc[i];
1204 txd->tx_dmamap = NULL;
1205 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0,
1208 device_printf(sc->ale_dev,
1209 "could not create Tx dmamap.\n");
1218 ale_dma_free(struct ale_softc *sc)
1220 struct ale_txdesc *txd;
1224 if (sc->ale_cdata.ale_tx_tag != NULL) {
1225 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1226 txd = &sc->ale_cdata.ale_txdesc[i];
1227 if (txd->tx_dmamap != NULL) {
1228 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag,
1230 txd->tx_dmamap = NULL;
1233 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag);
1234 sc->ale_cdata.ale_tx_tag = NULL;
1236 /* Tx descriptor ring. */
1237 if (sc->ale_cdata.ale_tx_ring_tag != NULL) {
1238 if (sc->ale_cdata.ale_tx_ring_map != NULL)
1239 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag,
1240 sc->ale_cdata.ale_tx_ring_map);
1241 if (sc->ale_cdata.ale_tx_ring_map != NULL &&
1242 sc->ale_cdata.ale_tx_ring != NULL)
1243 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag,
1244 sc->ale_cdata.ale_tx_ring,
1245 sc->ale_cdata.ale_tx_ring_map);
1246 sc->ale_cdata.ale_tx_ring = NULL;
1247 sc->ale_cdata.ale_tx_ring_map = NULL;
1248 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag);
1249 sc->ale_cdata.ale_tx_ring_tag = NULL;
1251 /* Rx page block. */
1252 for (i = 0; i < ALE_RX_PAGES; i++) {
1253 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) {
1254 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL)
1256 sc->ale_cdata.ale_rx_page[i].page_tag,
1257 sc->ale_cdata.ale_rx_page[i].page_map);
1258 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL &&
1259 sc->ale_cdata.ale_rx_page[i].page_addr != NULL)
1261 sc->ale_cdata.ale_rx_page[i].page_tag,
1262 sc->ale_cdata.ale_rx_page[i].page_addr,
1263 sc->ale_cdata.ale_rx_page[i].page_map);
1264 sc->ale_cdata.ale_rx_page[i].page_addr = NULL;
1265 sc->ale_cdata.ale_rx_page[i].page_map = NULL;
1266 bus_dma_tag_destroy(
1267 sc->ale_cdata.ale_rx_page[i].page_tag);
1268 sc->ale_cdata.ale_rx_page[i].page_tag = NULL;
1272 for (i = 0; i < ALE_RX_PAGES; i++) {
1273 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) {
1274 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL)
1276 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1277 sc->ale_cdata.ale_rx_page[i].cmb_map);
1278 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL &&
1279 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL)
1281 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1282 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1283 sc->ale_cdata.ale_rx_page[i].cmb_map);
1284 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL;
1285 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL;
1286 bus_dma_tag_destroy(
1287 sc->ale_cdata.ale_rx_page[i].cmb_tag);
1288 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL;
1292 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) {
1293 if (sc->ale_cdata.ale_tx_cmb_map != NULL)
1294 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag,
1295 sc->ale_cdata.ale_tx_cmb_map);
1296 if (sc->ale_cdata.ale_tx_cmb_map != NULL &&
1297 sc->ale_cdata.ale_tx_cmb != NULL)
1298 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag,
1299 sc->ale_cdata.ale_tx_cmb,
1300 sc->ale_cdata.ale_tx_cmb_map);
1301 sc->ale_cdata.ale_tx_cmb = NULL;
1302 sc->ale_cdata.ale_tx_cmb_map = NULL;
1303 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag);
1304 sc->ale_cdata.ale_tx_cmb_tag = NULL;
1306 if (sc->ale_cdata.ale_buffer_tag != NULL) {
1307 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag);
1308 sc->ale_cdata.ale_buffer_tag = NULL;
1310 if (sc->ale_cdata.ale_parent_tag != NULL) {
1311 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag);
1312 sc->ale_cdata.ale_parent_tag = NULL;
1317 ale_shutdown(device_t dev)
1319 return (ale_suspend(dev));
1325 * Note, this driver resets the link speed to 10/100Mbps by
1326 * restarting auto-negotiation in suspend/shutdown phase but we
1327 * don't know whether that auto-negotiation would succeed or not
1328 * as driver has no control after powering off/suspend operation.
1329 * If the renegotiation fail WOL may not work. Running at 1Gbps
1330 * will draw more power than 375mA at 3.3V which is specified in
1331 * PCI specification and that would result in complete
1332 * shutdowning power to ethernet controller.
1335 * Save current negotiated media speed/duplex/flow-control to
1336 * softc and restore the same link again after resuming. PHY
1337 * handling such as power down/resetting to 100Mbps may be better
1338 * handled in suspend method in phy driver.
1341 ale_setlinkspeed(struct ale_softc *sc)
1343 struct mii_data *mii;
1346 mii = device_get_softc(sc->ale_miibus);
1349 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1350 (IFM_ACTIVE | IFM_AVALID)) {
1351 switch IFM_SUBTYPE(mii->mii_media_active) {
1362 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0);
1363 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1364 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1365 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1366 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1370 * Poll link state until ale(4) get a 10/100Mbps link.
1372 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1374 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
1375 == (IFM_ACTIVE | IFM_AVALID)) {
1376 switch (IFM_SUBTYPE(
1377 mii->mii_media_active)) {
1387 pause("alelnk", hz);
1390 if (i == MII_ANEGTICKS_GIGE)
1391 device_printf(sc->ale_dev,
1392 "establishing a link failed, WOL may not work!");
1395 * No link, force MAC to have 100Mbps, full-duplex link.
1396 * This is the last resort and may/may not work.
1398 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1399 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1404 ale_setwol(struct ale_softc *sc)
1411 ALE_LOCK_ASSERT(sc);
1413 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) != 0) {
1415 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
1416 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1417 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1418 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1419 /* Force PHY power down. */
1420 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1421 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1422 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON |
1423 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ |
1424 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW);
1429 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1430 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
1431 ale_setlinkspeed(sc);
1435 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1436 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1437 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs);
1438 reg = CSR_READ_4(sc, ALE_MAC_CFG);
1439 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
1441 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
1442 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1443 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1444 reg |= MAC_CFG_RX_ENB;
1445 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1447 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1448 /* WOL disabled, PHY power down. */
1449 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1450 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1451 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1452 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1453 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1454 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
1455 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS |
1456 GPHY_CTRL_PWDOWN_HW);
1459 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2);
1460 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1461 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1462 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1463 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1469 ale_suspend(device_t dev)
1471 struct ale_softc *sc = device_get_softc(dev);
1472 struct ifnet *ifp = &sc->arpcom.ac_if;
1474 lwkt_serialize_enter(ifp->if_serializer);
1479 lwkt_serialize_exit(ifp->if_serializer);
1484 ale_resume(device_t dev)
1486 struct ale_softc *sc = device_get_softc(dev);
1487 struct ifnet *ifp = &sc->arpcom.ac_if;
1490 lwkt_serialize_enter(ifp->if_serializer);
1493 * Clear INTx emulation disable for hardwares that
1494 * is set in resume event. From Linux.
1496 cmd = pci_read_config(sc->ale_dev, PCIR_COMMAND, 2);
1497 if ((cmd & 0x0400) != 0) {
1499 pci_write_config(sc->ale_dev, PCIR_COMMAND, cmd, 2);
1503 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) == 0) {
1507 /* Disable PME and clear PME status. */
1508 pmstat = pci_read_config(sc->ale_dev,
1509 pmc + PCIR_POWER_STATUS, 2);
1510 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
1511 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1512 pci_write_config(sc->ale_dev,
1513 pmc + PCIR_POWER_STATUS, pmstat, 2);
1520 if ((ifp->if_flags & IFF_UP) != 0)
1523 lwkt_serialize_exit(ifp->if_serializer);
1528 ale_encap(struct ale_softc *sc, struct mbuf **m_head)
1530 struct ale_txdesc *txd, *txd_last;
1531 struct tx_desc *desc;
1533 bus_dma_segment_t txsegs[ALE_MAXTXSEGS];
1534 struct ale_dmamap_ctx ctx;
1536 uint32_t cflags, poff, vtag;
1537 int error, i, nsegs, prod, si;
1539 M_ASSERTPKTHDR((*m_head));
1545 si = prod = sc->ale_cdata.ale_tx_prod;
1546 txd = &sc->ale_cdata.ale_txdesc[prod];
1548 map = txd->tx_dmamap;
1550 ctx.nsegs = ALE_MAXTXSEGS;
1552 error = bus_dmamap_load_mbuf(sc->ale_cdata.ale_tx_tag, map,
1553 *m_head, ale_dmamap_buf_cb, &ctx,
1555 if (error == EFBIG) {
1556 m = m_defrag(*m_head, MB_DONTWAIT);
1564 ctx.nsegs = ALE_MAXTXSEGS;
1566 error = bus_dmamap_load_mbuf(sc->ale_cdata.ale_tx_tag, map,
1567 *m_head, ale_dmamap_buf_cb, &ctx,
1574 } else if (error != 0) {
1585 /* Check descriptor overrun. */
1586 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 2) {
1587 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map);
1590 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE);
1593 /* Configure Tx checksum offload. */
1594 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) {
1596 * AR81xx supports Tx custom checksum offload feature
1597 * that offloads single 16bit checksum computation.
1598 * So you can choose one among IP, TCP and UDP.
1599 * Normally driver sets checksum start/insertion
1600 * position from the information of TCP/UDP frame as
1601 * TCP/UDP checksum takes more time than that of IP.
1602 * However it seems that custom checksum offload
1603 * requires 4 bytes aligned Tx buffers due to hardware
1605 * AR81xx also supports explicit Tx checksum computation
1606 * if it is told that the size of IP header and TCP
1607 * header(for UDP, the header size does not matter
1608 * because it's fixed length). However with this scheme
1609 * TSO does not work so you have to choose one either
1610 * TSO or explicit Tx checksum offload. I chosen TSO
1611 * plus custom checksum offload with work-around which
1612 * will cover most common usage for this consumer
1613 * ethernet controller. The work-around takes a lot of
1614 * CPU cycles if Tx buffer is not aligned on 4 bytes
1617 cflags |= ALE_TD_CXSUM;
1618 /* Set checksum start offset. */
1619 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT);
1620 /* Set checksum insertion position of TCP/UDP. */
1621 cflags |= ((poff + m->m_pkthdr.csum_data) <<
1622 ALE_TD_CSUM_XSUMOFFSET_SHIFT);
1625 /* Configure VLAN hardware tag insertion. */
1626 if ((m->m_flags & M_VLANTAG) != 0) {
1627 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vlantag);
1628 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK);
1629 cflags |= ALE_TD_INSERT_VLAN_TAG;
1633 for (i = 0; i < nsegs; i++) {
1634 desc = &sc->ale_cdata.ale_tx_ring[prod];
1635 desc->addr = htole64(txsegs[i].ds_addr);
1636 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag);
1637 desc->flags = htole32(cflags);
1638 sc->ale_cdata.ale_tx_cnt++;
1639 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1641 /* Update producer index. */
1642 sc->ale_cdata.ale_tx_prod = prod;
1644 /* Finally set EOP on the last descriptor. */
1645 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT;
1646 desc = &sc->ale_cdata.ale_tx_ring[prod];
1647 desc->flags |= htole32(ALE_TD_EOP);
1649 /* Swap dmamap of the first and the last. */
1650 txd = &sc->ale_cdata.ale_txdesc[prod];
1651 map = txd_last->tx_dmamap;
1652 txd_last->tx_dmamap = txd->tx_dmamap;
1653 txd->tx_dmamap = map;
1656 /* Sync descriptors. */
1657 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
1658 sc->ale_cdata.ale_tx_ring_map, BUS_DMASYNC_PREWRITE);
1664 ale_start(struct ifnet *ifp)
1666 struct ale_softc *sc = ifp->if_softc;
1667 struct mbuf *m_head;
1670 ASSERT_SERIALIZED(ifp->if_serializer);
1672 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) {
1673 ifq_purge(&ifp->if_snd);
1677 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1680 /* Reclaim transmitted frames. */
1681 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT)
1685 while (!ifq_is_empty(&ifp->if_snd)) {
1686 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1691 * Pack the data into the transmit ring. If we
1692 * don't have room, set the OACTIVE flag and wait
1693 * for the NIC to drain the ring.
1695 if (ale_encap(sc, &m_head)) {
1698 ifq_prepend(&ifp->if_snd, m_head);
1699 ifp->if_flags |= IFF_OACTIVE;
1705 * If there's a BPF listener, bounce a copy of this frame
1708 ETHER_BPF_MTAP(ifp, m_head);
1713 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX,
1714 sc->ale_cdata.ale_tx_prod);
1716 /* Set a timeout in case the chip goes out to lunch. */
1717 ifp->if_timer = ALE_TX_TIMEOUT;
1722 ale_watchdog(struct ifnet *ifp)
1724 struct ale_softc *sc = ifp->if_softc;
1726 ASSERT_SERIALIZED(ifp->if_serializer);
1728 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) {
1729 if_printf(ifp, "watchdog timeout (lost link)\n");
1735 if_printf(ifp, "watchdog timeout -- resetting\n");
1739 if (!ifq_is_empty(&ifp->if_snd))
1744 ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1746 struct ale_softc *sc;
1748 struct mii_data *mii;
1751 ASSERT_SERIALIZED(ifp->if_serializer);
1754 ifr = (struct ifreq *)data;
1759 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU ||
1760 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 &&
1761 ifr->ifr_mtu > ETHERMTU))
1763 else if (ifp->if_mtu != ifr->ifr_mtu) {
1764 ifp->if_mtu = ifr->ifr_mtu;
1765 if ((ifp->if_flags & IFF_RUNNING) != 0)
1771 if ((ifp->if_flags & IFF_UP) != 0) {
1772 if ((ifp->if_flags & IFF_RUNNING) != 0) {
1773 if (((ifp->if_flags ^ sc->ale_if_flags)
1774 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1777 if ((sc->ale_flags & ALE_FLAG_DETACH) == 0)
1781 if ((ifp->if_flags & IFF_RUNNING) != 0)
1784 sc->ale_if_flags = ifp->if_flags;
1789 if ((ifp->if_flags & IFF_RUNNING) != 0)
1795 mii = device_get_softc(sc->ale_miibus);
1796 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1800 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1801 if ((mask & IFCAP_TXCSUM) != 0 &&
1802 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
1803 ifp->if_capenable ^= IFCAP_TXCSUM;
1804 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1805 ifp->if_hwassist |= ALE_CSUM_FEATURES;
1807 ifp->if_hwassist &= ~ALE_CSUM_FEATURES;
1809 if ((mask & IFCAP_RXCSUM) != 0 &&
1810 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
1811 ifp->if_capenable ^= IFCAP_RXCSUM;
1813 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1814 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
1815 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1821 error = ether_ioctl(ifp, cmd, data);
1828 ale_mac_config(struct ale_softc *sc)
1830 struct mii_data *mii;
1833 mii = device_get_softc(sc->ale_miibus);
1834 reg = CSR_READ_4(sc, ALE_MAC_CFG);
1835 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
1836 MAC_CFG_SPEED_MASK);
1837 /* Reprogram MAC with resolved speed/duplex. */
1838 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1841 reg |= MAC_CFG_SPEED_10_100;
1844 reg |= MAC_CFG_SPEED_1000;
1847 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1848 reg |= MAC_CFG_FULL_DUPLEX;
1850 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1851 reg |= MAC_CFG_TX_FC;
1852 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1853 reg |= MAC_CFG_RX_FC;
1856 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1860 ale_stats_clear(struct ale_softc *sc)
1866 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
1867 CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
1868 i += sizeof(uint32_t);
1870 /* Read Tx statistics. */
1871 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
1872 CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
1873 i += sizeof(uint32_t);
1878 ale_stats_update(struct ale_softc *sc)
1880 struct ale_hw_stats *stat;
1881 struct smb sb, *smb;
1886 ifp = &sc->arpcom.ac_if;
1887 stat = &sc->ale_stats;
1890 /* Read Rx statistics. */
1891 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
1892 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
1893 i += sizeof(uint32_t);
1895 /* Read Tx statistics. */
1896 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
1897 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
1898 i += sizeof(uint32_t);
1902 stat->rx_frames += smb->rx_frames;
1903 stat->rx_bcast_frames += smb->rx_bcast_frames;
1904 stat->rx_mcast_frames += smb->rx_mcast_frames;
1905 stat->rx_pause_frames += smb->rx_pause_frames;
1906 stat->rx_control_frames += smb->rx_control_frames;
1907 stat->rx_crcerrs += smb->rx_crcerrs;
1908 stat->rx_lenerrs += smb->rx_lenerrs;
1909 stat->rx_bytes += smb->rx_bytes;
1910 stat->rx_runts += smb->rx_runts;
1911 stat->rx_fragments += smb->rx_fragments;
1912 stat->rx_pkts_64 += smb->rx_pkts_64;
1913 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
1914 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
1915 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
1916 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
1917 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
1918 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
1919 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
1920 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
1921 stat->rx_rrs_errs += smb->rx_rrs_errs;
1922 stat->rx_alignerrs += smb->rx_alignerrs;
1923 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
1924 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
1925 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
1928 stat->tx_frames += smb->tx_frames;
1929 stat->tx_bcast_frames += smb->tx_bcast_frames;
1930 stat->tx_mcast_frames += smb->tx_mcast_frames;
1931 stat->tx_pause_frames += smb->tx_pause_frames;
1932 stat->tx_excess_defer += smb->tx_excess_defer;
1933 stat->tx_control_frames += smb->tx_control_frames;
1934 stat->tx_deferred += smb->tx_deferred;
1935 stat->tx_bytes += smb->tx_bytes;
1936 stat->tx_pkts_64 += smb->tx_pkts_64;
1937 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
1938 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
1939 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
1940 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
1941 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
1942 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
1943 stat->tx_single_colls += smb->tx_single_colls;
1944 stat->tx_multi_colls += smb->tx_multi_colls;
1945 stat->tx_late_colls += smb->tx_late_colls;
1946 stat->tx_excess_colls += smb->tx_excess_colls;
1947 stat->tx_abort += smb->tx_abort;
1948 stat->tx_underrun += smb->tx_underrun;
1949 stat->tx_desc_underrun += smb->tx_desc_underrun;
1950 stat->tx_lenerrs += smb->tx_lenerrs;
1951 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
1952 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
1953 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
1955 /* Update counters in ifnet. */
1956 ifp->if_opackets += smb->tx_frames;
1958 ifp->if_collisions += smb->tx_single_colls +
1959 smb->tx_multi_colls * 2 + smb->tx_late_colls +
1960 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT;
1964 * tx_pkts_truncated counter looks suspicious. It constantly
1965 * increments with no sign of Tx errors. This may indicate
1966 * the counter name is not correct one so I've removed the
1967 * counter in output errors.
1969 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls +
1972 ifp->if_ipackets += smb->rx_frames;
1974 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs +
1975 smb->rx_runts + smb->rx_pkts_truncated +
1976 smb->rx_fifo_oflows + smb->rx_rrs_errs +
1983 struct ale_softc *sc = xsc;
1984 struct ifnet *ifp = &sc->arpcom.ac_if;
1987 ASSERT_SERIALIZED(ifp->if_serializer);
1989 status = CSR_READ_4(sc, ALE_INTR_STATUS);
1990 if ((status & ALE_INTRS) == 0)
1993 /* Acknowledge and disable interrupts. */
1994 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT);
1996 if ((ifp->if_flags & IFF_RUNNING) != 0) {
1999 error = ale_rxeof(sc);
2001 sc->ale_stats.reset_brk_seq++;
2006 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
2007 if ((status & INTR_DMA_RD_TO_RST) != 0)
2008 device_printf(sc->ale_dev,
2009 "DMA read error! -- resetting\n");
2010 if ((status & INTR_DMA_WR_TO_RST) != 0)
2011 device_printf(sc->ale_dev,
2012 "DMA write error! -- resetting\n");
2018 if (!ifq_is_empty(&ifp->if_snd))
2022 /* Re-enable interrupts. */
2023 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF);
2027 ale_txeof(struct ale_softc *sc)
2029 struct ifnet *ifp = &sc->arpcom.ac_if;
2030 struct ale_txdesc *txd;
2031 uint32_t cons, prod;
2034 if (sc->ale_cdata.ale_tx_cnt == 0)
2037 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2038 sc->ale_cdata.ale_tx_ring_map, BUS_DMASYNC_POSTREAD);
2039 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) {
2040 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2041 sc->ale_cdata.ale_tx_cmb_map, BUS_DMASYNC_POSTREAD);
2042 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK;
2044 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX);
2045 cons = sc->ale_cdata.ale_tx_cons;
2047 * Go through our Tx list and free mbufs for those
2048 * frames which have been transmitted.
2050 for (prog = 0; cons != prod; prog++,
2051 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) {
2052 if (sc->ale_cdata.ale_tx_cnt <= 0)
2055 ifp->if_flags &= ~IFF_OACTIVE;
2056 sc->ale_cdata.ale_tx_cnt--;
2057 txd = &sc->ale_cdata.ale_txdesc[cons];
2058 if (txd->tx_m != NULL) {
2059 /* Reclaim transmitted mbufs. */
2060 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2068 sc->ale_cdata.ale_tx_cons = cons;
2070 * Unarm watchdog timer only when there is no pending
2071 * Tx descriptors in queue.
2073 if (sc->ale_cdata.ale_tx_cnt == 0)
2079 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page,
2080 uint32_t length, uint32_t *prod)
2082 struct ale_rx_page *rx_page;
2085 /* Update consumer position. */
2086 rx_page->cons += roundup(length + sizeof(struct rx_rs),
2088 if (rx_page->cons >= ALE_RX_PAGE_SZ) {
2090 * End of Rx page reached, let hardware reuse
2094 *rx_page->cmb_addr = 0;
2095 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2096 BUS_DMASYNC_PREWRITE);
2097 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp,
2099 /* Switch to alternate Rx page. */
2100 sc->ale_cdata.ale_rx_curp ^= 1;
2102 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2103 /* Page flipped, sync CMB and Rx page. */
2104 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2105 BUS_DMASYNC_POSTREAD);
2106 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2107 BUS_DMASYNC_POSTREAD);
2108 /* Sync completed, cache updated producer index. */
2109 *prod = *rx_page->cmb_addr;
2115 * It seems that AR81xx controller can compute partial checksum.
2116 * The partial checksum value can be used to accelerate checksum
2117 * computation for fragmented TCP/UDP packets. Upper network stack
2118 * already takes advantage of the partial checksum value in IP
2119 * reassembly stage. But I'm not sure the correctness of the
2120 * partial hardware checksum assistance due to lack of data sheet.
2121 * In addition, the Rx feature of controller that requires copying
2122 * for every frames effectively nullifies one of most nice offload
2123 * capability of controller.
2126 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status)
2128 struct ifnet *ifp = &sc->arpcom.ac_if;
2132 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2133 if ((status & ALE_RD_IPCSUM_NOK) == 0)
2134 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2136 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) {
2137 if (((status & ALE_RD_IPV4_FRAG) == 0) &&
2138 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) &&
2139 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) {
2140 m->m_pkthdr.csum_flags |=
2141 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2142 m->m_pkthdr.csum_data = 0xffff;
2145 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 &&
2146 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) {
2147 p = mtod(m, char *);
2149 if ((status & ALE_RD_802_3) != 0)
2150 p += LLC_SNAPFRAMELEN;
2151 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 &&
2152 (status & ALE_RD_VLAN) != 0)
2154 ip = (struct ip *)p;
2155 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0)
2157 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2159 m->m_pkthdr.csum_data = 0xffff;
2163 * Don't mark bad checksum for TCP/UDP frames
2164 * as fragmented frames may always have set
2165 * bad checksummed bit of frame status.
2169 /* Process received frames. */
2171 ale_rxeof(struct ale_softc *sc)
2173 struct ifnet *ifp = &sc->arpcom.ac_if;
2174 struct ale_rx_page *rx_page;
2177 uint32_t length, prod, seqno, status, vtags;
2180 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2181 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2182 BUS_DMASYNC_POSTREAD);
2183 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2184 BUS_DMASYNC_POSTREAD);
2186 * Don't directly access producer index as hardware may
2187 * update it while Rx handler is in progress. It would
2188 * be even better if there is a way to let hardware
2189 * know how far driver processed its received frames.
2190 * Alternatively, hardware could provide a way to disable
2191 * CMB updates until driver acknowledges the end of CMB
2194 prod = *rx_page->cmb_addr;
2195 for (prog = 0; ; prog++) {
2196 if (rx_page->cons >= prod)
2198 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons);
2199 seqno = ALE_RX_SEQNO(le32toh(rs->seqno));
2200 if (sc->ale_cdata.ale_rx_seqno != seqno) {
2202 * Normally I believe this should not happen unless
2203 * severe driver bug or corrupted memory. However
2204 * it seems to happen under certain conditions which
2205 * is triggered by abrupt Rx events such as initiation
2206 * of bulk transfer of remote host. It's not easy to
2207 * reproduce this and I doubt it could be related
2208 * with FIFO overflow of hardware or activity of Tx
2209 * CMB updates. I also remember similar behaviour
2210 * seen on RealTek 8139 which uses resembling Rx
2214 device_printf(sc->ale_dev,
2215 "garbled seq: %u, expected: %u -- "
2216 "resetting!\n", seqno,
2217 sc->ale_cdata.ale_rx_seqno);
2220 /* Frame received. */
2221 sc->ale_cdata.ale_rx_seqno++;
2222 length = ALE_RX_BYTES(le32toh(rs->length));
2223 status = le32toh(rs->flags);
2224 if ((status & ALE_RD_ERROR) != 0) {
2226 * We want to pass the following frames to upper
2227 * layer regardless of error status of Rx return
2230 * o IP/TCP/UDP checksum is bad.
2231 * o frame length and protocol specific length
2234 if ((status & (ALE_RD_CRC | ALE_RD_CODE |
2235 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW |
2236 ALE_RD_TRUNC)) != 0) {
2237 ale_rx_update_page(sc, &rx_page, length, &prod);
2242 * m_devget(9) is major bottle-neck of ale(4)(It comes
2243 * from hardware limitation). For jumbo frames we could
2244 * get a slightly better performance if driver use
2245 * m_getjcl(9) with proper buffer size argument. However
2246 * that would make code more complicated and I don't
2247 * think users would expect good Rx performance numbers
2248 * on these low-end consumer ethernet controller.
2250 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN,
2251 ETHER_ALIGN, ifp, NULL);
2254 ale_rx_update_page(sc, &rx_page, length, &prod);
2257 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
2258 (status & ALE_RD_IPV4) != 0)
2259 ale_rxcsum(sc, m, status);
2260 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2261 (status & ALE_RD_VLAN) != 0) {
2262 vtags = ALE_RX_VLAN(le32toh(rs->vtags));
2263 m->m_pkthdr.ether_vlantag = ALE_RX_VLAN_TAG(vtags);
2264 m->m_flags |= M_VLANTAG;
2267 /* Pass it to upper layer. */
2268 ifp->if_input(ifp, m);
2270 ale_rx_update_page(sc, &rx_page, length, &prod);
2278 struct ale_softc *sc = xsc;
2279 struct ifnet *ifp = &sc->arpcom.ac_if;
2280 struct mii_data *mii;
2282 lwkt_serialize_enter(ifp->if_serializer);
2284 mii = device_get_softc(sc->ale_miibus);
2286 ale_stats_update(sc);
2288 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2290 lwkt_serialize_exit(ifp->if_serializer);
2294 ale_reset(struct ale_softc *sc)
2299 /* Initialize PCIe module. From Linux. */
2300 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2302 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET);
2303 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2305 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0)
2309 device_printf(sc->ale_dev, "master reset timeout!\n");
2311 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2312 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)
2318 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg);
2324 struct ale_softc *sc = xsc;
2325 struct ifnet *ifp = &sc->arpcom.ac_if;
2326 struct mii_data *mii;
2327 uint8_t eaddr[ETHER_ADDR_LEN];
2329 uint32_t reg, rxf_hi, rxf_lo;
2331 ASSERT_SERIALIZED(ifp->if_serializer);
2333 mii = device_get_softc(sc->ale_miibus);
2336 * Cancel any pending I/O.
2341 * Reset the chip to a known state.
2345 /* Initialize Tx descriptors, DMA memory blocks. */
2346 ale_init_rx_pages(sc);
2347 ale_init_tx_ring(sc);
2349 /* Reprogram the station address. */
2350 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2351 CSR_WRITE_4(sc, ALE_PAR0,
2352 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2353 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]);
2356 * Clear WOL status and disable all WOL feature as WOL
2357 * would interfere Rx operation under normal environments.
2359 CSR_READ_4(sc, ALE_WOL_CFG);
2360 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
2363 * Set Tx descriptor/RXF0/CMB base addresses. They share
2364 * the same high address part of DMAable region.
2366 paddr = sc->ale_cdata.ale_tx_ring_paddr;
2367 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr));
2368 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr));
2369 CSR_WRITE_4(sc, ALE_TPD_CNT,
2370 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK);
2372 /* Set Rx page base address, note we use single queue. */
2373 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr;
2374 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr));
2375 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr;
2376 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr));
2378 /* Set Tx/Rx CMB addresses. */
2379 paddr = sc->ale_cdata.ale_tx_cmb_paddr;
2380 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr));
2381 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr;
2382 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr));
2383 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr;
2384 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr));
2386 /* Mark RXF0 is valid. */
2387 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID);
2388 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID);
2390 * No need to initialize RFX1/RXF2/RXF3. We don't use
2394 /* Set Rx page size, excluding guard frame size. */
2395 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ);
2397 /* Tell hardware that we're ready to load DMA blocks. */
2398 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD);
2400 /* Set Rx/Tx interrupt trigger threshold. */
2401 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) |
2402 (4 << INT_TRIG_TX_THRESH_SHIFT));
2405 * Set interrupt trigger timer, its purpose and relation
2406 * with interrupt moderation mechanism is not clear yet.
2408 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER,
2409 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) |
2410 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT)));
2412 /* Configure interrupt moderation timer. */
2413 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT;
2414 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT;
2415 CSR_WRITE_4(sc, ALE_IM_TIMER, reg);
2416 reg = CSR_READ_4(sc, ALE_MASTER_CFG);
2417 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
2418 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
2419 if (ALE_USECS(sc->ale_int_rx_mod) != 0)
2420 reg |= MASTER_IM_RX_TIMER_ENB;
2421 if (ALE_USECS(sc->ale_int_tx_mod) != 0)
2422 reg |= MASTER_IM_TX_TIMER_ENB;
2423 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg);
2424 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000));
2426 /* Set Maximum frame size of controller. */
2427 if (ifp->if_mtu < ETHERMTU)
2428 sc->ale_max_frame_size = ETHERMTU;
2430 sc->ale_max_frame_size = ifp->if_mtu;
2431 sc->ale_max_frame_size += ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN;
2432 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size);
2434 /* Configure IPG/IFG parameters. */
2435 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG,
2436 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) |
2437 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
2438 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
2439 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK));
2441 /* Set parameters for half-duplex media. */
2442 CSR_WRITE_4(sc, ALE_HDPX_CFG,
2443 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2444 HDPX_CFG_LCOL_MASK) |
2445 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2446 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2447 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2448 HDPX_CFG_ABEBT_MASK) |
2449 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2450 HDPX_CFG_JAMIPG_MASK));
2452 /* Configure Tx jumbo frame parameters. */
2453 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2454 if (ifp->if_mtu < ETHERMTU)
2455 reg = sc->ale_max_frame_size;
2456 else if (ifp->if_mtu < 6 * 1024)
2457 reg = (sc->ale_max_frame_size * 2) / 3;
2459 reg = sc->ale_max_frame_size / 2;
2460 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH,
2461 roundup(reg, TX_JUMBO_THRESH_UNIT) >>
2462 TX_JUMBO_THRESH_UNIT_SHIFT);
2465 /* Configure TxQ. */
2466 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT))
2467 << TXQ_CFG_TX_FIFO_BURST_SHIFT;
2468 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2469 TXQ_CFG_TPD_BURST_MASK;
2470 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB);
2472 /* Configure Rx jumbo frame & flow control parameters. */
2473 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2474 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT);
2475 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH,
2476 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) <<
2477 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) |
2478 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) &
2479 RX_JUMBO_LKAH_MASK));
2480 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
2481 rxf_hi = (reg * 7) / 10;
2482 rxf_lo = (reg * 3)/ 10;
2483 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH,
2484 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
2485 RX_FIFO_PAUSE_THRESH_LO_MASK) |
2486 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
2487 RX_FIFO_PAUSE_THRESH_HI_MASK));
2491 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0);
2492 CSR_WRITE_4(sc, ALE_RSS_CPU, 0);
2494 /* Configure RxQ. */
2495 CSR_WRITE_4(sc, ALE_RXQ_CFG,
2496 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
2498 /* Configure DMA parameters. */
2500 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0)
2501 reg |= DMA_CFG_TXCMB_ENB;
2502 CSR_WRITE_4(sc, ALE_DMA_CFG,
2503 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 |
2504 sc->ale_dma_rd_burst | reg |
2505 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB |
2506 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
2507 DMA_CFG_RD_DELAY_CNT_MASK) |
2508 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
2509 DMA_CFG_WR_DELAY_CNT_MASK));
2512 * Hardware can be configured to issue SMB interrupt based
2513 * on programmed interval. Since there is a callout that is
2514 * invoked for every hz in driver we use that instead of
2515 * relying on periodic SMB interrupt.
2517 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0));
2519 /* Clear MAC statistics. */
2520 ale_stats_clear(sc);
2523 * Configure Tx/Rx MACs.
2524 * - Auto-padding for short frames.
2525 * - Enable CRC generation.
2526 * Actual reconfiguration of MAC for resolved speed/duplex
2527 * is followed after detection of link establishment.
2528 * AR81xx always does checksum computation regardless of
2529 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will
2530 * cause Rx handling issue for fragmented IP datagrams due
2533 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
2534 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
2535 MAC_CFG_PREAMBLE_MASK);
2536 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0)
2537 reg |= MAC_CFG_SPEED_10_100;
2539 reg |= MAC_CFG_SPEED_1000;
2540 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2542 /* Set up the receive filter. */
2546 /* Acknowledge all pending interrupts and clear it. */
2547 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS);
2548 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2549 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0);
2551 sc->ale_flags &= ~ALE_FLAG_LINK;
2553 /* Switch to the current media. */
2556 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2558 ifp->if_flags |= IFF_RUNNING;
2559 ifp->if_flags &= ~IFF_OACTIVE;
2563 ale_stop(struct ale_softc *sc)
2565 struct ifnet *ifp = &sc->arpcom.ac_if;
2566 struct ale_txdesc *txd;
2570 ASSERT_SERIALIZED(ifp->if_serializer);
2573 * Mark the interface down and cancel the watchdog timer.
2575 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2578 callout_stop(&sc->ale_tick_ch);
2579 sc->ale_flags &= ~ALE_FLAG_LINK;
2581 ale_stats_update(sc);
2583 /* Disable interrupts. */
2584 CSR_WRITE_4(sc, ALE_INTR_MASK, 0);
2585 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2587 /* Disable queue processing and DMA. */
2588 reg = CSR_READ_4(sc, ALE_TXQ_CFG);
2589 reg &= ~TXQ_CFG_ENB;
2590 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg);
2591 reg = CSR_READ_4(sc, ALE_RXQ_CFG);
2592 reg &= ~RXQ_CFG_ENB;
2593 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg);
2594 reg = CSR_READ_4(sc, ALE_DMA_CFG);
2595 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB);
2596 CSR_WRITE_4(sc, ALE_DMA_CFG, reg);
2599 /* Stop Rx/Tx MACs. */
2602 /* Disable interrupts again? XXX */
2603 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2606 * Free TX mbufs still in the queues.
2608 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2609 txd = &sc->ale_cdata.ale_txdesc[i];
2610 if (txd->tx_m != NULL) {
2611 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2620 ale_stop_mac(struct ale_softc *sc)
2625 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2626 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
2627 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
2628 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2631 for (i = ALE_TIMEOUT; i > 0; i--) {
2632 reg = CSR_READ_4(sc, ALE_IDLE_STATUS);
2638 device_printf(sc->ale_dev,
2639 "could not disable Tx/Rx MAC(0x%08x)!\n", reg);
2643 ale_init_tx_ring(struct ale_softc *sc)
2645 struct ale_txdesc *txd;
2648 sc->ale_cdata.ale_tx_prod = 0;
2649 sc->ale_cdata.ale_tx_cons = 0;
2650 sc->ale_cdata.ale_tx_cnt = 0;
2652 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ);
2653 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ);
2654 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2655 txd = &sc->ale_cdata.ale_txdesc[i];
2658 *sc->ale_cdata.ale_tx_cmb = 0;
2659 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2660 sc->ale_cdata.ale_tx_cmb_map,
2661 BUS_DMASYNC_PREWRITE);
2662 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2663 sc->ale_cdata.ale_tx_ring_map,
2664 BUS_DMASYNC_PREWRITE);
2668 ale_init_rx_pages(struct ale_softc *sc)
2670 struct ale_rx_page *rx_page;
2673 sc->ale_cdata.ale_rx_seqno = 0;
2674 sc->ale_cdata.ale_rx_curp = 0;
2676 for (i = 0; i < ALE_RX_PAGES; i++) {
2677 rx_page = &sc->ale_cdata.ale_rx_page[i];
2678 bzero(rx_page->page_addr, sc->ale_pagesize);
2679 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ);
2681 *rx_page->cmb_addr = 0;
2682 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2683 BUS_DMASYNC_PREWRITE);
2684 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2685 BUS_DMASYNC_PREWRITE);
2690 ale_rxvlan(struct ale_softc *sc)
2695 ifp = &sc->arpcom.ac_if;
2696 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2697 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
2698 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2699 reg |= MAC_CFG_VLAN_TAG_STRIP;
2700 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2704 ale_rxfilter(struct ale_softc *sc)
2707 struct ifmultiaddr *ifma;
2712 ifp = &sc->arpcom.ac_if;
2714 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG);
2715 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
2716 if ((ifp->if_flags & IFF_BROADCAST) != 0)
2717 rxcfg |= MAC_CFG_BCAST;
2718 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
2719 if ((ifp->if_flags & IFF_PROMISC) != 0)
2720 rxcfg |= MAC_CFG_PROMISC;
2721 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
2722 rxcfg |= MAC_CFG_ALLMULTI;
2723 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF);
2724 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF);
2725 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
2729 /* Program new filter. */
2730 bzero(mchash, sizeof(mchash));
2732 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2733 if (ifma->ifma_addr->sa_family != AF_LINK)
2735 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
2736 ifma->ifma_addr), ETHER_ADDR_LEN);
2737 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
2740 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]);
2741 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]);
2742 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
2746 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS)
2748 return (sysctl_int_range(oidp, arg1, arg2, req,
2749 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX));
2753 ale_dmamap_buf_cb(void *xctx, bus_dma_segment_t *segs, int nsegs,
2754 bus_size_t mapsz __unused, int error)
2756 struct ale_dmamap_ctx *ctx = xctx;
2762 if (nsegs > ctx->nsegs) {
2768 for (i = 0; i < nsegs; ++i)
2769 ctx->segs[i] = segs[i];