2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
37 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Engineer, Wind River Systems
44 * The Broadcom BCM5700 is based on technology originally developed by
45 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
46 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
47 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
48 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
49 * frames, highly configurable RX filtering, and 16 RX and TX queues
50 * (which, along with RX filter rules, can be used for QOS applications).
51 * Other features, such as TCP segmentation, may be available as part
52 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
53 * firmware images can be stored in hardware and need not be compiled
56 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
57 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
59 * The BCM5701 is a single-chip solution incorporating both the BCM5700
60 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
61 * does not support external SSRAM.
63 * Broadcom also produces a variation of the BCM5700 under the "Altima"
64 * brand name, which is functionally similar but lacks PCI-X support.
66 * Without external SSRAM, you can only have at most 4 TX rings,
67 * and the use of the mini RX ring is disabled. This seems to imply
68 * that these features are simply not available on the BCM5701. As a
69 * result, this driver does not implement any support for the mini RX
73 #include "opt_polling.h"
75 #include <sys/param.h>
77 #include <sys/endian.h>
78 #include <sys/kernel.h>
80 #include <sys/interrupt.h>
82 #include <sys/malloc.h>
83 #include <sys/queue.h>
85 #include <sys/serialize.h>
86 #include <sys/socket.h>
87 #include <sys/sockio.h>
88 #include <sys/sysctl.h>
91 #include <net/ethernet.h>
93 #include <net/if_arp.h>
94 #include <net/if_dl.h>
95 #include <net/if_media.h>
96 #include <net/if_types.h>
97 #include <net/ifq_var.h>
98 #include <net/vlan/if_vlan_var.h>
99 #include <net/vlan/if_vlan_ether.h>
101 #include <dev/netif/mii_layer/mii.h>
102 #include <dev/netif/mii_layer/miivar.h>
103 #include <dev/netif/mii_layer/brgphyreg.h>
105 #include <bus/pci/pcidevs.h>
106 #include <bus/pci/pcireg.h>
107 #include <bus/pci/pcivar.h>
109 #include <dev/netif/bge/if_bgereg.h>
111 /* "device miibus" required. See GENERIC if you get errors here. */
112 #include "miibus_if.h"
114 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP)
115 #define BGE_MIN_FRAME 60
117 static const struct bge_type bge_devs[] = {
118 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
119 "3COM 3C996 Gigabit Ethernet" },
121 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
122 "Alteon BCM5700 Gigabit Ethernet" },
123 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
124 "Alteon BCM5701 Gigabit Ethernet" },
126 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
127 "Altima AC1000 Gigabit Ethernet" },
128 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
129 "Altima AC1002 Gigabit Ethernet" },
130 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
131 "Altima AC9100 Gigabit Ethernet" },
133 { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
134 "Apple BCM5701 Gigabit Ethernet" },
136 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
137 "Broadcom BCM5700 Gigabit Ethernet" },
138 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
139 "Broadcom BCM5701 Gigabit Ethernet" },
140 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
141 "Broadcom BCM5702 Gigabit Ethernet" },
142 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
143 "Broadcom BCM5702X Gigabit Ethernet" },
144 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
145 "Broadcom BCM5702 Gigabit Ethernet" },
146 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
147 "Broadcom BCM5703 Gigabit Ethernet" },
148 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
149 "Broadcom BCM5703X Gigabit Ethernet" },
150 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
151 "Broadcom BCM5703 Gigabit Ethernet" },
152 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
153 "Broadcom BCM5704C Dual Gigabit Ethernet" },
154 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
155 "Broadcom BCM5704S Dual Gigabit Ethernet" },
156 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
157 "Broadcom BCM5704S Dual Gigabit Ethernet" },
158 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
159 "Broadcom BCM5705 Gigabit Ethernet" },
160 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
161 "Broadcom BCM5705F Gigabit Ethernet" },
162 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
163 "Broadcom BCM5705K Gigabit Ethernet" },
164 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
165 "Broadcom BCM5705M Gigabit Ethernet" },
166 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
167 "Broadcom BCM5705M Gigabit Ethernet" },
168 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
169 "Broadcom BCM5714C Gigabit Ethernet" },
170 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
171 "Broadcom BCM5714S Gigabit Ethernet" },
172 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
173 "Broadcom BCM5715 Gigabit Ethernet" },
174 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
175 "Broadcom BCM5715S Gigabit Ethernet" },
176 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
177 "Broadcom BCM5720 Gigabit Ethernet" },
178 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
179 "Broadcom BCM5721 Gigabit Ethernet" },
180 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
181 "Broadcom BCM5722 Gigabit Ethernet" },
182 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723,
183 "Broadcom BCM5723 Gigabit Ethernet" },
184 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
185 "Broadcom BCM5750 Gigabit Ethernet" },
186 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
187 "Broadcom BCM5750M Gigabit Ethernet" },
188 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
189 "Broadcom BCM5751 Gigabit Ethernet" },
190 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
191 "Broadcom BCM5751F Gigabit Ethernet" },
192 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
193 "Broadcom BCM5751M Gigabit Ethernet" },
194 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
195 "Broadcom BCM5752 Gigabit Ethernet" },
196 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
197 "Broadcom BCM5752M Gigabit Ethernet" },
198 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
199 "Broadcom BCM5753 Gigabit Ethernet" },
200 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
201 "Broadcom BCM5753F Gigabit Ethernet" },
202 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
203 "Broadcom BCM5753M Gigabit Ethernet" },
204 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
205 "Broadcom BCM5754 Gigabit Ethernet" },
206 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
207 "Broadcom BCM5754M Gigabit Ethernet" },
208 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
209 "Broadcom BCM5755 Gigabit Ethernet" },
210 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
211 "Broadcom BCM5755M Gigabit Ethernet" },
212 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
213 "Broadcom BCM5756 Gigabit Ethernet" },
214 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761,
215 "Broadcom BCM5761 Gigabit Ethernet" },
216 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E,
217 "Broadcom BCM5761E Gigabit Ethernet" },
218 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S,
219 "Broadcom BCM5761S Gigabit Ethernet" },
220 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE,
221 "Broadcom BCM5761SE Gigabit Ethernet" },
222 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764,
223 "Broadcom BCM5764 Gigabit Ethernet" },
224 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
225 "Broadcom BCM5780 Gigabit Ethernet" },
226 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
227 "Broadcom BCM5780S Gigabit Ethernet" },
228 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
229 "Broadcom BCM5781 Gigabit Ethernet" },
230 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
231 "Broadcom BCM5782 Gigabit Ethernet" },
232 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784,
233 "Broadcom BCM5784 Gigabit Ethernet" },
234 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F,
235 "Broadcom BCM5785F Gigabit Ethernet" },
236 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G,
237 "Broadcom BCM5785G Gigabit Ethernet" },
238 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
239 "Broadcom BCM5786 Gigabit Ethernet" },
240 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
241 "Broadcom BCM5787 Gigabit Ethernet" },
242 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
243 "Broadcom BCM5787F Gigabit Ethernet" },
244 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
245 "Broadcom BCM5787M Gigabit Ethernet" },
246 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
247 "Broadcom BCM5788 Gigabit Ethernet" },
248 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
249 "Broadcom BCM5789 Gigabit Ethernet" },
250 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
251 "Broadcom BCM5901 Fast Ethernet" },
252 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
253 "Broadcom BCM5901A2 Fast Ethernet" },
254 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
255 "Broadcom BCM5903M Fast Ethernet" },
256 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
257 "Broadcom BCM5906 Fast Ethernet"},
258 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
259 "Broadcom BCM5906M Fast Ethernet"},
260 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760,
261 "Broadcom BCM57760 Gigabit Ethernet"},
262 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780,
263 "Broadcom BCM57780 Gigabit Ethernet"},
264 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788,
265 "Broadcom BCM57788 Gigabit Ethernet"},
266 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790,
267 "Broadcom BCM57790 Gigabit Ethernet"},
268 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
269 "SysKonnect Gigabit Ethernet" },
274 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
275 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
276 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
277 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
278 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
279 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
280 #define BGE_IS_5788(sc) ((sc)->bge_flags & BGE_FLAG_5788)
282 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
284 static int bge_probe(device_t);
285 static int bge_attach(device_t);
286 static int bge_detach(device_t);
287 static void bge_txeof(struct bge_softc *);
288 static void bge_rxeof(struct bge_softc *);
290 static void bge_tick(void *);
291 static void bge_stats_update(struct bge_softc *);
292 static void bge_stats_update_regs(struct bge_softc *);
294 bge_defrag_shortdma(struct mbuf *);
295 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
297 #ifdef DEVICE_POLLING
298 static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
300 static void bge_intr(void *);
301 static void bge_enable_intr(struct bge_softc *);
302 static void bge_disable_intr(struct bge_softc *);
303 static void bge_start(struct ifnet *);
304 static int bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
305 static void bge_init(void *);
306 static void bge_stop(struct bge_softc *);
307 static void bge_watchdog(struct ifnet *);
308 static void bge_shutdown(device_t);
309 static int bge_suspend(device_t);
310 static int bge_resume(device_t);
311 static int bge_ifmedia_upd(struct ifnet *);
312 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
314 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
315 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
317 static uint8_t bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
318 static int bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
320 static void bge_setmulti(struct bge_softc *);
321 static void bge_setpromisc(struct bge_softc *);
323 static int bge_alloc_jumbo_mem(struct bge_softc *);
324 static void bge_free_jumbo_mem(struct bge_softc *);
325 static struct bge_jslot
326 *bge_jalloc(struct bge_softc *);
327 static void bge_jfree(void *);
328 static void bge_jref(void *);
329 static int bge_newbuf_std(struct bge_softc *, int, int);
330 static int bge_newbuf_jumbo(struct bge_softc *, int, int);
331 static void bge_setup_rxdesc_std(struct bge_softc *, int);
332 static void bge_setup_rxdesc_jumbo(struct bge_softc *, int);
333 static int bge_init_rx_ring_std(struct bge_softc *);
334 static void bge_free_rx_ring_std(struct bge_softc *);
335 static int bge_init_rx_ring_jumbo(struct bge_softc *);
336 static void bge_free_rx_ring_jumbo(struct bge_softc *);
337 static void bge_free_tx_ring(struct bge_softc *);
338 static int bge_init_tx_ring(struct bge_softc *);
340 static int bge_chipinit(struct bge_softc *);
341 static int bge_blockinit(struct bge_softc *);
342 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
344 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
345 static void bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
347 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
349 static void bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
350 static void bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
351 static void bge_writembx(struct bge_softc *, int, int);
353 static int bge_miibus_readreg(device_t, int, int);
354 static int bge_miibus_writereg(device_t, int, int, int);
355 static void bge_miibus_statchg(device_t);
356 static void bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
357 static void bge_tbi_link_upd(struct bge_softc *, uint32_t);
358 static void bge_copper_link_upd(struct bge_softc *, uint32_t);
359 static void bge_autopoll_link_upd(struct bge_softc *, uint32_t);
361 static void bge_reset(struct bge_softc *);
363 static int bge_dma_alloc(struct bge_softc *);
364 static void bge_dma_free(struct bge_softc *);
365 static int bge_dma_block_alloc(struct bge_softc *, bus_size_t,
366 bus_dma_tag_t *, bus_dmamap_t *,
367 void **, bus_addr_t *);
368 static void bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
370 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
371 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
372 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
373 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
375 static void bge_coal_change(struct bge_softc *);
376 static int bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
377 static int bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
378 static int bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
379 static int bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
380 static int bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
383 * Set following tunable to 1 for some IBM blade servers with the DNLK
384 * switch module. Auto negotiation is broken for those configurations.
386 static int bge_fake_autoneg = 0;
387 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
389 /* Interrupt moderation control variables. */
390 static int bge_rx_coal_ticks = 100; /* usec */
391 static int bge_tx_coal_ticks = 1023; /* usec */
392 static int bge_rx_max_coal_bds = 80;
393 static int bge_tx_max_coal_bds = 128;
395 TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
396 TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
397 TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
398 TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
400 #if !defined(KTR_IF_BGE)
401 #define KTR_IF_BGE KTR_ALL
403 KTR_INFO_MASTER(if_bge);
404 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr");
405 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt");
406 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt");
407 #define logif(name) KTR_LOG(if_bge_ ## name)
409 static device_method_t bge_methods[] = {
410 /* Device interface */
411 DEVMETHOD(device_probe, bge_probe),
412 DEVMETHOD(device_attach, bge_attach),
413 DEVMETHOD(device_detach, bge_detach),
414 DEVMETHOD(device_shutdown, bge_shutdown),
415 DEVMETHOD(device_suspend, bge_suspend),
416 DEVMETHOD(device_resume, bge_resume),
419 DEVMETHOD(bus_print_child, bus_generic_print_child),
420 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
423 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
424 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
425 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
430 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
431 static devclass_t bge_devclass;
433 DECLARE_DUMMY_MODULE(if_bge);
434 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL);
435 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL);
438 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
440 device_t dev = sc->bge_dev;
443 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
444 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
447 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
448 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
449 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
454 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
456 device_t dev = sc->bge_dev;
458 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
459 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
462 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
463 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
464 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
469 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
471 device_t dev = sc->bge_dev;
473 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
474 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
479 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
481 device_t dev = sc->bge_dev;
483 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
484 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
488 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
490 CSR_WRITE_4(sc, off, val);
494 bge_writembx(struct bge_softc *sc, int off, int val)
496 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
497 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
499 CSR_WRITE_4(sc, off, val);
503 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
505 uint32_t access, byte = 0;
509 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
510 for (i = 0; i < 8000; i++) {
511 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
519 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
520 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
522 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
523 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
524 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
526 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
532 if (i == BGE_TIMEOUT * 10) {
533 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
538 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
540 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
542 /* Disable access. */
543 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
546 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
547 CSR_READ_4(sc, BGE_NVRAM_SWARB);
553 * Read a sequence of bytes from NVRAM.
556 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
561 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
564 for (i = 0; i < cnt; i++) {
565 err = bge_nvram_getbyte(sc, off + i, &byte);
571 return (err ? 1 : 0);
575 * Read a byte of data stored in the EEPROM at address 'addr.' The
576 * BCM570x supports both the traditional bitbang interface and an
577 * auto access interface for reading the EEPROM. We use the auto
581 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
587 * Enable use of auto EEPROM access so we can avoid
588 * having to use the bitbang method.
590 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
592 /* Reset the EEPROM, load the clock period. */
593 CSR_WRITE_4(sc, BGE_EE_ADDR,
594 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
597 /* Issue the read EEPROM command. */
598 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
600 /* Wait for completion */
601 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
603 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
607 if (i == BGE_TIMEOUT) {
608 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
613 byte = CSR_READ_4(sc, BGE_EE_DATA);
615 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
621 * Read a sequence of bytes from the EEPROM.
624 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
630 for (byte = 0, err = 0, i = 0; i < len; i++) {
631 err = bge_eeprom_getbyte(sc, off + i, &byte);
641 bge_miibus_readreg(device_t dev, int phy, int reg)
643 struct bge_softc *sc = device_get_softc(dev);
647 KASSERT(phy == sc->bge_phyno,
648 ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
650 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
651 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
652 CSR_WRITE_4(sc, BGE_MI_MODE,
653 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
657 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
658 BGE_MIPHY(phy) | BGE_MIREG(reg));
660 /* Poll for the PHY register access to complete. */
661 for (i = 0; i < BGE_TIMEOUT; i++) {
663 val = CSR_READ_4(sc, BGE_MI_COMM);
664 if ((val & BGE_MICOMM_BUSY) == 0) {
666 val = CSR_READ_4(sc, BGE_MI_COMM);
670 if (i == BGE_TIMEOUT) {
671 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
672 "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
676 /* Restore the autopoll bit if necessary. */
677 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
678 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
682 if (val & BGE_MICOMM_READFAIL)
685 return (val & 0xFFFF);
689 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
691 struct bge_softc *sc = device_get_softc(dev);
694 KASSERT(phy == sc->bge_phyno,
695 ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
697 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
698 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
701 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
702 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
703 CSR_WRITE_4(sc, BGE_MI_MODE,
704 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
708 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
709 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
711 for (i = 0; i < BGE_TIMEOUT; i++) {
713 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
715 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
719 if (i == BGE_TIMEOUT) {
720 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
721 "(phy %d, reg %d, val %d)\n", phy, reg, val);
724 /* Restore the autopoll bit if necessary. */
725 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
726 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
734 bge_miibus_statchg(device_t dev)
736 struct bge_softc *sc;
737 struct mii_data *mii;
739 sc = device_get_softc(dev);
740 mii = device_get_softc(sc->bge_miibus);
742 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
743 (IFM_ACTIVE | IFM_AVALID)) {
744 switch (IFM_SUBTYPE(mii->mii_media_active)) {
752 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
764 if (sc->bge_link == 0)
767 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
768 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
769 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
770 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
772 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
775 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
776 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
778 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
783 * Memory management for jumbo frames.
786 bge_alloc_jumbo_mem(struct bge_softc *sc)
788 struct ifnet *ifp = &sc->arpcom.ac_if;
789 struct bge_jslot *entry;
795 * Create tag for jumbo mbufs.
796 * This is really a bit of a kludge. We allocate a special
797 * jumbo buffer pool which (thanks to the way our DMA
798 * memory allocation works) will consist of contiguous
799 * pages. This means that even though a jumbo buffer might
800 * be larger than a page size, we don't really need to
801 * map it into more than one DMA segment. However, the
802 * default mbuf tag will result in multi-segment mappings,
803 * so we have to create a special jumbo mbuf tag that
804 * lets us get away with mapping the jumbo buffers as
805 * a single segment. I think eventually the driver should
806 * be changed so that it uses ordinary mbufs and cluster
807 * buffers, i.e. jumbo frames can span multiple DMA
808 * descriptors. But that's a project for another day.
812 * Create DMA stuffs for jumbo RX ring.
814 error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
815 &sc->bge_cdata.bge_rx_jumbo_ring_tag,
816 &sc->bge_cdata.bge_rx_jumbo_ring_map,
817 (void *)&sc->bge_ldata.bge_rx_jumbo_ring,
818 &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
820 if_printf(ifp, "could not create jumbo RX ring\n");
825 * Create DMA stuffs for jumbo buffer block.
827 error = bge_dma_block_alloc(sc, BGE_JMEM,
828 &sc->bge_cdata.bge_jumbo_tag,
829 &sc->bge_cdata.bge_jumbo_map,
830 (void **)&sc->bge_ldata.bge_jumbo_buf,
833 if_printf(ifp, "could not create jumbo buffer\n");
837 SLIST_INIT(&sc->bge_jfree_listhead);
840 * Now divide it up into 9K pieces and save the addresses
841 * in an array. Note that we play an evil trick here by using
842 * the first few bytes in the buffer to hold the the address
843 * of the softc structure for this interface. This is because
844 * bge_jfree() needs it, but it is called by the mbuf management
845 * code which will not pass it to us explicitly.
847 for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
848 entry = &sc->bge_cdata.bge_jslots[i];
850 entry->bge_buf = ptr;
851 entry->bge_paddr = paddr;
852 entry->bge_inuse = 0;
854 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
863 bge_free_jumbo_mem(struct bge_softc *sc)
865 /* Destroy jumbo RX ring. */
866 bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
867 sc->bge_cdata.bge_rx_jumbo_ring_map,
868 sc->bge_ldata.bge_rx_jumbo_ring);
870 /* Destroy jumbo buffer block. */
871 bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
872 sc->bge_cdata.bge_jumbo_map,
873 sc->bge_ldata.bge_jumbo_buf);
877 * Allocate a jumbo buffer.
879 static struct bge_jslot *
880 bge_jalloc(struct bge_softc *sc)
882 struct bge_jslot *entry;
884 lwkt_serialize_enter(&sc->bge_jslot_serializer);
885 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
887 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
888 entry->bge_inuse = 1;
890 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
892 lwkt_serialize_exit(&sc->bge_jslot_serializer);
897 * Adjust usage count on a jumbo buffer.
902 struct bge_jslot *entry = (struct bge_jslot *)arg;
903 struct bge_softc *sc = entry->bge_sc;
906 panic("bge_jref: can't find softc pointer!");
908 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
909 panic("bge_jref: asked to reference buffer "
910 "that we don't manage!");
911 } else if (entry->bge_inuse == 0) {
912 panic("bge_jref: buffer already free!");
914 atomic_add_int(&entry->bge_inuse, 1);
919 * Release a jumbo buffer.
924 struct bge_jslot *entry = (struct bge_jslot *)arg;
925 struct bge_softc *sc = entry->bge_sc;
928 panic("bge_jfree: can't find softc pointer!");
930 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
931 panic("bge_jfree: asked to free buffer that we don't manage!");
932 } else if (entry->bge_inuse == 0) {
933 panic("bge_jfree: buffer already free!");
936 * Possible MP race to 0, use the serializer. The atomic insn
937 * is still needed for races against bge_jref().
939 lwkt_serialize_enter(&sc->bge_jslot_serializer);
940 atomic_subtract_int(&entry->bge_inuse, 1);
941 if (entry->bge_inuse == 0) {
942 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
945 lwkt_serialize_exit(&sc->bge_jslot_serializer);
951 * Intialize a standard receive ring descriptor.
954 bge_newbuf_std(struct bge_softc *sc, int i, int init)
956 struct mbuf *m_new = NULL;
957 bus_dma_segment_t seg;
961 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
964 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
966 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
967 m_adj(m_new, ETHER_ALIGN);
969 error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag,
970 sc->bge_cdata.bge_rx_tmpmap, m_new,
971 &seg, 1, &nsegs, BUS_DMA_NOWAIT);
978 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
979 sc->bge_cdata.bge_rx_std_dmamap[i],
980 BUS_DMASYNC_POSTREAD);
981 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
982 sc->bge_cdata.bge_rx_std_dmamap[i]);
985 map = sc->bge_cdata.bge_rx_tmpmap;
986 sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i];
987 sc->bge_cdata.bge_rx_std_dmamap[i] = map;
989 sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new;
990 sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr;
992 bge_setup_rxdesc_std(sc, i);
997 bge_setup_rxdesc_std(struct bge_softc *sc, int i)
999 struct bge_rxchain *rc;
1000 struct bge_rx_bd *r;
1002 rc = &sc->bge_cdata.bge_rx_std_chain[i];
1003 r = &sc->bge_ldata.bge_rx_std_ring[i];
1005 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1006 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1007 r->bge_len = rc->bge_mbuf->m_len;
1009 r->bge_flags = BGE_RXBDFLAG_END;
1013 * Initialize a jumbo receive ring descriptor. This allocates
1014 * a jumbo buffer from the pool managed internally by the driver.
1017 bge_newbuf_jumbo(struct bge_softc *sc, int i, int init)
1019 struct mbuf *m_new = NULL;
1020 struct bge_jslot *buf;
1023 /* Allocate the mbuf. */
1024 MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1028 /* Allocate the jumbo buffer */
1029 buf = bge_jalloc(sc);
1035 /* Attach the buffer to the mbuf. */
1036 m_new->m_ext.ext_arg = buf;
1037 m_new->m_ext.ext_buf = buf->bge_buf;
1038 m_new->m_ext.ext_free = bge_jfree;
1039 m_new->m_ext.ext_ref = bge_jref;
1040 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
1042 m_new->m_flags |= M_EXT;
1044 m_new->m_data = m_new->m_ext.ext_buf;
1045 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1047 paddr = buf->bge_paddr;
1048 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
1049 m_adj(m_new, ETHER_ALIGN);
1050 paddr += ETHER_ALIGN;
1053 /* Save necessary information */
1054 sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new;
1055 sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr;
1057 /* Set up the descriptor. */
1058 bge_setup_rxdesc_jumbo(sc, i);
1063 bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i)
1065 struct bge_rx_bd *r;
1066 struct bge_rxchain *rc;
1068 r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1069 rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1071 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1072 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1073 r->bge_len = rc->bge_mbuf->m_len;
1075 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
1079 bge_init_rx_ring_std(struct bge_softc *sc)
1083 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1084 error = bge_newbuf_std(sc, i, 1);
1089 sc->bge_std = BGE_STD_RX_RING_CNT - 1;
1090 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1096 bge_free_rx_ring_std(struct bge_softc *sc)
1100 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1101 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i];
1103 if (rc->bge_mbuf != NULL) {
1104 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1105 sc->bge_cdata.bge_rx_std_dmamap[i]);
1106 m_freem(rc->bge_mbuf);
1107 rc->bge_mbuf = NULL;
1109 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
1110 sizeof(struct bge_rx_bd));
1115 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1117 struct bge_rcb *rcb;
1120 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1121 error = bge_newbuf_jumbo(sc, i, 1);
1126 sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
1128 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1129 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1130 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1132 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1138 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1142 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1143 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1145 if (rc->bge_mbuf != NULL) {
1146 m_freem(rc->bge_mbuf);
1147 rc->bge_mbuf = NULL;
1149 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1150 sizeof(struct bge_rx_bd));
1155 bge_free_tx_ring(struct bge_softc *sc)
1159 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1160 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1161 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1162 sc->bge_cdata.bge_tx_dmamap[i]);
1163 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1164 sc->bge_cdata.bge_tx_chain[i] = NULL;
1166 bzero(&sc->bge_ldata.bge_tx_ring[i],
1167 sizeof(struct bge_tx_bd));
1172 bge_init_tx_ring(struct bge_softc *sc)
1175 sc->bge_tx_saved_considx = 0;
1176 sc->bge_tx_prodidx = 0;
1178 /* Initialize transmit producer index for host-memory send ring. */
1179 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1181 /* 5700 b2 errata */
1182 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1183 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1185 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1186 /* 5700 b2 errata */
1187 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1188 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1194 bge_setmulti(struct bge_softc *sc)
1197 struct ifmultiaddr *ifma;
1198 uint32_t hashes[4] = { 0, 0, 0, 0 };
1201 ifp = &sc->arpcom.ac_if;
1203 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1204 for (i = 0; i < 4; i++)
1205 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1209 /* First, zot all the existing filters. */
1210 for (i = 0; i < 4; i++)
1211 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1213 /* Now program new ones. */
1214 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1215 if (ifma->ifma_addr->sa_family != AF_LINK)
1218 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1219 ETHER_ADDR_LEN) & 0x7f;
1220 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1223 for (i = 0; i < 4; i++)
1224 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1228 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1229 * self-test results.
1232 bge_chipinit(struct bge_softc *sc)
1235 uint32_t dma_rw_ctl;
1238 /* Set endian type before we access any non-PCI registers. */
1239 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1241 /* Clear the MAC control register */
1242 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1245 * Clear the MAC statistics block in the NIC's
1248 for (i = BGE_STATS_BLOCK;
1249 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1250 BGE_MEMWIN_WRITE(sc, i, 0);
1252 for (i = BGE_STATUS_BLOCK;
1253 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1254 BGE_MEMWIN_WRITE(sc, i, 0);
1256 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1258 * Fix data corruption caused by non-qword write with WB.
1259 * Fix master abort in PCI mode.
1260 * Fix PCI latency timer.
1262 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1263 val |= (1 << 10) | (1 << 12) | (1 << 13);
1264 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1267 /* Set up the PCI DMA control register. */
1268 if (sc->bge_flags & BGE_FLAG_PCIE) {
1270 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1271 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1272 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1273 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1275 if (BGE_IS_5714_FAMILY(sc)) {
1276 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1277 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1278 /* XXX magic values, Broadcom-supplied Linux driver */
1279 if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1280 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1281 BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1283 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1285 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1287 * In the BCM5703, the DMA read watermark should
1288 * be set to less than or equal to the maximum
1289 * memory read byte count of the PCI-X command
1292 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1293 (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1294 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1295 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1297 * The 5704 uses a different encoding of read/write
1300 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1301 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1302 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1304 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1305 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1306 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1311 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1312 * for hardware bugs.
1314 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1315 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1318 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1319 if (tmp == 0x6 || tmp == 0x7)
1320 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1323 /* Conventional PCI bus */
1324 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1325 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1326 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1330 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1331 sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1332 sc->bge_asicrev == BGE_ASICREV_BCM5705)
1333 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1334 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1337 * Set up general mode register.
1339 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1340 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1341 BGE_MODECTL_TX_NO_PHDR_CSUM);
1344 * BCM5701 B5 have a bug causing data corruption when using
1345 * 64-bit DMA reads, which can be terminated early and then
1346 * completed later as 32-bit accesses, in combination with
1349 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1350 sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1351 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1354 * Disable memory write invalidate. Apparently it is not supported
1355 * properly by these devices.
1357 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1359 /* Set the timer prescaler (always 66Mhz) */
1360 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1362 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1363 DELAY(40); /* XXX */
1365 /* Put PHY into ready state */
1366 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1367 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1375 bge_blockinit(struct bge_softc *sc)
1377 struct bge_rcb *rcb;
1384 * Initialize the memory window pointer register so that
1385 * we can access the first 32K of internal NIC RAM. This will
1386 * allow us to set up the TX send ring RCBs and the RX return
1387 * ring RCBs, plus other things which live in NIC memory.
1389 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1391 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1393 if (!BGE_IS_5705_PLUS(sc)) {
1394 /* Configure mbuf memory pool */
1395 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1396 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1397 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1399 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1401 /* Configure DMA resource pool */
1402 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1403 BGE_DMA_DESCRIPTORS);
1404 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1407 /* Configure mbuf pool watermarks */
1408 if (!BGE_IS_5705_PLUS(sc)) {
1409 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1410 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1411 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1412 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1413 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1414 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1415 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1417 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1418 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1419 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1422 /* Configure DMA resource watermarks */
1423 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1424 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1426 /* Enable buffer manager */
1427 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1428 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1430 /* Poll for buffer manager start indication */
1431 for (i = 0; i < BGE_TIMEOUT; i++) {
1432 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1437 if (i == BGE_TIMEOUT) {
1438 if_printf(&sc->arpcom.ac_if,
1439 "buffer manager failed to start\n");
1443 /* Enable flow-through queues */
1444 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1445 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1447 /* Wait until queue initialization is complete */
1448 for (i = 0; i < BGE_TIMEOUT; i++) {
1449 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1454 if (i == BGE_TIMEOUT) {
1455 if_printf(&sc->arpcom.ac_if,
1456 "flow-through queue init failed\n");
1461 * Summary of rings supported by the controller:
1463 * Standard Receive Producer Ring
1464 * - This ring is used to feed receive buffers for "standard"
1465 * sized frames (typically 1536 bytes) to the controller.
1467 * Jumbo Receive Producer Ring
1468 * - This ring is used to feed receive buffers for jumbo sized
1469 * frames (i.e. anything bigger than the "standard" frames)
1470 * to the controller.
1472 * Mini Receive Producer Ring
1473 * - This ring is used to feed receive buffers for "mini"
1474 * sized frames to the controller.
1475 * - This feature required external memory for the controller
1476 * but was never used in a production system. Should always
1479 * Receive Return Ring
1480 * - After the controller has placed an incoming frame into a
1481 * receive buffer that buffer is moved into a receive return
1482 * ring. The driver is then responsible to passing the
1483 * buffer up to the stack. Many versions of the controller
1484 * support multiple RR rings.
1487 * - This ring is used for outgoing frames. Many versions of
1488 * the controller support multiple send rings.
1491 /* Initialize the standard receive producer ring control block. */
1492 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1493 rcb->bge_hostaddr.bge_addr_lo =
1494 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1495 rcb->bge_hostaddr.bge_addr_hi =
1496 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1497 if (BGE_IS_5705_PLUS(sc)) {
1499 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1500 * Bits 15-2 : Reserved (should be 0)
1501 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
1504 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1507 * Ring size is always XXX entries
1508 * Bits 31-16: Maximum RX frame size
1509 * Bits 15-2 : Reserved (should be 0)
1510 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
1513 rcb->bge_maxlen_flags =
1514 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1516 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1517 /* Write the standard receive producer ring control block. */
1518 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1519 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1520 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1521 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1522 /* Reset the standard receive producer ring producer index. */
1523 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1526 * Initialize the jumbo RX producer ring control
1527 * block. We set the 'ring disabled' bit in the
1528 * flags field until we're actually ready to start
1529 * using this ring (i.e. once we set the MTU
1530 * high enough to require it).
1532 if (BGE_IS_JUMBO_CAPABLE(sc)) {
1533 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1534 /* Get the jumbo receive producer ring RCB parameters. */
1535 rcb->bge_hostaddr.bge_addr_lo =
1536 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1537 rcb->bge_hostaddr.bge_addr_hi =
1538 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1539 rcb->bge_maxlen_flags =
1540 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1541 BGE_RCB_FLAG_RING_DISABLED);
1542 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1543 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1544 rcb->bge_hostaddr.bge_addr_hi);
1545 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1546 rcb->bge_hostaddr.bge_addr_lo);
1547 /* Program the jumbo receive producer ring RCB parameters. */
1548 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1549 rcb->bge_maxlen_flags);
1550 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1551 /* Reset the jumbo receive producer ring producer index. */
1552 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1555 /* Disable the mini receive producer ring RCB. */
1556 if (BGE_IS_5700_FAMILY(sc)) {
1557 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1558 rcb->bge_maxlen_flags =
1559 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1560 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1561 rcb->bge_maxlen_flags);
1562 /* Reset the mini receive producer ring producer index. */
1563 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1566 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
1567 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1568 (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
1569 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
1570 sc->bge_chipid == BGE_CHIPID_BCM5906_A2)) {
1571 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
1572 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
1576 * The BD ring replenish thresholds control how often the
1577 * hardware fetches new BD's from the producer rings in host
1578 * memory. Setting the value too low on a busy system can
1579 * starve the hardware and recue the throughpout.
1581 * Set the BD ring replentish thresholds. The recommended
1582 * values are 1/8th the number of descriptors allocated to
1585 if (BGE_IS_5705_PLUS(sc))
1588 val = BGE_STD_RX_RING_CNT / 8;
1589 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1590 if (BGE_IS_JUMBO_CAPABLE(sc)) {
1591 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1592 BGE_JUMBO_RX_RING_CNT/8);
1596 * Disable all send rings by setting the 'ring disabled' bit
1597 * in the flags field of all the TX send ring control blocks,
1598 * located in NIC memory.
1600 if (!BGE_IS_5705_PLUS(sc)) {
1601 /* 5700 to 5704 had 16 send rings. */
1602 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
1606 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1607 for (i = 0; i < limit; i++) {
1608 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1609 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1610 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1611 vrcb += sizeof(struct bge_rcb);
1614 /* Configure send ring RCB 0 (we use only the first ring) */
1615 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1616 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1617 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1618 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1619 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1620 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1621 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1622 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1625 * Disable all receive return rings by setting the
1626 * 'ring diabled' bit in the flags field of all the receive
1627 * return ring control blocks, located in NIC memory.
1629 if (!BGE_IS_5705_PLUS(sc))
1630 limit = BGE_RX_RINGS_MAX;
1631 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755)
1635 /* Disable all receive return rings. */
1636 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1637 for (i = 0; i < limit; i++) {
1638 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1639 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1640 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1641 BGE_RCB_FLAG_RING_DISABLED);
1642 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1643 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1644 (i * (sizeof(uint64_t))), 0);
1645 vrcb += sizeof(struct bge_rcb);
1649 * Set up receive return ring 0. Note that the NIC address
1650 * for RX return rings is 0x0. The return rings live entirely
1651 * within the host, so the nicaddr field in the RCB isn't used.
1653 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1654 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1655 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1656 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1657 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1658 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1659 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1661 /* Set random backoff seed for TX */
1662 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1663 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1664 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1665 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1666 BGE_TX_BACKOFF_SEED_MASK);
1668 /* Set inter-packet gap */
1669 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1672 * Specify which ring to use for packets that don't match
1675 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1678 * Configure number of RX lists. One interrupt distribution
1679 * list, sixteen active lists, one bad frames class.
1681 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1683 /* Inialize RX list placement stats mask. */
1684 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1685 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1687 /* Disable host coalescing until we get it set up */
1688 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1690 /* Poll to make sure it's shut down. */
1691 for (i = 0; i < BGE_TIMEOUT; i++) {
1692 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1697 if (i == BGE_TIMEOUT) {
1698 if_printf(&sc->arpcom.ac_if,
1699 "host coalescing engine failed to idle\n");
1703 /* Set up host coalescing defaults */
1704 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1705 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1706 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1707 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1708 if (!BGE_IS_5705_PLUS(sc)) {
1709 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1710 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1712 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1713 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1715 /* Set up address of statistics block */
1716 if (!BGE_IS_5705_PLUS(sc)) {
1717 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1718 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1719 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1720 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1722 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1723 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1724 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1727 /* Set up address of status block */
1728 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
1729 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1730 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1731 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1732 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1735 * Set up status block partail update size.
1737 * Because only single TX ring, RX produce ring and Rx return ring
1738 * are used, ask device to update only minimum part of status block
1739 * except for BCM5700 AX/BX, whose status block partial update size
1740 * can't be configured.
1742 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1743 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
1744 /* XXX Actually reserved on BCM5700 AX/BX */
1745 val = BGE_STATBLKSZ_FULL;
1747 val = BGE_STATBLKSZ_32BYTE;
1750 /* Turn on host coalescing state machine */
1751 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1753 /* Turn on RX BD completion state machine and enable attentions */
1754 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1755 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1757 /* Turn on RX list placement state machine */
1758 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1760 /* Turn on RX list selector state machine. */
1761 if (!BGE_IS_5705_PLUS(sc))
1762 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1764 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1765 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1766 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1767 BGE_MACMODE_FRMHDR_DMA_ENB;
1769 if (sc->bge_flags & BGE_FLAG_TBI)
1770 val |= BGE_PORTMODE_TBI;
1771 else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
1772 val |= BGE_PORTMODE_GMII;
1774 val |= BGE_PORTMODE_MII;
1776 /* Turn on DMA, clear stats */
1777 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1779 /* Set misc. local control, enable interrupts on attentions */
1780 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1783 /* Assert GPIO pins for PHY reset */
1784 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1785 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1786 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1787 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1790 /* Turn on DMA completion state machine */
1791 if (!BGE_IS_5705_PLUS(sc))
1792 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1794 /* Turn on write DMA state machine */
1795 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1796 if (BGE_IS_5755_PLUS(sc)) {
1797 /* Enable host coalescing bug fix. */
1798 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1800 if (sc->bge_asicrev == BGE_ASICREV_BCM5785) {
1801 /* Request larger DMA burst size to get better performance. */
1802 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1804 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1807 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
1808 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1809 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1810 sc->bge_asicrev == BGE_ASICREV_BCM57780) {
1812 * Enable fix for read DMA FIFO overruns.
1813 * The fix is to limit the number of RX BDs
1814 * the hardware would fetch at a fime.
1816 val = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
1817 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
1818 val| BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1821 /* Turn on read DMA state machine */
1822 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1823 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1824 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1825 sc->bge_asicrev == BGE_ASICREV_BCM57780)
1826 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1827 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1828 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1829 if (sc->bge_flags & BGE_FLAG_PCIE)
1830 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1831 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1834 /* Turn on RX data completion state machine */
1835 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1837 /* Turn on RX BD initiator state machine */
1838 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1840 /* Turn on RX data and RX BD initiator state machine */
1841 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1843 /* Turn on Mbuf cluster free state machine */
1844 if (!BGE_IS_5705_PLUS(sc))
1845 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1847 /* Turn on send BD completion state machine */
1848 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1850 /* Turn on send data completion state machine */
1851 val = BGE_SDCMODE_ENABLE;
1852 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1853 val |= BGE_SDCMODE_CDELAY;
1854 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1856 /* Turn on send data initiator state machine */
1857 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1859 /* Turn on send BD initiator state machine */
1860 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1862 /* Turn on send BD selector state machine */
1863 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1865 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1866 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1867 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1869 /* ack/clear link change events */
1870 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1871 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1872 BGE_MACSTAT_LINK_CHANGED);
1873 CSR_WRITE_4(sc, BGE_MI_STS, 0);
1876 * Enable attention when the link has changed state for
1877 * devices that use auto polling.
1879 if (sc->bge_flags & BGE_FLAG_TBI) {
1880 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1882 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
1883 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1886 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1887 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1888 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1889 BGE_EVTENB_MI_INTERRUPT);
1894 * Clear any pending link state attention.
1895 * Otherwise some link state change events may be lost until attention
1896 * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1897 * It's not necessary on newer BCM chips - perhaps enabling link
1898 * state change attentions implies clearing pending attention.
1900 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1901 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1902 BGE_MACSTAT_LINK_CHANGED);
1904 /* Enable link state change attentions. */
1905 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1911 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1912 * against our list and return its name if we find a match. Note
1913 * that since the Broadcom controller contains VPD support, we
1914 * can get the device name string from the controller itself instead
1915 * of the compiled-in string. This is a little slow, but it guarantees
1916 * we'll always announce the right product name.
1919 bge_probe(device_t dev)
1921 const struct bge_type *t;
1922 uint16_t product, vendor;
1924 product = pci_get_device(dev);
1925 vendor = pci_get_vendor(dev);
1927 for (t = bge_devs; t->bge_name != NULL; t++) {
1928 if (vendor == t->bge_vid && product == t->bge_did)
1931 if (t->bge_name == NULL)
1934 device_set_desc(dev, t->bge_name);
1939 bge_attach(device_t dev)
1942 struct bge_softc *sc;
1943 uint32_t hwcfg = 0, misccfg;
1944 int error = 0, rid, capmask;
1945 uint8_t ether_addr[ETHER_ADDR_LEN];
1946 uint16_t product, vendor;
1948 sc = device_get_softc(dev);
1950 callout_init(&sc->bge_stat_timer);
1951 lwkt_serialize_init(&sc->bge_jslot_serializer);
1953 #ifndef BURN_BRIDGES
1954 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1957 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1958 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1960 device_printf(dev, "chip is in D%d power mode "
1961 "-- setting to D0\n", pci_get_powerstate(dev));
1963 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1965 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1966 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1968 #endif /* !BURN_BRIDGE */
1971 * Map control/status registers.
1973 pci_enable_busmaster(dev);
1976 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1979 if (sc->bge_res == NULL) {
1980 device_printf(dev, "couldn't map memory\n");
1984 sc->bge_btag = rman_get_bustag(sc->bge_res);
1985 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1987 /* Save various chip information */
1989 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1990 BGE_PCIMISCCTL_ASICREV_SHIFT;
1991 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
1992 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
1993 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1994 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1996 /* Save chipset family. */
1997 switch (sc->bge_asicrev) {
1998 case BGE_ASICREV_BCM5755:
1999 case BGE_ASICREV_BCM5761:
2000 case BGE_ASICREV_BCM5784:
2001 case BGE_ASICREV_BCM5785:
2002 case BGE_ASICREV_BCM5787:
2003 case BGE_ASICREV_BCM57780:
2004 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2008 case BGE_ASICREV_BCM5700:
2009 case BGE_ASICREV_BCM5701:
2010 case BGE_ASICREV_BCM5703:
2011 case BGE_ASICREV_BCM5704:
2012 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2015 case BGE_ASICREV_BCM5714_A0:
2016 case BGE_ASICREV_BCM5780:
2017 case BGE_ASICREV_BCM5714:
2018 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
2021 case BGE_ASICREV_BCM5750:
2022 case BGE_ASICREV_BCM5752:
2023 case BGE_ASICREV_BCM5906:
2024 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2027 case BGE_ASICREV_BCM5705:
2028 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2032 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
2033 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
2035 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
2036 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2037 (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2038 misccfg == BGE_MISCCFG_BOARD_ID_5788M))
2039 sc->bge_flags |= BGE_FLAG_5788;
2041 /* BCM5755 or higher and BCM5906 have short DMA bug. */
2042 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
2043 sc->bge_flags |= BGE_FLAG_SHORTDMA;
2046 * Set various quirk flags.
2049 product = pci_get_device(dev);
2050 vendor = pci_get_vendor(dev);
2052 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2053 sc->bge_asicrev == BGE_ASICREV_BCM5701) &&
2054 pci_get_subvendor(dev) == PCI_VENDOR_DELL)
2055 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
2057 capmask = MII_CAPMASK_DEFAULT;
2058 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
2059 (misccfg == 0x4000 || misccfg == 0x8000)) ||
2060 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2061 vendor == PCI_VENDOR_BROADCOM &&
2062 (product == PCI_PRODUCT_BROADCOM_BCM5901 ||
2063 product == PCI_PRODUCT_BROADCOM_BCM5901A2 ||
2064 product == PCI_PRODUCT_BROADCOM_BCM5705F)) ||
2065 (vendor == PCI_VENDOR_BROADCOM &&
2066 (product == PCI_PRODUCT_BROADCOM_BCM5751F ||
2067 product == PCI_PRODUCT_BROADCOM_BCM5753F ||
2068 product == PCI_PRODUCT_BROADCOM_BCM5787F)) ||
2069 product == PCI_PRODUCT_BROADCOM_BCM57790 ||
2070 sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2072 capmask &= ~BMSR_EXTSTAT;
2075 sc->bge_phy_flags |= BGE_PHY_WIRESPEED;
2076 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2077 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2078 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2079 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
2080 sc->bge_asicrev == BGE_ASICREV_BCM5906)
2081 sc->bge_phy_flags &= ~BGE_PHY_WIRESPEED;
2083 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2084 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2085 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
2087 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2088 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2089 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
2091 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2092 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
2094 if (BGE_IS_5705_PLUS(sc) &&
2095 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2096 /* sc->bge_asicrev != BGE_ASICREV_BCM5717 && */
2097 sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2098 /* sc->bge_asicrev != BGE_ASICREV_BCM57765 && */
2099 sc->bge_asicrev != BGE_ASICREV_BCM57780) {
2100 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2101 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2102 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2103 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2104 if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
2105 product != PCI_PRODUCT_BROADCOM_BCM5756)
2106 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
2107 if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
2108 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
2110 sc->bge_phy_flags |= BGE_PHY_BER_BUG;
2114 /* Identify the chips that use an CPMU. */
2115 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2116 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2117 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2118 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2119 sc->bge_flags |= BGE_FLAG_CPMU;
2120 if (sc->bge_flags & BGE_FLAG_CPMU)
2121 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
2123 sc->bge_mi_mode = BGE_MIMODE_BASE;
2125 /* Enable auto polling for BCM570[0-5]. */
2126 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
2127 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
2129 /* Allocate interrupt */
2132 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2133 RF_SHAREABLE | RF_ACTIVE);
2135 if (sc->bge_irq == NULL) {
2136 device_printf(dev, "couldn't map interrupt\n");
2142 * Check if this is a PCI-X or PCI Express device.
2144 if (BGE_IS_5705_PLUS(sc)) {
2145 if (pci_is_pcie(dev)) {
2146 sc->bge_flags |= BGE_FLAG_PCIE;
2147 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
2151 * Check if the device is in PCI-X Mode.
2152 * (This bit is not valid on PCI Express controllers.)
2154 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
2155 BGE_PCISTATE_PCI_BUSMODE) == 0) {
2156 sc->bge_flags |= BGE_FLAG_PCIX;
2157 sc->bge_pcixcap = pci_get_pcixcap_ptr(sc->bge_dev);
2161 device_printf(dev, "CHIP ID 0x%08x; "
2162 "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
2163 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
2164 (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
2165 : ((sc->bge_flags & BGE_FLAG_PCIE) ?
2169 * The 40bit DMA bug applies to the 5714/5715 controllers and is
2170 * not actually a MAC controller bug but an issue with the embedded
2171 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2173 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
2174 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT;
2176 ifp = &sc->arpcom.ac_if;
2177 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2179 /* Try to reset the chip. */
2182 if (bge_chipinit(sc)) {
2183 device_printf(dev, "chip initialization failed\n");
2189 * Get station address
2191 error = bge_get_eaddr(sc, ether_addr);
2193 device_printf(dev, "failed to read station address\n");
2197 /* 5705/5750 limits RX return ring to 512 entries. */
2198 if (BGE_IS_5705_PLUS(sc))
2199 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2201 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2203 error = bge_dma_alloc(sc);
2207 /* Set default tuneable values. */
2208 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2209 sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
2210 sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
2211 sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
2212 sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
2214 /* Set up ifnet structure */
2216 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2217 ifp->if_ioctl = bge_ioctl;
2218 ifp->if_start = bge_start;
2219 #ifdef DEVICE_POLLING
2220 ifp->if_poll = bge_poll;
2222 ifp->if_watchdog = bge_watchdog;
2223 ifp->if_init = bge_init;
2224 ifp->if_mtu = ETHERMTU;
2225 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2226 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2227 ifq_set_ready(&ifp->if_snd);
2230 * 5700 B0 chips do not support checksumming correctly due
2233 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
2234 ifp->if_capabilities |= IFCAP_HWCSUM;
2235 ifp->if_hwassist = BGE_CSUM_FEATURES;
2237 ifp->if_capenable = ifp->if_capabilities;
2240 * Figure out what sort of media we have by checking the
2241 * hardware config word in the first 32k of NIC internal memory,
2242 * or fall back to examining the EEPROM if necessary.
2243 * Note: on some BCM5700 cards, this value appears to be unset.
2244 * If that's the case, we have to rely on identifying the NIC
2245 * by its PCI subsystem ID, as we do below for the SysKonnect
2248 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2249 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2251 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2253 device_printf(dev, "failed to read EEPROM\n");
2257 hwcfg = ntohl(hwcfg);
2260 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2261 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
2262 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
2263 if (BGE_IS_5714_FAMILY(sc))
2264 sc->bge_flags |= BGE_FLAG_MII_SERDES;
2266 sc->bge_flags |= BGE_FLAG_TBI;
2270 * Broadcom's own driver always assumes the internal
2271 * PHY is at GMII address 1. On some chips, the PHY responds
2272 * to accesses at all addresses, which could cause us to
2273 * bogusly attach the PHY 32 times at probe type. Always
2274 * restricting the lookup to address 1 is simpler than
2275 * trying to figure out which chips revisions should be
2280 if (sc->bge_flags & BGE_FLAG_TBI) {
2281 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
2282 bge_ifmedia_upd, bge_ifmedia_sts);
2283 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2284 ifmedia_add(&sc->bge_ifmedia,
2285 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2286 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2287 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
2288 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2290 struct mii_probe_args mii_args;
2292 mii_probe_args_init(&mii_args, bge_ifmedia_upd, bge_ifmedia_sts);
2293 mii_args.mii_probemask = 1 << sc->bge_phyno;
2294 mii_args.mii_capmask = capmask;
2296 error = mii_probe(dev, &sc->bge_miibus, &mii_args);
2298 device_printf(dev, "MII without any PHY!\n");
2304 * When using the BCM5701 in PCI-X mode, data corruption has
2305 * been observed in the first few bytes of some received packets.
2306 * Aligning the packet buffer in memory eliminates the corruption.
2307 * Unfortunately, this misaligns the packet payloads. On platforms
2308 * which do not support unaligned accesses, we will realign the
2309 * payloads by copying the received packets.
2311 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2312 (sc->bge_flags & BGE_FLAG_PCIX))
2313 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2315 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2316 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2317 sc->bge_link_upd = bge_bcm5700_link_upd;
2318 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
2319 } else if (sc->bge_flags & BGE_FLAG_TBI) {
2320 sc->bge_link_upd = bge_tbi_link_upd;
2321 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2322 } else if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2323 sc->bge_link_upd = bge_autopoll_link_upd;
2324 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2326 sc->bge_link_upd = bge_copper_link_upd;
2327 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2331 * Create sysctl nodes.
2333 sysctl_ctx_init(&sc->bge_sysctl_ctx);
2334 sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
2335 SYSCTL_STATIC_CHILDREN(_hw),
2337 device_get_nameunit(dev),
2339 if (sc->bge_sysctl_tree == NULL) {
2340 device_printf(dev, "can't add sysctl node\n");
2345 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2346 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2347 OID_AUTO, "rx_coal_ticks",
2348 CTLTYPE_INT | CTLFLAG_RW,
2349 sc, 0, bge_sysctl_rx_coal_ticks, "I",
2350 "Receive coalescing ticks (usec).");
2351 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2352 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2353 OID_AUTO, "tx_coal_ticks",
2354 CTLTYPE_INT | CTLFLAG_RW,
2355 sc, 0, bge_sysctl_tx_coal_ticks, "I",
2356 "Transmit coalescing ticks (usec).");
2357 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2358 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2359 OID_AUTO, "rx_max_coal_bds",
2360 CTLTYPE_INT | CTLFLAG_RW,
2361 sc, 0, bge_sysctl_rx_max_coal_bds, "I",
2362 "Receive max coalesced BD count.");
2363 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2364 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2365 OID_AUTO, "tx_max_coal_bds",
2366 CTLTYPE_INT | CTLFLAG_RW,
2367 sc, 0, bge_sysctl_tx_max_coal_bds, "I",
2368 "Transmit max coalesced BD count.");
2370 if (sc->bge_flags & BGE_FLAG_PCIE) {
2372 * A common design characteristic for many Broadcom
2373 * client controllers is that they only support a
2374 * single outstanding DMA read operation on the PCIe
2375 * bus. This means that it will take twice as long to
2376 * fetch a TX frame that is split into header and
2377 * payload buffers as it does to fetch a single,
2378 * contiguous TX frame (2 reads vs. 1 read). For these
2379 * controllers, coalescing buffers to reduce the number
2380 * of memory reads is effective way to get maximum
2381 * performance(about 940Mbps). Without collapsing TX
2382 * buffers the maximum TCP bulk transfer performance
2383 * is about 850Mbps. However forcing coalescing mbufs
2384 * consumes a lot of CPU cycles, so leave it off by
2387 SYSCTL_ADD_INT(&sc->bge_sysctl_ctx,
2388 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2389 OID_AUTO, "force_defrag", CTLFLAG_RW,
2390 &sc->bge_force_defrag, 0,
2391 "Force defragment on TX path");
2395 * Call MI attach routine.
2397 ether_ifattach(ifp, ether_addr, NULL);
2399 error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE,
2400 bge_intr, sc, &sc->bge_intrhand,
2401 ifp->if_serializer);
2403 ether_ifdetach(ifp);
2404 device_printf(dev, "couldn't set up irq\n");
2408 ifp->if_cpuid = rman_get_cpuid(sc->bge_irq);
2409 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2418 bge_detach(device_t dev)
2420 struct bge_softc *sc = device_get_softc(dev);
2422 if (device_is_attached(dev)) {
2423 struct ifnet *ifp = &sc->arpcom.ac_if;
2425 lwkt_serialize_enter(ifp->if_serializer);
2428 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2429 lwkt_serialize_exit(ifp->if_serializer);
2431 ether_ifdetach(ifp);
2434 if (sc->bge_flags & BGE_FLAG_TBI)
2435 ifmedia_removeall(&sc->bge_ifmedia);
2437 device_delete_child(dev, sc->bge_miibus);
2438 bus_generic_detach(dev);
2440 if (sc->bge_irq != NULL)
2441 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
2443 if (sc->bge_res != NULL)
2444 bus_release_resource(dev, SYS_RES_MEMORY,
2445 BGE_PCI_BAR0, sc->bge_res);
2447 if (sc->bge_sysctl_tree != NULL)
2448 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2456 bge_reset(struct bge_softc *sc)
2459 uint32_t cachesize, command, pcistate, reset;
2460 void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2465 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2466 sc->bge_asicrev != BGE_ASICREV_BCM5906) {
2467 if (sc->bge_flags & BGE_FLAG_PCIE)
2468 write_op = bge_writemem_direct;
2470 write_op = bge_writemem_ind;
2472 write_op = bge_writereg_ind;
2475 /* Save some important PCI state. */
2476 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2477 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2478 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2480 pci_write_config(dev, BGE_PCI_MISC_CTL,
2481 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2482 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2484 /* Disable fastboot on controllers that support it. */
2485 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2486 BGE_IS_5755_PLUS(sc)) {
2488 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2489 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2493 * Write the magic number to SRAM at offset 0xB50.
2494 * When firmware finishes its initialization it will
2495 * write ~BGE_MAGIC_NUMBER to the same location.
2497 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2499 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2501 /* XXX: Broadcom Linux driver. */
2502 if (sc->bge_flags & BGE_FLAG_PCIE) {
2503 if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */
2504 CSR_WRITE_4(sc, 0x7e2c, 0x20);
2505 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2506 /* Prevent PCIE link training during global reset */
2507 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2513 * Set GPHY Power Down Override to leave GPHY
2514 * powered up in D0 uninitialized.
2516 if (BGE_IS_5705_PLUS(sc))
2517 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2519 /* Issue global reset */
2520 write_op(sc, BGE_MISC_CFG, reset);
2522 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2523 uint32_t status, ctrl;
2525 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2526 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2527 status | BGE_VCPU_STATUS_DRV_RESET);
2528 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2529 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2530 ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2535 /* XXX: Broadcom Linux driver. */
2536 if (sc->bge_flags & BGE_FLAG_PCIE) {
2537 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2540 DELAY(500000); /* wait for link training to complete */
2541 v = pci_read_config(dev, 0xc4, 4);
2542 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2545 * Set PCIE max payload size to 128 bytes and
2546 * clear error status.
2548 pci_write_config(dev, 0xd8, 0xf5000, 4);
2551 /* Reset some of the PCI state that got zapped by reset */
2552 pci_write_config(dev, BGE_PCI_MISC_CTL,
2553 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2554 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2555 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2556 pci_write_config(dev, BGE_PCI_CMD, command, 4);
2557 write_op(sc, BGE_MISC_CFG, (65 << 1));
2560 * Disable PCI-X relaxed ordering to ensure status block update
2561 * comes first then packet buffer DMA. Otherwise driver may
2562 * read stale status block.
2564 if (sc->bge_flags & BGE_FLAG_PCIX) {
2567 devctl = pci_read_config(dev,
2568 sc->bge_pcixcap + PCIXR_COMMAND, 2);
2569 devctl &= ~PCIXM_COMMAND_ERO;
2570 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
2571 devctl &= ~PCIXM_COMMAND_MAX_READ;
2572 devctl |= PCIXM_COMMAND_MAX_READ_2048;
2573 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2574 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
2575 PCIXM_COMMAND_MAX_READ);
2576 devctl |= PCIXM_COMMAND_MAX_READ_2048;
2578 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
2582 /* Enable memory arbiter. */
2583 if (BGE_IS_5714_FAMILY(sc)) {
2586 val = CSR_READ_4(sc, BGE_MARB_MODE);
2587 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2589 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2592 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2593 for (i = 0; i < BGE_TIMEOUT; i++) {
2594 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2595 if (val & BGE_VCPU_STATUS_INIT_DONE)
2599 if (i == BGE_TIMEOUT) {
2600 if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2605 * Poll until we see the 1's complement of the magic number.
2606 * This indicates that the firmware initialization
2609 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
2610 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2611 if (val == ~BGE_MAGIC_NUMBER)
2615 if (i == BGE_FIRMWARE_TIMEOUT) {
2616 if_printf(&sc->arpcom.ac_if, "firmware handshake "
2617 "timed out, found 0x%08x\n", val);
2623 * XXX Wait for the value of the PCISTATE register to
2624 * return to its original pre-reset state. This is a
2625 * fairly good indicator of reset completion. If we don't
2626 * wait for the reset to fully complete, trying to read
2627 * from the device's non-PCI registers may yield garbage
2630 for (i = 0; i < BGE_TIMEOUT; i++) {
2631 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2636 /* Fix up byte swapping */
2637 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2638 BGE_MODECTL_BYTESWAP_DATA);
2640 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2643 * The 5704 in TBI mode apparently needs some special
2644 * adjustment to insure the SERDES drive level is set
2647 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2648 (sc->bge_flags & BGE_FLAG_TBI)) {
2651 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2652 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2653 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2656 /* XXX: Broadcom Linux driver. */
2657 if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2658 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
2659 sc->bge_asicrev != BGE_ASICREV_BCM5785) {
2662 /* Enable Data FIFO protection. */
2663 v = CSR_READ_4(sc, 0x7c00);
2664 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2671 * Frame reception handling. This is called if there's a frame
2672 * on the receive return list.
2674 * Note: we have to be able to handle two possibilities here:
2675 * 1) the frame is from the jumbo recieve ring
2676 * 2) the frame is from the standard receive ring
2680 bge_rxeof(struct bge_softc *sc)
2683 int stdcnt = 0, jumbocnt = 0;
2685 if (sc->bge_rx_saved_considx ==
2686 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2689 ifp = &sc->arpcom.ac_if;
2691 while (sc->bge_rx_saved_considx !=
2692 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2693 struct bge_rx_bd *cur_rx;
2695 struct mbuf *m = NULL;
2696 uint16_t vlan_tag = 0;
2700 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2702 rxidx = cur_rx->bge_idx;
2703 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2706 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2708 vlan_tag = cur_rx->bge_vlan_tag;
2711 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2712 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2715 if (rxidx != sc->bge_jumbo) {
2717 if_printf(ifp, "sw jumbo index(%d) "
2718 "and hw jumbo index(%d) mismatch, drop!\n",
2719 sc->bge_jumbo, rxidx);
2720 bge_setup_rxdesc_jumbo(sc, rxidx);
2724 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf;
2725 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2727 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2730 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) {
2732 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2736 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2739 if (rxidx != sc->bge_std) {
2741 if_printf(ifp, "sw std index(%d) "
2742 "and hw std index(%d) mismatch, drop!\n",
2743 sc->bge_std, rxidx);
2744 bge_setup_rxdesc_std(sc, rxidx);
2748 m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf;
2749 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2751 bge_setup_rxdesc_std(sc, sc->bge_std);
2754 if (bge_newbuf_std(sc, sc->bge_std, 0)) {
2756 bge_setup_rxdesc_std(sc, sc->bge_std);
2762 #if !defined(__i386__) && !defined(__x86_64__)
2764 * The x86 allows unaligned accesses, but for other
2765 * platforms we must make sure the payload is aligned.
2767 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2768 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2770 m->m_data += ETHER_ALIGN;
2773 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2774 m->m_pkthdr.rcvif = ifp;
2776 if (ifp->if_capenable & IFCAP_RXCSUM) {
2777 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2778 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2779 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2780 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2782 if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
2783 m->m_pkthdr.len >= BGE_MIN_FRAME) {
2784 m->m_pkthdr.csum_data =
2785 cur_rx->bge_tcp_udp_csum;
2786 m->m_pkthdr.csum_flags |=
2787 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2792 * If we received a packet with a vlan tag, pass it
2793 * to vlan_input() instead of ether_input().
2796 m->m_flags |= M_VLANTAG;
2797 m->m_pkthdr.ether_vlantag = vlan_tag;
2798 have_tag = vlan_tag = 0;
2800 ifp->if_input(ifp, m);
2803 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2805 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2807 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2811 bge_txeof(struct bge_softc *sc)
2813 struct bge_tx_bd *cur_tx = NULL;
2816 if (sc->bge_tx_saved_considx ==
2817 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2820 ifp = &sc->arpcom.ac_if;
2823 * Go through our tx ring and free mbufs for those
2824 * frames that have been sent.
2826 while (sc->bge_tx_saved_considx !=
2827 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2830 idx = sc->bge_tx_saved_considx;
2831 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2832 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2834 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2835 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
2836 sc->bge_cdata.bge_tx_dmamap[idx]);
2837 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2838 sc->bge_cdata.bge_tx_chain[idx] = NULL;
2841 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2845 if (cur_tx != NULL &&
2846 (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2847 (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2848 ifp->if_flags &= ~IFF_OACTIVE;
2850 if (sc->bge_txcnt == 0)
2853 if (!ifq_is_empty(&ifp->if_snd))
2857 #ifdef DEVICE_POLLING
2860 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2862 struct bge_softc *sc = ifp->if_softc;
2867 bge_disable_intr(sc);
2869 case POLL_DEREGISTER:
2870 bge_enable_intr(sc);
2872 case POLL_AND_CHECK_STATUS:
2874 * Process link state changes.
2876 status = CSR_READ_4(sc, BGE_MAC_STS);
2877 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2878 sc->bge_link_evt = 0;
2879 sc->bge_link_upd(sc, status);
2883 if (ifp->if_flags & IFF_RUNNING) {
2896 struct bge_softc *sc = xsc;
2897 struct ifnet *ifp = &sc->arpcom.ac_if;
2903 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
2904 * disable interrupts by writing nonzero like we used to, since with
2905 * our current organization this just gives complications and
2906 * pessimizations for re-enabling interrupts. We used to have races
2907 * instead of the necessary complications. Disabling interrupts
2908 * would just reduce the chance of a status update while we are
2909 * running (by switching to the interrupt-mode coalescence
2910 * parameters), but this chance is already very low so it is more
2911 * efficient to get another interrupt than prevent it.
2913 * We do the ack first to ensure another interrupt if there is a
2914 * status update after the ack. We don't check for the status
2915 * changing later because it is more efficient to get another
2916 * interrupt than prevent it, not quite as above (not checking is
2917 * a smaller optimization than not toggling the interrupt enable,
2918 * since checking doesn't involve PCI accesses and toggling require
2919 * the status check). So toggling would probably be a pessimization
2920 * even with MSI. It would only be needed for using a task queue.
2922 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
2925 * Process link state changes.
2927 status = CSR_READ_4(sc, BGE_MAC_STS);
2928 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2929 sc->bge_link_evt = 0;
2930 sc->bge_link_upd(sc, status);
2933 if (ifp->if_flags & IFF_RUNNING) {
2934 /* Check RX return ring producer/consumer */
2937 /* Check TX ring producer/consumer */
2941 if (sc->bge_coal_chg)
2942 bge_coal_change(sc);
2948 struct bge_softc *sc = xsc;
2949 struct ifnet *ifp = &sc->arpcom.ac_if;
2951 lwkt_serialize_enter(ifp->if_serializer);
2953 if (BGE_IS_5705_PLUS(sc))
2954 bge_stats_update_regs(sc);
2956 bge_stats_update(sc);
2958 if (sc->bge_flags & BGE_FLAG_TBI) {
2960 * Since in TBI mode auto-polling can't be used we should poll
2961 * link status manually. Here we register pending link event
2962 * and trigger interrupt.
2965 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2967 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
2969 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
2970 } else if (!sc->bge_link) {
2971 mii_tick(device_get_softc(sc->bge_miibus));
2974 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2976 lwkt_serialize_exit(ifp->if_serializer);
2980 bge_stats_update_regs(struct bge_softc *sc)
2982 struct ifnet *ifp = &sc->arpcom.ac_if;
2983 struct bge_mac_stats_regs stats;
2987 s = (uint32_t *)&stats;
2988 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2989 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2993 ifp->if_collisions +=
2994 (stats.dot3StatsSingleCollisionFrames +
2995 stats.dot3StatsMultipleCollisionFrames +
2996 stats.dot3StatsExcessiveCollisions +
2997 stats.dot3StatsLateCollisions) -
3002 bge_stats_update(struct bge_softc *sc)
3004 struct ifnet *ifp = &sc->arpcom.ac_if;
3007 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3009 #define READ_STAT(sc, stats, stat) \
3010 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3012 ifp->if_collisions +=
3013 (READ_STAT(sc, stats,
3014 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
3015 READ_STAT(sc, stats,
3016 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
3017 READ_STAT(sc, stats,
3018 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
3019 READ_STAT(sc, stats,
3020 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
3026 ifp->if_collisions +=
3027 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
3028 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
3029 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
3030 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
3036 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
3037 * pointers to descriptors.
3040 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
3042 struct bge_tx_bd *d = NULL;
3043 uint16_t csum_flags = 0;
3044 bus_dma_segment_t segs[BGE_NSEG_NEW];
3046 int error, maxsegs, nsegs, idx, i;
3047 struct mbuf *m_head = *m_head0, *m_new;
3049 if (m_head->m_pkthdr.csum_flags) {
3050 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3051 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3052 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
3053 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3054 if (m_head->m_flags & M_LASTFRAG)
3055 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3056 else if (m_head->m_flags & M_FRAG)
3057 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3061 map = sc->bge_cdata.bge_tx_dmamap[idx];
3063 maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
3064 KASSERT(maxsegs >= BGE_NSEG_SPARE,
3065 ("not enough segments %d", maxsegs));
3067 if (maxsegs > BGE_NSEG_NEW)
3068 maxsegs = BGE_NSEG_NEW;
3071 * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
3072 * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
3073 * but when such padded frames employ the bge IP/TCP checksum
3074 * offload, the hardware checksum assist gives incorrect results
3075 * (possibly from incorporating its own padding into the UDP/TCP
3076 * checksum; who knows). If we pad such runts with zeros, the
3077 * onboard checksum comes out correct.
3079 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
3080 m_head->m_pkthdr.len < BGE_MIN_FRAME) {
3081 error = m_devpad(m_head, BGE_MIN_FRAME);
3086 if ((sc->bge_flags & BGE_FLAG_SHORTDMA) && m_head->m_next != NULL) {
3087 m_new = bge_defrag_shortdma(m_head);
3088 if (m_new == NULL) {
3092 *m_head0 = m_head = m_new;
3094 if (sc->bge_force_defrag && (sc->bge_flags & BGE_FLAG_PCIE) &&
3095 m_head->m_next != NULL) {
3097 * Forcefully defragment mbuf chain to overcome hardware
3098 * limitation which only support a single outstanding
3099 * DMA read operation. If it fails, keep moving on using
3100 * the original mbuf chain.
3102 m_new = m_defrag(m_head, MB_DONTWAIT);
3104 *m_head0 = m_head = m_new;
3107 error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map,
3108 m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3113 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
3115 for (i = 0; ; i++) {
3116 d = &sc->bge_ldata.bge_tx_ring[idx];
3118 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3119 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3120 d->bge_len = segs[i].ds_len;
3121 d->bge_flags = csum_flags;
3125 BGE_INC(idx, BGE_TX_RING_CNT);
3127 /* Mark the last segment as end of packet... */
3128 d->bge_flags |= BGE_TXBDFLAG_END;
3130 /* Set vlan tag to the first segment of the packet. */
3131 d = &sc->bge_ldata.bge_tx_ring[*txidx];
3132 if (m_head->m_flags & M_VLANTAG) {
3133 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3134 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
3136 d->bge_vlan_tag = 0;
3140 * Insure that the map for this transmission is placed at
3141 * the array index of the last descriptor in this chain.
3143 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
3144 sc->bge_cdata.bge_tx_dmamap[idx] = map;
3145 sc->bge_cdata.bge_tx_chain[idx] = m_head;
3146 sc->bge_txcnt += nsegs;
3148 BGE_INC(idx, BGE_TX_RING_CNT);
3159 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3160 * to the mbuf data regions directly in the transmit descriptors.
3163 bge_start(struct ifnet *ifp)
3165 struct bge_softc *sc = ifp->if_softc;
3166 struct mbuf *m_head = NULL;
3170 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
3173 prodidx = sc->bge_tx_prodidx;
3176 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
3177 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3183 * The code inside the if() block is never reached since we
3184 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
3185 * requests to checksum TCP/UDP in a fragmented packet.
3188 * safety overkill. If this is a fragmented packet chain
3189 * with delayed TCP/UDP checksums, then only encapsulate
3190 * it if we have enough descriptors to handle the entire
3192 * (paranoia -- may not actually be needed)
3194 if ((m_head->m_flags & M_FIRSTFRAG) &&
3195 (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
3196 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3197 m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
3198 ifp->if_flags |= IFF_OACTIVE;
3199 ifq_prepend(&ifp->if_snd, m_head);
3205 * Sanity check: avoid coming within BGE_NSEG_RSVD
3206 * descriptors of the end of the ring. Also make
3207 * sure there are BGE_NSEG_SPARE descriptors for
3208 * jumbo buffers' defragmentation.
3210 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3211 (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
3212 ifp->if_flags |= IFF_OACTIVE;
3213 ifq_prepend(&ifp->if_snd, m_head);
3218 * Pack the data into the transmit ring. If we
3219 * don't have room, set the OACTIVE flag and wait
3220 * for the NIC to drain the ring.
3222 if (bge_encap(sc, &m_head, &prodidx)) {
3223 ifp->if_flags |= IFF_OACTIVE;
3229 ETHER_BPF_MTAP(ifp, m_head);
3236 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3237 /* 5700 b2 errata */
3238 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
3239 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3241 sc->bge_tx_prodidx = prodidx;
3244 * Set a timeout in case the chip goes out to lunch.
3252 struct bge_softc *sc = xsc;
3253 struct ifnet *ifp = &sc->arpcom.ac_if;
3257 ASSERT_SERIALIZED(ifp->if_serializer);
3259 /* Cancel pending I/O and flush buffers. */
3265 * Init the various state machines, ring
3266 * control blocks and firmware.
3268 if (bge_blockinit(sc)) {
3269 if_printf(ifp, "initialization failure\n");
3275 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3276 ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3278 /* Load our MAC address. */
3279 m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3280 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3281 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3283 /* Enable or disable promiscuous mode as needed. */
3286 /* Program multicast filter. */
3290 if (bge_init_rx_ring_std(sc)) {
3291 if_printf(ifp, "RX ring initialization failed\n");
3297 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3298 * memory to insure that the chip has in fact read the first
3299 * entry of the ring.
3301 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3303 for (i = 0; i < 10; i++) {
3305 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3306 if (v == (MCLBYTES - ETHER_ALIGN))
3310 if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
3313 /* Init jumbo RX ring. */
3314 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3315 if (bge_init_rx_ring_jumbo(sc)) {
3316 if_printf(ifp, "Jumbo RX ring initialization failed\n");
3322 /* Init our RX return ring index */
3323 sc->bge_rx_saved_considx = 0;
3326 bge_init_tx_ring(sc);
3328 /* Enable TX MAC state machine lockup fix. */
3329 mode = CSR_READ_4(sc, BGE_TX_MODE);
3330 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3331 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3332 /* Turn on transmitter */
3333 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3335 /* Turn on receiver */
3336 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3339 * Set the number of good frames to receive after RX MBUF
3340 * Low Watermark has been reached. After the RX MAC receives
3341 * this number of frames, it will drop subsequent incoming
3342 * frames until the MBUF High Watermark is reached.
3344 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3346 /* Tell firmware we're alive. */
3347 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3349 /* Enable host interrupts if polling(4) is not enabled. */
3350 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
3351 #ifdef DEVICE_POLLING
3352 if (ifp->if_flags & IFF_POLLING)
3353 bge_disable_intr(sc);
3356 bge_enable_intr(sc);
3358 bge_ifmedia_upd(ifp);
3360 ifp->if_flags |= IFF_RUNNING;
3361 ifp->if_flags &= ~IFF_OACTIVE;
3363 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3367 * Set media options.
3370 bge_ifmedia_upd(struct ifnet *ifp)
3372 struct bge_softc *sc = ifp->if_softc;
3374 /* If this is a 1000baseX NIC, enable the TBI port. */
3375 if (sc->bge_flags & BGE_FLAG_TBI) {
3376 struct ifmedia *ifm = &sc->bge_ifmedia;
3378 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3381 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3384 * The BCM5704 ASIC appears to have a special
3385 * mechanism for programming the autoneg
3386 * advertisement registers in TBI mode.
3388 if (!bge_fake_autoneg &&
3389 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3392 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3393 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3394 sgdig |= BGE_SGDIGCFG_AUTO |
3395 BGE_SGDIGCFG_PAUSE_CAP |
3396 BGE_SGDIGCFG_ASYM_PAUSE;
3397 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3398 sgdig | BGE_SGDIGCFG_SEND);
3400 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3404 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3405 BGE_CLRBIT(sc, BGE_MAC_MODE,
3406 BGE_MACMODE_HALF_DUPLEX);
3408 BGE_SETBIT(sc, BGE_MAC_MODE,
3409 BGE_MACMODE_HALF_DUPLEX);
3416 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3420 if (mii->mii_instance) {
3421 struct mii_softc *miisc;
3423 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3424 mii_phy_reset(miisc);
3429 * Force an interrupt so that we will call bge_link_upd
3430 * if needed and clear any pending link state attention.
3431 * Without this we are not getting any further interrupts
3432 * for link state changes and thus will not UP the link and
3433 * not be able to send in bge_start. The only way to get
3434 * things working was to receive a packet and get an RX
3437 * bge_tick should help for fiber cards and we might not
3438 * need to do this here if BGE_FLAG_TBI is set but as
3439 * we poll for fiber anyway it should not harm.
3441 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3443 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3445 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3451 * Report current media status.
3454 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3456 struct bge_softc *sc = ifp->if_softc;
3458 if (sc->bge_flags & BGE_FLAG_TBI) {
3459 ifmr->ifm_status = IFM_AVALID;
3460 ifmr->ifm_active = IFM_ETHER;
3461 if (CSR_READ_4(sc, BGE_MAC_STS) &
3462 BGE_MACSTAT_TBI_PCS_SYNCHED) {
3463 ifmr->ifm_status |= IFM_ACTIVE;
3465 ifmr->ifm_active |= IFM_NONE;
3469 ifmr->ifm_active |= IFM_1000_SX;
3470 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3471 ifmr->ifm_active |= IFM_HDX;
3473 ifmr->ifm_active |= IFM_FDX;
3475 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3478 ifmr->ifm_active = mii->mii_media_active;
3479 ifmr->ifm_status = mii->mii_media_status;
3484 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3486 struct bge_softc *sc = ifp->if_softc;
3487 struct ifreq *ifr = (struct ifreq *)data;
3488 int mask, error = 0;
3490 ASSERT_SERIALIZED(ifp->if_serializer);
3494 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3495 (BGE_IS_JUMBO_CAPABLE(sc) &&
3496 ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3498 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3499 ifp->if_mtu = ifr->ifr_mtu;
3500 if (ifp->if_flags & IFF_RUNNING)
3505 if (ifp->if_flags & IFF_UP) {
3506 if (ifp->if_flags & IFF_RUNNING) {
3507 mask = ifp->if_flags ^ sc->bge_if_flags;
3510 * If only the state of the PROMISC flag
3511 * changed, then just use the 'set promisc
3512 * mode' command instead of reinitializing
3513 * the entire NIC. Doing a full re-init
3514 * means reloading the firmware and waiting
3515 * for it to start up, which may take a
3516 * second or two. Similarly for ALLMULTI.
3518 if (mask & IFF_PROMISC)
3520 if (mask & IFF_ALLMULTI)
3525 } else if (ifp->if_flags & IFF_RUNNING) {
3528 sc->bge_if_flags = ifp->if_flags;
3532 if (ifp->if_flags & IFF_RUNNING)
3537 if (sc->bge_flags & BGE_FLAG_TBI) {
3538 error = ifmedia_ioctl(ifp, ifr,
3539 &sc->bge_ifmedia, command);
3541 struct mii_data *mii;
3543 mii = device_get_softc(sc->bge_miibus);
3544 error = ifmedia_ioctl(ifp, ifr,
3545 &mii->mii_media, command);
3549 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3550 if (mask & IFCAP_HWCSUM) {
3551 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3552 if (IFCAP_HWCSUM & ifp->if_capenable)
3553 ifp->if_hwassist = BGE_CSUM_FEATURES;
3555 ifp->if_hwassist = 0;
3559 error = ether_ioctl(ifp, command, data);
3566 bge_watchdog(struct ifnet *ifp)
3568 struct bge_softc *sc = ifp->if_softc;
3570 if_printf(ifp, "watchdog timeout -- resetting\n");
3576 if (!ifq_is_empty(&ifp->if_snd))
3581 * Stop the adapter and free any mbufs allocated to the
3585 bge_stop(struct bge_softc *sc)
3587 struct ifnet *ifp = &sc->arpcom.ac_if;
3589 ASSERT_SERIALIZED(ifp->if_serializer);
3591 callout_stop(&sc->bge_stat_timer);
3594 * Disable all of the receiver blocks
3596 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3597 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3598 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3599 if (BGE_IS_5700_FAMILY(sc))
3600 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3601 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3602 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3603 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3606 * Disable all of the transmit blocks
3608 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3609 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3610 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3611 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3612 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3613 if (BGE_IS_5700_FAMILY(sc))
3614 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3615 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3618 * Shut down all of the memory managers and related
3621 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3622 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3623 if (BGE_IS_5700_FAMILY(sc))
3624 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3625 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3626 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3627 if (!BGE_IS_5705_PLUS(sc)) {
3628 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3629 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3632 /* Disable host interrupts. */
3633 bge_disable_intr(sc);
3636 * Tell firmware we're shutting down.
3638 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3640 /* Free the RX lists. */
3641 bge_free_rx_ring_std(sc);
3643 /* Free jumbo RX list. */
3644 if (BGE_IS_JUMBO_CAPABLE(sc))
3645 bge_free_rx_ring_jumbo(sc);
3647 /* Free TX buffers. */
3648 bge_free_tx_ring(sc);
3651 sc->bge_coal_chg = 0;
3653 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3655 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3660 * Stop all chip I/O so that the kernel's probe routines don't
3661 * get confused by errant DMAs when rebooting.
3664 bge_shutdown(device_t dev)
3666 struct bge_softc *sc = device_get_softc(dev);
3667 struct ifnet *ifp = &sc->arpcom.ac_if;
3669 lwkt_serialize_enter(ifp->if_serializer);
3672 lwkt_serialize_exit(ifp->if_serializer);
3676 bge_suspend(device_t dev)
3678 struct bge_softc *sc = device_get_softc(dev);
3679 struct ifnet *ifp = &sc->arpcom.ac_if;
3681 lwkt_serialize_enter(ifp->if_serializer);
3683 lwkt_serialize_exit(ifp->if_serializer);
3689 bge_resume(device_t dev)
3691 struct bge_softc *sc = device_get_softc(dev);
3692 struct ifnet *ifp = &sc->arpcom.ac_if;
3694 lwkt_serialize_enter(ifp->if_serializer);
3696 if (ifp->if_flags & IFF_UP) {
3699 if (!ifq_is_empty(&ifp->if_snd))
3703 lwkt_serialize_exit(ifp->if_serializer);
3709 bge_setpromisc(struct bge_softc *sc)
3711 struct ifnet *ifp = &sc->arpcom.ac_if;
3713 if (ifp->if_flags & IFF_PROMISC)
3714 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3716 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3720 bge_dma_free(struct bge_softc *sc)
3724 /* Destroy RX mbuf DMA stuffs. */
3725 if (sc->bge_cdata.bge_rx_mtag != NULL) {
3726 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3727 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3728 sc->bge_cdata.bge_rx_std_dmamap[i]);
3730 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3731 sc->bge_cdata.bge_rx_tmpmap);
3732 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3735 /* Destroy TX mbuf DMA stuffs. */
3736 if (sc->bge_cdata.bge_tx_mtag != NULL) {
3737 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3738 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3739 sc->bge_cdata.bge_tx_dmamap[i]);
3741 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3744 /* Destroy standard RX ring */
3745 bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3746 sc->bge_cdata.bge_rx_std_ring_map,
3747 sc->bge_ldata.bge_rx_std_ring);
3749 if (BGE_IS_JUMBO_CAPABLE(sc))
3750 bge_free_jumbo_mem(sc);
3752 /* Destroy RX return ring */
3753 bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3754 sc->bge_cdata.bge_rx_return_ring_map,
3755 sc->bge_ldata.bge_rx_return_ring);
3757 /* Destroy TX ring */
3758 bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3759 sc->bge_cdata.bge_tx_ring_map,
3760 sc->bge_ldata.bge_tx_ring);
3762 /* Destroy status block */
3763 bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3764 sc->bge_cdata.bge_status_map,
3765 sc->bge_ldata.bge_status_block);
3767 /* Destroy statistics block */
3768 bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3769 sc->bge_cdata.bge_stats_map,
3770 sc->bge_ldata.bge_stats);
3772 /* Destroy the parent tag */
3773 if (sc->bge_cdata.bge_parent_tag != NULL)
3774 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3778 bge_dma_alloc(struct bge_softc *sc)
3780 struct ifnet *ifp = &sc->arpcom.ac_if;
3784 lowaddr = BUS_SPACE_MAXADDR;
3785 if (sc->bge_flags & BGE_FLAG_MAXADDR_40BIT)
3786 lowaddr = BGE_DMA_MAXADDR_40BIT;
3789 * Allocate the parent bus DMA tag appropriate for PCI.
3791 * All of the NetExtreme/NetLink controllers have 4GB boundary
3793 * Whenever an address crosses a multiple of the 4GB boundary
3794 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3795 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3796 * state machine will lockup and cause the device to hang.
3798 error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
3799 lowaddr, BUS_SPACE_MAXADDR,
3801 BUS_SPACE_MAXSIZE_32BIT, 0,
3802 BUS_SPACE_MAXSIZE_32BIT,
3803 0, &sc->bge_cdata.bge_parent_tag);
3805 if_printf(ifp, "could not allocate parent dma tag\n");
3810 * Create DMA tag and maps for RX mbufs.
3812 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3813 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3814 NULL, NULL, MCLBYTES, 1, MCLBYTES,
3815 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3816 &sc->bge_cdata.bge_rx_mtag);
3818 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
3822 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3823 BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_tmpmap);
3825 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3826 sc->bge_cdata.bge_rx_mtag = NULL;
3830 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3831 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3833 &sc->bge_cdata.bge_rx_std_dmamap[i]);
3837 for (j = 0; j < i; ++j) {
3838 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3839 sc->bge_cdata.bge_rx_std_dmamap[j]);
3841 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3842 sc->bge_cdata.bge_rx_mtag = NULL;
3844 if_printf(ifp, "could not create DMA map for RX\n");
3850 * Create DMA tag and maps for TX mbufs.
3852 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3853 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3855 BGE_JUMBO_FRAMELEN, BGE_NSEG_NEW, MCLBYTES,
3856 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
3858 &sc->bge_cdata.bge_tx_mtag);
3860 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
3864 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3865 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag,
3866 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
3867 &sc->bge_cdata.bge_tx_dmamap[i]);
3871 for (j = 0; j < i; ++j) {
3872 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3873 sc->bge_cdata.bge_tx_dmamap[j]);
3875 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3876 sc->bge_cdata.bge_tx_mtag = NULL;
3878 if_printf(ifp, "could not create DMA map for TX\n");
3884 * Create DMA stuffs for standard RX ring.
3886 error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3887 &sc->bge_cdata.bge_rx_std_ring_tag,
3888 &sc->bge_cdata.bge_rx_std_ring_map,
3889 (void *)&sc->bge_ldata.bge_rx_std_ring,
3890 &sc->bge_ldata.bge_rx_std_ring_paddr);
3892 if_printf(ifp, "could not create std RX ring\n");
3897 * Create jumbo buffer pool.
3899 if (BGE_IS_JUMBO_CAPABLE(sc)) {
3900 error = bge_alloc_jumbo_mem(sc);
3902 if_printf(ifp, "could not create jumbo buffer pool\n");
3908 * Create DMA stuffs for RX return ring.
3910 error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3911 &sc->bge_cdata.bge_rx_return_ring_tag,
3912 &sc->bge_cdata.bge_rx_return_ring_map,
3913 (void *)&sc->bge_ldata.bge_rx_return_ring,
3914 &sc->bge_ldata.bge_rx_return_ring_paddr);
3916 if_printf(ifp, "could not create RX ret ring\n");
3921 * Create DMA stuffs for TX ring.
3923 error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
3924 &sc->bge_cdata.bge_tx_ring_tag,
3925 &sc->bge_cdata.bge_tx_ring_map,
3926 (void *)&sc->bge_ldata.bge_tx_ring,
3927 &sc->bge_ldata.bge_tx_ring_paddr);
3929 if_printf(ifp, "could not create TX ring\n");
3934 * Create DMA stuffs for status block.
3936 error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3937 &sc->bge_cdata.bge_status_tag,
3938 &sc->bge_cdata.bge_status_map,
3939 (void *)&sc->bge_ldata.bge_status_block,
3940 &sc->bge_ldata.bge_status_block_paddr);
3942 if_printf(ifp, "could not create status block\n");
3947 * Create DMA stuffs for statistics block.
3949 error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
3950 &sc->bge_cdata.bge_stats_tag,
3951 &sc->bge_cdata.bge_stats_map,
3952 (void *)&sc->bge_ldata.bge_stats,
3953 &sc->bge_ldata.bge_stats_paddr);
3955 if_printf(ifp, "could not create stats block\n");
3962 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3963 bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3968 error = bus_dmamem_coherent(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
3969 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3970 size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3974 *tag = dmem.dmem_tag;
3975 *map = dmem.dmem_map;
3976 *addr = dmem.dmem_addr;
3977 *paddr = dmem.dmem_busaddr;
3983 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3986 bus_dmamap_unload(tag, map);
3987 bus_dmamem_free(tag, addr, map);
3988 bus_dma_tag_destroy(tag);
3993 * Grrr. The link status word in the status block does
3994 * not work correctly on the BCM5700 rev AX and BX chips,
3995 * according to all available information. Hence, we have
3996 * to enable MII interrupts in order to properly obtain
3997 * async link changes. Unfortunately, this also means that
3998 * we have to read the MAC status register to detect link
3999 * changes, thereby adding an additional register access to
4000 * the interrupt handler.
4002 * XXX: perhaps link state detection procedure used for
4003 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
4006 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
4008 struct ifnet *ifp = &sc->arpcom.ac_if;
4009 struct mii_data *mii = device_get_softc(sc->bge_miibus);
4013 if (!sc->bge_link &&
4014 (mii->mii_media_status & IFM_ACTIVE) &&
4015 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4018 if_printf(ifp, "link UP\n");
4019 } else if (sc->bge_link &&
4020 (!(mii->mii_media_status & IFM_ACTIVE) ||
4021 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4024 if_printf(ifp, "link DOWN\n");
4027 /* Clear the interrupt. */
4028 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
4029 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
4030 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
4034 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
4036 struct ifnet *ifp = &sc->arpcom.ac_if;
4038 #define PCS_ENCODE_ERR (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
4041 * Sometimes PCS encoding errors are detected in
4042 * TBI mode (on fiber NICs), and for some reason
4043 * the chip will signal them as link changes.
4044 * If we get a link change event, but the 'PCS
4045 * encoding error' bit in the MAC status register
4046 * is set, don't bother doing a link check.
4047 * This avoids spurious "gigabit link up" messages
4048 * that sometimes appear on fiber NICs during
4049 * periods of heavy traffic.
4051 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4052 if (!sc->bge_link) {
4054 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4055 BGE_CLRBIT(sc, BGE_MAC_MODE,
4056 BGE_MACMODE_TBI_SEND_CFGS);
4058 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4061 if_printf(ifp, "link UP\n");
4063 ifp->if_link_state = LINK_STATE_UP;
4064 if_link_state_change(ifp);
4066 } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
4071 if_printf(ifp, "link DOWN\n");
4073 ifp->if_link_state = LINK_STATE_DOWN;
4074 if_link_state_change(ifp);
4078 #undef PCS_ENCODE_ERR
4080 /* Clear the attention. */
4081 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4082 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4083 BGE_MACSTAT_LINK_CHANGED);
4087 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
4089 struct ifnet *ifp = &sc->arpcom.ac_if;
4090 struct mii_data *mii = device_get_softc(sc->bge_miibus);
4093 bge_miibus_statchg(sc->bge_dev);
4097 if_printf(ifp, "link UP\n");
4099 if_printf(ifp, "link DOWN\n");
4102 /* Clear the attention. */
4103 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4104 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4105 BGE_MACSTAT_LINK_CHANGED);
4109 bge_autopoll_link_upd(struct bge_softc *sc, uint32_t status __unused)
4111 struct ifnet *ifp = &sc->arpcom.ac_if;
4112 struct mii_data *mii = device_get_softc(sc->bge_miibus);
4116 if (!sc->bge_link &&
4117 (mii->mii_media_status & IFM_ACTIVE) &&
4118 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4121 if_printf(ifp, "link UP\n");
4122 } else if (sc->bge_link &&
4123 (!(mii->mii_media_status & IFM_ACTIVE) ||
4124 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4127 if_printf(ifp, "link DOWN\n");
4130 /* Clear the attention. */
4131 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4132 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4133 BGE_MACSTAT_LINK_CHANGED);
4137 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
4139 struct bge_softc *sc = arg1;
4141 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4142 &sc->bge_rx_coal_ticks,
4143 BGE_RX_COAL_TICKS_CHG);
4147 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
4149 struct bge_softc *sc = arg1;
4151 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4152 &sc->bge_tx_coal_ticks,
4153 BGE_TX_COAL_TICKS_CHG);
4157 bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS)
4159 struct bge_softc *sc = arg1;
4161 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4162 &sc->bge_rx_max_coal_bds,
4163 BGE_RX_MAX_COAL_BDS_CHG);
4167 bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS)
4169 struct bge_softc *sc = arg1;
4171 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4172 &sc->bge_tx_max_coal_bds,
4173 BGE_TX_MAX_COAL_BDS_CHG);
4177 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
4178 uint32_t coal_chg_mask)
4180 struct bge_softc *sc = arg1;
4181 struct ifnet *ifp = &sc->arpcom.ac_if;
4184 lwkt_serialize_enter(ifp->if_serializer);
4187 error = sysctl_handle_int(oidp, &v, 0, req);
4188 if (!error && req->newptr != NULL) {
4193 sc->bge_coal_chg |= coal_chg_mask;
4197 lwkt_serialize_exit(ifp->if_serializer);
4202 bge_coal_change(struct bge_softc *sc)
4204 struct ifnet *ifp = &sc->arpcom.ac_if;
4207 ASSERT_SERIALIZED(ifp->if_serializer);
4209 if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
4210 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
4211 sc->bge_rx_coal_ticks);
4213 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
4216 if_printf(ifp, "rx_coal_ticks -> %u\n",
4217 sc->bge_rx_coal_ticks);
4221 if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
4222 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
4223 sc->bge_tx_coal_ticks);
4225 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
4228 if_printf(ifp, "tx_coal_ticks -> %u\n",
4229 sc->bge_tx_coal_ticks);
4233 if (sc->bge_coal_chg & BGE_RX_MAX_COAL_BDS_CHG) {
4234 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
4235 sc->bge_rx_max_coal_bds);
4237 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
4240 if_printf(ifp, "rx_max_coal_bds -> %u\n",
4241 sc->bge_rx_max_coal_bds);
4245 if (sc->bge_coal_chg & BGE_TX_MAX_COAL_BDS_CHG) {
4246 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
4247 sc->bge_tx_max_coal_bds);
4249 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
4252 if_printf(ifp, "tx_max_coal_bds -> %u\n",
4253 sc->bge_tx_max_coal_bds);
4257 sc->bge_coal_chg = 0;
4261 bge_enable_intr(struct bge_softc *sc)
4263 struct ifnet *ifp = &sc->arpcom.ac_if;
4265 lwkt_serialize_handler_enable(ifp->if_serializer);
4270 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4273 * Unmask the interrupt when we stop polling.
4275 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4278 * Trigger another interrupt, since above writing
4279 * to interrupt mailbox0 may acknowledge pending
4282 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4286 bge_disable_intr(struct bge_softc *sc)
4288 struct ifnet *ifp = &sc->arpcom.ac_if;
4291 * Mask the interrupt when we start polling.
4293 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4296 * Acknowledge possible asserted interrupt.
4298 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4300 lwkt_serialize_handler_disable(ifp->if_serializer);
4304 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
4309 mac_addr = bge_readmem_ind(sc, 0x0c14);
4310 if ((mac_addr >> 16) == 0x484b) {
4311 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4312 ether_addr[1] = (uint8_t)mac_addr;
4313 mac_addr = bge_readmem_ind(sc, 0x0c18);
4314 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4315 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4316 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4317 ether_addr[5] = (uint8_t)mac_addr;
4324 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
4326 int mac_offset = BGE_EE_MAC_OFFSET;
4328 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
4329 mac_offset = BGE_EE_MAC_OFFSET_5906;
4331 return bge_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4335 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
4337 if (sc->bge_flags & BGE_FLAG_NO_EEPROM)
4340 return bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4345 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
4347 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
4348 /* NOTE: Order is critical */
4350 bge_get_eaddr_nvram,
4351 bge_get_eaddr_eeprom,
4354 const bge_eaddr_fcn_t *func;
4356 for (func = bge_eaddr_funcs; *func != NULL; ++func) {
4357 if ((*func)(sc, eaddr) == 0)
4360 return (*func == NULL ? ENXIO : 0);
4364 * NOTE: 'm' is not freed upon failure
4367 bge_defrag_shortdma(struct mbuf *m)
4373 * If device receive two back-to-back send BDs with less than
4374 * or equal to 8 total bytes then the device may hang. The two
4375 * back-to-back send BDs must in the same frame for this failure
4376 * to occur. Scan mbuf chains and see whether two back-to-back
4377 * send BDs are there. If this is the case, allocate new mbuf
4378 * and copy the frame to workaround the silicon bug.
4380 for (n = m, found = 0; n != NULL; n = n->m_next) {
4391 n = m_defrag(m, MB_DONTWAIT);
4398 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
4402 BGE_CLRBIT(sc, reg, bit);
4403 for (i = 0; i < BGE_TIMEOUT; i++) {
4404 if ((CSR_READ_4(sc, reg) & bit) == 0)