3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.99 2008/10/30 11:27:40 sephe Exp $
40 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
42 * Written by Bill Paul <wpaul@windriver.com>
43 * Senior Networking Software Engineer
48 * This driver is designed to support RealTek's next generation of
49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
50 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
51 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
54 * with the older 8139 family, however it also supports a special
55 * C+ mode of operation that provides several new performance enhancing
56 * features. These include:
58 * o Descriptor based DMA mechanism. Each descriptor represents
59 * a single packet fragment. Data buffers may be aligned on
64 * o TCP/IP checksum offload for both RX and TX
66 * o High and normal priority transmit DMA rings
68 * o VLAN tag insertion and extraction
70 * o TCP large send (segmentation offload)
72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
73 * programming API is fairly straightforward. The RX filtering, EEPROM
74 * access and PHY access is the same as it is on the older 8139 series
77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
78 * same programming API and feature set as the 8139C+ with the following
79 * differences and additions:
85 * o GMII and TBI ports/registers for interfacing with copper
88 * o RX and TX DMA rings can have up to 1024 descriptors
89 * (the 8139C+ allows a maximum of 64)
91 * o Slight differences in register layout from the 8139C+
93 * The TX start and timer interrupt registers are at different locations
94 * on the 8169 than they are on the 8139C+. Also, the status word in the
95 * RX descriptor has a slightly different bit layout. The 8169 does not
96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
100 * (the 'S' stands for 'single-chip'). These devices have the same
101 * programming API as the older 8169, but also have some vendor-specific
102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
105 * This driver takes advantage of the RX and TX checksum offload and
106 * VLAN tag insertion/extraction features. It also implements TX
107 * interrupt moderation using the timer interrupt registers, which
108 * significantly reduces TX interrupt load. There is also support
109 * for jumbo frames, however the 8169/8169S/8110S can not transmit
110 * jumbo frames larger than 7440, so the max MTU possible with this
111 * driver is 7422 bytes.
116 #include "opt_polling.h"
118 #include <sys/param.h>
120 #include <sys/endian.h>
121 #include <sys/kernel.h>
122 #include <sys/in_cksum.h>
123 #include <sys/interrupt.h>
124 #include <sys/malloc.h>
125 #include <sys/mbuf.h>
126 #include <sys/rman.h>
127 #include <sys/serialize.h>
128 #include <sys/socket.h>
129 #include <sys/sockio.h>
130 #include <sys/sysctl.h>
133 #include <net/ethernet.h>
135 #include <net/ifq_var.h>
136 #include <net/if_arp.h>
137 #include <net/if_dl.h>
138 #include <net/if_media.h>
139 #include <net/if_types.h>
140 #include <net/vlan/if_vlan_var.h>
141 #include <net/vlan/if_vlan_ether.h>
143 #include <netinet/ip.h>
145 #include <dev/netif/mii_layer/mii.h>
146 #include <dev/netif/mii_layer/miivar.h>
148 #include <bus/pci/pcidevs.h>
149 #include <bus/pci/pcireg.h>
150 #include <bus/pci/pcivar.h>
152 /* "device miibus" required. See GENERIC if you get errors here. */
153 #include "miibus_if.h"
155 #include <dev/netif/re/if_rereg.h>
156 #include <dev/netif/re/if_revar.h>
158 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
161 * Various supported device vendors/types and their names.
163 static const struct re_type {
168 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T,
169 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
171 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139,
172 "RealTek 8139C+ 10/100BaseTX" },
174 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E,
175 "RealTek 810x PCIe 10/100baseTX" },
177 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168,
178 "RealTek 8111/8168 PCIe Gigabit Ethernet" },
180 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169,
181 "RealTek 8110/8169 Gigabit Ethernet" },
183 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC,
184 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
186 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT,
187 "Corega CG-LAPCIGT Gigabit Ethernet" },
189 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032,
190 "Linksys EG1032 Gigabit Ethernet" },
192 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902,
193 "US Robotics 997902 Gigabit Ethernet" },
195 { PCI_VENDOR_TTTECH, PCI_PRODUCT_TTTECH_MC322,
196 "TTTech MC322 Gigabit Ethernet" },
201 static const struct re_hwrev re_hwrevs[] = {
202 { RE_HWREV_8139CPLUS, RE_MACVER_UNKN, ETHERMTU,
203 RE_C_HWCSUM | RE_C_8139CP | RE_C_FASTE },
205 { RE_HWREV_8169, RE_MACVER_UNKN, ETHERMTU,
206 RE_C_HWCSUM | RE_C_8169 },
208 { RE_HWREV_8110S, RE_MACVER_03, RE_MTU_6K,
209 RE_C_HWCSUM | RE_C_8169 },
211 { RE_HWREV_8169S, RE_MACVER_03, RE_MTU_6K,
212 RE_C_HWCSUM | RE_C_8169 },
214 { RE_HWREV_8169SB, RE_MACVER_04, RE_MTU_6K,
215 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 },
217 { RE_HWREV_8169SC1, RE_MACVER_05, RE_MTU_6K,
218 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 },
220 { RE_HWREV_8169SC2, RE_MACVER_06, RE_MTU_6K,
221 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 },
223 { RE_HWREV_8168B1, RE_MACVER_21, RE_MTU_6K,
224 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT },
226 { RE_HWREV_8168B2, RE_MACVER_23, RE_MTU_6K,
227 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD },
229 { RE_HWREV_8168B3, RE_MACVER_23, RE_MTU_6K,
230 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD },
232 { RE_HWREV_8168C, RE_MACVER_29, RE_MTU_6K,
233 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
234 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
236 { RE_HWREV_8168CP, RE_MACVER_2B, RE_MTU_6K,
237 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
238 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
240 { RE_HWREV_8168D, RE_MACVER_2A, RE_MTU_9K,
241 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
242 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
244 { RE_HWREV_8168DP, RE_MACVER_2D, RE_MTU_9K,
245 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
246 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
248 { RE_HWREV_8168E, RE_MACVER_UNKN, RE_MTU_9K,
249 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
250 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
252 { RE_HWREV_8100E, RE_MACVER_UNKN, ETHERMTU,
253 RE_C_HWCSUM | RE_C_FASTE },
255 { RE_HWREV_8101E1, RE_MACVER_16, ETHERMTU,
256 RE_C_HWCSUM | RE_C_FASTE },
258 { RE_HWREV_8101E2, RE_MACVER_16, ETHERMTU,
259 RE_C_HWCSUM | RE_C_FASTE },
261 { RE_HWREV_8102E, RE_MACVER_15, ETHERMTU,
262 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX |
265 { RE_HWREV_8102EL, RE_MACVER_15, ETHERMTU,
266 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX |
269 { RE_HWREV_NULL, 0, 0, 0 }
272 static int re_probe(device_t);
273 static int re_attach(device_t);
274 static int re_detach(device_t);
275 static int re_suspend(device_t);
276 static int re_resume(device_t);
277 static void re_shutdown(device_t);
279 static int re_allocmem(device_t);
280 static void re_freemem(device_t);
281 static void re_freebufmem(struct re_softc *, int, int);
282 static int re_encap(struct re_softc *, struct mbuf **, int *);
283 static int re_newbuf_std(struct re_softc *, int, int);
284 static int re_newbuf_jumbo(struct re_softc *, int, int);
285 static void re_setup_rxdesc(struct re_softc *, int);
286 static int re_rx_list_init(struct re_softc *);
287 static int re_tx_list_init(struct re_softc *);
288 static int re_rxeof(struct re_softc *);
289 static int re_txeof(struct re_softc *);
290 static int re_tx_collect(struct re_softc *);
291 static void re_intr(void *);
292 static void re_tick(void *);
293 static void re_tick_serialized(void *);
295 static void re_start(struct ifnet *);
296 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
297 static void re_init(void *);
298 static void re_stop(struct re_softc *);
299 static void re_watchdog(struct ifnet *);
300 static int re_ifmedia_upd(struct ifnet *);
301 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *);
303 static void re_eeprom_putbyte(struct re_softc *, int);
304 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *);
305 static void re_read_eeprom(struct re_softc *, caddr_t, int, int);
306 static void re_get_eewidth(struct re_softc *);
308 static int re_gmii_readreg(device_t, int, int);
309 static int re_gmii_writereg(device_t, int, int, int);
311 static int re_miibus_readreg(device_t, int, int);
312 static int re_miibus_writereg(device_t, int, int, int);
313 static void re_miibus_statchg(device_t);
315 static void re_setmulti(struct re_softc *);
316 static void re_reset(struct re_softc *, int);
317 static void re_get_eaddr(struct re_softc *, uint8_t *);
319 static void re_setup_hw_im(struct re_softc *);
320 static void re_setup_sim_im(struct re_softc *);
321 static void re_disable_hw_im(struct re_softc *);
322 static void re_disable_sim_im(struct re_softc *);
323 static void re_config_imtype(struct re_softc *, int);
324 static void re_setup_intr(struct re_softc *, int, int);
326 static int re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *);
327 static int re_sysctl_rxtime(SYSCTL_HANDLER_ARGS);
328 static int re_sysctl_txtime(SYSCTL_HANDLER_ARGS);
329 static int re_sysctl_simtime(SYSCTL_HANDLER_ARGS);
330 static int re_sysctl_imtype(SYSCTL_HANDLER_ARGS);
332 static int re_jpool_alloc(struct re_softc *);
333 static void re_jpool_free(struct re_softc *);
334 static struct re_jbuf *re_jbuf_alloc(struct re_softc *);
335 static void re_jbuf_free(void *);
336 static void re_jbuf_ref(void *);
339 static int re_diag(struct re_softc *);
342 #ifdef DEVICE_POLLING
343 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
346 static device_method_t re_methods[] = {
347 /* Device interface */
348 DEVMETHOD(device_probe, re_probe),
349 DEVMETHOD(device_attach, re_attach),
350 DEVMETHOD(device_detach, re_detach),
351 DEVMETHOD(device_suspend, re_suspend),
352 DEVMETHOD(device_resume, re_resume),
353 DEVMETHOD(device_shutdown, re_shutdown),
356 DEVMETHOD(bus_print_child, bus_generic_print_child),
357 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
360 DEVMETHOD(miibus_readreg, re_miibus_readreg),
361 DEVMETHOD(miibus_writereg, re_miibus_writereg),
362 DEVMETHOD(miibus_statchg, re_miibus_statchg),
367 static driver_t re_driver = {
370 sizeof(struct re_softc)
373 static devclass_t re_devclass;
375 DECLARE_DUMMY_MODULE(if_re);
376 MODULE_DEPEND(if_re, miibus, 1, 1, 1);
377 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0);
378 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0);
379 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
381 static int re_rx_desc_count = RE_RX_DESC_CNT_DEF;
382 static int re_tx_desc_count = RE_TX_DESC_CNT_DEF;
384 TUNABLE_INT("hw.re.rx_desc_count", &re_rx_desc_count);
385 TUNABLE_INT("hw.re.tx_desc_count", &re_tx_desc_count);
388 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
391 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
394 re_free_rxchain(struct re_softc *sc)
396 if (sc->re_head != NULL) {
397 m_freem(sc->re_head);
398 sc->re_head = sc->re_tail = NULL;
403 * Send a read command and address to the EEPROM, check for ACK.
406 re_eeprom_putbyte(struct re_softc *sc, int addr)
410 d = addr | (RE_9346_READ << sc->re_eewidth);
413 * Feed in each bit and strobe the clock.
415 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) {
417 EE_SET(RE_EE_DATAIN);
419 EE_CLR(RE_EE_DATAIN);
429 * Read a word of data stored in the EEPROM at address 'addr.'
432 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest)
438 * Send address of word we want to read.
440 re_eeprom_putbyte(sc, addr);
443 * Start reading bits from EEPROM.
445 for (i = 0x8000; i != 0; i >>= 1) {
448 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT)
458 * Read a sequence of words from the EEPROM.
461 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt)
464 uint16_t word = 0, *ptr;
466 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
469 for (i = 0; i < cnt; i++) {
470 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL);
471 re_eeprom_getword(sc, off + i, &word);
472 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL);
473 ptr = (uint16_t *)(dest + (i * 2));
477 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
481 re_get_eewidth(struct re_softc *sc)
486 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
487 if (re_did != 0x8129)
492 re_gmii_readreg(device_t dev, int phy, int reg)
494 struct re_softc *sc = device_get_softc(dev);
501 /* Let the rgephy driver read the GMEDIASTAT register */
503 if (reg == RE_GMEDIASTAT)
504 return(CSR_READ_1(sc, RE_GMEDIASTAT));
506 CSR_WRITE_4(sc, RE_PHYAR, reg << 16);
509 for (i = 0; i < RE_TIMEOUT; i++) {
510 rval = CSR_READ_4(sc, RE_PHYAR);
511 if (rval & RE_PHYAR_BUSY)
516 if (i == RE_TIMEOUT) {
517 device_printf(dev, "PHY read failed\n");
521 return(rval & RE_PHYAR_PHYDATA);
525 re_gmii_writereg(device_t dev, int phy, int reg, int data)
527 struct re_softc *sc = device_get_softc(dev);
531 CSR_WRITE_4(sc, RE_PHYAR,
532 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY);
535 for (i = 0; i < RE_TIMEOUT; i++) {
536 rval = CSR_READ_4(sc, RE_PHYAR);
537 if ((rval & RE_PHYAR_BUSY) == 0)
543 device_printf(dev, "PHY write failed\n");
549 re_miibus_readreg(device_t dev, int phy, int reg)
551 struct re_softc *sc = device_get_softc(dev);
553 uint16_t re8139_reg = 0;
555 if (!RE_IS_8139CP(sc)) {
556 rval = re_gmii_readreg(dev, phy, reg);
560 /* Pretend the internal PHY is only at address 0 */
566 re8139_reg = RE_BMCR;
569 re8139_reg = RE_BMSR;
572 re8139_reg = RE_ANAR;
575 re8139_reg = RE_ANER;
578 re8139_reg = RE_LPAR;
584 * Allow the rlphy driver to read the media status
585 * register. If we have a link partner which does not
586 * support NWAY, this is the register which will tell
587 * us the results of parallel detection.
590 return(CSR_READ_1(sc, RE_MEDIASTAT));
592 device_printf(dev, "bad phy register\n");
595 rval = CSR_READ_2(sc, re8139_reg);
596 if (re8139_reg == RE_BMCR) {
597 /* 8139C+ has different bit layout. */
598 rval &= ~(BMCR_LOOP | BMCR_ISO);
604 re_miibus_writereg(device_t dev, int phy, int reg, int data)
606 struct re_softc *sc= device_get_softc(dev);
607 u_int16_t re8139_reg = 0;
609 if (!RE_IS_8139CP(sc))
610 return(re_gmii_writereg(dev, phy, reg, data));
612 /* Pretend the internal PHY is only at address 0 */
618 re8139_reg = RE_BMCR;
619 /* 8139C+ has different bit layout. */
620 data &= ~(BMCR_LOOP | BMCR_ISO);
623 re8139_reg = RE_BMSR;
626 re8139_reg = RE_ANAR;
629 re8139_reg = RE_ANER;
632 re8139_reg = RE_LPAR;
638 device_printf(dev, "bad phy register\n");
641 CSR_WRITE_2(sc, re8139_reg, data);
646 re_miibus_statchg(device_t dev)
651 * Program the 64-bit multicast hash filter.
654 re_setmulti(struct re_softc *sc)
656 struct ifnet *ifp = &sc->arpcom.ac_if;
658 uint32_t hashes[2] = { 0, 0 };
659 struct ifmultiaddr *ifma;
663 rxfilt = CSR_READ_4(sc, RE_RXCFG);
665 /* Set the individual bit to receive frames for this host only. */
666 rxfilt |= RE_RXCFG_RX_INDIV;
667 /* Set capture broadcast bit to capture broadcast frames. */
668 rxfilt |= RE_RXCFG_RX_BROAD;
670 rxfilt &= ~(RE_RXCFG_RX_ALLPHYS | RE_RXCFG_RX_MULTI);
671 if ((ifp->if_flags & IFF_ALLMULTI) || (ifp->if_flags & IFF_PROMISC)) {
672 rxfilt |= RE_RXCFG_RX_MULTI;
674 /* If we want promiscuous mode, set the allframes bit. */
675 if (ifp->if_flags & IFF_PROMISC)
676 rxfilt |= RE_RXCFG_RX_ALLPHYS;
678 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
679 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF);
680 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF);
684 /* first, zot all the existing hash bits */
685 CSR_WRITE_4(sc, RE_MAR0, 0);
686 CSR_WRITE_4(sc, RE_MAR4, 0);
688 /* now program new ones */
689 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
690 if (ifma->ifma_addr->sa_family != AF_LINK)
692 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
693 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
695 hashes[0] |= (1 << h);
697 hashes[1] |= (1 << (h - 32));
702 rxfilt |= RE_RXCFG_RX_MULTI;
704 rxfilt &= ~RE_RXCFG_RX_MULTI;
706 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
709 * For some unfathomable reason, RealTek decided to reverse
710 * the order of the multicast hash registers in the PCI Express
711 * parts. This means we have to write the hash pattern in reverse
712 * order for those devices.
714 if (sc->re_caps & RE_C_PCIE) {
715 CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[1]));
716 CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[0]));
718 CSR_WRITE_4(sc, RE_MAR0, hashes[0]);
719 CSR_WRITE_4(sc, RE_MAR4, hashes[1]);
724 re_reset(struct re_softc *sc, int running)
728 if ((sc->re_caps & RE_C_STOP_RXTX) && running) {
729 CSR_WRITE_1(sc, RE_COMMAND,
730 RE_CMD_STOPREQ | RE_CMD_TX_ENB | RE_CMD_RX_ENB);
734 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET);
736 for (i = 0; i < RE_TIMEOUT; i++) {
738 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0)
742 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
747 * The following routine is designed to test for a defect on some
748 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
749 * lines connected to the bus, however for a 32-bit only card, they
750 * should be pulled high. The result of this defect is that the
751 * NIC will not work right if you plug it into a 64-bit slot: DMA
752 * operations will be done with 64-bit transfers, which will fail
753 * because the 64-bit data lines aren't connected.
755 * There's no way to work around this (short of talking a soldering
756 * iron to the board), however we can detect it. The method we use
757 * here is to put the NIC into digital loopback mode, set the receiver
758 * to promiscuous mode, and then try to send a frame. We then compare
759 * the frame data we sent to what was received. If the data matches,
760 * then the NIC is working correctly, otherwise we know the user has
761 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
762 * slot. In the latter case, there's no way the NIC can work correctly,
763 * so we print out a message on the console and abort the device attach.
767 re_diag(struct re_softc *sc)
769 struct ifnet *ifp = &sc->arpcom.ac_if;
771 struct ether_header *eh;
772 struct re_desc *cur_rx;
775 int total_len, i, error = 0, phyaddr;
776 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
777 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
779 /* Allocate a single mbuf */
781 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
786 * Initialize the NIC in test mode. This sets the chip up
787 * so that it can send and receive frames, but performs the
788 * following special functions:
789 * - Puts receiver in promiscuous mode
790 * - Enables digital loopback mode
791 * - Leaves interrupts turned off
794 ifp->if_flags |= IFF_PROMISC;
795 sc->re_flags |= RE_F_TESTMODE;
797 sc->re_flags |= RE_F_LINKED;
798 if (!RE_IS_8139CP(sc))
803 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET);
804 for (i = 0; i < RE_TIMEOUT; i++) {
805 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR);
806 if (!(status & BMCR_RESET))
810 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP);
811 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG);
815 /* Put some data in the mbuf */
817 eh = mtod(m0, struct ether_header *);
818 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN);
819 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN);
820 eh->ether_type = htons(ETHERTYPE_IP);
821 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
824 * Queue the packet, start transmission.
825 * Note: ifq_handoff() ultimately calls re_start() for us.
828 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
829 error = ifq_handoff(ifp, m0, NULL);
836 /* Wait for it to propagate through the chip */
839 for (i = 0; i < RE_TIMEOUT; i++) {
840 status = CSR_READ_2(sc, RE_ISR);
841 CSR_WRITE_2(sc, RE_ISR, status);
842 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) ==
843 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK))
848 if (i == RE_TIMEOUT) {
849 if_printf(ifp, "diagnostic failed to receive packet "
850 "in loopback mode\n");
856 * The packet should have been dumped into the first
857 * entry in the RX DMA ring. Grab it from there.
860 bus_dmamap_sync(sc->re_ldata.re_rx_mtag, sc->re_ldata.re_rx_dmamap[0],
861 BUS_DMASYNC_POSTREAD);
862 bus_dmamap_unload(sc->re_ldata.re_rx_mtag,
863 sc->re_ldata.re_rx_dmamap[0]);
865 m0 = sc->re_ldata.re_rx_mbuf[0];
866 sc->re_ldata.re_rx_mbuf[0] = NULL;
867 eh = mtod(m0, struct ether_header *);
869 cur_rx = &sc->re_ldata.re_rx_list[0];
870 total_len = RE_RXBYTES(cur_rx);
871 rxstat = le32toh(cur_rx->re_cmdstat);
873 if (total_len != ETHER_MIN_LEN) {
874 if_printf(ifp, "diagnostic failed, received short packet\n");
879 /* Test that the received packet data matches what we sent. */
881 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) ||
882 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) ||
883 be16toh(eh->ether_type) != ETHERTYPE_IP) {
884 if_printf(ifp, "WARNING, DMA FAILURE!\n");
885 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
886 dst, ":", src, ":", ETHERTYPE_IP);
887 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
888 eh->ether_dhost, ":", eh->ether_shost, ":",
889 ntohs(eh->ether_type));
890 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
891 "into a 64-bit PCI slot.\n");
892 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
893 "for proper operation.\n");
894 if_printf(ifp, "Read the re(4) man page for more details.\n");
899 /* Turn interface off, release resources */
901 sc->re_flags &= ~(RE_F_LINKED | RE_F_TESTMODE);
902 ifp->if_flags &= ~IFF_PROMISC;
912 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
913 * IDs against our list and return a device name if we find a match.
916 re_probe(device_t dev)
918 const struct re_type *t;
919 const struct re_hwrev *hw_rev;
922 uint32_t hwrev, macmode, txcfg;
923 uint16_t vendor, product;
925 vendor = pci_get_vendor(dev);
926 product = pci_get_device(dev);
929 * Only attach to rev.3 of the Linksys EG1032 adapter.
930 * Rev.2 is supported by sk(4).
932 if (vendor == PCI_VENDOR_LINKSYS &&
933 product == PCI_PRODUCT_LINKSYS_EG1032 &&
934 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3)
937 if (vendor == PCI_VENDOR_REALTEK &&
938 product == PCI_PRODUCT_REALTEK_RT8139 &&
939 pci_get_revid(dev) != PCI_REVID_REALTEK_RT8139CP) {
944 for (t = re_devs; t->re_name != NULL; t++) {
945 if (product == t->re_did && vendor == t->re_vid)
950 * Check if we found a RealTek device.
952 if (t->re_name == NULL)
956 * Temporarily map the I/O space so we can read the chip ID register.
958 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO);
960 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
962 if (sc->re_res == NULL) {
963 device_printf(dev, "couldn't map ports/memory\n");
968 sc->re_btag = rman_get_bustag(sc->re_res);
969 sc->re_bhandle = rman_get_bushandle(sc->re_res);
971 txcfg = CSR_READ_4(sc, RE_TXCFG);
972 hwrev = txcfg & RE_TXCFG_HWREV;
973 macmode = txcfg & RE_TXCFG_MACMODE;
974 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res);
978 * and continue matching for the specific chip...
980 for (hw_rev = re_hwrevs; hw_rev->re_hwrev != RE_HWREV_NULL; hw_rev++) {
981 if (hw_rev->re_hwrev == hwrev) {
982 sc = device_get_softc(dev);
984 sc->re_hwrev = hw_rev->re_hwrev;
985 sc->re_macver = hw_rev->re_macver;
986 sc->re_caps = hw_rev->re_caps;
987 sc->re_maxmtu = hw_rev->re_maxmtu;
990 * Apply chip property fixup
992 switch (sc->re_hwrev) {
993 case RE_HWREV_8101E1:
994 case RE_HWREV_8101E2:
996 sc->re_macver = RE_MACVER_11;
997 else if (macmode == 0x200000)
998 sc->re_macver = RE_MACVER_12;
1000 case RE_HWREV_8102E:
1001 case RE_HWREV_8102EL:
1003 sc->re_macver = RE_MACVER_13;
1004 else if (macmode == 0x100000)
1005 sc->re_macver = RE_MACVER_14;
1007 case RE_HWREV_8168B2:
1008 case RE_HWREV_8168B3:
1010 sc->re_macver = RE_MACVER_22;
1012 case RE_HWREV_8168C:
1014 sc->re_macver = RE_MACVER_24;
1015 else if (macmode == 0x200000)
1016 sc->re_macver = RE_MACVER_25;
1017 else if (macmode == 0x300000)
1018 sc->re_macver = RE_MACVER_27;
1020 case RE_HWREV_8168CP:
1022 sc->re_macver = RE_MACVER_26;
1023 else if (macmode == 0x100000)
1024 sc->re_macver = RE_MACVER_28;
1026 case RE_HWREV_8168DP:
1028 sc->re_macver = RE_MACVER_2B;
1029 else if (macmode == 0x200000)
1030 sc->re_macver = RE_MACVER_2C;
1032 case RE_HWREV_8168E:
1033 if (macmode == 0x100000)
1034 sc->re_macver = RE_MACVER_2E;
1035 else if (macmode == 0x200000)
1036 sc->re_macver = RE_MACVER_2F;
1039 if (pci_is_pcie(dev))
1040 sc->re_caps |= RE_C_PCIE;
1042 device_set_desc(dev, t->re_name);
1048 device_printf(dev, "unknown hwrev 0x%08x, macmode 0x%08x\n",
1055 re_allocmem(device_t dev)
1057 struct re_softc *sc = device_get_softc(dev);
1062 * Allocate list data
1064 sc->re_ldata.re_tx_mbuf =
1065 kmalloc(sc->re_tx_desc_cnt * sizeof(struct mbuf *),
1066 M_DEVBUF, M_ZERO | M_WAITOK);
1068 sc->re_ldata.re_rx_mbuf =
1069 kmalloc(sc->re_rx_desc_cnt * sizeof(struct mbuf *),
1070 M_DEVBUF, M_ZERO | M_WAITOK);
1072 sc->re_ldata.re_rx_paddr =
1073 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_addr_t),
1074 M_DEVBUF, M_ZERO | M_WAITOK);
1076 sc->re_ldata.re_tx_dmamap =
1077 kmalloc(sc->re_tx_desc_cnt * sizeof(bus_dmamap_t),
1078 M_DEVBUF, M_ZERO | M_WAITOK);
1080 sc->re_ldata.re_rx_dmamap =
1081 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_dmamap_t),
1082 M_DEVBUF, M_ZERO | M_WAITOK);
1085 * Allocate the parent bus DMA tag appropriate for PCI.
1087 error = bus_dma_tag_create(NULL, /* parent */
1088 1, 0, /* alignment, boundary */
1089 BUS_SPACE_MAXADDR, /* lowaddr */
1090 BUS_SPACE_MAXADDR, /* highaddr */
1091 NULL, NULL, /* filter, filterarg */
1092 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
1094 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1096 &sc->re_parent_tag);
1098 device_printf(dev, "could not allocate parent dma tag\n");
1102 /* Allocate TX descriptor list. */
1103 error = bus_dmamem_coherent(sc->re_parent_tag,
1105 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1106 RE_TX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO,
1109 device_printf(dev, "could not allocate TX ring\n");
1112 sc->re_ldata.re_tx_list_tag = dmem.dmem_tag;
1113 sc->re_ldata.re_tx_list_map = dmem.dmem_map;
1114 sc->re_ldata.re_tx_list = dmem.dmem_addr;
1115 sc->re_ldata.re_tx_list_addr = dmem.dmem_busaddr;
1117 /* Allocate RX descriptor list. */
1118 error = bus_dmamem_coherent(sc->re_parent_tag,
1120 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1121 RE_RX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO,
1124 device_printf(dev, "could not allocate RX ring\n");
1127 sc->re_ldata.re_rx_list_tag = dmem.dmem_tag;
1128 sc->re_ldata.re_rx_list_map = dmem.dmem_map;
1129 sc->re_ldata.re_rx_list = dmem.dmem_addr;
1130 sc->re_ldata.re_rx_list_addr = dmem.dmem_busaddr;
1132 /* Allocate maps for TX mbufs. */
1133 error = bus_dma_tag_create(sc->re_parent_tag,
1135 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1137 RE_FRAMELEN_MAX, RE_MAXSEGS, MCLBYTES,
1138 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1139 &sc->re_ldata.re_tx_mtag);
1141 device_printf(dev, "could not allocate TX buf dma tag\n");
1145 /* Create DMA maps for TX buffers */
1146 for (i = 0; i < sc->re_tx_desc_cnt; i++) {
1147 error = bus_dmamap_create(sc->re_ldata.re_tx_mtag,
1148 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1149 &sc->re_ldata.re_tx_dmamap[i]);
1151 device_printf(dev, "can't create DMA map for TX buf\n");
1152 re_freebufmem(sc, i, 0);
1157 /* Allocate maps for RX mbufs. */
1158 error = bus_dma_tag_create(sc->re_parent_tag,
1160 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1162 MCLBYTES, 1, MCLBYTES,
1163 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,
1164 &sc->re_ldata.re_rx_mtag);
1166 device_printf(dev, "could not allocate RX buf dma tag\n");
1170 /* Create spare DMA map for RX */
1171 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag, BUS_DMA_WAITOK,
1172 &sc->re_ldata.re_rx_spare);
1174 device_printf(dev, "can't create spare DMA map for RX\n");
1175 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag);
1176 sc->re_ldata.re_rx_mtag = NULL;
1180 /* Create DMA maps for RX buffers */
1181 for (i = 0; i < sc->re_rx_desc_cnt; i++) {
1182 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag,
1183 BUS_DMA_WAITOK, &sc->re_ldata.re_rx_dmamap[i]);
1185 device_printf(dev, "can't create DMA map for RX buf\n");
1186 re_freebufmem(sc, sc->re_tx_desc_cnt, i);
1191 /* Create jumbo buffer pool for RX if required */
1192 if (sc->re_caps & RE_C_CONTIGRX) {
1193 error = re_jpool_alloc(sc);
1196 /* Disable jumbo frame support */
1197 sc->re_maxmtu = ETHERMTU;
1204 re_freebufmem(struct re_softc *sc, int tx_cnt, int rx_cnt)
1208 /* Destroy all the RX and TX buffer maps */
1209 if (sc->re_ldata.re_tx_mtag) {
1210 for (i = 0; i < tx_cnt; i++) {
1211 bus_dmamap_destroy(sc->re_ldata.re_tx_mtag,
1212 sc->re_ldata.re_tx_dmamap[i]);
1214 bus_dma_tag_destroy(sc->re_ldata.re_tx_mtag);
1215 sc->re_ldata.re_tx_mtag = NULL;
1218 if (sc->re_ldata.re_rx_mtag) {
1219 for (i = 0; i < rx_cnt; i++) {
1220 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag,
1221 sc->re_ldata.re_rx_dmamap[i]);
1223 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag,
1224 sc->re_ldata.re_rx_spare);
1225 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag);
1226 sc->re_ldata.re_rx_mtag = NULL;
1231 re_freemem(device_t dev)
1233 struct re_softc *sc = device_get_softc(dev);
1235 /* Unload and free the RX DMA ring memory and map */
1236 if (sc->re_ldata.re_rx_list_tag) {
1237 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag,
1238 sc->re_ldata.re_rx_list_map);
1239 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1240 sc->re_ldata.re_rx_list,
1241 sc->re_ldata.re_rx_list_map);
1242 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1245 /* Unload and free the TX DMA ring memory and map */
1246 if (sc->re_ldata.re_tx_list_tag) {
1247 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag,
1248 sc->re_ldata.re_tx_list_map);
1249 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1250 sc->re_ldata.re_tx_list,
1251 sc->re_ldata.re_tx_list_map);
1252 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1255 /* Free RX/TX buf DMA stuffs */
1256 re_freebufmem(sc, sc->re_tx_desc_cnt, sc->re_rx_desc_cnt);
1258 /* Unload and free the stats buffer and map */
1259 if (sc->re_ldata.re_stag) {
1260 bus_dmamap_unload(sc->re_ldata.re_stag, sc->re_ldata.re_smap);
1261 bus_dmamem_free(sc->re_ldata.re_stag,
1262 sc->re_ldata.re_stats,
1263 sc->re_ldata.re_smap);
1264 bus_dma_tag_destroy(sc->re_ldata.re_stag);
1267 if (sc->re_caps & RE_C_CONTIGRX)
1270 if (sc->re_parent_tag)
1271 bus_dma_tag_destroy(sc->re_parent_tag);
1273 if (sc->re_ldata.re_tx_mbuf != NULL)
1274 kfree(sc->re_ldata.re_tx_mbuf, M_DEVBUF);
1275 if (sc->re_ldata.re_rx_mbuf != NULL)
1276 kfree(sc->re_ldata.re_rx_mbuf, M_DEVBUF);
1277 if (sc->re_ldata.re_rx_paddr != NULL)
1278 kfree(sc->re_ldata.re_rx_paddr, M_DEVBUF);
1279 if (sc->re_ldata.re_tx_dmamap != NULL)
1280 kfree(sc->re_ldata.re_tx_dmamap, M_DEVBUF);
1281 if (sc->re_ldata.re_rx_dmamap != NULL)
1282 kfree(sc->re_ldata.re_rx_dmamap, M_DEVBUF);
1286 * Attach the interface. Allocate softc structures, do ifmedia
1287 * setup and ethernet/BPF attach.
1290 re_attach(device_t dev)
1292 struct re_softc *sc = device_get_softc(dev);
1294 uint8_t eaddr[ETHER_ADDR_LEN];
1295 int error = 0, rid, qlen;
1297 callout_init(&sc->re_timer);
1300 if (RE_IS_8139CP(sc)) {
1301 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_8139CP;
1302 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_8139CP;
1304 sc->re_rx_desc_cnt = re_rx_desc_count;
1305 if (sc->re_rx_desc_cnt > RE_RX_DESC_CNT_MAX)
1306 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_MAX;
1308 sc->re_tx_desc_cnt = re_tx_desc_count;
1309 if (sc->re_tx_desc_cnt > RE_TX_DESC_CNT_MAX)
1310 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_MAX;
1313 qlen = RE_IFQ_MAXLEN;
1314 if (sc->re_tx_desc_cnt > qlen)
1315 qlen = sc->re_tx_desc_cnt;
1317 sc->re_rxbuf_size = MCLBYTES;
1318 sc->re_newbuf = re_newbuf_std;
1320 sc->re_tx_time = 5; /* 125us */
1321 sc->re_rx_time = 2; /* 50us */
1322 if (sc->re_caps & RE_C_PCIE)
1323 sc->re_sim_time = 75; /* 75us */
1325 sc->re_sim_time = 125; /* 125us */
1326 if (!RE_IS_8139CP(sc)) {
1327 /* simulated interrupt moderation */
1328 sc->re_imtype = RE_IMTYPE_SIM;
1330 sc->re_imtype = RE_IMTYPE_NONE;
1332 re_config_imtype(sc, sc->re_imtype);
1334 sysctl_ctx_init(&sc->re_sysctl_ctx);
1335 sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx,
1336 SYSCTL_STATIC_CHILDREN(_hw),
1338 device_get_nameunit(dev),
1340 if (sc->re_sysctl_tree == NULL) {
1341 device_printf(dev, "can't add sysctl node\n");
1345 SYSCTL_ADD_INT(&sc->re_sysctl_ctx,
1346 SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO,
1347 "rx_desc_count", CTLFLAG_RD, &sc->re_rx_desc_cnt,
1348 0, "RX desc count");
1349 SYSCTL_ADD_INT(&sc->re_sysctl_ctx,
1350 SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO,
1351 "tx_desc_count", CTLFLAG_RD, &sc->re_tx_desc_cnt,
1352 0, "TX desc count");
1353 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1354 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1355 OID_AUTO, "sim_time",
1356 CTLTYPE_INT | CTLFLAG_RW,
1357 sc, 0, re_sysctl_simtime, "I",
1358 "Simulated interrupt moderation time (usec).");
1359 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1360 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1362 CTLTYPE_INT | CTLFLAG_RW,
1363 sc, 0, re_sysctl_imtype, "I",
1364 "Interrupt moderation type -- "
1365 "0:disable, 1:simulated, "
1366 "2:hardware(if supported)");
1367 if (sc->re_caps & RE_C_HWIM) {
1368 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1369 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1370 OID_AUTO, "hw_rxtime",
1371 CTLTYPE_INT | CTLFLAG_RW,
1372 sc, 0, re_sysctl_rxtime, "I",
1373 "Hardware interrupt moderation time "
1375 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1376 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1377 OID_AUTO, "hw_txtime",
1378 CTLTYPE_INT | CTLFLAG_RW,
1379 sc, 0, re_sysctl_txtime, "I",
1380 "Hardware interrupt moderation time "
1384 #ifndef BURN_BRIDGES
1386 * Handle power management nonsense.
1389 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1390 uint32_t membase, irq;
1392 /* Save important PCI config data. */
1393 membase = pci_read_config(dev, RE_PCI_LOMEM, 4);
1394 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1396 /* Reset the power state. */
1397 device_printf(dev, "chip is in D%d power mode "
1398 "-- setting to D0\n", pci_get_powerstate(dev));
1400 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1402 /* Restore PCI config data. */
1403 pci_write_config(dev, RE_PCI_LOMEM, membase, 4);
1404 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1408 * Map control/status registers.
1410 pci_enable_busmaster(dev);
1413 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1416 if (sc->re_res == NULL) {
1417 device_printf(dev, "couldn't map ports\n");
1422 sc->re_btag = rman_get_bustag(sc->re_res);
1423 sc->re_bhandle = rman_get_bushandle(sc->re_res);
1425 /* Allocate interrupt */
1427 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1428 RF_SHAREABLE | RF_ACTIVE);
1430 if (sc->re_irq == NULL) {
1431 device_printf(dev, "couldn't map interrupt\n");
1436 /* Reset the adapter. */
1439 if (RE_IS_8139CP(sc)) {
1440 sc->re_bus_speed = 33; /* XXX */
1441 } else if (sc->re_caps & RE_C_PCIE) {
1442 sc->re_bus_speed = 125;
1446 cfg2 = CSR_READ_1(sc, RE_CFG2);
1447 switch (cfg2 & RE_CFG2_PCICLK_MASK) {
1448 case RE_CFG2_PCICLK_33MHZ:
1449 sc->re_bus_speed = 33;
1451 case RE_CFG2_PCICLK_66MHZ:
1452 sc->re_bus_speed = 66;
1455 device_printf(dev, "unknown bus speed, assume 33MHz\n");
1456 sc->re_bus_speed = 33;
1459 if (cfg2 & RE_CFG2_PCI64)
1460 sc->re_caps |= RE_C_PCI64;
1462 device_printf(dev, "Hardware rev. 0x%08x; MAC ver. 0x%02x; "
1464 sc->re_hwrev, sc->re_macver,
1465 (sc->re_caps & RE_C_PCIE) ?
1466 "-E" : ((sc->re_caps & RE_C_PCI64) ? "64" : "32"),
1471 * DO NOT try to adjust config1 and config5 which was spotted in
1472 * Realtek's Linux drivers. It will _permanently_ damage certain
1473 * cards EEPROM, e.g. one of my 8168B (0x38000000) card ...
1476 re_get_eaddr(sc, eaddr);
1478 if (!RE_IS_8139CP(sc)) {
1479 /* Set RX length mask */
1480 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
1481 sc->re_txstart = RE_GTXSTART;
1483 /* Set RX length mask */
1484 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
1485 sc->re_txstart = RE_TXSTART;
1488 /* Allocate DMA stuffs */
1489 error = re_allocmem(dev);
1494 * Apply some magic PCI settings from Realtek ...
1496 if (RE_IS_8169(sc)) {
1497 CSR_WRITE_1(sc, 0x82, 1);
1498 pci_write_config(dev, PCIR_CACHELNSZ, 0x8, 1);
1500 pci_write_config(dev, PCIR_LATTIMER, 0x40, 1);
1502 if (sc->re_caps & RE_C_MAC2) {
1504 * Following part is extracted from Realtek BSD driver v176.
1505 * However, this does _not_ make much/any sense:
1506 * 8168C's PCI Express device control is located at 0x78,
1507 * so the reading from 0x79 (higher part of 0x78) and setting
1508 * the 4~6bits intend to enlarge the "max read request size"
1509 * (we will do it). The content of the rest part of this
1510 * register is not meaningful to other PCI registers, so
1511 * writing the value to 0x54 could be completely wrong.
1512 * 0x80 is the lower part of PCI Express device status, non-
1513 * reserved bits are RW1C, writing 0 to them will not have
1514 * any effect at all.
1519 val = pci_read_config(dev, 0x79, 1);
1520 val = (val & ~0x70) | 0x50;
1521 pci_write_config(dev, 0x54, val, 1);
1522 pci_write_config(dev, 0x80, 0, 1);
1527 * Apply some PHY fixup from Realtek ...
1529 if (sc->re_hwrev == RE_HWREV_8110S) {
1530 CSR_WRITE_1(sc, 0x82, 1);
1531 re_miibus_writereg(dev, 1, 0xb, 0);
1533 if (sc->re_caps & RE_C_PHYPMGT) {
1535 re_miibus_writereg(dev, 1, 0x1f, 0);
1536 re_miibus_writereg(dev, 1, 0xe, 0);
1540 if (mii_phy_probe(dev, &sc->re_miibus,
1541 re_ifmedia_upd, re_ifmedia_sts)) {
1542 device_printf(dev, "MII without any phy!\n");
1547 ifp = &sc->arpcom.ac_if;
1549 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1550 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1551 ifp->if_ioctl = re_ioctl;
1552 ifp->if_start = re_start;
1553 #ifdef DEVICE_POLLING
1554 ifp->if_poll = re_poll;
1556 ifp->if_watchdog = re_watchdog;
1557 ifp->if_init = re_init;
1558 if (!RE_IS_8139CP(sc)) /* XXX */
1559 ifp->if_baudrate = 1000000000;
1561 ifp->if_baudrate = 100000000;
1562 ifq_set_maxlen(&ifp->if_snd, qlen);
1563 ifq_set_ready(&ifp->if_snd);
1565 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1566 if (sc->re_caps & RE_C_HWCSUM)
1567 ifp->if_capabilities |= IFCAP_HWCSUM;
1569 ifp->if_capenable = ifp->if_capabilities;
1570 if (ifp->if_capabilities & IFCAP_HWCSUM)
1571 ifp->if_hwassist = RE_CSUM_FEATURES;
1573 ifp->if_hwassist = 0;
1576 * Call MI attach routine.
1578 ether_ifattach(ifp, eaddr, NULL);
1582 * Perform hardware diagnostic on the original RTL8169.
1583 * Some 32-bit cards were incorrectly wired and would
1584 * malfunction if plugged into a 64-bit slot.
1586 if (sc->re_hwrev == RE_HWREV_8169) {
1587 lwkt_serialize_enter(ifp->if_serializer);
1588 error = re_diag(sc);
1589 lwkt_serialize_exit(ifp->if_serializer);
1592 device_printf(dev, "hardware diagnostic failure\n");
1593 ether_ifdetach(ifp);
1597 #endif /* RE_DIAG */
1599 /* Hook interrupt last to avoid having to lock softc */
1600 error = bus_setup_intr(dev, sc->re_irq, INTR_MPSAFE, re_intr, sc,
1601 &sc->re_intrhand, ifp->if_serializer);
1604 device_printf(dev, "couldn't set up irq\n");
1605 ether_ifdetach(ifp);
1609 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->re_irq));
1610 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1620 * Shutdown hardware and free up resources. This can be called any
1621 * time after the mutex has been initialized. It is called in both
1622 * the error case in attach and the normal detach case so it needs
1623 * to be careful about only freeing resources that have actually been
1627 re_detach(device_t dev)
1629 struct re_softc *sc = device_get_softc(dev);
1630 struct ifnet *ifp = &sc->arpcom.ac_if;
1632 /* These should only be active if attach succeeded */
1633 if (device_is_attached(dev)) {
1634 lwkt_serialize_enter(ifp->if_serializer);
1636 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand);
1637 lwkt_serialize_exit(ifp->if_serializer);
1639 ether_ifdetach(ifp);
1642 device_delete_child(dev, sc->re_miibus);
1643 bus_generic_detach(dev);
1645 if (sc->re_sysctl_tree != NULL)
1646 sysctl_ctx_free(&sc->re_sysctl_ctx);
1649 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq);
1651 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO,
1655 /* Free DMA stuffs */
1662 re_setup_rxdesc(struct re_softc *sc, int idx)
1668 paddr = sc->re_ldata.re_rx_paddr[idx];
1669 d = &sc->re_ldata.re_rx_list[idx];
1671 d->re_bufaddr_lo = htole32(RE_ADDR_LO(paddr));
1672 d->re_bufaddr_hi = htole32(RE_ADDR_HI(paddr));
1674 cmdstat = sc->re_rxbuf_size | RE_RDESC_CMD_OWN;
1675 if (idx == (sc->re_rx_desc_cnt - 1))
1676 cmdstat |= RE_RDESC_CMD_EOR;
1677 d->re_cmdstat = htole32(cmdstat);
1681 re_newbuf_std(struct re_softc *sc, int idx, int init)
1683 bus_dma_segment_t seg;
1688 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
1693 if_printf(&sc->arpcom.ac_if, "m_getcl failed\n");
1699 m->m_len = m->m_pkthdr.len = MCLBYTES;
1703 * re(4) chips need address of the receive buffer to be 8-byte
1704 * aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1707 error = bus_dmamap_load_mbuf_segment(sc->re_ldata.re_rx_mtag,
1708 sc->re_ldata.re_rx_spare, m,
1709 &seg, 1, &nsegs, BUS_DMA_NOWAIT);
1713 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
1721 bus_dmamap_sync(sc->re_ldata.re_rx_mtag,
1722 sc->re_ldata.re_rx_dmamap[idx],
1723 BUS_DMASYNC_POSTREAD);
1724 bus_dmamap_unload(sc->re_ldata.re_rx_mtag,
1725 sc->re_ldata.re_rx_dmamap[idx]);
1727 sc->re_ldata.re_rx_mbuf[idx] = m;
1728 sc->re_ldata.re_rx_paddr[idx] = seg.ds_addr;
1730 map = sc->re_ldata.re_rx_dmamap[idx];
1731 sc->re_ldata.re_rx_dmamap[idx] = sc->re_ldata.re_rx_spare;
1732 sc->re_ldata.re_rx_spare = map;
1734 re_setup_rxdesc(sc, idx);
1739 re_newbuf_jumbo(struct re_softc *sc, int idx, int init)
1742 struct re_jbuf *jbuf;
1745 MGETHDR(m, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1749 if_printf(&sc->arpcom.ac_if, "MGETHDR failed\n");
1756 jbuf = re_jbuf_alloc(sc);
1762 if_printf(&sc->arpcom.ac_if, "jpool is empty\n");
1769 m->m_ext.ext_arg = jbuf;
1770 m->m_ext.ext_buf = jbuf->re_buf;
1771 m->m_ext.ext_free = re_jbuf_free;
1772 m->m_ext.ext_ref = re_jbuf_ref;
1773 m->m_ext.ext_size = sc->re_rxbuf_size;
1775 m->m_data = m->m_ext.ext_buf;
1776 m->m_flags |= M_EXT;
1777 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
1781 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer
1782 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1785 sc->re_ldata.re_rx_mbuf[idx] = m;
1786 sc->re_ldata.re_rx_paddr[idx] = jbuf->re_paddr;
1788 re_setup_rxdesc(sc, idx);
1793 re_tx_list_init(struct re_softc *sc)
1795 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc));
1797 sc->re_ldata.re_tx_prodidx = 0;
1798 sc->re_ldata.re_tx_considx = 0;
1799 sc->re_ldata.re_tx_free = sc->re_tx_desc_cnt;
1805 re_rx_list_init(struct re_softc *sc)
1809 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ(sc));
1811 for (i = 0; i < sc->re_rx_desc_cnt; i++) {
1812 error = sc->re_newbuf(sc, i, 1);
1817 sc->re_ldata.re_rx_prodidx = 0;
1818 sc->re_head = sc->re_tail = NULL;
1823 #define RE_IP4_PACKET 0x1
1824 #define RE_TCP_PACKET 0x2
1825 #define RE_UDP_PACKET 0x4
1827 static __inline uint8_t
1828 re_packet_type(struct re_softc *sc, uint32_t rxstat, uint32_t rxctrl)
1830 uint8_t packet_type = 0;
1832 if (sc->re_caps & RE_C_MAC2) {
1833 if (rxctrl & RE_RDESC_CTL_PROTOIP4)
1834 packet_type |= RE_IP4_PACKET;
1836 if (rxstat & RE_RDESC_STAT_PROTOID)
1837 packet_type |= RE_IP4_PACKET;
1839 if (RE_TCPPKT(rxstat))
1840 packet_type |= RE_TCP_PACKET;
1841 else if (RE_UDPPKT(rxstat))
1842 packet_type |= RE_UDP_PACKET;
1847 * RX handler for C+ and 8169. For the gigE chips, we support
1848 * the reception of jumbo frames that have been fragmented
1849 * across multiple 2K mbuf cluster buffers.
1852 re_rxeof(struct re_softc *sc)
1854 struct ifnet *ifp = &sc->arpcom.ac_if;
1856 struct re_desc *cur_rx;
1857 uint32_t rxstat, rxctrl;
1858 int i, total_len, rx = 0;
1859 struct mbuf_chain chain[MAXCPU];
1861 ether_input_chain_init(chain);
1863 for (i = sc->re_ldata.re_rx_prodidx;
1864 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0; RE_RXDESC_INC(sc, i)) {
1865 cur_rx = &sc->re_ldata.re_rx_list[i];
1866 m = sc->re_ldata.re_rx_mbuf[i];
1867 total_len = RE_RXBYTES(cur_rx);
1868 rxstat = le32toh(cur_rx->re_cmdstat);
1869 rxctrl = le32toh(cur_rx->re_control);
1874 if (sc->re_flags & RE_F_USE_JPOOL)
1875 KKASSERT(rxstat & RE_RDESC_STAT_EOF);
1878 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1879 if (sc->re_flags & RE_F_DROP_RXFRAG) {
1880 re_setup_rxdesc(sc, i);
1884 if (sc->re_newbuf(sc, i, 0)) {
1885 /* Drop upcoming fragments */
1886 sc->re_flags |= RE_F_DROP_RXFRAG;
1890 m->m_len = MCLBYTES;
1891 if (sc->re_head == NULL) {
1892 sc->re_head = sc->re_tail = m;
1894 sc->re_tail->m_next = m;
1898 } else if (sc->re_flags & RE_F_DROP_RXFRAG) {
1900 * Last fragment of a multi-fragment packet.
1902 * Since error already happened, this fragment
1903 * must be dropped as well as the fragment chain.
1905 re_setup_rxdesc(sc, i);
1906 re_free_rxchain(sc);
1907 sc->re_flags &= ~RE_F_DROP_RXFRAG;
1912 * NOTE: for the 8139C+, the frame length field
1913 * is always 12 bits in size, but for the gigE chips,
1914 * it is 13 bits (since the max RX frame length is 16K).
1915 * Unfortunately, all 32 bits in the status word
1916 * were already used, so to make room for the extra
1917 * length bit, RealTek took out the 'frame alignment
1918 * error' bit and shifted the other status bits
1919 * over one slot. The OWN, EOR, FS and LS bits are
1920 * still in the same places. We have already extracted
1921 * the frame length and checked the OWN bit, so rather
1922 * than using an alternate bit mapping, we shift the
1923 * status bits one space to the right so we can evaluate
1924 * them using the 8169 status as though it was in the
1925 * same format as that of the 8139C+.
1927 if (!RE_IS_8139CP(sc))
1930 if (rxstat & RE_RDESC_STAT_RXERRSUM) {
1933 * If this is part of a multi-fragment packet,
1934 * discard all the pieces.
1936 re_free_rxchain(sc);
1937 re_setup_rxdesc(sc, i);
1942 * If allocating a replacement mbuf fails,
1943 * reload the current one.
1946 if (sc->re_newbuf(sc, i, 0)) {
1951 if (sc->re_head != NULL) {
1952 m->m_len = total_len % MCLBYTES;
1954 * Special case: if there's 4 bytes or less
1955 * in this buffer, the mbuf can be discarded:
1956 * the last 4 bytes is the CRC, which we don't
1957 * care about anyway.
1959 if (m->m_len <= ETHER_CRC_LEN) {
1960 sc->re_tail->m_len -=
1961 (ETHER_CRC_LEN - m->m_len);
1964 m->m_len -= ETHER_CRC_LEN;
1965 sc->re_tail->m_next = m;
1968 sc->re_head = sc->re_tail = NULL;
1969 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1971 m->m_pkthdr.len = m->m_len =
1972 (total_len - ETHER_CRC_LEN);
1976 m->m_pkthdr.rcvif = ifp;
1978 /* Do RX checksumming if enabled */
1980 if (ifp->if_capenable & IFCAP_RXCSUM) {
1981 uint8_t packet_type;
1983 packet_type = re_packet_type(sc, rxstat, rxctrl);
1985 /* Check IP header checksum */
1986 if (packet_type & RE_IP4_PACKET) {
1987 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1988 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0)
1989 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1992 /* Check TCP/UDP checksum */
1993 if (((packet_type & RE_TCP_PACKET) &&
1994 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) ||
1995 ((packet_type & RE_UDP_PACKET) &&
1996 (rxstat & RE_RDESC_STAT_UDPSUMBAD) == 0)) {
1997 m->m_pkthdr.csum_flags |=
1998 CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
1999 CSUM_FRAG_NOT_CHECKED;
2000 m->m_pkthdr.csum_data = 0xffff;
2004 if (rxctrl & RE_RDESC_CTL_HASTAG) {
2005 m->m_flags |= M_VLANTAG;
2006 m->m_pkthdr.ether_vlantag =
2007 be16toh((rxctrl & RE_RDESC_CTL_TAGDATA));
2009 ether_input_chain(ifp, m, NULL, chain);
2012 ether_input_dispatch(chain);
2014 sc->re_ldata.re_rx_prodidx = i;
2019 #undef RE_IP4_PACKET
2020 #undef RE_TCP_PACKET
2021 #undef RE_UDP_PACKET
2024 re_tx_collect(struct re_softc *sc)
2026 struct ifnet *ifp = &sc->arpcom.ac_if;
2030 for (idx = sc->re_ldata.re_tx_considx;
2031 sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt;
2032 RE_TXDESC_INC(sc, idx)) {
2033 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat);
2034 if (txstat & RE_TDESC_CMD_OWN)
2039 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0;
2042 * We only stash mbufs in the last descriptor
2043 * in a fragment chain, which also happens to
2044 * be the only place where the TX status bits
2047 if (txstat & RE_TDESC_CMD_EOF) {
2048 bus_dmamap_unload(sc->re_ldata.re_tx_mtag,
2049 sc->re_ldata.re_tx_dmamap[idx]);
2050 m_freem(sc->re_ldata.re_tx_mbuf[idx]);
2051 sc->re_ldata.re_tx_mbuf[idx] = NULL;
2052 if (txstat & (RE_TDESC_STAT_EXCESSCOL|
2053 RE_TDESC_STAT_COLCNT))
2054 ifp->if_collisions++;
2055 if (txstat & RE_TDESC_STAT_TXERRSUM)
2060 sc->re_ldata.re_tx_free++;
2062 sc->re_ldata.re_tx_considx = idx;
2068 re_txeof(struct re_softc *sc)
2070 struct ifnet *ifp = &sc->arpcom.ac_if;
2073 tx = re_tx_collect(sc);
2075 /* There is enough free TX descs */
2076 if (sc->re_ldata.re_tx_free > RE_TXDESC_SPARE)
2077 ifp->if_flags &= ~IFF_OACTIVE;
2080 * Some chips will ignore a second TX request issued while an
2081 * existing transmission is in progress. If the transmitter goes
2082 * idle but there are still packets waiting to be sent, we need
2083 * to restart the channel here to flush them out. This only seems
2084 * to be required with the PCIe devices.
2086 if (sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt)
2087 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
2097 struct re_softc *sc = xsc;
2099 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
2100 re_tick_serialized(xsc);
2101 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
2105 re_tick_serialized(void *xsc)
2107 struct re_softc *sc = xsc;
2108 struct ifnet *ifp = &sc->arpcom.ac_if;
2109 struct mii_data *mii;
2111 ASSERT_SERIALIZED(ifp->if_serializer);
2113 mii = device_get_softc(sc->re_miibus);
2115 if (sc->re_flags & RE_F_LINKED) {
2116 if (!(mii->mii_media_status & IFM_ACTIVE))
2117 sc->re_flags &= ~RE_F_LINKED;
2119 if (mii->mii_media_status & IFM_ACTIVE &&
2120 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2121 sc->re_flags |= RE_F_LINKED;
2122 if (!ifq_is_empty(&ifp->if_snd))
2127 callout_reset(&sc->re_timer, hz, re_tick, sc);
2130 #ifdef DEVICE_POLLING
2133 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2135 struct re_softc *sc = ifp->if_softc;
2137 ASSERT_SERIALIZED(ifp->if_serializer);
2141 /* disable interrupts */
2142 re_setup_intr(sc, 0, RE_IMTYPE_NONE);
2145 case POLL_DEREGISTER:
2146 /* enable interrupts */
2147 re_setup_intr(sc, 1, sc->re_imtype);
2151 sc->rxcycles = count;
2155 if (!ifq_is_empty(&ifp->if_snd))
2158 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2161 status = CSR_READ_2(sc, RE_ISR);
2162 if (status == 0xffff)
2165 CSR_WRITE_2(sc, RE_ISR, status);
2168 * XXX check behaviour on receiver stalls.
2171 if (status & RE_ISR_SYSTEM_ERR)
2177 #endif /* DEVICE_POLLING */
2182 struct re_softc *sc = arg;
2183 struct ifnet *ifp = &sc->arpcom.ac_if;
2187 ASSERT_SERIALIZED(ifp->if_serializer);
2189 if ((sc->re_flags & RE_F_SUSPENDED) ||
2190 (ifp->if_flags & IFF_RUNNING) == 0)
2195 status = CSR_READ_2(sc, RE_ISR);
2196 /* If the card has gone away the read returns 0xffff. */
2197 if (status == 0xffff)
2200 CSR_WRITE_2(sc, RE_ISR, status);
2202 if ((status & sc->re_intrs) == 0)
2205 if (status & (sc->re_rx_ack | RE_ISR_RX_ERR))
2208 if (status & (sc->re_tx_ack | RE_ISR_TX_ERR))
2211 if (status & RE_ISR_SYSTEM_ERR)
2214 if (status & RE_ISR_LINKCHG) {
2215 callout_stop(&sc->re_timer);
2216 re_tick_serialized(sc);
2220 if (sc->re_imtype == RE_IMTYPE_SIM) {
2221 if ((sc->re_flags & RE_F_TIMER_INTR)) {
2222 if ((tx | rx) == 0) {
2224 * Nothing needs to be processed, fallback
2225 * to use TX/RX interrupts.
2227 re_setup_intr(sc, 1, RE_IMTYPE_NONE);
2230 * Recollect, mainly to avoid the possible
2231 * race introduced by changing interrupt
2237 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */
2239 } else if (tx | rx) {
2241 * Assume that using simulated interrupt moderation
2242 * (hardware timer based) could reduce the interript
2245 re_setup_intr(sc, 1, RE_IMTYPE_SIM);
2249 if (tx && !ifq_is_empty(&ifp->if_snd))
2254 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx0)
2256 struct mbuf *m = *m_head;
2257 bus_dma_segment_t segs[RE_MAXSEGS];
2259 int error, maxsegs, idx, i, nsegs;
2260 struct re_desc *d, *tx_ring;
2261 uint32_t cmd_csum, ctl_csum, vlantag;
2263 KASSERT(sc->re_ldata.re_tx_free > RE_TXDESC_SPARE,
2264 ("not enough free TX desc\n"));
2266 map = sc->re_ldata.re_tx_dmamap[*idx0];
2269 * Set up checksum offload. Note: checksum offload bits must
2270 * appear in all descriptors of a multi-descriptor transmit
2271 * attempt. (This is according to testing done with an 8169
2272 * chip. I'm not sure if this is a requirement or a bug.)
2274 cmd_csum = ctl_csum = 0;
2275 if (m->m_pkthdr.csum_flags & CSUM_IP) {
2276 cmd_csum |= RE_TDESC_CMD_IPCSUM;
2277 ctl_csum |= RE_TDESC_CTL_IPCSUM;
2279 if (m->m_pkthdr.csum_flags & CSUM_TCP) {
2280 cmd_csum |= RE_TDESC_CMD_TCPCSUM;
2281 ctl_csum |= RE_TDESC_CTL_TCPCSUM;
2283 if (m->m_pkthdr.csum_flags & CSUM_UDP) {
2284 cmd_csum |= RE_TDESC_CMD_UDPCSUM;
2285 ctl_csum |= RE_TDESC_CTL_UDPCSUM;
2288 /* For MAC2 chips, csum flags are set on re_control */
2289 if (sc->re_caps & RE_C_MAC2)
2294 if ((sc->re_caps & RE_C_AUTOPAD) == 0) {
2296 * With some of the RealTek chips, using the checksum offload
2297 * support in conjunction with the autopadding feature results
2298 * in the transmission of corrupt frames. For example, if we
2299 * need to send a really small IP fragment that's less than 60
2300 * bytes in size, and IP header checksumming is enabled, the
2301 * resulting ethernet frame that appears on the wire will
2302 * have garbled payload. To work around this, if TX checksum
2303 * offload is enabled, we always manually pad short frames out
2304 * to the minimum ethernet frame size.
2306 * Note: this appears unnecessary for TCP, and doing it for TCP
2307 * with PCIe adapters seems to result in bad checksums.
2309 if ((m->m_pkthdr.csum_flags &
2310 (CSUM_DELAY_IP | CSUM_DELAY_DATA)) &&
2311 (m->m_pkthdr.csum_flags & CSUM_TCP) == 0 &&
2312 m->m_pkthdr.len < RE_MIN_FRAMELEN) {
2313 error = m_devpad(m, RE_MIN_FRAMELEN);
2320 if (m->m_flags & M_VLANTAG) {
2321 vlantag = htobe16(m->m_pkthdr.ether_vlantag) |
2322 RE_TDESC_CTL_INSTAG;
2325 maxsegs = sc->re_ldata.re_tx_free;
2326 if (maxsegs > RE_MAXSEGS)
2327 maxsegs = RE_MAXSEGS;
2329 error = bus_dmamap_load_mbuf_defrag(sc->re_ldata.re_tx_mtag, map,
2330 m_head, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2335 bus_dmamap_sync(sc->re_ldata.re_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2338 * Map the segment array into descriptors. We also keep track
2339 * of the end of the ring and set the end-of-ring bits as needed,
2340 * and we set the ownership bits in all except the very first
2341 * descriptor, whose ownership bits will be turned on later.
2343 tx_ring = sc->re_ldata.re_tx_list;
2351 cmdstat = segs[i].ds_len;
2352 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr));
2353 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr));
2355 cmdstat |= RE_TDESC_CMD_SOF;
2357 cmdstat |= RE_TDESC_CMD_OWN;
2358 if (idx == (sc->re_tx_desc_cnt - 1))
2359 cmdstat |= RE_TDESC_CMD_EOR;
2360 d->re_cmdstat = htole32(cmdstat | cmd_csum);
2361 d->re_control = htole32(ctl_csum | vlantag);
2366 RE_TXDESC_INC(sc, idx);
2368 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF);
2370 /* Transfer ownership of packet to the chip. */
2371 d->re_cmdstat |= htole32(RE_TDESC_CMD_OWN);
2373 tx_ring[*idx0].re_cmdstat |= htole32(RE_TDESC_CMD_OWN);
2376 * Insure that the map for this transmission
2377 * is placed at the array index of the last descriptor
2380 sc->re_ldata.re_tx_dmamap[*idx0] = sc->re_ldata.re_tx_dmamap[idx];
2381 sc->re_ldata.re_tx_dmamap[idx] = map;
2383 sc->re_ldata.re_tx_mbuf[idx] = m;
2384 sc->re_ldata.re_tx_free -= nsegs;
2386 RE_TXDESC_INC(sc, idx);
2397 * Main transmit routine for C+ and gigE NICs.
2401 re_start(struct ifnet *ifp)
2403 struct re_softc *sc = ifp->if_softc;
2404 struct mbuf *m_head;
2405 int idx, need_trans, oactive, error;
2407 ASSERT_SERIALIZED(ifp->if_serializer);
2409 if ((sc->re_flags & RE_F_LINKED) == 0) {
2410 ifq_purge(&ifp->if_snd);
2414 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
2417 idx = sc->re_ldata.re_tx_prodidx;
2421 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) {
2422 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) {
2424 if (re_tx_collect(sc)) {
2429 ifp->if_flags |= IFF_OACTIVE;
2433 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2437 error = re_encap(sc, &m_head, &idx);
2439 /* m_head is freed by re_encap(), if we reach here */
2442 if (error == EFBIG && !oactive) {
2443 if (re_tx_collect(sc)) {
2448 ifp->if_flags |= IFF_OACTIVE;
2456 * If there's a BPF listener, bounce a copy of this frame
2459 ETHER_BPF_MTAP(ifp, m_head);
2465 sc->re_ldata.re_tx_prodidx = idx;
2468 * RealTek put the TX poll request register in a different
2469 * location on the 8169 gigE chip. I don't know why.
2471 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
2474 * Set a timeout in case the chip goes out to lunch.
2482 struct re_softc *sc = xsc;
2483 struct ifnet *ifp = &sc->arpcom.ac_if;
2484 struct mii_data *mii;
2485 int error, framelen;
2487 ASSERT_SERIALIZED(ifp->if_serializer);
2489 mii = device_get_softc(sc->re_miibus);
2492 * Cancel pending I/O and free all RX/TX buffers.
2496 if (sc->re_caps & RE_C_CONTIGRX) {
2497 if (ifp->if_mtu > ETHERMTU) {
2498 KKASSERT(sc->re_ldata.re_jbuf != NULL);
2499 sc->re_flags |= RE_F_USE_JPOOL;
2500 sc->re_rxbuf_size = RE_FRAMELEN_MAX;
2501 sc->re_newbuf = re_newbuf_jumbo;
2503 sc->re_flags &= ~RE_F_USE_JPOOL;
2504 sc->re_rxbuf_size = MCLBYTES;
2505 sc->re_newbuf = re_newbuf_std;
2510 * Adjust max read request size according to MTU; mainly to
2511 * improve TX performance for common case (ETHERMTU) on GigE
2512 * NICs. However, this could _not_ be done on 10/100 only
2513 * NICs; their DMA engines will malfunction using non-default
2514 * max read request size.
2516 if ((sc->re_caps & (RE_C_PCIE | RE_C_FASTE)) == RE_C_PCIE) {
2517 if (ifp->if_mtu > ETHERMTU) {
2519 * 512 seems to be the only value that works
2520 * reliably with jumbo frame
2522 pcie_set_max_readrq(sc->re_dev,
2523 PCIEM_DEVCTL_MAX_READRQ_512);
2525 pcie_set_max_readrq(sc->re_dev,
2526 PCIEM_DEVCTL_MAX_READRQ_4096);
2531 * Enable C+ RX and TX mode, as well as VLAN stripping and
2532 * RX checksum offload. We must configure the C+ register
2533 * before all others.
2535 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB |
2536 RE_CPLUSCMD_PCI_MRW |
2537 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING ?
2538 RE_CPLUSCMD_VLANSTRIP : 0) |
2539 (ifp->if_capenable & IFCAP_RXCSUM ?
2540 RE_CPLUSCMD_RXCSUM_ENB : 0));
2543 * Init our MAC address. Even though the chipset
2544 * documentation doesn't mention it, we need to enter "Config
2545 * register write enable" mode to modify the ID registers.
2547 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG);
2548 CSR_WRITE_4(sc, RE_IDR0,
2549 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0])));
2550 CSR_WRITE_2(sc, RE_IDR4,
2551 htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4])));
2552 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
2555 * For C+ mode, initialize the RX descriptors and mbufs.
2557 error = re_rx_list_init(sc);
2562 error = re_tx_list_init(sc);
2569 * Load the addresses of the RX and TX lists into the chip.
2571 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI,
2572 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr));
2573 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO,
2574 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr));
2576 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI,
2577 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr));
2578 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO,
2579 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr));
2582 * Enable transmit and receive.
2584 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2587 * Set the initial TX and RX configuration.
2589 if (sc->re_flags & RE_F_TESTMODE) {
2590 if (!RE_IS_8139CP(sc))
2591 CSR_WRITE_4(sc, RE_TXCFG,
2592 RE_TXCFG_CONFIG | RE_LOOPTEST_ON);
2594 CSR_WRITE_4(sc, RE_TXCFG,
2595 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS);
2597 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG);
2599 framelen = RE_FRAMELEN(ifp->if_mtu);
2600 if (framelen < MCLBYTES)
2601 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(MCLBYTES, 128));
2603 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(framelen, 128));
2605 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG);
2608 * Program the multicast filter, if necessary.
2612 #ifdef DEVICE_POLLING
2614 * Disable interrupts if we are polling.
2616 if (ifp->if_flags & IFF_POLLING)
2617 re_setup_intr(sc, 0, RE_IMTYPE_NONE);
2618 else /* otherwise ... */
2619 #endif /* DEVICE_POLLING */
2621 * Enable interrupts.
2623 if (sc->re_flags & RE_F_TESTMODE)
2624 CSR_WRITE_2(sc, RE_IMR, 0);
2626 re_setup_intr(sc, 1, sc->re_imtype);
2627 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs);
2629 /* Start RX/TX process. */
2630 CSR_WRITE_4(sc, RE_MISSEDPKT, 0);
2633 /* Enable receiver and transmitter. */
2634 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2638 * For 8169 gigE NICs, set the max allowed RX packet
2639 * size so we can receive jumbo frames.
2641 if (!RE_IS_8139CP(sc)) {
2642 if (sc->re_caps & RE_C_CONTIGRX)
2643 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, sc->re_rxbuf_size);
2645 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383);
2648 if (sc->re_flags & RE_F_TESTMODE)
2653 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX);
2655 ifp->if_flags |= IFF_RUNNING;
2656 ifp->if_flags &= ~IFF_OACTIVE;
2658 callout_reset(&sc->re_timer, hz, re_tick, sc);
2662 * Set media options.
2665 re_ifmedia_upd(struct ifnet *ifp)
2667 struct re_softc *sc = ifp->if_softc;
2668 struct mii_data *mii;
2670 ASSERT_SERIALIZED(ifp->if_serializer);
2672 mii = device_get_softc(sc->re_miibus);
2679 * Report current media status.
2682 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2684 struct re_softc *sc = ifp->if_softc;
2685 struct mii_data *mii;
2687 ASSERT_SERIALIZED(ifp->if_serializer);
2689 mii = device_get_softc(sc->re_miibus);
2692 ifmr->ifm_active = mii->mii_media_active;
2693 ifmr->ifm_status = mii->mii_media_status;
2697 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2699 struct re_softc *sc = ifp->if_softc;
2700 struct ifreq *ifr = (struct ifreq *) data;
2701 struct mii_data *mii;
2702 int error = 0, mask;
2704 ASSERT_SERIALIZED(ifp->if_serializer);
2708 if (ifr->ifr_mtu > sc->re_maxmtu) {
2710 } else if (ifp->if_mtu != ifr->ifr_mtu) {
2711 ifp->if_mtu = ifr->ifr_mtu;
2712 if (ifp->if_flags & IFF_RUNNING)
2718 if (ifp->if_flags & IFF_UP) {
2719 if (ifp->if_flags & IFF_RUNNING) {
2720 if ((ifp->if_flags ^ sc->re_if_flags) &
2721 (IFF_PROMISC | IFF_ALLMULTI))
2726 } else if (ifp->if_flags & IFF_RUNNING) {
2729 sc->re_if_flags = ifp->if_flags;
2739 mii = device_get_softc(sc->re_miibus);
2740 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2744 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) &
2745 ifp->if_capabilities;
2746 ifp->if_capenable ^= mask;
2748 if (mask & IFCAP_HWCSUM) {
2749 if (ifp->if_capenable & IFCAP_TXCSUM)
2750 ifp->if_hwassist = RE_CSUM_FEATURES;
2752 ifp->if_hwassist = 0;
2754 if (mask && (ifp->if_flags & IFF_RUNNING))
2759 error = ether_ioctl(ifp, command, data);
2766 re_watchdog(struct ifnet *ifp)
2768 struct re_softc *sc = ifp->if_softc;
2770 ASSERT_SERIALIZED(ifp->if_serializer);
2772 if_printf(ifp, "watchdog timeout\n");
2781 if (!ifq_is_empty(&ifp->if_snd))
2786 * Stop the adapter and free any mbufs allocated to the
2790 re_stop(struct re_softc *sc)
2792 struct ifnet *ifp = &sc->arpcom.ac_if;
2795 ASSERT_SERIALIZED(ifp->if_serializer);
2797 /* Reset the adapter. */
2798 re_reset(sc, ifp->if_flags & IFF_RUNNING);
2801 callout_stop(&sc->re_timer);
2803 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2804 sc->re_flags &= ~(RE_F_TIMER_INTR | RE_F_DROP_RXFRAG | RE_F_LINKED);
2806 CSR_WRITE_1(sc, RE_COMMAND, 0x00);
2807 CSR_WRITE_2(sc, RE_IMR, 0x0000);
2808 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
2810 re_free_rxchain(sc);
2812 /* Free the TX list buffers. */
2813 for (i = 0; i < sc->re_tx_desc_cnt; i++) {
2814 if (sc->re_ldata.re_tx_mbuf[i] != NULL) {
2815 bus_dmamap_unload(sc->re_ldata.re_tx_mtag,
2816 sc->re_ldata.re_tx_dmamap[i]);
2817 m_freem(sc->re_ldata.re_tx_mbuf[i]);
2818 sc->re_ldata.re_tx_mbuf[i] = NULL;
2822 /* Free the RX list buffers. */
2823 for (i = 0; i < sc->re_rx_desc_cnt; i++) {
2824 if (sc->re_ldata.re_rx_mbuf[i] != NULL) {
2825 if ((sc->re_flags & RE_F_USE_JPOOL) == 0) {
2826 bus_dmamap_unload(sc->re_ldata.re_rx_mtag,
2827 sc->re_ldata.re_rx_dmamap[i]);
2829 m_freem(sc->re_ldata.re_rx_mbuf[i]);
2830 sc->re_ldata.re_rx_mbuf[i] = NULL;
2836 * Device suspend routine. Stop the interface and save some PCI
2837 * settings in case the BIOS doesn't restore them properly on
2841 re_suspend(device_t dev)
2843 #ifndef BURN_BRIDGES
2846 struct re_softc *sc = device_get_softc(dev);
2847 struct ifnet *ifp = &sc->arpcom.ac_if;
2849 lwkt_serialize_enter(ifp->if_serializer);
2853 #ifndef BURN_BRIDGES
2854 for (i = 0; i < 5; i++)
2855 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2856 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2857 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2858 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2859 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2862 sc->re_flags |= RE_F_SUSPENDED;
2864 lwkt_serialize_exit(ifp->if_serializer);
2870 * Device resume routine. Restore some PCI settings in case the BIOS
2871 * doesn't, re-enable busmastering, and restart the interface if
2875 re_resume(device_t dev)
2877 struct re_softc *sc = device_get_softc(dev);
2878 struct ifnet *ifp = &sc->arpcom.ac_if;
2879 #ifndef BURN_BRIDGES
2883 lwkt_serialize_enter(ifp->if_serializer);
2885 #ifndef BURN_BRIDGES
2886 /* better way to do this? */
2887 for (i = 0; i < 5; i++)
2888 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
2889 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
2890 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
2891 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
2892 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
2894 /* reenable busmastering */
2895 pci_enable_busmaster(dev);
2896 pci_enable_io(dev, SYS_RES_IOPORT);
2899 /* reinitialize interface if necessary */
2900 if (ifp->if_flags & IFF_UP)
2903 sc->re_flags &= ~RE_F_SUSPENDED;
2905 lwkt_serialize_exit(ifp->if_serializer);
2911 * Stop all chip I/O so that the kernel's probe routines don't
2912 * get confused by errant DMAs when rebooting.
2915 re_shutdown(device_t dev)
2917 struct re_softc *sc = device_get_softc(dev);
2918 struct ifnet *ifp = &sc->arpcom.ac_if;
2920 lwkt_serialize_enter(ifp->if_serializer);
2922 lwkt_serialize_exit(ifp->if_serializer);
2926 re_sysctl_rxtime(SYSCTL_HANDLER_ARGS)
2928 struct re_softc *sc = arg1;
2930 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_rx_time);
2934 re_sysctl_txtime(SYSCTL_HANDLER_ARGS)
2936 struct re_softc *sc = arg1;
2938 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_tx_time);
2942 re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *hwtime)
2944 struct re_softc *sc = arg1;
2945 struct ifnet *ifp = &sc->arpcom.ac_if;
2948 lwkt_serialize_enter(ifp->if_serializer);
2951 error = sysctl_handle_int(oidp, &v, 0, req);
2952 if (error || req->newptr == NULL)
2963 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) ==
2964 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_HW)
2968 lwkt_serialize_exit(ifp->if_serializer);
2973 re_sysctl_simtime(SYSCTL_HANDLER_ARGS)
2975 struct re_softc *sc = arg1;
2976 struct ifnet *ifp = &sc->arpcom.ac_if;
2979 lwkt_serialize_enter(ifp->if_serializer);
2981 v = sc->re_sim_time;
2982 error = sysctl_handle_int(oidp, &v, 0, req);
2983 if (error || req->newptr == NULL)
2991 if (v != sc->re_sim_time) {
2992 sc->re_sim_time = v;
2994 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) ==
2995 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_SIM) {
3000 * Following code causes various strange
3001 * performance problems. Hmm ...
3003 CSR_WRITE_2(sc, RE_IMR, 0);
3004 if (!RE_IS_8139CP(sc))
3005 reg = RE_TIMERINT_8169;
3008 CSR_WRITE_4(sc, reg, 0);
3009 CSR_READ_4(sc, reg); /* flush */
3011 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
3012 re_setup_sim_im(sc);
3014 re_setup_intr(sc, 0, RE_IMTYPE_NONE);
3016 re_setup_intr(sc, 1, RE_IMTYPE_SIM);
3021 lwkt_serialize_exit(ifp->if_serializer);
3026 re_sysctl_imtype(SYSCTL_HANDLER_ARGS)
3028 struct re_softc *sc = arg1;
3029 struct ifnet *ifp = &sc->arpcom.ac_if;
3032 lwkt_serialize_enter(ifp->if_serializer);
3035 error = sysctl_handle_int(oidp, &v, 0, req);
3036 if (error || req->newptr == NULL)
3039 if (v != RE_IMTYPE_HW && v != RE_IMTYPE_SIM && v != RE_IMTYPE_NONE) {
3043 if (v == RE_IMTYPE_HW && (sc->re_caps & RE_C_HWIM) == 0) {
3044 /* Can't do hardware interrupt moderation */
3049 if (v != sc->re_imtype) {
3051 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) ==
3053 re_setup_intr(sc, 1, sc->re_imtype);
3056 lwkt_serialize_exit(ifp->if_serializer);
3061 re_setup_hw_im(struct re_softc *sc)
3063 KKASSERT(sc->re_caps & RE_C_HWIM);
3066 * Interrupt moderation
3069 * A - unknown (maybe TX related)
3070 * B - TX timer (unit: 25us)
3071 * C - unknown (maybe RX related)
3072 * D - RX timer (unit: 25us)
3075 * re(4)'s interrupt moderation is actually controlled by
3076 * two variables, like most other NICs (bge, bce etc.)
3078 * o number of packets [P]
3080 * The logic relationship between these two variables is
3081 * similar to other NICs too:
3082 * if (timer expire || packets > [P])
3083 * Interrupt is delivered
3085 * Currently we only know how to set 'timer', but not
3086 * 'number of packets', which should be ~30, as far as I
3087 * tested (sink ~900Kpps, interrupt rate is 30KHz)
3089 CSR_WRITE_2(sc, RE_IM,
3090 RE_IM_RXTIME(sc->re_rx_time) |
3091 RE_IM_TXTIME(sc->re_tx_time) |
3096 re_disable_hw_im(struct re_softc *sc)
3098 if (sc->re_caps & RE_C_HWIM)
3099 CSR_WRITE_2(sc, RE_IM, 0);
3103 re_setup_sim_im(struct re_softc *sc)
3105 if (!RE_IS_8139CP(sc)) {
3109 * Datasheet says tick decreases at bus speed,
3110 * but it seems the clock runs a little bit
3111 * faster, so we do some compensation here.
3113 ticks = (sc->re_sim_time * sc->re_bus_speed * 8) / 5;
3114 CSR_WRITE_4(sc, RE_TIMERINT_8169, ticks);
3116 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); /* XXX */
3118 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */
3119 sc->re_flags |= RE_F_TIMER_INTR;
3123 re_disable_sim_im(struct re_softc *sc)
3125 if (!RE_IS_8139CP(sc))
3126 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0);
3128 CSR_WRITE_4(sc, RE_TIMERINT, 0);
3129 sc->re_flags &= ~RE_F_TIMER_INTR;
3133 re_config_imtype(struct re_softc *sc, int imtype)
3137 KKASSERT(sc->re_caps & RE_C_HWIM);
3139 case RE_IMTYPE_NONE:
3140 sc->re_intrs = RE_INTRS;
3141 sc->re_rx_ack = RE_ISR_RX_OK | RE_ISR_FIFO_OFLOW |
3143 sc->re_tx_ack = RE_ISR_TX_OK;
3147 sc->re_intrs = RE_INTRS_TIMER;
3148 sc->re_rx_ack = RE_ISR_TIMEOUT_EXPIRED;
3149 sc->re_tx_ack = RE_ISR_TIMEOUT_EXPIRED;
3153 panic("%s: unknown imtype %d\n",
3154 sc->arpcom.ac_if.if_xname, imtype);
3159 re_setup_intr(struct re_softc *sc, int enable_intrs, int imtype)
3161 re_config_imtype(sc, imtype);
3164 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
3166 CSR_WRITE_2(sc, RE_IMR, 0);
3169 case RE_IMTYPE_NONE:
3170 re_disable_sim_im(sc);
3171 re_disable_hw_im(sc);
3175 KKASSERT(sc->re_caps & RE_C_HWIM);
3176 re_disable_sim_im(sc);
3181 re_disable_hw_im(sc);
3182 re_setup_sim_im(sc);
3186 panic("%s: unknown imtype %d\n",
3187 sc->arpcom.ac_if.if_xname, imtype);
3192 re_get_eaddr(struct re_softc *sc, uint8_t *eaddr)
3196 if (sc->re_macver == RE_MACVER_11 || sc->re_macver == RE_MACVER_12) {
3200 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
3201 if (re_did == 0x8128) {
3202 uint16_t as[ETHER_ADDR_LEN / 2];
3205 * Get station address from the EEPROM.
3207 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3);
3208 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
3209 as[i] = le16toh(as[i]);
3210 bcopy(as, eaddr, sizeof(eaddr));
3216 * Get station address from IDRx.
3218 for (i = 0; i < ETHER_ADDR_LEN; ++i)
3219 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i);
3223 re_jpool_alloc(struct re_softc *sc)
3225 struct re_list_data *ldata = &sc->re_ldata;
3226 struct re_jbuf *jbuf;
3228 bus_size_t jpool_size;
3233 lwkt_serialize_init(&ldata->re_jbuf_serializer);
3235 ldata->re_jbuf = kmalloc(sizeof(struct re_jbuf) * RE_JBUF_COUNT(sc),
3236 M_DEVBUF, M_WAITOK | M_ZERO);
3238 jpool_size = RE_JBUF_COUNT(sc) * RE_JBUF_SIZE;
3240 error = bus_dmamem_coherent(sc->re_parent_tag,
3242 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3243 jpool_size, BUS_DMA_WAITOK, &dmem);
3245 device_printf(sc->re_dev, "could not allocate jumbo memory\n");
3248 ldata->re_jpool_tag = dmem.dmem_tag;
3249 ldata->re_jpool_map = dmem.dmem_map;
3250 ldata->re_jpool = dmem.dmem_addr;
3251 paddr = dmem.dmem_busaddr;
3253 /* ..and split it into 9KB chunks */
3254 SLIST_INIT(&ldata->re_jbuf_free);
3256 buf = ldata->re_jpool;
3257 for (i = 0; i < RE_JBUF_COUNT(sc); i++) {
3258 jbuf = &ldata->re_jbuf[i];
3264 jbuf->re_paddr = paddr;
3266 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link);
3268 buf += RE_JBUF_SIZE;
3269 paddr += RE_JBUF_SIZE;
3275 re_jpool_free(struct re_softc *sc)
3277 struct re_list_data *ldata = &sc->re_ldata;
3279 if (ldata->re_jpool_tag != NULL) {
3280 bus_dmamap_unload(ldata->re_jpool_tag, ldata->re_jpool_map);
3281 bus_dmamem_free(ldata->re_jpool_tag, ldata->re_jpool,
3282 ldata->re_jpool_map);
3283 bus_dma_tag_destroy(ldata->re_jpool_tag);
3284 ldata->re_jpool_tag = NULL;
3287 if (ldata->re_jbuf != NULL) {
3288 kfree(ldata->re_jbuf, M_DEVBUF);
3289 ldata->re_jbuf = NULL;
3293 static struct re_jbuf *
3294 re_jbuf_alloc(struct re_softc *sc)
3296 struct re_list_data *ldata = &sc->re_ldata;
3297 struct re_jbuf *jbuf;
3299 lwkt_serialize_enter(&ldata->re_jbuf_serializer);
3301 jbuf = SLIST_FIRST(&ldata->re_jbuf_free);
3303 SLIST_REMOVE_HEAD(&ldata->re_jbuf_free, re_link);
3307 lwkt_serialize_exit(&ldata->re_jbuf_serializer);
3313 re_jbuf_free(void *arg)
3315 struct re_jbuf *jbuf = arg;
3316 struct re_softc *sc = jbuf->re_sc;
3317 struct re_list_data *ldata = &sc->re_ldata;
3319 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) {
3320 panic("%s: free wrong jumbo buffer\n",
3321 sc->arpcom.ac_if.if_xname);
3322 } else if (jbuf->re_inuse == 0) {
3323 panic("%s: jumbo buffer already freed\n",
3324 sc->arpcom.ac_if.if_xname);
3327 lwkt_serialize_enter(&ldata->re_jbuf_serializer);
3328 atomic_subtract_int(&jbuf->re_inuse, 1);
3329 if (jbuf->re_inuse == 0)
3330 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link);
3331 lwkt_serialize_exit(&ldata->re_jbuf_serializer);
3335 re_jbuf_ref(void *arg)
3337 struct re_jbuf *jbuf = arg;
3338 struct re_softc *sc = jbuf->re_sc;
3339 struct re_list_data *ldata = &sc->re_ldata;
3341 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) {
3342 panic("%s: ref wrong jumbo buffer\n",
3343 sc->arpcom.ac_if.if_xname);
3344 } else if (jbuf->re_inuse == 0) {
3345 panic("%s: jumbo buffer already freed\n",
3346 sc->arpcom.ac_if.if_xname);
3348 atomic_add_int(&jbuf->re_inuse, 1);