2 * Copyright (c) 2001-2011, Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
32 #include "opt_ifpoll.h"
35 #include <sys/param.h>
37 #include <sys/endian.h>
38 #include <sys/interrupt.h>
39 #include <sys/kernel.h>
40 #include <sys/malloc.h>
44 #include <sys/serialize.h>
45 #include <sys/serialize2.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
49 #include <sys/systm.h>
52 #include <net/ethernet.h>
54 #include <net/if_arp.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/ifq_var.h>
58 #include <net/toeplitz.h>
59 #include <net/toeplitz2.h>
60 #include <net/vlan/if_vlan_var.h>
61 #include <net/vlan/if_vlan_ether.h>
62 #include <net/if_poll.h>
64 #include <netinet/in_systm.h>
65 #include <netinet/in.h>
66 #include <netinet/ip.h>
67 #include <netinet/tcp.h>
68 #include <netinet/udp.h>
70 #include <bus/pci/pcivar.h>
71 #include <bus/pci/pcireg.h>
73 #include <dev/netif/ig_hal/e1000_api.h>
74 #include <dev/netif/ig_hal/e1000_82575.h>
75 #include <dev/netif/igb/if_igb.h>
78 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
80 if (sc->rss_debug >= lvl) \
81 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
83 #else /* !IGB_RSS_DEBUG */
84 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
85 #endif /* IGB_RSS_DEBUG */
87 #define IGB_NAME "Intel(R) PRO/1000 "
88 #define IGB_DEVICE(id) \
89 { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
90 #define IGB_DEVICE_NULL { 0, 0, NULL }
92 static struct igb_device {
97 IGB_DEVICE(82575EB_COPPER),
98 IGB_DEVICE(82575EB_FIBER_SERDES),
99 IGB_DEVICE(82575GB_QUAD_COPPER),
101 IGB_DEVICE(82576_NS),
102 IGB_DEVICE(82576_NS_SERDES),
103 IGB_DEVICE(82576_FIBER),
104 IGB_DEVICE(82576_SERDES),
105 IGB_DEVICE(82576_SERDES_QUAD),
106 IGB_DEVICE(82576_QUAD_COPPER),
107 IGB_DEVICE(82576_QUAD_COPPER_ET2),
108 IGB_DEVICE(82576_VF),
109 IGB_DEVICE(82580_COPPER),
110 IGB_DEVICE(82580_FIBER),
111 IGB_DEVICE(82580_SERDES),
112 IGB_DEVICE(82580_SGMII),
113 IGB_DEVICE(82580_COPPER_DUAL),
114 IGB_DEVICE(82580_QUAD_FIBER),
115 IGB_DEVICE(DH89XXCC_SERDES),
116 IGB_DEVICE(DH89XXCC_SGMII),
117 IGB_DEVICE(DH89XXCC_SFP),
118 IGB_DEVICE(DH89XXCC_BACKPLANE),
119 IGB_DEVICE(I350_COPPER),
120 IGB_DEVICE(I350_FIBER),
121 IGB_DEVICE(I350_SERDES),
122 IGB_DEVICE(I350_SGMII),
125 /* required last entry */
129 static int igb_probe(device_t);
130 static int igb_attach(device_t);
131 static int igb_detach(device_t);
132 static int igb_shutdown(device_t);
133 static int igb_suspend(device_t);
134 static int igb_resume(device_t);
136 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
137 static void igb_setup_ifp(struct igb_softc *);
138 static boolean_t igb_txcsum_ctx(struct igb_tx_ring *, struct mbuf *);
139 static int igb_tso_pullup(struct igb_tx_ring *, struct mbuf **);
140 static void igb_tso_ctx(struct igb_tx_ring *, struct mbuf *, uint32_t *);
141 static void igb_add_sysctl(struct igb_softc *);
142 static int igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
143 static int igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS);
144 static int igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
145 static void igb_set_ring_inuse(struct igb_softc *, boolean_t);
146 static int igb_get_rxring_inuse(const struct igb_softc *, boolean_t);
148 static int igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
149 static int igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
152 static void igb_vf_init_stats(struct igb_softc *);
153 static void igb_reset(struct igb_softc *);
154 static void igb_update_stats_counters(struct igb_softc *);
155 static void igb_update_vf_stats_counters(struct igb_softc *);
156 static void igb_update_link_status(struct igb_softc *);
157 static void igb_init_tx_unit(struct igb_softc *);
158 static void igb_init_rx_unit(struct igb_softc *);
160 static void igb_set_vlan(struct igb_softc *);
161 static void igb_set_multi(struct igb_softc *);
162 static void igb_set_promisc(struct igb_softc *);
163 static void igb_disable_promisc(struct igb_softc *);
165 static int igb_alloc_rings(struct igb_softc *);
166 static void igb_free_rings(struct igb_softc *);
167 static int igb_create_tx_ring(struct igb_tx_ring *);
168 static int igb_create_rx_ring(struct igb_rx_ring *);
169 static void igb_free_tx_ring(struct igb_tx_ring *);
170 static void igb_free_rx_ring(struct igb_rx_ring *);
171 static void igb_destroy_tx_ring(struct igb_tx_ring *, int);
172 static void igb_destroy_rx_ring(struct igb_rx_ring *, int);
173 static void igb_init_tx_ring(struct igb_tx_ring *);
174 static int igb_init_rx_ring(struct igb_rx_ring *);
175 static int igb_newbuf(struct igb_rx_ring *, int, boolean_t);
176 static int igb_encap(struct igb_tx_ring *, struct mbuf **, int *, int *);
177 static void igb_rx_refresh(struct igb_rx_ring *, int);
179 static void igb_stop(struct igb_softc *);
180 static void igb_init(void *);
181 static int igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
182 static void igb_media_status(struct ifnet *, struct ifmediareq *);
183 static int igb_media_change(struct ifnet *);
184 static void igb_timer(void *);
185 static void igb_watchdog(struct ifaltq_subque *);
186 static void igb_start(struct ifnet *, struct ifaltq_subque *);
188 static void igb_npoll(struct ifnet *, struct ifpoll_info *);
189 static void igb_npoll_rx(struct ifnet *, void *, int);
190 static void igb_npoll_tx(struct ifnet *, void *, int);
191 static void igb_npoll_status(struct ifnet *);
193 static void igb_serialize(struct ifnet *, enum ifnet_serialize);
194 static void igb_deserialize(struct ifnet *, enum ifnet_serialize);
195 static int igb_tryserialize(struct ifnet *, enum ifnet_serialize);
197 static void igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
201 static void igb_intr(void *);
202 static void igb_intr_shared(void *);
203 static void igb_rxeof(struct igb_rx_ring *, int);
204 static void igb_txeof(struct igb_tx_ring *);
205 static void igb_set_eitr(struct igb_softc *, int, int);
206 static void igb_enable_intr(struct igb_softc *);
207 static void igb_disable_intr(struct igb_softc *);
208 static void igb_init_unshared_intr(struct igb_softc *);
209 static void igb_init_intr(struct igb_softc *);
210 static int igb_setup_intr(struct igb_softc *);
211 static void igb_set_txintr_mask(struct igb_tx_ring *, int *, int);
212 static void igb_set_rxintr_mask(struct igb_rx_ring *, int *, int);
213 static void igb_set_intr_mask(struct igb_softc *);
214 static int igb_alloc_intr(struct igb_softc *);
215 static void igb_free_intr(struct igb_softc *);
216 static void igb_teardown_intr(struct igb_softc *);
217 static void igb_msix_try_alloc(struct igb_softc *);
218 static void igb_msix_free(struct igb_softc *, boolean_t);
219 static int igb_msix_setup(struct igb_softc *);
220 static void igb_msix_teardown(struct igb_softc *, int);
221 static void igb_msix_rx(void *);
222 static void igb_msix_tx(void *);
223 static void igb_msix_status(void *);
225 /* Management and WOL Support */
226 static void igb_get_mgmt(struct igb_softc *);
227 static void igb_rel_mgmt(struct igb_softc *);
228 static void igb_get_hw_control(struct igb_softc *);
229 static void igb_rel_hw_control(struct igb_softc *);
230 static void igb_enable_wol(device_t);
232 static device_method_t igb_methods[] = {
233 /* Device interface */
234 DEVMETHOD(device_probe, igb_probe),
235 DEVMETHOD(device_attach, igb_attach),
236 DEVMETHOD(device_detach, igb_detach),
237 DEVMETHOD(device_shutdown, igb_shutdown),
238 DEVMETHOD(device_suspend, igb_suspend),
239 DEVMETHOD(device_resume, igb_resume),
243 static driver_t igb_driver = {
246 sizeof(struct igb_softc),
249 static devclass_t igb_devclass;
251 DECLARE_DUMMY_MODULE(if_igb);
252 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
253 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
255 static int igb_rxd = IGB_DEFAULT_RXD;
256 static int igb_txd = IGB_DEFAULT_TXD;
257 static int igb_rxr = 0;
258 static int igb_msi_enable = 1;
259 static int igb_msix_enable = 1;
260 static int igb_eee_disabled = 1; /* Energy Efficient Ethernet */
261 static int igb_fc_setting = e1000_fc_full;
264 * DMA Coalescing, only for i350 - default to off,
265 * this feature is for power savings
267 static int igb_dma_coalesce = 0;
269 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
270 TUNABLE_INT("hw.igb.txd", &igb_txd);
271 TUNABLE_INT("hw.igb.rxr", &igb_rxr);
272 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
273 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
274 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
277 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
278 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
281 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
283 /* Ignore Checksum bit is set */
284 if (staterr & E1000_RXD_STAT_IXSM)
287 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
289 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
291 if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
292 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
293 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
294 CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
295 mp->m_pkthdr.csum_data = htons(0xffff);
300 static __inline struct pktinfo *
301 igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
302 uint32_t hash, uint32_t hashtype, uint32_t staterr)
305 case E1000_RXDADV_RSSTYPE_IPV4_TCP:
306 pi->pi_netisr = NETISR_IP;
308 pi->pi_l3proto = IPPROTO_TCP;
311 case E1000_RXDADV_RSSTYPE_IPV4:
312 if (staterr & E1000_RXD_STAT_IXSM)
316 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
317 E1000_RXD_STAT_TCPCS) {
318 pi->pi_netisr = NETISR_IP;
320 pi->pi_l3proto = IPPROTO_UDP;
328 m->m_flags |= M_HASH;
329 m->m_pkthdr.hash = toeplitz_hash(hash);
334 igb_probe(device_t dev)
336 const struct igb_device *d;
339 vid = pci_get_vendor(dev);
340 did = pci_get_device(dev);
342 for (d = igb_devices; d->desc != NULL; ++d) {
343 if (vid == d->vid && did == d->did) {
344 device_set_desc(dev, d->desc);
352 igb_attach(device_t dev)
354 struct igb_softc *sc = device_get_softc(dev);
355 uint16_t eeprom_data;
356 int error = 0, i, j, ring_max;
358 int offset, offset_def;
363 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
364 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
365 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
366 igb_sysctl_nvm_info, "I", "NVM Information");
367 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
368 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
369 OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
370 adapter, 0, igb_set_flowcntl, "I", "Flow Control");
373 callout_init_mp(&sc->timer);
374 lwkt_serialize_init(&sc->main_serialize);
376 if_initname(&sc->arpcom.ac_if, device_get_name(dev),
377 device_get_unit(dev));
378 sc->dev = sc->osdep.dev = dev;
381 * Determine hardware and mac type
383 sc->hw.vendor_id = pci_get_vendor(dev);
384 sc->hw.device_id = pci_get_device(dev);
385 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
386 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
387 sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
389 if (e1000_set_mac_type(&sc->hw))
392 /* Are we a VF device? */
393 if (sc->hw.mac.type == e1000_vfadapt ||
394 sc->hw.mac.type == e1000_vfadapt_i350)
400 * Configure total supported RX/TX ring count
402 switch (sc->hw.mac.type) {
404 ring_max = IGB_MAX_RING_82575;
407 ring_max = IGB_MAX_RING_82580;
410 ring_max = IGB_MAX_RING_I350;
413 ring_max = IGB_MAX_RING_82576;
416 ring_max = IGB_MIN_RING;
419 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
420 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
422 sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
424 sc->rx_ring_inuse = sc->rx_ring_cnt;
425 sc->tx_ring_cnt = 1; /* XXX */
427 if (sc->hw.mac.type == e1000_82575)
428 sc->flags |= IGB_FLAG_TSO_IPLEN0;
430 /* Enable bus mastering */
431 pci_enable_busmaster(dev);
436 sc->mem_rid = PCIR_BAR(0);
437 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
439 if (sc->mem_res == NULL) {
440 device_printf(dev, "Unable to allocate bus resource: memory\n");
444 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
445 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
447 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
449 /* Save PCI command register for Shared Code */
450 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
451 sc->hw.back = &sc->osdep;
453 /* Do Shared Code initialization */
454 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
455 device_printf(dev, "Setup of Shared code failed\n");
460 e1000_get_bus_info(&sc->hw);
462 sc->hw.mac.autoneg = DO_AUTO_NEG;
463 sc->hw.phy.autoneg_wait_to_complete = FALSE;
464 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
467 if (sc->hw.phy.media_type == e1000_media_type_copper) {
468 sc->hw.phy.mdix = AUTO_ALL_MODES;
469 sc->hw.phy.disable_polarity_correction = FALSE;
470 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
473 /* Set the frame limits assuming standard ethernet sized frames. */
474 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
476 /* Allocate RX/TX rings */
477 error = igb_alloc_rings(sc);
483 * NPOLLING RX CPU offset
485 if (sc->rx_ring_cnt == ncpus2) {
488 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
489 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
490 if (offset >= ncpus2 ||
491 offset % sc->rx_ring_cnt != 0) {
492 device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
497 sc->rx_npoll_off = offset;
500 * NPOLLING TX CPU offset
502 offset_def = sc->rx_npoll_off;
503 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
504 if (offset >= ncpus2) {
505 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
509 sc->tx_npoll_off = offset;
512 /* Allocate interrupt */
513 error = igb_alloc_intr(sc);
521 sc->serializes[i++] = &sc->main_serialize;
523 sc->tx_serialize = i;
524 for (j = 0; j < sc->tx_ring_cnt; ++j)
525 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
527 sc->rx_serialize = i;
528 for (j = 0; j < sc->rx_ring_cnt; ++j)
529 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
531 sc->serialize_cnt = i;
532 KKASSERT(sc->serialize_cnt <= IGB_NSERIALIZE);
534 /* Allocate the appropriate stats memory */
536 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
538 igb_vf_init_stats(sc);
540 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
544 /* Allocate multicast array memory. */
545 sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
548 /* Some adapter-specific advanced features */
549 if (sc->hw.mac.type >= e1000_i350) {
551 igb_set_sysctl_value(adapter, "dma_coalesce",
552 "configure dma coalesce",
553 &adapter->dma_coalesce, igb_dma_coalesce);
554 igb_set_sysctl_value(adapter, "eee_disabled",
555 "enable Energy Efficient Ethernet",
556 &adapter->hw.dev_spec._82575.eee_disable,
559 sc->dma_coalesce = igb_dma_coalesce;
560 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
562 e1000_set_eee_i350(&sc->hw);
566 * Start from a known state, this is important in reading the nvm and
569 e1000_reset_hw(&sc->hw);
571 /* Make sure we have a good EEPROM before we read from it */
572 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
574 * Some PCI-E parts fail the first check due to
575 * the link being in sleep state, call it again,
576 * if it fails a second time its a real issue.
578 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
580 "The EEPROM Checksum Is Not Valid\n");
586 /* Copy the permanent MAC address out of the EEPROM */
587 if (e1000_read_mac_addr(&sc->hw) < 0) {
588 device_printf(dev, "EEPROM read error while reading MAC"
593 if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
594 device_printf(dev, "Invalid MAC address\n");
599 /* Setup OS specific network interface */
602 /* Add sysctl tree, must after igb_setup_ifp() */
605 /* Now get a good starting state */
608 /* Initialize statistics */
609 igb_update_stats_counters(sc);
611 sc->hw.mac.get_link_status = 1;
612 igb_update_link_status(sc);
614 /* Indicate SOL/IDER usage */
615 if (e1000_check_reset_block(&sc->hw)) {
617 "PHY reset is blocked due to SOL/IDER session.\n");
620 /* Determine if we have to control management hardware */
621 if (e1000_enable_mng_pass_thru(&sc->hw))
622 sc->flags |= IGB_FLAG_HAS_MGMT;
627 /* APME bit in EEPROM is mapped to WUC.APME */
628 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
630 sc->wol = E1000_WUFC_MAG;
631 /* XXX disable WOL */
635 /* Register for VLAN events */
636 adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
637 igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
638 adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
639 igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
643 igb_add_hw_stats(adapter);
646 error = igb_setup_intr(sc);
648 ether_ifdetach(&sc->arpcom.ac_if);
652 for (i = 0; i < sc->tx_ring_cnt; ++i) {
653 struct ifaltq_subque *ifsq =
654 ifq_get_subq(&sc->arpcom.ac_if.if_snd, i);
655 struct igb_tx_ring *txr = &sc->tx_rings[i];
657 ifsq_set_cpuid(ifsq, txr->tx_intr_cpuid);
658 ifsq_set_priv(ifsq, txr);
661 ifsq_watchdog_init(&txr->tx_watchdog, ifsq, igb_watchdog);
672 igb_detach(device_t dev)
674 struct igb_softc *sc = device_get_softc(dev);
676 if (device_is_attached(dev)) {
677 struct ifnet *ifp = &sc->arpcom.ac_if;
679 ifnet_serialize_all(ifp);
683 e1000_phy_hw_reset(&sc->hw);
685 /* Give control back to firmware */
687 igb_rel_hw_control(sc);
690 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
691 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
695 igb_teardown_intr(sc);
697 ifnet_deserialize_all(ifp);
700 } else if (sc->mem_res != NULL) {
701 igb_rel_hw_control(sc);
703 bus_generic_detach(dev);
705 if (sc->sysctl_tree != NULL)
706 sysctl_ctx_free(&sc->sysctl_ctx);
710 if (sc->msix_mem_res != NULL) {
711 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_mem_rid,
714 if (sc->mem_res != NULL) {
715 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
722 kfree(sc->mta, M_DEVBUF);
723 if (sc->stats != NULL)
724 kfree(sc->stats, M_DEVBUF);
730 igb_shutdown(device_t dev)
732 return igb_suspend(dev);
736 igb_suspend(device_t dev)
738 struct igb_softc *sc = device_get_softc(dev);
739 struct ifnet *ifp = &sc->arpcom.ac_if;
741 ifnet_serialize_all(ifp);
746 igb_rel_hw_control(sc);
749 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
750 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
754 ifnet_deserialize_all(ifp);
756 return bus_generic_suspend(dev);
760 igb_resume(device_t dev)
762 struct igb_softc *sc = device_get_softc(dev);
763 struct ifnet *ifp = &sc->arpcom.ac_if;
766 ifnet_serialize_all(ifp);
771 for (i = 0; i < sc->tx_ring_cnt; ++i)
772 ifsq_devstart_sched(sc->tx_rings[i].ifsq);
774 ifnet_deserialize_all(ifp);
776 return bus_generic_resume(dev);
780 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
782 struct igb_softc *sc = ifp->if_softc;
783 struct ifreq *ifr = (struct ifreq *)data;
784 int max_frame_size, mask, reinit;
787 ASSERT_IFNET_SERIALIZED_ALL(ifp);
791 max_frame_size = 9234;
792 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
798 ifp->if_mtu = ifr->ifr_mtu;
799 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
802 if (ifp->if_flags & IFF_RUNNING)
807 if (ifp->if_flags & IFF_UP) {
808 if (ifp->if_flags & IFF_RUNNING) {
809 if ((ifp->if_flags ^ sc->if_flags) &
810 (IFF_PROMISC | IFF_ALLMULTI)) {
811 igb_disable_promisc(sc);
817 } else if (ifp->if_flags & IFF_RUNNING) {
820 sc->if_flags = ifp->if_flags;
825 if (ifp->if_flags & IFF_RUNNING) {
826 igb_disable_intr(sc);
829 if (!(ifp->if_flags & IFF_NPOLLING))
837 * As the speed/duplex settings are being
838 * changed, we need toreset the PHY.
840 sc->hw.phy.reset_disable = FALSE;
842 /* Check SOL/IDER usage */
843 if (e1000_check_reset_block(&sc->hw)) {
844 if_printf(ifp, "Media change is "
845 "blocked due to SOL/IDER session.\n");
851 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
856 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
857 if (mask & IFCAP_RXCSUM) {
858 ifp->if_capenable ^= IFCAP_RXCSUM;
861 if (mask & IFCAP_VLAN_HWTAGGING) {
862 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
865 if (mask & IFCAP_TXCSUM) {
866 ifp->if_capenable ^= IFCAP_TXCSUM;
867 if (ifp->if_capenable & IFCAP_TXCSUM)
868 ifp->if_hwassist |= IGB_CSUM_FEATURES;
870 ifp->if_hwassist &= ~IGB_CSUM_FEATURES;
872 if (mask & IFCAP_TSO) {
873 ifp->if_capenable ^= IFCAP_TSO;
874 if (ifp->if_capenable & IFCAP_TSO)
875 ifp->if_hwassist |= CSUM_TSO;
877 ifp->if_hwassist &= ~CSUM_TSO;
879 if (mask & IFCAP_RSS)
880 ifp->if_capenable ^= IFCAP_RSS;
881 if (reinit && (ifp->if_flags & IFF_RUNNING))
886 error = ether_ioctl(ifp, command, data);
895 struct igb_softc *sc = xsc;
896 struct ifnet *ifp = &sc->arpcom.ac_if;
900 ASSERT_IFNET_SERIALIZED_ALL(ifp);
904 /* Get the latest mac address, User can use a LAA */
905 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
907 /* Put the address into the Receive Address Array */
908 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
911 igb_update_link_status(sc);
913 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
915 /* Configure for OS presence */
920 if (ifp->if_flags & IFF_NPOLLING)
924 /* Configured used RX/TX rings */
925 igb_set_ring_inuse(sc, polling);
927 /* Initialize interrupt */
930 /* Prepare transmit descriptors and buffers */
931 for (i = 0; i < sc->tx_ring_cnt; ++i)
932 igb_init_tx_ring(&sc->tx_rings[i]);
933 igb_init_tx_unit(sc);
935 /* Setup Multicast table */
940 * Figure out the desired mbuf pool
941 * for doing jumbo/packetsplit
943 if (adapter->max_frame_size <= 2048)
944 adapter->rx_mbuf_sz = MCLBYTES;
945 else if (adapter->max_frame_size <= 4096)
946 adapter->rx_mbuf_sz = MJUMPAGESIZE;
948 adapter->rx_mbuf_sz = MJUM9BYTES;
951 /* Prepare receive descriptors and buffers */
952 for (i = 0; i < sc->rx_ring_inuse; ++i) {
955 error = igb_init_rx_ring(&sc->rx_rings[i]);
957 if_printf(ifp, "Could not setup receive structures\n");
962 igb_init_rx_unit(sc);
964 /* Enable VLAN support */
965 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
968 /* Don't lose promiscuous settings */
971 ifp->if_flags |= IFF_RUNNING;
972 for (i = 0; i < sc->tx_ring_cnt; ++i) {
973 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
974 ifsq_watchdog_start(&sc->tx_rings[i].tx_watchdog);
977 if (polling || sc->intr_type == PCI_INTR_TYPE_MSIX)
978 sc->timer_cpuid = 0; /* XXX fixed */
980 sc->timer_cpuid = rman_get_cpuid(sc->intr_res);
981 callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
982 e1000_clear_hw_cntrs_base_generic(&sc->hw);
984 /* This clears any pending interrupts */
985 E1000_READ_REG(&sc->hw, E1000_ICR);
988 * Only enable interrupts if we are not polling, make sure
989 * they are off otherwise.
992 igb_disable_intr(sc);
995 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
998 /* Set Energy Efficient Ethernet */
999 e1000_set_eee_i350(&sc->hw);
1001 /* Don't reset the phy next time init gets called */
1002 sc->hw.phy.reset_disable = TRUE;
1006 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1008 struct igb_softc *sc = ifp->if_softc;
1009 u_char fiber_type = IFM_1000_SX;
1011 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1013 igb_update_link_status(sc);
1015 ifmr->ifm_status = IFM_AVALID;
1016 ifmr->ifm_active = IFM_ETHER;
1018 if (!sc->link_active)
1021 ifmr->ifm_status |= IFM_ACTIVE;
1023 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1024 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1025 ifmr->ifm_active |= fiber_type | IFM_FDX;
1027 switch (sc->link_speed) {
1029 ifmr->ifm_active |= IFM_10_T;
1033 ifmr->ifm_active |= IFM_100_TX;
1037 ifmr->ifm_active |= IFM_1000_T;
1040 if (sc->link_duplex == FULL_DUPLEX)
1041 ifmr->ifm_active |= IFM_FDX;
1043 ifmr->ifm_active |= IFM_HDX;
1048 igb_media_change(struct ifnet *ifp)
1050 struct igb_softc *sc = ifp->if_softc;
1051 struct ifmedia *ifm = &sc->media;
1053 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1055 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1058 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1060 sc->hw.mac.autoneg = DO_AUTO_NEG;
1061 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1067 sc->hw.mac.autoneg = DO_AUTO_NEG;
1068 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1072 sc->hw.mac.autoneg = FALSE;
1073 sc->hw.phy.autoneg_advertised = 0;
1074 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1075 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1077 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1081 sc->hw.mac.autoneg = FALSE;
1082 sc->hw.phy.autoneg_advertised = 0;
1083 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1084 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1086 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1090 if_printf(ifp, "Unsupported media type\n");
1100 igb_set_promisc(struct igb_softc *sc)
1102 struct ifnet *ifp = &sc->arpcom.ac_if;
1103 struct e1000_hw *hw = &sc->hw;
1107 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1111 reg = E1000_READ_REG(hw, E1000_RCTL);
1112 if (ifp->if_flags & IFF_PROMISC) {
1113 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1114 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1115 } else if (ifp->if_flags & IFF_ALLMULTI) {
1116 reg |= E1000_RCTL_MPE;
1117 reg &= ~E1000_RCTL_UPE;
1118 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1123 igb_disable_promisc(struct igb_softc *sc)
1125 struct e1000_hw *hw = &sc->hw;
1129 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1132 reg = E1000_READ_REG(hw, E1000_RCTL);
1133 reg &= ~E1000_RCTL_UPE;
1134 reg &= ~E1000_RCTL_MPE;
1135 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1139 igb_set_multi(struct igb_softc *sc)
1141 struct ifnet *ifp = &sc->arpcom.ac_if;
1142 struct ifmultiaddr *ifma;
1143 uint32_t reg_rctl = 0;
1148 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1150 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1151 if (ifma->ifma_addr->sa_family != AF_LINK)
1154 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1157 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1158 &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1162 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1163 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1164 reg_rctl |= E1000_RCTL_MPE;
1165 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1167 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1172 igb_timer(void *xsc)
1174 struct igb_softc *sc = xsc;
1176 lwkt_serialize_enter(&sc->main_serialize);
1178 igb_update_link_status(sc);
1179 igb_update_stats_counters(sc);
1181 callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
1183 lwkt_serialize_exit(&sc->main_serialize);
1187 igb_update_link_status(struct igb_softc *sc)
1189 struct ifnet *ifp = &sc->arpcom.ac_if;
1190 struct e1000_hw *hw = &sc->hw;
1191 uint32_t link_check, thstat, ctrl;
1193 link_check = thstat = ctrl = 0;
1195 /* Get the cached link value or read for real */
1196 switch (hw->phy.media_type) {
1197 case e1000_media_type_copper:
1198 if (hw->mac.get_link_status) {
1199 /* Do the work to read phy */
1200 e1000_check_for_link(hw);
1201 link_check = !hw->mac.get_link_status;
1207 case e1000_media_type_fiber:
1208 e1000_check_for_link(hw);
1209 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1212 case e1000_media_type_internal_serdes:
1213 e1000_check_for_link(hw);
1214 link_check = hw->mac.serdes_has_link;
1217 /* VF device is type_unknown */
1218 case e1000_media_type_unknown:
1219 e1000_check_for_link(hw);
1220 link_check = !hw->mac.get_link_status;
1226 /* Check for thermal downshift or shutdown */
1227 if (hw->mac.type == e1000_i350) {
1228 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1229 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1232 /* Now we check if a transition has happened */
1233 if (link_check && sc->link_active == 0) {
1234 e1000_get_speed_and_duplex(hw,
1235 &sc->link_speed, &sc->link_duplex);
1237 if_printf(ifp, "Link is up %d Mbps %s\n",
1239 sc->link_duplex == FULL_DUPLEX ?
1240 "Full Duplex" : "Half Duplex");
1242 sc->link_active = 1;
1244 ifp->if_baudrate = sc->link_speed * 1000000;
1245 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1246 (thstat & E1000_THSTAT_LINK_THROTTLE))
1247 if_printf(ifp, "Link: thermal downshift\n");
1248 /* This can sleep */
1249 ifp->if_link_state = LINK_STATE_UP;
1250 if_link_state_change(ifp);
1251 } else if (!link_check && sc->link_active == 1) {
1252 ifp->if_baudrate = sc->link_speed = 0;
1253 sc->link_duplex = 0;
1255 if_printf(ifp, "Link is Down\n");
1256 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1257 (thstat & E1000_THSTAT_PWR_DOWN))
1258 if_printf(ifp, "Link: thermal shutdown\n");
1259 sc->link_active = 0;
1260 /* This can sleep */
1261 ifp->if_link_state = LINK_STATE_DOWN;
1262 if_link_state_change(ifp);
1267 igb_stop(struct igb_softc *sc)
1269 struct ifnet *ifp = &sc->arpcom.ac_if;
1272 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1274 igb_disable_intr(sc);
1276 callout_stop(&sc->timer);
1278 ifp->if_flags &= ~IFF_RUNNING;
1279 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1280 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
1281 ifsq_watchdog_stop(&sc->tx_rings[i].tx_watchdog);
1284 e1000_reset_hw(&sc->hw);
1285 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1287 e1000_led_off(&sc->hw);
1288 e1000_cleanup_led(&sc->hw);
1290 for (i = 0; i < sc->tx_ring_cnt; ++i)
1291 igb_free_tx_ring(&sc->tx_rings[i]);
1292 for (i = 0; i < sc->rx_ring_cnt; ++i)
1293 igb_free_rx_ring(&sc->rx_rings[i]);
1297 igb_reset(struct igb_softc *sc)
1299 struct ifnet *ifp = &sc->arpcom.ac_if;
1300 struct e1000_hw *hw = &sc->hw;
1301 struct e1000_fc_info *fc = &hw->fc;
1305 /* Let the firmware know the OS is in control */
1306 igb_get_hw_control(sc);
1309 * Packet Buffer Allocation (PBA)
1310 * Writing PBA sets the receive portion of the buffer
1311 * the remainder is used for the transmit buffer.
1313 switch (hw->mac.type) {
1315 pba = E1000_PBA_32K;
1320 pba = E1000_READ_REG(hw, E1000_RXPBS);
1321 pba &= E1000_RXPBS_SIZE_MASK_82576;
1326 case e1000_vfadapt_i350:
1327 pba = E1000_READ_REG(hw, E1000_RXPBS);
1328 pba = e1000_rxpbs_adjust_82580(pba);
1330 /* XXX pba = E1000_PBA_35K; */
1336 /* Special needs in case of Jumbo frames */
1337 if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1338 uint32_t tx_space, min_tx, min_rx;
1340 pba = E1000_READ_REG(hw, E1000_PBA);
1341 tx_space = pba >> 16;
1344 min_tx = (sc->max_frame_size +
1345 sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1346 min_tx = roundup2(min_tx, 1024);
1348 min_rx = sc->max_frame_size;
1349 min_rx = roundup2(min_rx, 1024);
1351 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1352 pba = pba - (min_tx - tx_space);
1354 * if short on rx space, rx wins
1355 * and must trump tx adjustment
1360 E1000_WRITE_REG(hw, E1000_PBA, pba);
1364 * These parameters control the automatic generation (Tx) and
1365 * response (Rx) to Ethernet PAUSE frames.
1366 * - High water mark should allow for at least two frames to be
1367 * received after sending an XOFF.
1368 * - Low water mark works best when it is very near the high water mark.
1369 * This allows the receiver to restart by sending XON when it has
1372 hwm = min(((pba << 10) * 9 / 10),
1373 ((pba << 10) - 2 * sc->max_frame_size));
1375 if (hw->mac.type < e1000_82576) {
1376 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1377 fc->low_water = fc->high_water - 8;
1379 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1380 fc->low_water = fc->high_water - 16;
1382 fc->pause_time = IGB_FC_PAUSE_TIME;
1383 fc->send_xon = TRUE;
1385 /* Issue a global reset */
1387 E1000_WRITE_REG(hw, E1000_WUC, 0);
1389 if (e1000_init_hw(hw) < 0)
1390 if_printf(ifp, "Hardware Initialization Failed\n");
1392 /* Setup DMA Coalescing */
1393 if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1396 hwm = (pba - 4) << 10;
1397 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1398 & E1000_DMACR_DMACTHR_MASK;
1400 /* transition to L0x or L1 if available..*/
1401 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1403 /* timer = +-1000 usec in 32usec intervals */
1405 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1407 /* No lower threshold */
1408 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1410 /* set hwm to PBA - 2 * max frame size */
1411 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1413 /* Set the interval before transition */
1414 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1415 reg |= 0x800000FF; /* 255 usec */
1416 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1418 /* free space in tx packet buffer to wake from DMA coal */
1419 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1420 (20480 - (2 * sc->max_frame_size)) >> 6);
1422 /* make low power state decision controlled by DMA coal */
1423 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1424 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1425 reg | E1000_PCIEMISC_LX_DECISION);
1426 if_printf(ifp, "DMA Coalescing enabled\n");
1429 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1430 e1000_get_phy_info(hw);
1431 e1000_check_for_link(hw);
1435 igb_setup_ifp(struct igb_softc *sc)
1437 struct ifnet *ifp = &sc->arpcom.ac_if;
1440 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1441 ifp->if_init = igb_init;
1442 ifp->if_ioctl = igb_ioctl;
1443 ifp->if_start = igb_start;
1444 ifp->if_serialize = igb_serialize;
1445 ifp->if_deserialize = igb_deserialize;
1446 ifp->if_tryserialize = igb_tryserialize;
1448 ifp->if_serialize_assert = igb_serialize_assert;
1450 #ifdef IFPOLL_ENABLE
1451 ifp->if_npoll = igb_npoll;
1454 ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1455 ifq_set_ready(&ifp->if_snd);
1457 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1459 ifp->if_capabilities =
1460 IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_TSO;
1461 if (IGB_ENABLE_HWRSS(sc))
1462 ifp->if_capabilities |= IFCAP_RSS;
1463 ifp->if_capenable = ifp->if_capabilities;
1464 ifp->if_hwassist = IGB_CSUM_FEATURES | CSUM_TSO;
1467 * Tell the upper layer(s) we support long frames
1469 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1472 * Specify the media types supported by this adapter and register
1473 * callbacks to update media and link information
1475 ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1476 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1477 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1478 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1480 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1482 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1483 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1485 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1486 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1488 if (sc->hw.phy.type != e1000_phy_ife) {
1489 ifmedia_add(&sc->media,
1490 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1491 ifmedia_add(&sc->media,
1492 IFM_ETHER | IFM_1000_T, 0, NULL);
1495 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1496 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1500 igb_add_sysctl(struct igb_softc *sc)
1505 sysctl_ctx_init(&sc->sysctl_ctx);
1506 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1507 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1508 device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1509 if (sc->sysctl_tree == NULL) {
1510 device_printf(sc->dev, "can't add sysctl node\n");
1514 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1515 OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1516 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1517 OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1518 "# of RX rings used");
1519 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1520 OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1522 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1523 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1526 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
1527 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1528 SYSCTL_CHILDREN(sc->sysctl_tree),
1529 OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1530 sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1532 for (i = 0; i < sc->msix_cnt; ++i) {
1533 struct igb_msix_data *msix = &sc->msix_data[i];
1535 ksnprintf(node, sizeof(node), "msix%d_rate", i);
1536 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1537 SYSCTL_CHILDREN(sc->sysctl_tree),
1538 OID_AUTO, node, CTLTYPE_INT | CTLFLAG_RW,
1539 msix, 0, igb_sysctl_msix_rate, "I",
1540 msix->msix_rate_desc);
1544 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1545 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1546 sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1547 "# of segments per TX interrupt");
1549 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1550 OID_AUTO, "tx_wreg_nsegs", CTLFLAG_RW,
1551 &sc->tx_rings[0].wreg_nsegs, 0,
1552 "# of segments before write to hardare register");
1554 #ifdef IFPOLL_ENABLE
1555 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1556 OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
1557 sc, 0, igb_sysctl_npoll_rxoff, "I", "NPOLLING RX cpu offset");
1558 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1559 OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
1560 sc, 0, igb_sysctl_npoll_txoff, "I", "NPOLLING TX cpu offset");
1563 #ifdef IGB_RSS_DEBUG
1564 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1565 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1568 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1569 #ifdef IGB_RSS_DEBUG
1570 ksnprintf(node, sizeof(node), "rx%d_pkt", i);
1571 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1572 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1573 CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1575 ksnprintf(node, sizeof(node), "rx%d_wreg", i);
1576 SYSCTL_ADD_INT(&sc->sysctl_ctx,
1577 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1578 CTLFLAG_RW, &sc->rx_rings[i].rx_wreg, 0,
1579 "# of segments before write to hardare register");
1584 igb_alloc_rings(struct igb_softc *sc)
1589 * Create top level busdma tag
1591 error = bus_dma_tag_create(NULL, 1, 0,
1592 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1593 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1596 device_printf(sc->dev, "could not create top level DMA tag\n");
1601 * Allocate TX descriptor rings and buffers
1603 sc->tx_rings = kmalloc_cachealign(
1604 sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1605 M_DEVBUF, M_WAITOK | M_ZERO);
1606 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1607 struct igb_tx_ring *txr = &sc->tx_rings[i];
1609 /* Set up some basics */
1612 lwkt_serialize_init(&txr->tx_serialize);
1614 error = igb_create_tx_ring(txr);
1620 * Allocate RX descriptor rings and buffers
1622 sc->rx_rings = kmalloc_cachealign(
1623 sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1624 M_DEVBUF, M_WAITOK | M_ZERO);
1625 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1626 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1628 /* Set up some basics */
1631 lwkt_serialize_init(&rxr->rx_serialize);
1633 error = igb_create_rx_ring(rxr);
1642 igb_free_rings(struct igb_softc *sc)
1646 if (sc->tx_rings != NULL) {
1647 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1648 struct igb_tx_ring *txr = &sc->tx_rings[i];
1650 igb_destroy_tx_ring(txr, txr->num_tx_desc);
1652 kfree(sc->tx_rings, M_DEVBUF);
1655 if (sc->rx_rings != NULL) {
1656 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1657 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1659 igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1661 kfree(sc->rx_rings, M_DEVBUF);
1666 igb_create_tx_ring(struct igb_tx_ring *txr)
1668 int tsize, error, i, ntxd;
1671 * Validate number of transmit descriptors. It must not exceed
1672 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1674 ntxd = device_getenv_int(txr->sc->dev, "txd", igb_txd);
1675 if ((ntxd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN != 0 ||
1676 ntxd > IGB_MAX_TXD || ntxd < IGB_MIN_TXD) {
1677 device_printf(txr->sc->dev,
1678 "Using %d TX descriptors instead of %d!\n",
1679 IGB_DEFAULT_TXD, ntxd);
1680 txr->num_tx_desc = IGB_DEFAULT_TXD;
1682 txr->num_tx_desc = ntxd;
1686 * Allocate TX descriptor ring
1688 tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1690 txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1691 IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1692 &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1693 if (txr->txdma.dma_vaddr == NULL) {
1694 device_printf(txr->sc->dev,
1695 "Unable to allocate TX Descriptor memory\n");
1698 txr->tx_base = txr->txdma.dma_vaddr;
1699 bzero(txr->tx_base, tsize);
1701 tsize = __VM_CACHELINE_ALIGN(
1702 sizeof(struct igb_tx_buf) * txr->num_tx_desc);
1703 txr->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
1706 * Allocate TX head write-back buffer
1708 txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1709 __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1710 &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1711 if (txr->tx_hdr == NULL) {
1712 device_printf(txr->sc->dev,
1713 "Unable to allocate TX head write-back buffer\n");
1718 * Create DMA tag for TX buffers
1720 error = bus_dma_tag_create(txr->sc->parent_tag,
1721 1, 0, /* alignment, bounds */
1722 BUS_SPACE_MAXADDR, /* lowaddr */
1723 BUS_SPACE_MAXADDR, /* highaddr */
1724 NULL, NULL, /* filter, filterarg */
1725 IGB_TSO_SIZE, /* maxsize */
1726 IGB_MAX_SCATTER, /* nsegments */
1727 PAGE_SIZE, /* maxsegsize */
1728 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1729 BUS_DMA_ONEBPAGE, /* flags */
1732 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1733 kfree(txr->tx_buf, M_DEVBUF);
1739 * Create DMA maps for TX buffers
1741 for (i = 0; i < txr->num_tx_desc; ++i) {
1742 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1744 error = bus_dmamap_create(txr->tx_tag,
1745 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1747 device_printf(txr->sc->dev,
1748 "Unable to create TX DMA map\n");
1749 igb_destroy_tx_ring(txr, i);
1755 * Initialize various watermark
1757 txr->spare_desc = IGB_TX_SPARE;
1758 txr->intr_nsegs = txr->num_tx_desc / 16;
1759 txr->wreg_nsegs = 8;
1760 txr->oact_hi_desc = txr->num_tx_desc / 2;
1761 txr->oact_lo_desc = txr->num_tx_desc / 8;
1762 if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1763 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1764 if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1765 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1771 igb_free_tx_ring(struct igb_tx_ring *txr)
1775 for (i = 0; i < txr->num_tx_desc; ++i) {
1776 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1778 if (txbuf->m_head != NULL) {
1779 bus_dmamap_unload(txr->tx_tag, txbuf->map);
1780 m_freem(txbuf->m_head);
1781 txbuf->m_head = NULL;
1787 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1791 if (txr->txdma.dma_vaddr != NULL) {
1792 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1793 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1794 txr->txdma.dma_map);
1795 bus_dma_tag_destroy(txr->txdma.dma_tag);
1796 txr->txdma.dma_vaddr = NULL;
1799 if (txr->tx_hdr != NULL) {
1800 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1801 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1803 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1807 if (txr->tx_buf == NULL)
1810 for (i = 0; i < ndesc; ++i) {
1811 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1813 KKASSERT(txbuf->m_head == NULL);
1814 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1816 bus_dma_tag_destroy(txr->tx_tag);
1818 kfree(txr->tx_buf, M_DEVBUF);
1823 igb_init_tx_ring(struct igb_tx_ring *txr)
1825 /* Clear the old descriptor contents */
1827 sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1829 /* Clear TX head write-back buffer */
1833 txr->next_avail_desc = 0;
1834 txr->next_to_clean = 0;
1837 /* Set number of descriptors available */
1838 txr->tx_avail = txr->num_tx_desc;
1842 igb_init_tx_unit(struct igb_softc *sc)
1844 struct e1000_hw *hw = &sc->hw;
1848 /* Setup the Tx Descriptor Rings */
1849 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1850 struct igb_tx_ring *txr = &sc->tx_rings[i];
1851 uint64_t bus_addr = txr->txdma.dma_paddr;
1852 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1853 uint32_t txdctl = 0;
1854 uint32_t dca_txctrl;
1856 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1857 txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1858 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1859 (uint32_t)(bus_addr >> 32));
1860 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1861 (uint32_t)bus_addr);
1863 /* Setup the HW Tx Head and Tail descriptor pointers */
1864 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1865 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1867 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1868 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1869 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1872 * Don't set WB_on_EITR:
1873 * - 82575 does not have it
1874 * - It almost has no effect on 82576, see:
1875 * 82576 specification update errata #26
1876 * - It causes unnecessary bus traffic
1878 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1879 (uint32_t)(hdr_paddr >> 32));
1880 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1881 ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1884 * WTHRESH is ignored by the hardware, since header
1885 * write back mode is used.
1887 txdctl |= IGB_TX_PTHRESH;
1888 txdctl |= IGB_TX_HTHRESH << 8;
1889 txdctl |= IGB_TX_WTHRESH << 16;
1890 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1891 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1897 e1000_config_collision_dist(hw);
1899 /* Program the Transmit Control Register */
1900 tctl = E1000_READ_REG(hw, E1000_TCTL);
1901 tctl &= ~E1000_TCTL_CT;
1902 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1903 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1905 /* This write will effectively turn on the transmit unit. */
1906 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1910 igb_txcsum_ctx(struct igb_tx_ring *txr, struct mbuf *mp)
1912 struct e1000_adv_tx_context_desc *TXD;
1913 uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1914 int ehdrlen, ctxd, ip_hlen = 0;
1915 boolean_t offload = TRUE;
1917 if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1920 vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1922 ctxd = txr->next_avail_desc;
1923 TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1926 * In advanced descriptors the vlan tag must
1927 * be placed into the context descriptor, thus
1928 * we need to be here just for that setup.
1930 if (mp->m_flags & M_VLANTAG) {
1933 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1934 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1935 } else if (!offload) {
1939 ehdrlen = mp->m_pkthdr.csum_lhlen;
1940 KASSERT(ehdrlen > 0, ("invalid ether hlen"));
1942 /* Set the ether header length */
1943 vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1944 if (mp->m_pkthdr.csum_flags & CSUM_IP) {
1945 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1946 ip_hlen = mp->m_pkthdr.csum_iphlen;
1947 KASSERT(ip_hlen > 0, ("invalid ip hlen"));
1949 vlan_macip_lens |= ip_hlen;
1951 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1952 if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1953 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1954 else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1955 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1957 /* 82575 needs the queue index added */
1958 if (txr->sc->hw.mac.type == e1000_82575)
1959 mss_l4len_idx = txr->me << 4;
1961 /* Now copy bits into descriptor */
1962 TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1963 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1964 TXD->seqnum_seed = htole32(0);
1965 TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1967 /* We've consumed the first desc, adjust counters */
1968 if (++ctxd == txr->num_tx_desc)
1970 txr->next_avail_desc = ctxd;
1977 igb_txeof(struct igb_tx_ring *txr)
1979 struct ifnet *ifp = &txr->sc->arpcom.ac_if;
1980 int first, hdr, avail;
1982 if (txr->tx_avail == txr->num_tx_desc)
1985 first = txr->next_to_clean;
1986 hdr = *(txr->tx_hdr);
1991 avail = txr->tx_avail;
1992 while (first != hdr) {
1993 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
1996 if (txbuf->m_head) {
1997 bus_dmamap_unload(txr->tx_tag, txbuf->map);
1998 m_freem(txbuf->m_head);
1999 txbuf->m_head = NULL;
2002 if (++first == txr->num_tx_desc)
2005 txr->next_to_clean = first;
2006 txr->tx_avail = avail;
2009 * If we have a minimum free, clear OACTIVE
2010 * to tell the stack that it is OK to send packets.
2012 if (IGB_IS_NOT_OACTIVE(txr)) {
2013 ifsq_clr_oactive(txr->ifsq);
2016 * We have enough TX descriptors, turn off
2017 * the watchdog. We allow small amount of
2018 * packets (roughly intr_nsegs) pending on
2019 * the transmit ring.
2021 txr->tx_watchdog.wd_timer = 0;
2026 igb_create_rx_ring(struct igb_rx_ring *rxr)
2028 int rsize, i, error, nrxd;
2031 * Validate number of receive descriptors. It must not exceed
2032 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
2034 nrxd = device_getenv_int(rxr->sc->dev, "rxd", igb_rxd);
2035 if ((nrxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN != 0 ||
2036 nrxd > IGB_MAX_RXD || nrxd < IGB_MIN_RXD) {
2037 device_printf(rxr->sc->dev,
2038 "Using %d RX descriptors instead of %d!\n",
2039 IGB_DEFAULT_RXD, nrxd);
2040 rxr->num_rx_desc = IGB_DEFAULT_RXD;
2042 rxr->num_rx_desc = nrxd;
2046 * Allocate RX descriptor ring
2048 rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
2050 rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
2051 IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2052 &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
2053 &rxr->rxdma.dma_paddr);
2054 if (rxr->rxdma.dma_vaddr == NULL) {
2055 device_printf(rxr->sc->dev,
2056 "Unable to allocate RxDescriptor memory\n");
2059 rxr->rx_base = rxr->rxdma.dma_vaddr;
2060 bzero(rxr->rx_base, rsize);
2062 rsize = __VM_CACHELINE_ALIGN(
2063 sizeof(struct igb_rx_buf) * rxr->num_rx_desc);
2064 rxr->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
2067 * Create DMA tag for RX buffers
2069 error = bus_dma_tag_create(rxr->sc->parent_tag,
2070 1, 0, /* alignment, bounds */
2071 BUS_SPACE_MAXADDR, /* lowaddr */
2072 BUS_SPACE_MAXADDR, /* highaddr */
2073 NULL, NULL, /* filter, filterarg */
2074 MCLBYTES, /* maxsize */
2076 MCLBYTES, /* maxsegsize */
2077 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2080 device_printf(rxr->sc->dev,
2081 "Unable to create RX payload DMA tag\n");
2082 kfree(rxr->rx_buf, M_DEVBUF);
2088 * Create spare DMA map for RX buffers
2090 error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2093 device_printf(rxr->sc->dev,
2094 "Unable to create spare RX DMA maps\n");
2095 bus_dma_tag_destroy(rxr->rx_tag);
2096 kfree(rxr->rx_buf, M_DEVBUF);
2102 * Create DMA maps for RX buffers
2104 for (i = 0; i < rxr->num_rx_desc; i++) {
2105 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2107 error = bus_dmamap_create(rxr->rx_tag,
2108 BUS_DMA_WAITOK, &rxbuf->map);
2110 device_printf(rxr->sc->dev,
2111 "Unable to create RX DMA maps\n");
2112 igb_destroy_rx_ring(rxr, i);
2118 * Initialize various watermark
2126 igb_free_rx_ring(struct igb_rx_ring *rxr)
2130 for (i = 0; i < rxr->num_rx_desc; ++i) {
2131 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2133 if (rxbuf->m_head != NULL) {
2134 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2135 m_freem(rxbuf->m_head);
2136 rxbuf->m_head = NULL;
2140 if (rxr->fmp != NULL)
2147 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2151 if (rxr->rxdma.dma_vaddr != NULL) {
2152 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2153 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2154 rxr->rxdma.dma_map);
2155 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2156 rxr->rxdma.dma_vaddr = NULL;
2159 if (rxr->rx_buf == NULL)
2162 for (i = 0; i < ndesc; ++i) {
2163 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2165 KKASSERT(rxbuf->m_head == NULL);
2166 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2168 bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2169 bus_dma_tag_destroy(rxr->rx_tag);
2171 kfree(rxr->rx_buf, M_DEVBUF);
2176 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2178 rxd->read.pkt_addr = htole64(rxbuf->paddr);
2179 rxd->wb.upper.status_error = 0;
2183 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2186 bus_dma_segment_t seg;
2188 struct igb_rx_buf *rxbuf;
2191 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2194 if_printf(&rxr->sc->arpcom.ac_if,
2195 "Unable to allocate RX mbuf\n");
2199 m->m_len = m->m_pkthdr.len = MCLBYTES;
2201 if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2202 m_adj(m, ETHER_ALIGN);
2204 error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2205 rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2209 if_printf(&rxr->sc->arpcom.ac_if,
2210 "Unable to load RX mbuf\n");
2215 rxbuf = &rxr->rx_buf[i];
2216 if (rxbuf->m_head != NULL)
2217 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2220 rxbuf->map = rxr->rx_sparemap;
2221 rxr->rx_sparemap = map;
2224 rxbuf->paddr = seg.ds_addr;
2226 igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2231 igb_init_rx_ring(struct igb_rx_ring *rxr)
2235 /* Clear the ring contents */
2237 rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2239 /* Now replenish the ring mbufs */
2240 for (i = 0; i < rxr->num_rx_desc; ++i) {
2243 error = igb_newbuf(rxr, i, TRUE);
2248 /* Setup our descriptor indices */
2249 rxr->next_to_check = 0;
2253 rxr->discard = FALSE;
2259 igb_init_rx_unit(struct igb_softc *sc)
2261 struct ifnet *ifp = &sc->arpcom.ac_if;
2262 struct e1000_hw *hw = &sc->hw;
2263 uint32_t rctl, rxcsum, srrctl = 0;
2267 * Make sure receives are disabled while setting
2268 * up the descriptor ring
2270 rctl = E1000_READ_REG(hw, E1000_RCTL);
2271 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2275 ** Set up for header split
2277 if (igb_header_split) {
2278 /* Use a standard mbuf for the header */
2279 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2280 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2283 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2286 ** Set up for jumbo frames
2288 if (ifp->if_mtu > ETHERMTU) {
2289 rctl |= E1000_RCTL_LPE;
2291 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2292 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2293 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2294 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2295 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2296 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2298 /* Set maximum packet len */
2299 psize = adapter->max_frame_size;
2300 /* are we on a vlan? */
2301 if (adapter->ifp->if_vlantrunk != NULL)
2302 psize += VLAN_TAG_SIZE;
2303 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2305 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2306 rctl |= E1000_RCTL_SZ_2048;
2309 rctl &= ~E1000_RCTL_LPE;
2310 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2311 rctl |= E1000_RCTL_SZ_2048;
2314 /* Setup the Base and Length of the Rx Descriptor Rings */
2315 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2316 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2317 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2320 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2321 rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
2322 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2323 (uint32_t)(bus_addr >> 32));
2324 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2325 (uint32_t)bus_addr);
2326 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2327 /* Enable this Queue */
2328 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2329 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2330 rxdctl &= 0xFFF00000;
2331 rxdctl |= IGB_RX_PTHRESH;
2332 rxdctl |= IGB_RX_HTHRESH << 8;
2334 * Don't set WTHRESH to a value above 1 on 82576, see:
2335 * 82576 specification update errata #26
2337 rxdctl |= IGB_RX_WTHRESH << 16;
2338 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2341 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2342 rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2345 * Receive Checksum Offload for TCP and UDP
2347 * Checksum offloading is also enabled if multiple receive
2348 * queue is to be supported, since we need it to figure out
2351 if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2354 * PCSD must be enabled to enable multiple
2357 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2360 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2363 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2365 if (IGB_ENABLE_HWRSS(sc)) {
2366 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
2367 uint32_t reta_shift;
2372 * When we reach here, RSS has already been disabled
2373 * in igb_stop(), so we could safely configure RSS key
2374 * and redirect table.
2380 toeplitz_get_key(key, sizeof(key));
2381 for (i = 0; i < IGB_NRSSRK; ++i) {
2384 rssrk = IGB_RSSRK_VAL(key, i);
2385 IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2387 E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
2391 * Configure RSS redirect table in following fashion:
2392 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2394 reta_shift = IGB_RETA_SHIFT;
2395 if (hw->mac.type == e1000_82575)
2396 reta_shift = IGB_RETA_SHIFT_82575;
2399 for (j = 0; j < IGB_NRETA; ++j) {
2402 for (i = 0; i < IGB_RETA_SIZE; ++i) {
2405 q = (r % sc->rx_ring_inuse) << reta_shift;
2406 reta |= q << (8 * i);
2409 IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2410 E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2414 * Enable multiple receive queues.
2415 * Enable IPv4 RSS standard hash functions.
2416 * Disable RSS interrupt on 82575
2418 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2419 E1000_MRQC_ENABLE_RSS_4Q |
2420 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2421 E1000_MRQC_RSS_FIELD_IPV4);
2424 /* Setup the Receive Control Register */
2425 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2426 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2427 E1000_RCTL_RDMTS_HALF |
2428 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2429 /* Strip CRC bytes. */
2430 rctl |= E1000_RCTL_SECRC;
2431 /* Make sure VLAN Filters are off */
2432 rctl &= ~E1000_RCTL_VFE;
2433 /* Don't store bad packets */
2434 rctl &= ~E1000_RCTL_SBP;
2436 /* Enable Receives */
2437 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2440 * Setup the HW Rx Head and Tail Descriptor Pointers
2441 * - needs to be after enable
2443 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2444 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2446 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2447 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
2452 igb_rx_refresh(struct igb_rx_ring *rxr, int i)
2455 i = rxr->num_rx_desc - 1;
2456 E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2460 igb_rxeof(struct igb_rx_ring *rxr, int count)
2462 struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2463 union e1000_adv_rx_desc *cur;
2467 i = rxr->next_to_check;
2468 cur = &rxr->rx_base[i];
2469 staterr = le32toh(cur->wb.upper.status_error);
2471 if ((staterr & E1000_RXD_STAT_DD) == 0)
2474 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2475 struct pktinfo *pi = NULL, pi0;
2476 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2477 struct mbuf *m = NULL;
2480 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2485 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2487 struct mbuf *mp = rxbuf->m_head;
2488 uint32_t hash, hashtype;
2492 len = le16toh(cur->wb.upper.length);
2493 if (rxr->sc->hw.mac.type == e1000_i350 &&
2494 (staterr & E1000_RXDEXT_STATERR_LB))
2495 vlan = be16toh(cur->wb.upper.vlan);
2497 vlan = le16toh(cur->wb.upper.vlan);
2499 hash = le32toh(cur->wb.lower.hi_dword.rss);
2500 hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2501 E1000_RXDADV_RSSTYPE_MASK;
2503 IGB_RSS_DPRINTF(rxr->sc, 10,
2504 "ring%d, hash 0x%08x, hashtype %u\n",
2505 rxr->me, hash, hashtype);
2507 bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2508 BUS_DMASYNC_POSTREAD);
2510 if (igb_newbuf(rxr, i, FALSE) != 0) {
2516 if (rxr->fmp == NULL) {
2517 mp->m_pkthdr.len = len;
2521 rxr->lmp->m_next = mp;
2522 rxr->lmp = rxr->lmp->m_next;
2523 rxr->fmp->m_pkthdr.len += len;
2531 m->m_pkthdr.rcvif = ifp;
2534 if (ifp->if_capenable & IFCAP_RXCSUM)
2535 igb_rxcsum(staterr, m);
2537 if (staterr & E1000_RXD_STAT_VP) {
2538 m->m_pkthdr.ether_vlantag = vlan;
2539 m->m_flags |= M_VLANTAG;
2542 if (ifp->if_capenable & IFCAP_RSS) {
2543 pi = igb_rssinfo(m, &pi0,
2544 hash, hashtype, staterr);
2546 #ifdef IGB_RSS_DEBUG
2553 igb_setup_rxdesc(cur, rxbuf);
2555 rxr->discard = TRUE;
2557 rxr->discard = FALSE;
2558 if (rxr->fmp != NULL) {
2567 ether_input_pkt(ifp, m, pi);
2569 /* Advance our pointers to the next descriptor. */
2570 if (++i == rxr->num_rx_desc)
2573 if (ncoll >= rxr->rx_wreg) {
2574 igb_rx_refresh(rxr, i);
2578 cur = &rxr->rx_base[i];
2579 staterr = le32toh(cur->wb.upper.status_error);
2581 rxr->next_to_check = i;
2584 igb_rx_refresh(rxr, i);
2589 igb_set_vlan(struct igb_softc *sc)
2591 struct e1000_hw *hw = &sc->hw;
2594 struct ifnet *ifp = sc->arpcom.ac_if;
2598 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2602 reg = E1000_READ_REG(hw, E1000_CTRL);
2603 reg |= E1000_CTRL_VME;
2604 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2607 /* Enable the Filter Table */
2608 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2609 reg = E1000_READ_REG(hw, E1000_RCTL);
2610 reg &= ~E1000_RCTL_CFIEN;
2611 reg |= E1000_RCTL_VFE;
2612 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2616 /* Update the frame size */
2617 E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2618 sc->max_frame_size + VLAN_TAG_SIZE);
2621 /* Don't bother with table if no vlans */
2622 if ((adapter->num_vlans == 0) ||
2623 ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2626 ** A soft reset zero's out the VFTA, so
2627 ** we need to repopulate it now.
2629 for (int i = 0; i < IGB_VFTA_SIZE; i++)
2630 if (adapter->shadow_vfta[i] != 0) {
2631 if (adapter->vf_ifp)
2632 e1000_vfta_set_vf(hw,
2633 adapter->shadow_vfta[i], TRUE);
2635 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2636 i, adapter->shadow_vfta[i]);
2642 igb_enable_intr(struct igb_softc *sc)
2644 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2645 lwkt_serialize_handler_enable(&sc->main_serialize);
2649 for (i = 0; i < sc->msix_cnt; ++i) {
2650 lwkt_serialize_handler_enable(
2651 sc->msix_data[i].msix_serialize);
2655 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2656 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
2657 E1000_WRITE_REG(&sc->hw, E1000_EIAC, sc->intr_mask);
2659 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2660 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2661 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2662 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2664 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2666 E1000_WRITE_FLUSH(&sc->hw);
2670 igb_disable_intr(struct igb_softc *sc)
2672 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2673 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2674 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2676 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2677 E1000_WRITE_FLUSH(&sc->hw);
2679 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2680 lwkt_serialize_handler_disable(&sc->main_serialize);
2684 for (i = 0; i < sc->msix_cnt; ++i) {
2685 lwkt_serialize_handler_disable(
2686 sc->msix_data[i].msix_serialize);
2692 * Bit of a misnomer, what this really means is
2693 * to enable OS management of the system... aka
2694 * to disable special hardware management features
2697 igb_get_mgmt(struct igb_softc *sc)
2699 if (sc->flags & IGB_FLAG_HAS_MGMT) {
2700 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2701 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2703 /* disable hardware interception of ARP */
2704 manc &= ~E1000_MANC_ARP_EN;
2706 /* enable receiving management packets to the host */
2707 manc |= E1000_MANC_EN_MNG2HOST;
2708 manc2h |= 1 << 5; /* Mng Port 623 */
2709 manc2h |= 1 << 6; /* Mng Port 664 */
2710 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2711 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2716 * Give control back to hardware management controller
2720 igb_rel_mgmt(struct igb_softc *sc)
2722 if (sc->flags & IGB_FLAG_HAS_MGMT) {
2723 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2725 /* Re-enable hardware interception of ARP */
2726 manc |= E1000_MANC_ARP_EN;
2727 manc &= ~E1000_MANC_EN_MNG2HOST;
2729 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2734 * Sets CTRL_EXT:DRV_LOAD bit.
2736 * For ASF and Pass Through versions of f/w this means that
2737 * the driver is loaded.
2740 igb_get_hw_control(struct igb_softc *sc)
2747 /* Let firmware know the driver has taken over */
2748 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2749 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2750 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2754 * Resets CTRL_EXT:DRV_LOAD bit.
2756 * For ASF and Pass Through versions of f/w this means that the
2757 * driver is no longer loaded.
2760 igb_rel_hw_control(struct igb_softc *sc)
2767 /* Let firmware taken over control of h/w */
2768 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2769 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2770 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2774 igb_is_valid_ether_addr(const uint8_t *addr)
2776 uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2778 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2784 * Enable PCI Wake On Lan capability
2787 igb_enable_wol(device_t dev)
2789 uint16_t cap, status;
2792 /* First find the capabilities pointer*/
2793 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2795 /* Read the PM Capabilities */
2796 id = pci_read_config(dev, cap, 1);
2797 if (id != PCIY_PMG) /* Something wrong */
2801 * OK, we have the power capabilities,
2802 * so now get the status register
2804 cap += PCIR_POWER_STATUS;
2805 status = pci_read_config(dev, cap, 2);
2806 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2807 pci_write_config(dev, cap, status, 2);
2811 igb_update_stats_counters(struct igb_softc *sc)
2813 struct e1000_hw *hw = &sc->hw;
2814 struct e1000_hw_stats *stats;
2815 struct ifnet *ifp = &sc->arpcom.ac_if;
2818 * The virtual function adapter has only a
2819 * small controlled set of stats, do only
2823 igb_update_vf_stats_counters(sc);
2828 if (sc->hw.phy.media_type == e1000_media_type_copper ||
2829 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2831 E1000_READ_REG(hw,E1000_SYMERRS);
2832 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2835 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2836 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2837 stats->scc += E1000_READ_REG(hw, E1000_SCC);
2838 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2840 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2841 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2842 stats->colc += E1000_READ_REG(hw, E1000_COLC);
2843 stats->dc += E1000_READ_REG(hw, E1000_DC);
2844 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2845 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2846 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2849 * For watchdog management we need to know if we have been
2850 * paused during the last interval, so capture that here.
2852 sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2853 stats->xoffrxc += sc->pause_frames;
2854 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2855 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2856 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2857 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2858 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2859 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2860 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2861 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2862 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2863 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2864 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2865 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2867 /* For the 64-bit byte counters the low dword must be read first. */
2868 /* Both registers clear on the read of the high dword */
2870 stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2871 ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2872 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2873 ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2875 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2876 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2877 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2878 stats->roc += E1000_READ_REG(hw, E1000_ROC);
2879 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2881 stats->tor += E1000_READ_REG(hw, E1000_TORH);
2882 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2884 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2885 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2886 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2887 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2888 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2889 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2890 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2891 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2892 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2893 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2895 /* Interrupt Counts */
2897 stats->iac += E1000_READ_REG(hw, E1000_IAC);
2898 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2899 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2900 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2901 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2902 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2903 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2904 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2905 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2907 /* Host to Card Statistics */
2909 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2910 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2911 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2912 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2913 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2914 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2915 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2916 stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2917 ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2918 stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2919 ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2920 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2921 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2922 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2924 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2925 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2926 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2927 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2928 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2929 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2931 ifp->if_collisions = stats->colc;
2934 ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2935 stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2938 ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2940 /* Driver specific counters */
2941 sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2942 sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2943 sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2944 sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2945 sc->packet_buf_alloc_tx =
2946 ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2947 sc->packet_buf_alloc_rx =
2948 (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2952 igb_vf_init_stats(struct igb_softc *sc)
2954 struct e1000_hw *hw = &sc->hw;
2955 struct e1000_vf_stats *stats;
2958 stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2959 stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2960 stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2961 stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2962 stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2966 igb_update_vf_stats_counters(struct igb_softc *sc)
2968 struct e1000_hw *hw = &sc->hw;
2969 struct e1000_vf_stats *stats;
2971 if (sc->link_speed == 0)
2975 UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2976 UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2977 UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2978 UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2979 UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
2982 #ifdef IFPOLL_ENABLE
2985 igb_npoll_status(struct ifnet *ifp)
2987 struct igb_softc *sc = ifp->if_softc;
2990 ASSERT_SERIALIZED(&sc->main_serialize);
2992 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2993 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2994 sc->hw.mac.get_link_status = 1;
2995 igb_update_link_status(sc);
3000 igb_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
3002 struct igb_tx_ring *txr = arg;
3004 ASSERT_SERIALIZED(&txr->tx_serialize);
3007 if (!ifsq_is_empty(txr->ifsq))
3008 ifsq_devstart(txr->ifsq);
3012 igb_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
3014 struct igb_rx_ring *rxr = arg;
3016 ASSERT_SERIALIZED(&rxr->rx_serialize);
3018 igb_rxeof(rxr, cycle);
3022 igb_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3024 struct igb_softc *sc = ifp->if_softc;
3027 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3032 info->ifpi_status.status_func = igb_npoll_status;
3033 info->ifpi_status.serializer = &sc->main_serialize;
3035 off = sc->tx_npoll_off;
3036 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3037 struct igb_tx_ring *txr = &sc->tx_rings[i];
3040 KKASSERT(idx < ncpus2);
3041 info->ifpi_tx[idx].poll_func = igb_npoll_tx;
3042 info->ifpi_tx[idx].arg = txr;
3043 info->ifpi_tx[idx].serializer = &txr->tx_serialize;
3044 ifsq_set_cpuid(txr->ifsq, idx);
3047 off = sc->rx_npoll_off;
3048 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3049 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3052 KKASSERT(idx < ncpus2);
3053 info->ifpi_rx[idx].poll_func = igb_npoll_rx;
3054 info->ifpi_rx[idx].arg = rxr;
3055 info->ifpi_rx[idx].serializer = &rxr->rx_serialize;
3058 if (ifp->if_flags & IFF_RUNNING) {
3059 if (igb_get_rxring_inuse(sc, TRUE) ==
3061 igb_disable_intr(sc);
3066 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3067 struct igb_tx_ring *txr = &sc->tx_rings[i];
3069 ifsq_set_cpuid(txr->ifsq, txr->tx_intr_cpuid);
3072 if (ifp->if_flags & IFF_RUNNING) {
3073 if (igb_get_rxring_inuse(sc, FALSE) ==
3075 igb_enable_intr(sc);
3082 #endif /* IFPOLL_ENABLE */
3087 struct igb_softc *sc = xsc;
3088 struct ifnet *ifp = &sc->arpcom.ac_if;
3091 ASSERT_SERIALIZED(&sc->main_serialize);
3093 eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
3098 if (ifp->if_flags & IFF_RUNNING) {
3099 struct igb_tx_ring *txr = &sc->tx_rings[0];
3102 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3103 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3105 if (eicr & rxr->rx_intr_mask) {
3106 lwkt_serialize_enter(&rxr->rx_serialize);
3108 lwkt_serialize_exit(&rxr->rx_serialize);
3112 if (eicr & txr->tx_intr_mask) {
3113 lwkt_serialize_enter(&txr->tx_serialize);
3115 if (!ifsq_is_empty(txr->ifsq))
3116 ifsq_devstart(txr->ifsq);
3117 lwkt_serialize_exit(&txr->tx_serialize);
3121 if (eicr & E1000_EICR_OTHER) {
3122 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3124 /* Link status change */
3125 if (icr & E1000_ICR_LSC) {
3126 sc->hw.mac.get_link_status = 1;
3127 igb_update_link_status(sc);
3132 * Reading EICR has the side effect to clear interrupt mask,
3133 * so all interrupts need to be enabled here.
3135 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
3139 igb_intr_shared(void *xsc)
3141 struct igb_softc *sc = xsc;
3142 struct ifnet *ifp = &sc->arpcom.ac_if;
3145 ASSERT_SERIALIZED(&sc->main_serialize);
3147 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3150 if (reg_icr == 0xffffffff)
3153 /* Definitely not our interrupt. */
3157 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3160 if (ifp->if_flags & IFF_RUNNING) {
3162 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3165 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3166 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3168 lwkt_serialize_enter(&rxr->rx_serialize);
3170 lwkt_serialize_exit(&rxr->rx_serialize);
3174 if (reg_icr & E1000_ICR_TXDW) {
3175 struct igb_tx_ring *txr = &sc->tx_rings[0];
3177 lwkt_serialize_enter(&txr->tx_serialize);
3179 if (!ifsq_is_empty(txr->ifsq))
3180 ifsq_devstart(txr->ifsq);
3181 lwkt_serialize_exit(&txr->tx_serialize);
3185 /* Link status change */
3186 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3187 sc->hw.mac.get_link_status = 1;
3188 igb_update_link_status(sc);
3191 if (reg_icr & E1000_ICR_RXO)
3196 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp,
3197 int *segs_used, int *idx)
3199 bus_dma_segment_t segs[IGB_MAX_SCATTER];
3201 struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3202 union e1000_adv_tx_desc *txd = NULL;
3203 struct mbuf *m_head = *m_headp;
3204 uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3205 int maxsegs, nsegs, i, j, error;
3206 uint32_t hdrlen = 0;
3208 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3209 error = igb_tso_pullup(txr, m_headp);
3215 /* Set basic descriptor constants */
3216 cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3217 cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3218 if (m_head->m_flags & M_VLANTAG)
3219 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3222 * Map the packet for DMA.
3224 tx_buf = &txr->tx_buf[txr->next_avail_desc];
3225 tx_buf_mapped = tx_buf;
3228 maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3229 KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
3230 if (maxsegs > IGB_MAX_SCATTER)
3231 maxsegs = IGB_MAX_SCATTER;
3233 error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3234 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3236 if (error == ENOBUFS)
3237 txr->sc->mbuf_defrag_failed++;
3239 txr->sc->no_tx_dma_setup++;
3245 bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3250 * Set up the TX context descriptor, if any hardware offloading is
3251 * needed. This includes CSUM, VLAN, and TSO. It will consume one
3254 * Unlike these chips' predecessors (em/emx), TX context descriptor
3255 * will _not_ interfere TX data fetching pipelining.
3257 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3258 igb_tso_ctx(txr, m_head, &hdrlen);
3259 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3260 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3261 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3264 } else if (igb_txcsum_ctx(txr, m_head)) {
3265 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3266 olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
3267 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3268 olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
3273 *segs_used += nsegs;
3274 txr->tx_nsegs += nsegs;
3275 if (txr->tx_nsegs >= txr->intr_nsegs) {
3277 * Report Status (RS) is turned on every intr_nsegs
3278 * descriptors (roughly).
3281 cmd_rs = E1000_ADVTXD_DCMD_RS;
3284 /* Calculate payload length */
3285 olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3286 << E1000_ADVTXD_PAYLEN_SHIFT);
3288 /* 82575 needs the queue index added */
3289 if (txr->sc->hw.mac.type == e1000_82575)
3290 olinfo_status |= txr->me << 4;
3292 /* Set up our transmit descriptors */
3293 i = txr->next_avail_desc;
3294 for (j = 0; j < nsegs; j++) {
3296 bus_addr_t seg_addr;
3298 tx_buf = &txr->tx_buf[i];
3299 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3300 seg_addr = segs[j].ds_addr;
3301 seg_len = segs[j].ds_len;
3303 txd->read.buffer_addr = htole64(seg_addr);
3304 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3305 txd->read.olinfo_status = htole32(olinfo_status);
3306 if (++i == txr->num_tx_desc)
3308 tx_buf->m_head = NULL;
3311 KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3312 txr->next_avail_desc = i;
3313 txr->tx_avail -= nsegs;
3315 tx_buf->m_head = m_head;
3316 tx_buf_mapped->map = tx_buf->map;
3320 * Last Descriptor of Packet needs End Of Packet (EOP)
3322 txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3325 * Defer TDT updating, until enough descrptors are setup
3334 igb_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
3336 struct igb_softc *sc = ifp->if_softc;
3337 struct igb_tx_ring *txr = ifsq_get_priv(ifsq);
3338 struct mbuf *m_head;
3339 int idx = -1, nsegs = 0;
3341 KKASSERT(txr->ifsq == ifsq);
3342 ASSERT_SERIALIZED(&txr->tx_serialize);
3344 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
3347 if (!sc->link_active) {
3352 if (!IGB_IS_NOT_OACTIVE(txr))
3355 while (!ifsq_is_empty(ifsq)) {
3356 if (IGB_IS_OACTIVE(txr)) {
3357 ifsq_set_oactive(ifsq);
3358 /* Set watchdog on */
3359 txr->tx_watchdog.wd_timer = 5;
3363 m_head = ifsq_dequeue(ifsq, NULL);
3367 if (igb_encap(txr, &m_head, &nsegs, &idx)) {
3372 if (nsegs >= txr->wreg_nsegs) {
3373 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3378 /* Send a copy of the frame to the BPF listener */
3379 ETHER_BPF_MTAP(ifp, m_head);
3382 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3386 igb_watchdog(struct ifaltq_subque *ifsq)
3388 struct igb_tx_ring *txr = ifsq_get_priv(ifsq);
3389 struct ifnet *ifp = ifsq_get_ifp(ifsq);
3390 struct igb_softc *sc = ifp->if_softc;
3393 KKASSERT(txr->ifsq == ifsq);
3394 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3397 * If flow control has paused us since last checking
3398 * it invalidates the watchdog timing, so dont run it.
3400 if (sc->pause_frames) {
3401 sc->pause_frames = 0;
3402 txr->tx_watchdog.wd_timer = 5;
3406 if_printf(ifp, "Watchdog timeout -- resetting\n");
3407 if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3408 E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3409 E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3410 if_printf(ifp, "TX(%d) desc avail = %d, "
3411 "Next TX to Clean = %d\n",
3412 txr->me, txr->tx_avail, txr->next_to_clean);
3415 sc->watchdog_events++;
3418 for (i = 0; i < sc->tx_ring_cnt; ++i)
3419 ifsq_devstart_sched(sc->tx_rings[i].ifsq);
3423 igb_set_eitr(struct igb_softc *sc, int idx, int rate)
3428 if (sc->hw.mac.type == e1000_82575) {
3429 eitr = 1000000000 / 256 / rate;
3432 * Document is wrong on the 2 bits left shift
3435 eitr = 1000000 / rate;
3436 eitr <<= IGB_EITR_INTVL_SHIFT;
3440 /* Don't disable it */
3441 eitr = 1 << IGB_EITR_INTVL_SHIFT;
3442 } else if (eitr > IGB_EITR_INTVL_MASK) {
3443 /* Don't allow it to be too large */
3444 eitr = IGB_EITR_INTVL_MASK;
3447 if (sc->hw.mac.type == e1000_82575)
3450 eitr |= E1000_EITR_CNT_IGNR;
3451 E1000_WRITE_REG(&sc->hw, E1000_EITR(idx), eitr);
3455 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3457 struct igb_softc *sc = (void *)arg1;
3458 struct ifnet *ifp = &sc->arpcom.ac_if;
3459 int error, intr_rate;
3461 intr_rate = sc->intr_rate;
3462 error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3463 if (error || req->newptr == NULL)
3468 ifnet_serialize_all(ifp);
3470 sc->intr_rate = intr_rate;
3471 if (ifp->if_flags & IFF_RUNNING)
3472 igb_set_eitr(sc, 0, sc->intr_rate);
3475 if_printf(ifp, "interrupt rate set to %d/sec\n", sc->intr_rate);
3477 ifnet_deserialize_all(ifp);
3483 igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS)
3485 struct igb_msix_data *msix = (void *)arg1;
3486 struct igb_softc *sc = msix->msix_sc;
3487 struct ifnet *ifp = &sc->arpcom.ac_if;
3488 int error, msix_rate;
3490 msix_rate = msix->msix_rate;
3491 error = sysctl_handle_int(oidp, &msix_rate, 0, req);
3492 if (error || req->newptr == NULL)
3497 lwkt_serialize_enter(msix->msix_serialize);
3499 msix->msix_rate = msix_rate;
3500 if (ifp->if_flags & IFF_RUNNING)
3501 igb_set_eitr(sc, msix->msix_vector, msix->msix_rate);
3504 if_printf(ifp, "%s set to %d/sec\n", msix->msix_rate_desc,
3508 lwkt_serialize_exit(msix->msix_serialize);
3514 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3516 struct igb_softc *sc = (void *)arg1;
3517 struct ifnet *ifp = &sc->arpcom.ac_if;
3518 struct igb_tx_ring *txr = &sc->tx_rings[0];
3521 nsegs = txr->intr_nsegs;
3522 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3523 if (error || req->newptr == NULL)
3528 ifnet_serialize_all(ifp);
3530 if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
3531 nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3535 txr->intr_nsegs = nsegs;
3538 ifnet_deserialize_all(ifp);
3543 #ifdef IFPOLL_ENABLE
3546 igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3548 struct igb_softc *sc = (void *)arg1;
3549 struct ifnet *ifp = &sc->arpcom.ac_if;
3552 off = sc->rx_npoll_off;
3553 error = sysctl_handle_int(oidp, &off, 0, req);
3554 if (error || req->newptr == NULL)
3559 ifnet_serialize_all(ifp);
3560 if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3564 sc->rx_npoll_off = off;
3566 ifnet_deserialize_all(ifp);
3572 igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3574 struct igb_softc *sc = (void *)arg1;
3575 struct ifnet *ifp = &sc->arpcom.ac_if;
3578 off = sc->tx_npoll_off;
3579 error = sysctl_handle_int(oidp, &off, 0, req);
3580 if (error || req->newptr == NULL)
3585 ifnet_serialize_all(ifp);
3586 if (off >= ncpus2) {
3590 sc->tx_npoll_off = off;
3592 ifnet_deserialize_all(ifp);
3597 #endif /* IFPOLL_ENABLE */
3600 igb_init_intr(struct igb_softc *sc)
3602 igb_set_intr_mask(sc);
3604 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0)
3605 igb_init_unshared_intr(sc);
3607 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3608 igb_set_eitr(sc, 0, sc->intr_rate);
3612 for (i = 0; i < sc->msix_cnt; ++i)
3613 igb_set_eitr(sc, i, sc->msix_data[i].msix_rate);
3618 igb_init_unshared_intr(struct igb_softc *sc)
3620 struct e1000_hw *hw = &sc->hw;
3621 const struct igb_rx_ring *rxr;
3622 const struct igb_tx_ring *txr;
3623 uint32_t ivar, index;
3627 * Enable extended mode
3629 if (sc->hw.mac.type != e1000_82575) {
3633 gpie = E1000_GPIE_NSICR;
3634 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3635 gpie |= E1000_GPIE_MSIX_MODE |
3639 E1000_WRITE_REG(hw, E1000_GPIE, gpie);
3644 switch (sc->hw.mac.type) {
3646 ivar_max = IGB_MAX_IVAR_82580;
3650 ivar_max = IGB_MAX_IVAR_I350;
3654 case e1000_vfadapt_i350:
3655 ivar_max = IGB_MAX_IVAR_VF;
3659 ivar_max = IGB_MAX_IVAR_82576;
3663 panic("unknown mac type %d\n", sc->hw.mac.type);
3665 for (i = 0; i < ivar_max; ++i)
3666 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, 0);
3667 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3671 KASSERT(sc->intr_type != PCI_INTR_TYPE_MSIX,
3672 ("82575 w/ MSI-X"));
3673 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3674 tmp |= E1000_CTRL_EXT_IRCA;
3675 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3679 * Map TX/RX interrupts to EICR
3681 switch (sc->hw.mac.type) {
3685 case e1000_vfadapt_i350:
3687 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3688 rxr = &sc->rx_rings[i];
3691 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3696 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3700 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3702 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3705 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3706 txr = &sc->tx_rings[i];
3709 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3714 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3718 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3720 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3722 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3723 ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3724 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3730 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3731 rxr = &sc->rx_rings[i];
3733 index = i & 0x7; /* Each IVAR has two entries */
3734 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3739 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3743 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3745 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3748 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3749 txr = &sc->tx_rings[i];
3751 index = i & 0x7; /* Each IVAR has two entries */
3752 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3757 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3761 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3763 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3765 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3766 ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3767 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3773 * Enable necessary interrupt bits.
3775 * The name of the register is confusing; in addition to
3776 * configuring the first vector of MSI-X, it also configures
3777 * which bits of EICR could be set by the hardware even when
3778 * MSI or line interrupt is used; it thus controls interrupt
3779 * generation. It MUST be configured explicitly; the default
3780 * value mentioned in the datasheet is wrong: RX queue0 and
3781 * TX queue0 are NOT enabled by default.
3783 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3787 panic("unknown mac type %d\n", sc->hw.mac.type);
3792 igb_setup_intr(struct igb_softc *sc)
3796 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3797 return igb_msix_setup(sc);
3799 error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
3800 (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_intr_shared : igb_intr,
3801 sc, &sc->intr_tag, &sc->main_serialize);
3803 device_printf(sc->dev, "Failed to register interrupt handler");
3806 sc->tx_rings[0].tx_intr_cpuid = rman_get_cpuid(sc->intr_res);
3812 igb_set_txintr_mask(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
3814 if (txr->sc->hw.mac.type == e1000_82575) {
3815 txr->tx_intr_bit = 0; /* unused */
3818 txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3821 txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3824 txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3827 txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3830 panic("unsupported # of TX ring, %d\n", txr->me);
3833 int intr_bit = *intr_bit0;
3835 txr->tx_intr_bit = intr_bit % intr_bitmax;
3836 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
3838 *intr_bit0 = intr_bit + 1;
3843 igb_set_rxintr_mask(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
3845 if (rxr->sc->hw.mac.type == e1000_82575) {
3846 rxr->rx_intr_bit = 0; /* unused */
3849 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3852 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3855 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3858 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3861 panic("unsupported # of RX ring, %d\n", rxr->me);
3864 int intr_bit = *intr_bit0;
3866 rxr->rx_intr_bit = intr_bit % intr_bitmax;
3867 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
3869 *intr_bit0 = intr_bit + 1;
3874 igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3876 struct igb_softc *sc = ifp->if_softc;
3878 ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt,
3879 sc->tx_serialize, sc->rx_serialize, slz);
3883 igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3885 struct igb_softc *sc = ifp->if_softc;
3887 ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt,
3888 sc->tx_serialize, sc->rx_serialize, slz);
3892 igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3894 struct igb_softc *sc = ifp->if_softc;
3896 return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
3897 sc->tx_serialize, sc->rx_serialize, slz);
3903 igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3904 boolean_t serialized)
3906 struct igb_softc *sc = ifp->if_softc;
3908 ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
3909 sc->tx_serialize, sc->rx_serialize, slz, serialized);
3912 #endif /* INVARIANTS */
3915 igb_set_intr_mask(struct igb_softc *sc)
3919 sc->intr_mask = sc->sts_intr_mask;
3920 for (i = 0; i < sc->rx_ring_inuse; ++i)
3921 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
3922 for (i = 0; i < sc->tx_ring_cnt; ++i)
3923 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
3925 if_printf(&sc->arpcom.ac_if, "intr mask 0x%08x\n",
3931 igb_alloc_intr(struct igb_softc *sc)
3933 int i, intr_bit, intr_bitmax;
3936 igb_msix_try_alloc(sc);
3937 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3941 * Allocate MSI/legacy interrupt resource
3943 sc->intr_type = pci_alloc_1intr(sc->dev, igb_msi_enable,
3944 &sc->intr_rid, &intr_flags);
3946 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
3949 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
3951 sc->flags |= IGB_FLAG_SHARED_INTR;
3953 device_printf(sc->dev, "IRQ shared\n");
3955 intr_flags &= ~RF_SHAREABLE;
3957 device_printf(sc->dev, "IRQ unshared\n");
3961 sc->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
3962 &sc->intr_rid, intr_flags);
3963 if (sc->intr_res == NULL) {
3964 device_printf(sc->dev, "Unable to allocate bus resource: "
3970 * Setup MSI/legacy interrupt mask
3972 switch (sc->hw.mac.type) {
3974 intr_bitmax = IGB_MAX_TXRXINT_82575;
3977 intr_bitmax = IGB_MAX_TXRXINT_82580;
3980 intr_bitmax = IGB_MAX_TXRXINT_I350;
3983 intr_bitmax = IGB_MAX_TXRXINT_82576;
3986 intr_bitmax = IGB_MIN_TXRXINT;
3990 for (i = 0; i < sc->tx_ring_cnt; ++i)
3991 igb_set_txintr_mask(&sc->tx_rings[i], &intr_bit, intr_bitmax);
3992 for (i = 0; i < sc->rx_ring_cnt; ++i)
3993 igb_set_rxintr_mask(&sc->rx_rings[i], &intr_bit, intr_bitmax);
3994 sc->sts_intr_bit = 0;
3995 sc->sts_intr_mask = E1000_EICR_OTHER;
3997 /* Initialize interrupt rate */
3998 sc->intr_rate = IGB_INTR_RATE;
4000 igb_set_ring_inuse(sc, FALSE);
4001 igb_set_intr_mask(sc);
4006 igb_free_intr(struct igb_softc *sc)
4008 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
4009 if (sc->intr_res != NULL) {
4010 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->intr_rid,
4013 if (sc->intr_type == PCI_INTR_TYPE_MSI)
4014 pci_release_msi(sc->dev);
4016 igb_msix_free(sc, TRUE);
4021 igb_teardown_intr(struct igb_softc *sc)
4023 if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4024 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_tag);
4026 igb_msix_teardown(sc, sc->msix_cnt);
4030 igb_msix_try_alloc(struct igb_softc *sc)
4032 int msix_enable, msix_cnt, msix_cnt2, alloc_cnt;
4034 struct igb_msix_data *msix;
4035 boolean_t aggregate, setup = FALSE;
4038 * Don't enable MSI-X on 82575, see:
4039 * 82575 specification update errata #25
4041 if (sc->hw.mac.type == e1000_82575)
4044 /* Don't enable MSI-X on VF */
4048 msix_enable = device_getenv_int(sc->dev, "msix.enable",
4053 msix_cnt = pci_msix_count(sc->dev);
4054 #ifdef IGB_MSIX_DEBUG
4055 msix_cnt = device_getenv_int(sc->dev, "msix.count", msix_cnt);
4057 if (msix_cnt <= 1) {
4058 /* One MSI-X model does not make sense */
4063 while ((1 << (i + 1)) <= msix_cnt)
4068 device_printf(sc->dev, "MSI-X count %d/%d\n",
4069 msix_cnt2, msix_cnt);
4072 KKASSERT(msix_cnt2 <= msix_cnt);
4073 if (msix_cnt == msix_cnt2) {
4074 /* We need at least one MSI-X for link status */
4076 if (msix_cnt2 <= 1) {
4077 /* One MSI-X for RX/TX does not make sense */
4078 device_printf(sc->dev, "not enough MSI-X for TX/RX, "
4079 "MSI-X count %d/%d\n", msix_cnt2, msix_cnt);
4082 KKASSERT(msix_cnt > msix_cnt2);
4085 device_printf(sc->dev, "MSI-X count fixup %d/%d\n",
4086 msix_cnt2, msix_cnt);
4090 sc->rx_ring_msix = sc->rx_ring_cnt;
4091 if (sc->rx_ring_msix > msix_cnt2)
4092 sc->rx_ring_msix = msix_cnt2;
4094 if (msix_cnt >= sc->tx_ring_cnt + sc->rx_ring_msix + 1) {
4096 * Independent TX/RX MSI-X
4100 device_printf(sc->dev, "independent TX/RX MSI-X\n");
4101 alloc_cnt = sc->tx_ring_cnt + sc->rx_ring_msix;
4104 * Aggregate TX/RX MSI-X
4108 device_printf(sc->dev, "aggregate TX/RX MSI-X\n");
4109 alloc_cnt = msix_cnt2;
4110 if (alloc_cnt > ncpus2)
4112 if (sc->rx_ring_msix > alloc_cnt)
4113 sc->rx_ring_msix = alloc_cnt;
4115 ++alloc_cnt; /* For link status */
4118 device_printf(sc->dev, "MSI-X alloc %d, RX ring %d\n",
4119 alloc_cnt, sc->rx_ring_msix);
4122 sc->msix_mem_rid = PCIR_BAR(IGB_MSIX_BAR);
4123 sc->msix_mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4124 &sc->msix_mem_rid, RF_ACTIVE);
4125 if (sc->msix_mem_res == NULL) {
4126 device_printf(sc->dev, "Unable to map MSI-X table\n");
4130 sc->msix_cnt = alloc_cnt;
4131 sc->msix_data = kmalloc_cachealign(
4132 sizeof(struct igb_msix_data) * sc->msix_cnt,
4133 M_DEVBUF, M_WAITOK | M_ZERO);
4134 for (x = 0; x < sc->msix_cnt; ++x) {
4135 msix = &sc->msix_data[x];
4137 lwkt_serialize_init(&msix->msix_serialize0);
4139 msix->msix_rid = -1;
4140 msix->msix_vector = x;
4141 msix->msix_mask = 1 << msix->msix_vector;
4142 msix->msix_rate = IGB_INTR_RATE;
4147 int offset, offset_def;
4149 if (sc->rx_ring_msix == ncpus2) {
4152 offset_def = (sc->rx_ring_msix *
4153 device_get_unit(sc->dev)) % ncpus2;
4155 offset = device_getenv_int(sc->dev,
4156 "msix.rxoff", offset_def);
4157 if (offset >= ncpus2 ||
4158 offset % sc->rx_ring_msix != 0) {
4159 device_printf(sc->dev,
4160 "invalid msix.rxoff %d, use %d\n",
4161 offset, offset_def);
4162 offset = offset_def;
4167 for (i = 0; i < sc->rx_ring_msix; ++i) {
4168 struct igb_rx_ring *rxr = &sc->rx_rings[i];
4170 KKASSERT(x < sc->msix_cnt);
4171 msix = &sc->msix_data[x++];
4172 rxr->rx_intr_bit = msix->msix_vector;
4173 rxr->rx_intr_mask = msix->msix_mask;
4175 msix->msix_serialize = &rxr->rx_serialize;
4176 msix->msix_func = igb_msix_rx;
4177 msix->msix_arg = rxr;
4178 msix->msix_cpuid = i + offset;
4179 KKASSERT(msix->msix_cpuid < ncpus2);
4180 ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
4181 "%s rx%d", device_get_nameunit(sc->dev), i);
4182 msix->msix_rate = IGB_MSIX_RX_RATE;
4183 ksnprintf(msix->msix_rate_desc,
4184 sizeof(msix->msix_rate_desc),
4185 "RX%d interrupt rate", i);
4188 offset_def = device_get_unit(sc->dev) % ncpus2;
4189 offset = device_getenv_int(sc->dev, "msix.txoff", offset_def);
4190 if (offset >= ncpus2) {
4191 device_printf(sc->dev, "invalid msix.txoff %d, "
4192 "use %d\n", offset, offset_def);
4193 offset = offset_def;
4197 for (i = 0; i < sc->tx_ring_cnt; ++i) {
4198 struct igb_tx_ring *txr = &sc->tx_rings[i];
4200 KKASSERT(x < sc->msix_cnt);
4201 msix = &sc->msix_data[x++];
4202 txr->tx_intr_bit = msix->msix_vector;
4203 txr->tx_intr_mask = msix->msix_mask;
4205 msix->msix_serialize = &txr->tx_serialize;
4206 msix->msix_func = igb_msix_tx;
4207 msix->msix_arg = txr;
4208 msix->msix_cpuid = i + offset;
4209 txr->tx_intr_cpuid = msix->msix_cpuid;
4210 KKASSERT(msix->msix_cpuid < ncpus2);
4211 ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
4212 "%s tx%d", device_get_nameunit(sc->dev), i);
4213 msix->msix_rate = IGB_MSIX_TX_RATE;
4214 ksnprintf(msix->msix_rate_desc,
4215 sizeof(msix->msix_rate_desc),
4216 "TX%d interrupt rate", i);
4227 KKASSERT(x < sc->msix_cnt);
4228 msix = &sc->msix_data[x++];
4229 sc->sts_intr_bit = msix->msix_vector;
4230 sc->sts_intr_mask = msix->msix_mask;
4232 msix->msix_serialize = &sc->main_serialize;
4233 msix->msix_func = igb_msix_status;
4234 msix->msix_arg = sc;
4235 msix->msix_cpuid = 0; /* TODO tunable */
4236 ksnprintf(msix->msix_desc, sizeof(msix->msix_desc), "%s sts",
4237 device_get_nameunit(sc->dev));
4238 ksnprintf(msix->msix_rate_desc, sizeof(msix->msix_rate_desc),
4239 "status interrupt rate");
4241 KKASSERT(x == sc->msix_cnt);
4243 error = pci_setup_msix(sc->dev);
4245 device_printf(sc->dev, "Setup MSI-X failed\n");
4250 for (i = 0; i < sc->msix_cnt; ++i) {
4251 msix = &sc->msix_data[i];
4253 error = pci_alloc_msix_vector(sc->dev, msix->msix_vector,
4254 &msix->msix_rid, msix->msix_cpuid);
4256 device_printf(sc->dev,
4257 "Unable to allocate MSI-X %d on cpu%d\n",
4258 msix->msix_vector, msix->msix_cpuid);
4262 msix->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
4263 &msix->msix_rid, RF_ACTIVE);
4264 if (msix->msix_res == NULL) {
4265 device_printf(sc->dev,
4266 "Unable to allocate MSI-X %d resource\n",
4273 pci_enable_msix(sc->dev);
4274 sc->intr_type = PCI_INTR_TYPE_MSIX;
4277 igb_msix_free(sc, setup);
4281 igb_msix_free(struct igb_softc *sc, boolean_t setup)
4285 KKASSERT(sc->msix_cnt > 1);
4287 for (i = 0; i < sc->msix_cnt; ++i) {
4288 struct igb_msix_data *msix = &sc->msix_data[i];
4290 if (msix->msix_res != NULL) {
4291 bus_release_resource(sc->dev, SYS_RES_IRQ,
4292 msix->msix_rid, msix->msix_res);
4294 if (msix->msix_rid >= 0)
4295 pci_release_msix_vector(sc->dev, msix->msix_rid);
4298 pci_teardown_msix(sc->dev);
4301 kfree(sc->msix_data, M_DEVBUF);
4302 sc->msix_data = NULL;
4306 igb_msix_setup(struct igb_softc *sc)
4310 for (i = 0; i < sc->msix_cnt; ++i) {
4311 struct igb_msix_data *msix = &sc->msix_data[i];
4314 error = bus_setup_intr_descr(sc->dev, msix->msix_res,
4315 INTR_MPSAFE, msix->msix_func, msix->msix_arg,
4316 &msix->msix_handle, msix->msix_serialize, msix->msix_desc);
4318 device_printf(sc->dev, "could not set up %s "
4319 "interrupt handler.\n", msix->msix_desc);
4320 igb_msix_teardown(sc, i);
4328 igb_msix_teardown(struct igb_softc *sc, int msix_cnt)
4332 for (i = 0; i < msix_cnt; ++i) {
4333 struct igb_msix_data *msix = &sc->msix_data[i];
4335 bus_teardown_intr(sc->dev, msix->msix_res, msix->msix_handle);
4340 igb_msix_rx(void *arg)
4342 struct igb_rx_ring *rxr = arg;
4344 ASSERT_SERIALIZED(&rxr->rx_serialize);
4347 E1000_WRITE_REG(&rxr->sc->hw, E1000_EIMS, rxr->rx_intr_mask);
4351 igb_msix_tx(void *arg)
4353 struct igb_tx_ring *txr = arg;
4355 ASSERT_SERIALIZED(&txr->tx_serialize);
4358 if (!ifsq_is_empty(txr->ifsq))
4359 ifsq_devstart(txr->ifsq);
4361 E1000_WRITE_REG(&txr->sc->hw, E1000_EIMS, txr->tx_intr_mask);
4365 igb_msix_status(void *arg)
4367 struct igb_softc *sc = arg;
4370 ASSERT_SERIALIZED(&sc->main_serialize);
4372 icr = E1000_READ_REG(&sc->hw, E1000_ICR);
4373 if (icr & E1000_ICR_LSC) {
4374 sc->hw.mac.get_link_status = 1;
4375 igb_update_link_status(sc);
4378 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->sts_intr_mask);
4382 igb_set_ring_inuse(struct igb_softc *sc, boolean_t polling)
4384 sc->rx_ring_inuse = igb_get_rxring_inuse(sc, polling);
4386 if_printf(&sc->arpcom.ac_if, "RX rings %d/%d\n",
4387 sc->rx_ring_inuse, sc->rx_ring_cnt);
4392 igb_get_rxring_inuse(const struct igb_softc *sc, boolean_t polling)
4394 if (!IGB_ENABLE_HWRSS(sc))
4398 return sc->rx_ring_cnt;
4399 else if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4400 return IGB_MIN_RING_RSS;
4402 return sc->rx_ring_msix;
4406 igb_tso_pullup(struct igb_tx_ring *txr, struct mbuf **mp)
4408 int hoff, iphlen, thoff;
4412 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4414 iphlen = m->m_pkthdr.csum_iphlen;
4415 thoff = m->m_pkthdr.csum_thlen;
4416 hoff = m->m_pkthdr.csum_lhlen;
4418 KASSERT(iphlen > 0, ("invalid ip hlen"));
4419 KASSERT(thoff > 0, ("invalid tcp hlen"));
4420 KASSERT(hoff > 0, ("invalid ether hlen"));
4422 if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
4423 m = m_pullup(m, hoff + iphlen + thoff);
4430 if (txr->sc->flags & IGB_FLAG_TSO_IPLEN0) {
4433 ip = mtodoff(m, struct ip *, hoff);
4441 igb_tso_ctx(struct igb_tx_ring *txr, struct mbuf *m, uint32_t *hlen)
4443 struct e1000_adv_tx_context_desc *TXD;
4444 uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
4445 int hoff, ctxd, iphlen, thoff;
4447 iphlen = m->m_pkthdr.csum_iphlen;
4448 thoff = m->m_pkthdr.csum_thlen;
4449 hoff = m->m_pkthdr.csum_lhlen;
4451 vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
4453 ctxd = txr->next_avail_desc;
4454 TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
4456 if (m->m_flags & M_VLANTAG) {
4459 vlantag = htole16(m->m_pkthdr.ether_vlantag);
4460 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
4463 vlan_macip_lens |= (hoff << E1000_ADVTXD_MACLEN_SHIFT);
4464 vlan_macip_lens |= iphlen;
4466 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4467 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
4468 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
4470 mss_l4len_idx |= (m->m_pkthdr.tso_segsz << E1000_ADVTXD_MSS_SHIFT);
4471 mss_l4len_idx |= (thoff << E1000_ADVTXD_L4LEN_SHIFT);
4472 /* 82575 needs the queue index added */
4473 if (txr->sc->hw.mac.type == e1000_82575)
4474 mss_l4len_idx |= txr->me << 4;
4476 TXD->vlan_macip_lens = htole32(vlan_macip_lens);
4477 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
4478 TXD->seqnum_seed = htole32(0);
4479 TXD->mss_l4len_idx = htole32(mss_l4len_idx);
4481 /* We've consumed the first desc, adjust counters */
4482 if (++ctxd == txr->num_tx_desc)
4484 txr->next_avail_desc = ctxd;
4487 *hlen = hoff + iphlen + thoff;