2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 #include "opt_ifpoll.h"
70 #include <sys/param.h>
72 #include <sys/endian.h>
73 #include <sys/interrupt.h>
74 #include <sys/kernel.h>
76 #include <sys/malloc.h>
80 #include <sys/serialize.h>
81 #include <sys/serialize2.h>
82 #include <sys/socket.h>
83 #include <sys/sockio.h>
84 #include <sys/sysctl.h>
85 #include <sys/systm.h>
88 #include <net/ethernet.h>
90 #include <net/if_arp.h>
91 #include <net/if_dl.h>
92 #include <net/if_media.h>
93 #include <net/ifq_var.h>
94 #include <net/toeplitz.h>
95 #include <net/toeplitz2.h>
96 #include <net/vlan/if_vlan_var.h>
97 #include <net/vlan/if_vlan_ether.h>
98 #include <net/if_poll.h>
100 #include <netinet/in_systm.h>
101 #include <netinet/in.h>
102 #include <netinet/ip.h>
103 #include <netinet/tcp.h>
104 #include <netinet/udp.h>
106 #include <bus/pci/pcivar.h>
107 #include <bus/pci/pcireg.h>
109 #include <dev/netif/ig_hal/e1000_api.h>
110 #include <dev/netif/ig_hal/e1000_82571.h>
111 #include <dev/netif/emx/if_emx.h>
114 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
116 if (sc->rss_debug >= lvl) \
117 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
119 #else /* !EMX_RSS_DEBUG */
120 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
121 #endif /* EMX_RSS_DEBUG */
123 #define EMX_TX_SERIALIZE 1
124 #define EMX_RX_SERIALIZE 2
126 #define EMX_NAME "Intel(R) PRO/1000 "
128 #define EMX_DEVICE(id) \
129 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
130 #define EMX_DEVICE_NULL { 0, 0, NULL }
132 static const struct emx_device {
137 EMX_DEVICE(82571EB_COPPER),
138 EMX_DEVICE(82571EB_FIBER),
139 EMX_DEVICE(82571EB_SERDES),
140 EMX_DEVICE(82571EB_SERDES_DUAL),
141 EMX_DEVICE(82571EB_SERDES_QUAD),
142 EMX_DEVICE(82571EB_QUAD_COPPER),
143 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
144 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
145 EMX_DEVICE(82571EB_QUAD_FIBER),
146 EMX_DEVICE(82571PT_QUAD_COPPER),
148 EMX_DEVICE(82572EI_COPPER),
149 EMX_DEVICE(82572EI_FIBER),
150 EMX_DEVICE(82572EI_SERDES),
154 EMX_DEVICE(82573E_IAMT),
157 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
158 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
159 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
160 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
165 /* required last entry */
169 static int emx_probe(device_t);
170 static int emx_attach(device_t);
171 static int emx_detach(device_t);
172 static int emx_shutdown(device_t);
173 static int emx_suspend(device_t);
174 static int emx_resume(device_t);
176 static void emx_init(void *);
177 static void emx_stop(struct emx_softc *);
178 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
179 static void emx_start(struct ifnet *);
181 static void emx_npoll(struct ifnet *, struct ifpoll_info *);
182 static void emx_npoll_status(struct ifnet *);
183 static void emx_npoll_tx(struct ifnet *, void *, int);
184 static void emx_npoll_rx(struct ifnet *, void *, int);
186 static void emx_watchdog(struct ifnet *);
187 static void emx_media_status(struct ifnet *, struct ifmediareq *);
188 static int emx_media_change(struct ifnet *);
189 static void emx_timer(void *);
190 static void emx_serialize(struct ifnet *, enum ifnet_serialize);
191 static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
192 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
194 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
198 static void emx_intr(void *);
199 static void emx_intr_mask(void *);
200 static void emx_intr_body(struct emx_softc *, boolean_t);
201 static void emx_rxeof(struct emx_rxdata *, int);
202 static void emx_txeof(struct emx_softc *);
203 static void emx_tx_collect(struct emx_softc *);
204 static void emx_tx_purge(struct emx_softc *);
205 static void emx_enable_intr(struct emx_softc *);
206 static void emx_disable_intr(struct emx_softc *);
208 static int emx_dma_alloc(struct emx_softc *);
209 static void emx_dma_free(struct emx_softc *);
210 static void emx_init_tx_ring(struct emx_softc *);
211 static int emx_init_rx_ring(struct emx_rxdata *);
212 static void emx_free_rx_ring(struct emx_rxdata *);
213 static int emx_create_tx_ring(struct emx_softc *);
214 static int emx_create_rx_ring(struct emx_rxdata *);
215 static void emx_destroy_tx_ring(struct emx_softc *, int);
216 static void emx_destroy_rx_ring(struct emx_rxdata *, int);
217 static int emx_newbuf(struct emx_rxdata *, int, int);
218 static int emx_encap(struct emx_softc *, struct mbuf **);
219 static int emx_txcsum(struct emx_softc *, struct mbuf *,
220 uint32_t *, uint32_t *);
221 static int emx_tso_pullup(struct emx_softc *, struct mbuf **);
222 static int emx_tso_setup(struct emx_softc *, struct mbuf *,
223 uint32_t *, uint32_t *);
225 static int emx_is_valid_eaddr(const uint8_t *);
226 static int emx_reset(struct emx_softc *);
227 static void emx_setup_ifp(struct emx_softc *);
228 static void emx_init_tx_unit(struct emx_softc *);
229 static void emx_init_rx_unit(struct emx_softc *);
230 static void emx_update_stats(struct emx_softc *);
231 static void emx_set_promisc(struct emx_softc *);
232 static void emx_disable_promisc(struct emx_softc *);
233 static void emx_set_multi(struct emx_softc *);
234 static void emx_update_link_status(struct emx_softc *);
235 static void emx_smartspeed(struct emx_softc *);
236 static void emx_set_itr(struct emx_softc *, uint32_t);
237 static void emx_disable_aspm(struct emx_softc *);
239 static void emx_print_debug_info(struct emx_softc *);
240 static void emx_print_nvm_info(struct emx_softc *);
241 static void emx_print_hw_stats(struct emx_softc *);
243 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
244 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
245 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
246 static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
248 static int emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
249 static int emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
251 static void emx_add_sysctl(struct emx_softc *);
253 static void emx_serialize_skipmain(struct emx_softc *);
254 static void emx_deserialize_skipmain(struct emx_softc *);
256 /* Management and WOL Support */
257 static void emx_get_mgmt(struct emx_softc *);
258 static void emx_rel_mgmt(struct emx_softc *);
259 static void emx_get_hw_control(struct emx_softc *);
260 static void emx_rel_hw_control(struct emx_softc *);
261 static void emx_enable_wol(device_t);
263 static device_method_t emx_methods[] = {
264 /* Device interface */
265 DEVMETHOD(device_probe, emx_probe),
266 DEVMETHOD(device_attach, emx_attach),
267 DEVMETHOD(device_detach, emx_detach),
268 DEVMETHOD(device_shutdown, emx_shutdown),
269 DEVMETHOD(device_suspend, emx_suspend),
270 DEVMETHOD(device_resume, emx_resume),
274 static driver_t emx_driver = {
277 sizeof(struct emx_softc),
280 static devclass_t emx_devclass;
282 DECLARE_DUMMY_MODULE(if_emx);
283 MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
284 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
289 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
290 static int emx_rxd = EMX_DEFAULT_RXD;
291 static int emx_txd = EMX_DEFAULT_TXD;
292 static int emx_smart_pwr_down = 0;
293 static int emx_rxr = 0;
295 /* Controls whether promiscuous also shows bad packets */
296 static int emx_debug_sbp = 0;
298 static int emx_82573_workaround = 1;
299 static int emx_msi_enable = 1;
301 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
302 TUNABLE_INT("hw.emx.rxd", &emx_rxd);
303 TUNABLE_INT("hw.emx.rxr", &emx_rxr);
304 TUNABLE_INT("hw.emx.txd", &emx_txd);
305 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
306 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
307 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
308 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
310 /* Global used in WOL setup with multiport cards */
311 static int emx_global_quad_port_a = 0;
313 /* Set this to one to display debug statistics */
314 static int emx_display_debug_stats = 0;
316 #if !defined(KTR_IF_EMX)
317 #define KTR_IF_EMX KTR_ALL
319 KTR_INFO_MASTER(if_emx);
320 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin");
321 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end");
322 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet");
323 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet");
324 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean");
325 #define logif(name) KTR_LOG(if_emx_ ## name)
328 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
330 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
331 /* DD bit must be cleared */
332 rxd->rxd_staterr = 0;
336 emx_rxcsum(uint32_t staterr, struct mbuf *mp)
338 /* Ignore Checksum bit is set */
339 if (staterr & E1000_RXD_STAT_IXSM)
342 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
344 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
346 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
347 E1000_RXD_STAT_TCPCS) {
348 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
350 CSUM_FRAG_NOT_CHECKED;
351 mp->m_pkthdr.csum_data = htons(0xffff);
355 static __inline struct pktinfo *
356 emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
357 uint32_t mrq, uint32_t hash, uint32_t staterr)
359 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
360 case EMX_RXDMRQ_IPV4_TCP:
361 pi->pi_netisr = NETISR_IP;
363 pi->pi_l3proto = IPPROTO_TCP;
366 case EMX_RXDMRQ_IPV6_TCP:
367 pi->pi_netisr = NETISR_IPV6;
369 pi->pi_l3proto = IPPROTO_TCP;
372 case EMX_RXDMRQ_IPV4:
373 if (staterr & E1000_RXD_STAT_IXSM)
377 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
378 E1000_RXD_STAT_TCPCS) {
379 pi->pi_netisr = NETISR_IP;
381 pi->pi_l3proto = IPPROTO_UDP;
389 m->m_flags |= M_HASH;
390 m->m_pkthdr.hash = toeplitz_hash(hash);
395 emx_probe(device_t dev)
397 const struct emx_device *d;
400 vid = pci_get_vendor(dev);
401 did = pci_get_device(dev);
403 for (d = emx_devices; d->desc != NULL; ++d) {
404 if (vid == d->vid && did == d->did) {
405 device_set_desc(dev, d->desc);
406 device_set_async_attach(dev, TRUE);
414 emx_attach(device_t dev)
416 struct emx_softc *sc = device_get_softc(dev);
417 struct ifnet *ifp = &sc->arpcom.ac_if;
418 int error = 0, i, throttle, msi_enable;
420 uint16_t eeprom_data, device_id, apme_mask;
421 driver_intr_t *intr_func;
423 int offset, offset_def;
429 for (i = 0; i < EMX_NRX_RING; ++i) {
430 sc->rx_data[i].sc = sc;
431 sc->rx_data[i].idx = i;
435 * Initialize serializers
437 lwkt_serialize_init(&sc->main_serialize);
438 lwkt_serialize_init(&sc->tx_serialize);
439 for (i = 0; i < EMX_NRX_RING; ++i)
440 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
443 * Initialize serializer array
446 sc->serializes[i++] = &sc->main_serialize;
448 KKASSERT(i == EMX_TX_SERIALIZE);
449 sc->serializes[i++] = &sc->tx_serialize;
451 KKASSERT(i == EMX_RX_SERIALIZE);
452 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
453 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
454 KKASSERT(i == EMX_NSERIALIZE);
456 callout_init_mp(&sc->timer);
458 sc->dev = sc->osdep.dev = dev;
461 * Determine hardware and mac type
463 sc->hw.vendor_id = pci_get_vendor(dev);
464 sc->hw.device_id = pci_get_device(dev);
465 sc->hw.revision_id = pci_get_revid(dev);
466 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
467 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
469 if (e1000_set_mac_type(&sc->hw))
473 * Pullup extra 4bytes into the first data segment, see:
474 * 82571/82572 specification update errata #7
477 * 4bytes instead of 2bytes, which are mentioned in the errata,
478 * are pulled; mainly to keep rest of the data properly aligned.
480 if (sc->hw.mac.type == e1000_82571 || sc->hw.mac.type == e1000_82572)
481 sc->flags |= EMX_FLAG_TSO_PULLEX;
483 /* Enable bus mastering */
484 pci_enable_busmaster(dev);
489 sc->memory_rid = EMX_BAR_MEM;
490 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
491 &sc->memory_rid, RF_ACTIVE);
492 if (sc->memory == NULL) {
493 device_printf(dev, "Unable to allocate bus resource: memory\n");
497 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
498 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
500 /* XXX This is quite goofy, it is not actually used */
501 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
504 * Don't enable MSI-X on 82574, see:
505 * 82574 specification update errata #15
507 * Don't enable MSI on 82571/82572, see:
508 * 82571/82572 specification update errata #63
510 msi_enable = emx_msi_enable;
512 (sc->hw.mac.type == e1000_82571 ||
513 sc->hw.mac.type == e1000_82572))
519 sc->intr_type = pci_alloc_1intr(dev, msi_enable,
520 &sc->intr_rid, &intr_flags);
522 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
525 unshared = device_getenv_int(dev, "irq.unshared", 0);
527 sc->flags |= EMX_FLAG_SHARED_INTR;
529 device_printf(dev, "IRQ shared\n");
531 intr_flags &= ~RF_SHAREABLE;
533 device_printf(dev, "IRQ unshared\n");
537 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
539 if (sc->intr_res == NULL) {
540 device_printf(dev, "Unable to allocate bus resource: "
546 /* Save PCI command register for Shared Code */
547 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
548 sc->hw.back = &sc->osdep;
550 /* Do Shared Code initialization */
551 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
552 device_printf(dev, "Setup of Shared code failed\n");
556 e1000_get_bus_info(&sc->hw);
558 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
559 sc->hw.phy.autoneg_wait_to_complete = FALSE;
560 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
563 * Interrupt throttle rate
565 throttle = device_getenv_int(dev, "int_throttle_ceil",
566 emx_int_throttle_ceil);
568 sc->int_throttle_ceil = 0;
571 throttle = EMX_DEFAULT_ITR;
573 /* Recalculate the tunable value to get the exact frequency. */
574 throttle = 1000000000 / 256 / throttle;
576 /* Upper 16bits of ITR is reserved and should be zero */
577 if (throttle & 0xffff0000)
578 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
580 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
583 e1000_init_script_state_82541(&sc->hw, TRUE);
584 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
587 if (sc->hw.phy.media_type == e1000_media_type_copper) {
588 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
589 sc->hw.phy.disable_polarity_correction = FALSE;
590 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
593 /* Set the frame limits assuming standard ethernet sized frames. */
594 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
595 sc->min_frame_size = ETHER_MIN_LEN;
597 /* This controls when hardware reports transmit completion status. */
598 sc->hw.mac.report_tx_early = 1;
600 /* Calculate # of RX rings */
601 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr);
602 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, EMX_NRX_RING);
604 /* Allocate RX/TX rings' busdma(9) stuffs */
605 error = emx_dma_alloc(sc);
609 /* Allocate multicast array memory. */
610 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
613 /* Indicate SOL/IDER usage */
614 if (e1000_check_reset_block(&sc->hw)) {
616 "PHY reset is blocked due to SOL/IDER session.\n");
620 * Start from a known state, this is important in reading the
621 * nvm and mac from that.
623 e1000_reset_hw(&sc->hw);
625 /* Make sure we have a good EEPROM before we read from it */
626 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
628 * Some PCI-E parts fail the first check due to
629 * the link being in sleep state, call it again,
630 * if it fails a second time its a real issue.
632 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
634 "The EEPROM Checksum Is Not Valid\n");
640 /* Copy the permanent MAC address out of the EEPROM */
641 if (e1000_read_mac_addr(&sc->hw) < 0) {
642 device_printf(dev, "EEPROM read error while reading MAC"
647 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
648 device_printf(dev, "Invalid MAC address\n");
653 /* Determine if we have to control management hardware */
654 if (e1000_enable_mng_pass_thru(&sc->hw))
655 sc->flags |= EMX_FLAG_HAS_MGMT;
660 apme_mask = EMX_EEPROM_APME;
662 switch (sc->hw.mac.type) {
664 sc->flags |= EMX_FLAG_HAS_AMT;
669 case e1000_80003es2lan:
670 if (sc->hw.bus.func == 1) {
671 e1000_read_nvm(&sc->hw,
672 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
674 e1000_read_nvm(&sc->hw,
675 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
680 e1000_read_nvm(&sc->hw,
681 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
684 if (eeprom_data & apme_mask)
685 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
688 * We have the eeprom settings, now apply the special cases
689 * where the eeprom may be wrong or the board won't support
690 * wake on lan on a particular port
692 device_id = pci_get_device(dev);
694 case E1000_DEV_ID_82571EB_FIBER:
696 * Wake events only supported on port A for dual fiber
697 * regardless of eeprom setting
699 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
704 case E1000_DEV_ID_82571EB_QUAD_COPPER:
705 case E1000_DEV_ID_82571EB_QUAD_FIBER:
706 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
707 /* if quad port sc, disable WoL on all but port A */
708 if (emx_global_quad_port_a != 0)
710 /* Reset for multiple quad port adapters */
711 if (++emx_global_quad_port_a == 4)
712 emx_global_quad_port_a = 0;
716 /* XXX disable wol */
721 * NPOLLING RX CPU offset
723 if (sc->rx_ring_cnt == ncpus2) {
726 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
727 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
728 if (offset >= ncpus2 ||
729 offset % sc->rx_ring_cnt != 0) {
730 device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
735 sc->rx_npoll_off = offset;
738 * NPOLLING TX CPU offset
740 offset_def = sc->rx_npoll_off;
741 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
742 if (offset >= ncpus2) {
743 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
747 sc->tx_npoll_off = offset;
750 /* Setup OS specific network interface */
753 /* Add sysctl tree, must after em_setup_ifp() */
756 /* Reset the hardware */
757 error = emx_reset(sc);
759 device_printf(dev, "Unable to reset the hardware\n");
763 /* Initialize statistics */
764 emx_update_stats(sc);
766 sc->hw.mac.get_link_status = 1;
767 emx_update_link_status(sc);
769 sc->spare_tx_desc = EMX_TX_SPARE;
772 * Keep following relationship between spare_tx_desc, oact_tx_desc
774 * (spare_tx_desc + EMX_TX_RESERVED) <=
775 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs
777 sc->oact_tx_desc = sc->num_tx_desc / 8;
778 if (sc->oact_tx_desc > EMX_TX_OACTIVE_MAX)
779 sc->oact_tx_desc = EMX_TX_OACTIVE_MAX;
780 if (sc->oact_tx_desc < sc->spare_tx_desc + EMX_TX_RESERVED)
781 sc->oact_tx_desc = sc->spare_tx_desc + EMX_TX_RESERVED;
783 sc->tx_int_nsegs = sc->num_tx_desc / 16;
784 if (sc->tx_int_nsegs < sc->oact_tx_desc)
785 sc->tx_int_nsegs = sc->oact_tx_desc;
787 /* Non-AMT based hardware can now take control from firmware */
788 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
790 emx_get_hw_control(sc);
793 * Missing Interrupt Following ICR read:
795 * 82571/82572 specification update errata #76
796 * 82573 specification update errata #31
797 * 82574 specification update errata #12
799 intr_func = emx_intr;
800 if ((sc->flags & EMX_FLAG_SHARED_INTR) &&
801 (sc->hw.mac.type == e1000_82571 ||
802 sc->hw.mac.type == e1000_82572 ||
803 sc->hw.mac.type == e1000_82573 ||
804 sc->hw.mac.type == e1000_82574))
805 intr_func = emx_intr_mask;
807 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc,
808 &sc->intr_tag, &sc->main_serialize);
810 device_printf(dev, "Failed to register interrupt handler");
811 ether_ifdetach(&sc->arpcom.ac_if);
815 ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
816 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
824 emx_detach(device_t dev)
826 struct emx_softc *sc = device_get_softc(dev);
828 if (device_is_attached(dev)) {
829 struct ifnet *ifp = &sc->arpcom.ac_if;
831 ifnet_serialize_all(ifp);
835 e1000_phy_hw_reset(&sc->hw);
838 emx_rel_hw_control(sc);
841 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
842 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
846 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
848 ifnet_deserialize_all(ifp);
851 } else if (sc->memory != NULL) {
852 emx_rel_hw_control(sc);
854 bus_generic_detach(dev);
856 if (sc->intr_res != NULL) {
857 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
861 if (sc->intr_type == PCI_INTR_TYPE_MSI)
862 pci_release_msi(dev);
864 if (sc->memory != NULL) {
865 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
871 /* Free sysctl tree */
872 if (sc->sysctl_tree != NULL)
873 sysctl_ctx_free(&sc->sysctl_ctx);
876 kfree(sc->mta, M_DEVBUF);
882 emx_shutdown(device_t dev)
884 return emx_suspend(dev);
888 emx_suspend(device_t dev)
890 struct emx_softc *sc = device_get_softc(dev);
891 struct ifnet *ifp = &sc->arpcom.ac_if;
893 ifnet_serialize_all(ifp);
898 emx_rel_hw_control(sc);
901 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
902 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
906 ifnet_deserialize_all(ifp);
908 return bus_generic_suspend(dev);
912 emx_resume(device_t dev)
914 struct emx_softc *sc = device_get_softc(dev);
915 struct ifnet *ifp = &sc->arpcom.ac_if;
917 ifnet_serialize_all(ifp);
923 ifnet_deserialize_all(ifp);
925 return bus_generic_resume(dev);
929 emx_start(struct ifnet *ifp)
931 struct emx_softc *sc = ifp->if_softc;
934 ASSERT_SERIALIZED(&sc->tx_serialize);
936 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
939 if (!sc->link_active) {
940 ifq_purge(&ifp->if_snd);
944 while (!ifq_is_empty(&ifp->if_snd)) {
945 /* Now do we at least have a minimal? */
946 if (EMX_IS_OACTIVE(sc)) {
948 if (EMX_IS_OACTIVE(sc)) {
949 ifp->if_flags |= IFF_OACTIVE;
955 m_head = ifq_dequeue(&ifp->if_snd, NULL);
959 if (emx_encap(sc, &m_head)) {
965 /* Send a copy of the frame to the BPF listener */
966 ETHER_BPF_MTAP(ifp, m_head);
968 /* Set timeout in case hardware has problems transmitting. */
969 ifp->if_timer = EMX_TX_TIMEOUT;
974 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
976 struct emx_softc *sc = ifp->if_softc;
977 struct ifreq *ifr = (struct ifreq *)data;
978 uint16_t eeprom_data = 0;
979 int max_frame_size, mask, reinit;
982 ASSERT_IFNET_SERIALIZED_ALL(ifp);
986 switch (sc->hw.mac.type) {
989 * 82573 only supports jumbo frames
990 * if ASPM is disabled.
992 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
994 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
995 max_frame_size = ETHER_MAX_LEN;
1000 /* Limit Jumbo Frame size */
1004 case e1000_80003es2lan:
1005 max_frame_size = 9234;
1009 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1012 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
1018 ifp->if_mtu = ifr->ifr_mtu;
1019 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
1022 if (ifp->if_flags & IFF_RUNNING)
1027 if (ifp->if_flags & IFF_UP) {
1028 if ((ifp->if_flags & IFF_RUNNING)) {
1029 if ((ifp->if_flags ^ sc->if_flags) &
1030 (IFF_PROMISC | IFF_ALLMULTI)) {
1031 emx_disable_promisc(sc);
1032 emx_set_promisc(sc);
1037 } else if (ifp->if_flags & IFF_RUNNING) {
1040 sc->if_flags = ifp->if_flags;
1045 if (ifp->if_flags & IFF_RUNNING) {
1046 emx_disable_intr(sc);
1048 #ifdef IFPOLL_ENABLE
1049 if (!(ifp->if_flags & IFF_NPOLLING))
1051 emx_enable_intr(sc);
1056 /* Check SOL/IDER usage */
1057 if (e1000_check_reset_block(&sc->hw)) {
1058 device_printf(sc->dev, "Media change is"
1059 " blocked due to SOL/IDER session.\n");
1065 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
1070 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1071 if (mask & IFCAP_RXCSUM) {
1072 ifp->if_capenable ^= IFCAP_RXCSUM;
1075 if (mask & IFCAP_VLAN_HWTAGGING) {
1076 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1079 if (mask & IFCAP_TXCSUM) {
1080 ifp->if_capenable ^= IFCAP_TXCSUM;
1081 if (ifp->if_capenable & IFCAP_TXCSUM)
1082 ifp->if_hwassist |= EMX_CSUM_FEATURES;
1084 ifp->if_hwassist &= ~EMX_CSUM_FEATURES;
1086 if (mask & IFCAP_TSO) {
1087 ifp->if_capenable ^= IFCAP_TSO;
1088 if (ifp->if_capenable & IFCAP_TSO)
1089 ifp->if_hwassist |= CSUM_TSO;
1091 ifp->if_hwassist &= ~CSUM_TSO;
1093 if (mask & IFCAP_RSS)
1094 ifp->if_capenable ^= IFCAP_RSS;
1095 if (reinit && (ifp->if_flags & IFF_RUNNING))
1100 error = ether_ioctl(ifp, command, data);
1107 emx_watchdog(struct ifnet *ifp)
1109 struct emx_softc *sc = ifp->if_softc;
1111 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1114 * The timer is set to 5 every time start queues a packet.
1115 * Then txeof keeps resetting it as long as it cleans at
1116 * least one descriptor.
1117 * Finally, anytime all descriptors are clean the timer is
1121 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) ==
1122 E1000_READ_REG(&sc->hw, E1000_TDH(0))) {
1124 * If we reach here, all TX jobs are completed and
1125 * the TX engine should have been idled for some time.
1126 * We don't need to call if_devstart() here.
1128 ifp->if_flags &= ~IFF_OACTIVE;
1134 * If we are in this routine because of pause frames, then
1135 * don't reset the hardware.
1137 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1138 ifp->if_timer = EMX_TX_TIMEOUT;
1142 if (e1000_check_for_link(&sc->hw) == 0)
1143 if_printf(ifp, "watchdog timeout -- resetting\n");
1149 if (!ifq_is_empty(&ifp->if_snd))
1156 struct emx_softc *sc = xsc;
1157 struct ifnet *ifp = &sc->arpcom.ac_if;
1158 device_t dev = sc->dev;
1162 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1167 * Packet Buffer Allocation (PBA)
1168 * Writing PBA sets the receive portion of the buffer
1169 * the remainder is used for the transmit buffer.
1171 switch (sc->hw.mac.type) {
1172 /* Total Packet Buffer on these is 48K */
1175 case e1000_80003es2lan:
1176 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1179 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1180 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1184 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1188 /* Devices before 82547 had a Packet Buffer of 64K. */
1189 if (sc->max_frame_size > 8192)
1190 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1192 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1194 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1196 /* Get the latest mac address, User can use a LAA */
1197 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1199 /* Put the address into the Receive Address Array */
1200 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1203 * With the 82571 sc, RAR[0] may be overwritten
1204 * when the other port is reset, we make a duplicate
1205 * in RAR[14] for that eventuality, this assures
1206 * the interface continues to function.
1208 if (sc->hw.mac.type == e1000_82571) {
1209 e1000_set_laa_state_82571(&sc->hw, TRUE);
1210 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1211 E1000_RAR_ENTRIES - 1);
1214 /* Initialize the hardware */
1215 if (emx_reset(sc)) {
1216 device_printf(dev, "Unable to reset the hardware\n");
1217 /* XXX emx_stop()? */
1220 emx_update_link_status(sc);
1222 /* Setup VLAN support, basic and offload if available */
1223 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1225 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1228 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1229 ctrl |= E1000_CTRL_VME;
1230 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1233 /* Configure for OS presence */
1236 /* Prepare transmit descriptors and buffers */
1237 emx_init_tx_ring(sc);
1238 emx_init_tx_unit(sc);
1240 /* Setup Multicast table */
1243 /* Prepare receive descriptors and buffers */
1244 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1245 if (emx_init_rx_ring(&sc->rx_data[i])) {
1247 "Could not setup receive structures\n");
1252 emx_init_rx_unit(sc);
1254 /* Don't lose promiscuous settings */
1255 emx_set_promisc(sc);
1257 ifp->if_flags |= IFF_RUNNING;
1258 ifp->if_flags &= ~IFF_OACTIVE;
1260 callout_reset(&sc->timer, hz, emx_timer, sc);
1261 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1263 /* MSI/X configuration for 82574 */
1264 if (sc->hw.mac.type == e1000_82574) {
1267 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1268 tmp |= E1000_CTRL_EXT_PBA_CLR;
1269 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1272 * Set the IVAR - interrupt vector routing.
1273 * Each nibble represents a vector, high bit
1274 * is enable, other 3 bits are the MSIX table
1275 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1276 * Link (other) to 2, hence the magic number.
1278 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1281 #ifdef IFPOLL_ENABLE
1283 * Only enable interrupts if we are not polling, make sure
1284 * they are off otherwise.
1286 if (ifp->if_flags & IFF_NPOLLING)
1287 emx_disable_intr(sc);
1289 #endif /* IFPOLL_ENABLE */
1290 emx_enable_intr(sc);
1292 /* AMT based hardware can now take control from firmware */
1293 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
1294 (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT))
1295 emx_get_hw_control(sc);
1297 /* Don't reset the phy next time init gets called */
1298 sc->hw.phy.reset_disable = TRUE;
1304 emx_intr_body(xsc, TRUE);
1308 emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted)
1310 struct ifnet *ifp = &sc->arpcom.ac_if;
1314 ASSERT_SERIALIZED(&sc->main_serialize);
1316 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1318 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
1324 * XXX: some laptops trigger several spurious interrupts
1325 * on emx(4) when in the resume cycle. The ICR register
1326 * reports all-ones value in this case. Processing such
1327 * interrupts would lead to a freeze. I don't know why.
1329 if (reg_icr == 0xffffffff) {
1334 if (ifp->if_flags & IFF_RUNNING) {
1336 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1339 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1340 lwkt_serialize_enter(
1341 &sc->rx_data[i].rx_serialize);
1342 emx_rxeof(&sc->rx_data[i], -1);
1343 lwkt_serialize_exit(
1344 &sc->rx_data[i].rx_serialize);
1347 if (reg_icr & E1000_ICR_TXDW) {
1348 lwkt_serialize_enter(&sc->tx_serialize);
1350 if (!ifq_is_empty(&ifp->if_snd))
1352 lwkt_serialize_exit(&sc->tx_serialize);
1356 /* Link status change */
1357 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1358 emx_serialize_skipmain(sc);
1360 callout_stop(&sc->timer);
1361 sc->hw.mac.get_link_status = 1;
1362 emx_update_link_status(sc);
1364 /* Deal with TX cruft when link lost */
1367 callout_reset(&sc->timer, hz, emx_timer, sc);
1369 emx_deserialize_skipmain(sc);
1372 if (reg_icr & E1000_ICR_RXO)
1379 emx_intr_mask(void *xsc)
1381 struct emx_softc *sc = xsc;
1383 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
1386 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1387 * so don't check it.
1389 emx_intr_body(sc, FALSE);
1390 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
1394 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1396 struct emx_softc *sc = ifp->if_softc;
1398 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1400 emx_update_link_status(sc);
1402 ifmr->ifm_status = IFM_AVALID;
1403 ifmr->ifm_active = IFM_ETHER;
1405 if (!sc->link_active)
1408 ifmr->ifm_status |= IFM_ACTIVE;
1410 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1411 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1412 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1414 switch (sc->link_speed) {
1416 ifmr->ifm_active |= IFM_10_T;
1419 ifmr->ifm_active |= IFM_100_TX;
1423 ifmr->ifm_active |= IFM_1000_T;
1426 if (sc->link_duplex == FULL_DUPLEX)
1427 ifmr->ifm_active |= IFM_FDX;
1429 ifmr->ifm_active |= IFM_HDX;
1434 emx_media_change(struct ifnet *ifp)
1436 struct emx_softc *sc = ifp->if_softc;
1437 struct ifmedia *ifm = &sc->media;
1439 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1441 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1444 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1446 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1447 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1453 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1454 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1458 sc->hw.mac.autoneg = FALSE;
1459 sc->hw.phy.autoneg_advertised = 0;
1460 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1461 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1463 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1467 sc->hw.mac.autoneg = FALSE;
1468 sc->hw.phy.autoneg_advertised = 0;
1469 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1470 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1472 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1476 if_printf(ifp, "Unsupported media type\n");
1481 * As the speed/duplex settings my have changed we need to
1484 sc->hw.phy.reset_disable = FALSE;
1492 emx_encap(struct emx_softc *sc, struct mbuf **m_headp)
1494 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1496 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
1497 struct e1000_tx_desc *ctxd = NULL;
1498 struct mbuf *m_head = *m_headp;
1499 uint32_t txd_upper, txd_lower, cmd = 0;
1500 int maxsegs, nsegs, i, j, first, last = 0, error;
1502 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1503 error = emx_tso_pullup(sc, m_headp);
1509 txd_upper = txd_lower = 0;
1512 * Capture the first descriptor index, this descriptor
1513 * will have the index of the EOP which is the only one
1514 * that now gets a DONE bit writeback.
1516 first = sc->next_avail_tx_desc;
1517 tx_buffer = &sc->tx_buf[first];
1518 tx_buffer_mapped = tx_buffer;
1519 map = tx_buffer->map;
1521 maxsegs = sc->num_tx_desc_avail - EMX_TX_RESERVED;
1522 KASSERT(maxsegs >= sc->spare_tx_desc, ("not enough spare TX desc"));
1523 if (maxsegs > EMX_MAX_SCATTER)
1524 maxsegs = EMX_MAX_SCATTER;
1526 error = bus_dmamap_load_mbuf_defrag(sc->txtag, map, m_headp,
1527 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1533 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE);
1536 sc->tx_nsegs += nsegs;
1538 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1539 /* TSO will consume one TX desc */
1540 sc->tx_nsegs += emx_tso_setup(sc, m_head,
1541 &txd_upper, &txd_lower);
1542 } else if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1543 /* TX csum offloading will consume one TX desc */
1544 sc->tx_nsegs += emx_txcsum(sc, m_head, &txd_upper, &txd_lower);
1546 i = sc->next_avail_tx_desc;
1548 /* Set up our transmit descriptors */
1549 for (j = 0; j < nsegs; j++) {
1550 tx_buffer = &sc->tx_buf[i];
1551 ctxd = &sc->tx_desc_base[i];
1553 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1554 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1555 txd_lower | segs[j].ds_len);
1556 ctxd->upper.data = htole32(txd_upper);
1559 if (++i == sc->num_tx_desc)
1563 sc->next_avail_tx_desc = i;
1565 KKASSERT(sc->num_tx_desc_avail > nsegs);
1566 sc->num_tx_desc_avail -= nsegs;
1568 /* Handle VLAN tag */
1569 if (m_head->m_flags & M_VLANTAG) {
1570 /* Set the vlan id. */
1571 ctxd->upper.fields.special =
1572 htole16(m_head->m_pkthdr.ether_vlantag);
1574 /* Tell hardware to add tag */
1575 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1578 tx_buffer->m_head = m_head;
1579 tx_buffer_mapped->map = tx_buffer->map;
1580 tx_buffer->map = map;
1582 if (sc->tx_nsegs >= sc->tx_int_nsegs) {
1586 * Report Status (RS) is turned on
1587 * every tx_int_nsegs descriptors.
1589 cmd = E1000_TXD_CMD_RS;
1592 * Keep track of the descriptor, which will
1593 * be written back by hardware.
1595 sc->tx_dd[sc->tx_dd_tail] = last;
1596 EMX_INC_TXDD_IDX(sc->tx_dd_tail);
1597 KKASSERT(sc->tx_dd_tail != sc->tx_dd_head);
1601 * Last Descriptor of Packet needs End Of Packet (EOP)
1603 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1606 * Advance the Transmit Descriptor Tail (TDT), this tells
1607 * the E1000 that this frame is available to transmit.
1609 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), i);
1615 emx_set_promisc(struct emx_softc *sc)
1617 struct ifnet *ifp = &sc->arpcom.ac_if;
1620 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1622 if (ifp->if_flags & IFF_PROMISC) {
1623 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1624 /* Turn this on if you want to see bad packets */
1626 reg_rctl |= E1000_RCTL_SBP;
1627 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1628 } else if (ifp->if_flags & IFF_ALLMULTI) {
1629 reg_rctl |= E1000_RCTL_MPE;
1630 reg_rctl &= ~E1000_RCTL_UPE;
1631 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1636 emx_disable_promisc(struct emx_softc *sc)
1640 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1642 reg_rctl &= ~E1000_RCTL_UPE;
1643 reg_rctl &= ~E1000_RCTL_MPE;
1644 reg_rctl &= ~E1000_RCTL_SBP;
1645 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1649 emx_set_multi(struct emx_softc *sc)
1651 struct ifnet *ifp = &sc->arpcom.ac_if;
1652 struct ifmultiaddr *ifma;
1653 uint32_t reg_rctl = 0;
1658 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1660 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1661 if (ifma->ifma_addr->sa_family != AF_LINK)
1664 if (mcnt == EMX_MCAST_ADDR_MAX)
1667 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1668 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1672 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1673 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1674 reg_rctl |= E1000_RCTL_MPE;
1675 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1677 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1682 * This routine checks for link status and updates statistics.
1685 emx_timer(void *xsc)
1687 struct emx_softc *sc = xsc;
1688 struct ifnet *ifp = &sc->arpcom.ac_if;
1690 lwkt_serialize_enter(&sc->main_serialize);
1692 emx_update_link_status(sc);
1693 emx_update_stats(sc);
1695 /* Reset LAA into RAR[0] on 82571 */
1696 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1697 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1699 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1700 emx_print_hw_stats(sc);
1704 callout_reset(&sc->timer, hz, emx_timer, sc);
1706 lwkt_serialize_exit(&sc->main_serialize);
1710 emx_update_link_status(struct emx_softc *sc)
1712 struct e1000_hw *hw = &sc->hw;
1713 struct ifnet *ifp = &sc->arpcom.ac_if;
1714 device_t dev = sc->dev;
1715 uint32_t link_check = 0;
1717 /* Get the cached link value or read phy for real */
1718 switch (hw->phy.media_type) {
1719 case e1000_media_type_copper:
1720 if (hw->mac.get_link_status) {
1721 /* Do the work to read phy */
1722 e1000_check_for_link(hw);
1723 link_check = !hw->mac.get_link_status;
1724 if (link_check) /* ESB2 fix */
1725 e1000_cfg_on_link_up(hw);
1731 case e1000_media_type_fiber:
1732 e1000_check_for_link(hw);
1733 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1736 case e1000_media_type_internal_serdes:
1737 e1000_check_for_link(hw);
1738 link_check = sc->hw.mac.serdes_has_link;
1741 case e1000_media_type_unknown:
1746 /* Now check for a transition */
1747 if (link_check && sc->link_active == 0) {
1748 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1752 * Check if we should enable/disable SPEED_MODE bit on
1755 if (sc->link_speed != SPEED_1000 &&
1756 (hw->mac.type == e1000_82571 ||
1757 hw->mac.type == e1000_82572)) {
1760 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1761 tarc0 &= ~EMX_TARC_SPEED_MODE;
1762 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1765 device_printf(dev, "Link is up %d Mbps %s\n",
1767 ((sc->link_duplex == FULL_DUPLEX) ?
1768 "Full Duplex" : "Half Duplex"));
1770 sc->link_active = 1;
1772 ifp->if_baudrate = sc->link_speed * 1000000;
1773 ifp->if_link_state = LINK_STATE_UP;
1774 if_link_state_change(ifp);
1775 } else if (!link_check && sc->link_active == 1) {
1776 ifp->if_baudrate = sc->link_speed = 0;
1777 sc->link_duplex = 0;
1779 device_printf(dev, "Link is Down\n");
1780 sc->link_active = 0;
1782 /* Link down, disable watchdog */
1785 ifp->if_link_state = LINK_STATE_DOWN;
1786 if_link_state_change(ifp);
1791 emx_stop(struct emx_softc *sc)
1793 struct ifnet *ifp = &sc->arpcom.ac_if;
1796 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1798 emx_disable_intr(sc);
1800 callout_stop(&sc->timer);
1802 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1806 * Disable multiple receive queues.
1809 * We should disable multiple receive queues before
1810 * resetting the hardware.
1812 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1814 e1000_reset_hw(&sc->hw);
1815 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1817 for (i = 0; i < sc->num_tx_desc; i++) {
1818 struct emx_txbuf *tx_buffer = &sc->tx_buf[i];
1820 if (tx_buffer->m_head != NULL) {
1821 bus_dmamap_unload(sc->txtag, tx_buffer->map);
1822 m_freem(tx_buffer->m_head);
1823 tx_buffer->m_head = NULL;
1827 for (i = 0; i < sc->rx_ring_cnt; ++i)
1828 emx_free_rx_ring(&sc->rx_data[i]);
1832 sc->csum_iphlen = 0;
1835 sc->csum_pktlen = 0;
1843 emx_reset(struct emx_softc *sc)
1845 device_t dev = sc->dev;
1846 uint16_t rx_buffer_size;
1848 /* Set up smart power down as default off on newer adapters. */
1849 if (!emx_smart_pwr_down &&
1850 (sc->hw.mac.type == e1000_82571 ||
1851 sc->hw.mac.type == e1000_82572)) {
1852 uint16_t phy_tmp = 0;
1854 /* Speed up time to link by disabling smart power down. */
1855 e1000_read_phy_reg(&sc->hw,
1856 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1857 phy_tmp &= ~IGP02E1000_PM_SPD;
1858 e1000_write_phy_reg(&sc->hw,
1859 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1863 * These parameters control the automatic generation (Tx) and
1864 * response (Rx) to Ethernet PAUSE frames.
1865 * - High water mark should allow for at least two frames to be
1866 * received after sending an XOFF.
1867 * - Low water mark works best when it is very near the high water mark.
1868 * This allows the receiver to restart by sending XON when it has
1869 * drained a bit. Here we use an arbitary value of 1500 which will
1870 * restart after one full frame is pulled from the buffer. There
1871 * could be several smaller frames in the buffer and if so they will
1872 * not trigger the XON until their total number reduces the buffer
1874 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1876 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1878 sc->hw.fc.high_water = rx_buffer_size -
1879 roundup2(sc->max_frame_size, 1024);
1880 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1882 if (sc->hw.mac.type == e1000_80003es2lan)
1883 sc->hw.fc.pause_time = 0xFFFF;
1885 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1886 sc->hw.fc.send_xon = TRUE;
1887 sc->hw.fc.requested_mode = e1000_fc_full;
1889 /* Issue a global reset */
1890 e1000_reset_hw(&sc->hw);
1891 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1892 emx_disable_aspm(sc);
1894 if (e1000_init_hw(&sc->hw) < 0) {
1895 device_printf(dev, "Hardware Initialization Failed\n");
1899 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1900 e1000_get_phy_info(&sc->hw);
1901 e1000_check_for_link(&sc->hw);
1907 emx_setup_ifp(struct emx_softc *sc)
1909 struct ifnet *ifp = &sc->arpcom.ac_if;
1911 if_initname(ifp, device_get_name(sc->dev),
1912 device_get_unit(sc->dev));
1914 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1915 ifp->if_init = emx_init;
1916 ifp->if_ioctl = emx_ioctl;
1917 ifp->if_start = emx_start;
1918 #ifdef IFPOLL_ENABLE
1919 ifp->if_npoll = emx_npoll;
1921 ifp->if_watchdog = emx_watchdog;
1922 ifp->if_serialize = emx_serialize;
1923 ifp->if_deserialize = emx_deserialize;
1924 ifp->if_tryserialize = emx_tryserialize;
1926 ifp->if_serialize_assert = emx_serialize_assert;
1928 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);
1929 ifq_set_ready(&ifp->if_snd);
1931 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1933 ifp->if_capabilities = IFCAP_HWCSUM |
1934 IFCAP_VLAN_HWTAGGING |
1937 if (sc->rx_ring_cnt > 1)
1938 ifp->if_capabilities |= IFCAP_RSS;
1939 ifp->if_capenable = ifp->if_capabilities;
1940 ifp->if_hwassist = EMX_CSUM_FEATURES | CSUM_TSO;
1943 * Tell the upper layer(s) we support long frames.
1945 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1948 * Specify the media types supported by this sc and register
1949 * callbacks to update media and link information
1951 ifmedia_init(&sc->media, IFM_IMASK,
1952 emx_media_change, emx_media_status);
1953 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1954 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1955 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1957 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1959 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1960 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1962 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1963 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1965 if (sc->hw.phy.type != e1000_phy_ife) {
1966 ifmedia_add(&sc->media,
1967 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1968 ifmedia_add(&sc->media,
1969 IFM_ETHER | IFM_1000_T, 0, NULL);
1972 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1973 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1977 * Workaround for SmartSpeed on 82541 and 82547 controllers
1980 emx_smartspeed(struct emx_softc *sc)
1984 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
1985 sc->hw.mac.autoneg == 0 ||
1986 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
1989 if (sc->smartspeed == 0) {
1991 * If Master/Slave config fault is asserted twice,
1992 * we assume back-to-back
1994 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1995 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
1997 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1998 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
1999 e1000_read_phy_reg(&sc->hw,
2000 PHY_1000T_CTRL, &phy_tmp);
2001 if (phy_tmp & CR_1000T_MS_ENABLE) {
2002 phy_tmp &= ~CR_1000T_MS_ENABLE;
2003 e1000_write_phy_reg(&sc->hw,
2004 PHY_1000T_CTRL, phy_tmp);
2006 if (sc->hw.mac.autoneg &&
2007 !e1000_phy_setup_autoneg(&sc->hw) &&
2008 !e1000_read_phy_reg(&sc->hw,
2009 PHY_CONTROL, &phy_tmp)) {
2010 phy_tmp |= MII_CR_AUTO_NEG_EN |
2011 MII_CR_RESTART_AUTO_NEG;
2012 e1000_write_phy_reg(&sc->hw,
2013 PHY_CONTROL, phy_tmp);
2018 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
2019 /* If still no link, perhaps using 2/3 pair cable */
2020 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
2021 phy_tmp |= CR_1000T_MS_ENABLE;
2022 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
2023 if (sc->hw.mac.autoneg &&
2024 !e1000_phy_setup_autoneg(&sc->hw) &&
2025 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
2026 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2027 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
2031 /* Restart process after EMX_SMARTSPEED_MAX iterations */
2032 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
2037 emx_create_tx_ring(struct emx_softc *sc)
2039 device_t dev = sc->dev;
2040 struct emx_txbuf *tx_buffer;
2041 int error, i, tsize, ntxd;
2044 * Validate number of transmit descriptors. It must not exceed
2045 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2047 ntxd = device_getenv_int(dev, "txd", emx_txd);
2048 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
2049 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) {
2050 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
2051 EMX_DEFAULT_TXD, ntxd);
2052 sc->num_tx_desc = EMX_DEFAULT_TXD;
2054 sc->num_tx_desc = ntxd;
2058 * Allocate Transmit Descriptor ring
2060 tsize = roundup2(sc->num_tx_desc * sizeof(struct e1000_tx_desc),
2062 sc->tx_desc_base = bus_dmamem_coherent_any(sc->parent_dtag,
2063 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
2064 &sc->tx_desc_dtag, &sc->tx_desc_dmap,
2065 &sc->tx_desc_paddr);
2066 if (sc->tx_desc_base == NULL) {
2067 device_printf(dev, "Unable to allocate tx_desc memory\n");
2071 sc->tx_buf = kmalloc(sizeof(struct emx_txbuf) * sc->num_tx_desc,
2072 M_DEVBUF, M_WAITOK | M_ZERO);
2075 * Create DMA tags for tx buffers
2077 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2078 1, 0, /* alignment, bounds */
2079 BUS_SPACE_MAXADDR, /* lowaddr */
2080 BUS_SPACE_MAXADDR, /* highaddr */
2081 NULL, NULL, /* filter, filterarg */
2082 EMX_TSO_SIZE, /* maxsize */
2083 EMX_MAX_SCATTER, /* nsegments */
2084 EMX_MAX_SEGSIZE, /* maxsegsize */
2085 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2086 BUS_DMA_ONEBPAGE, /* flags */
2089 device_printf(dev, "Unable to allocate TX DMA tag\n");
2090 kfree(sc->tx_buf, M_DEVBUF);
2096 * Create DMA maps for tx buffers
2098 for (i = 0; i < sc->num_tx_desc; i++) {
2099 tx_buffer = &sc->tx_buf[i];
2101 error = bus_dmamap_create(sc->txtag,
2102 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2105 device_printf(dev, "Unable to create TX DMA map\n");
2106 emx_destroy_tx_ring(sc, i);
2114 emx_init_tx_ring(struct emx_softc *sc)
2116 /* Clear the old ring contents */
2117 bzero(sc->tx_desc_base,
2118 sizeof(struct e1000_tx_desc) * sc->num_tx_desc);
2121 sc->next_avail_tx_desc = 0;
2122 sc->next_tx_to_clean = 0;
2123 sc->num_tx_desc_avail = sc->num_tx_desc;
2127 emx_init_tx_unit(struct emx_softc *sc)
2129 uint32_t tctl, tarc, tipg = 0;
2132 /* Setup the Base and Length of the Tx Descriptor Ring */
2133 bus_addr = sc->tx_desc_paddr;
2134 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0),
2135 sc->num_tx_desc * sizeof(struct e1000_tx_desc));
2136 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0),
2137 (uint32_t)(bus_addr >> 32));
2138 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0),
2139 (uint32_t)bus_addr);
2140 /* Setup the HW Tx Head and Tail descriptor pointers */
2141 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0);
2142 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0);
2144 /* Set the default values for the Tx Inter Packet Gap timer */
2145 switch (sc->hw.mac.type) {
2146 case e1000_80003es2lan:
2147 tipg = DEFAULT_82543_TIPG_IPGR1;
2148 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2149 E1000_TIPG_IPGR2_SHIFT;
2153 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2154 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2155 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2157 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2158 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2159 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2163 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2165 /* NOTE: 0 is not allowed for TIDV */
2166 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2167 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2169 if (sc->hw.mac.type == e1000_82571 ||
2170 sc->hw.mac.type == e1000_82572) {
2171 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2172 tarc |= EMX_TARC_SPEED_MODE;
2173 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2174 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2175 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2177 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2178 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2180 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2183 /* Program the Transmit Control Register */
2184 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2185 tctl &= ~E1000_TCTL_CT;
2186 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2187 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2188 tctl |= E1000_TCTL_MULR;
2190 /* This write will effectively turn on the transmit unit. */
2191 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2195 emx_destroy_tx_ring(struct emx_softc *sc, int ndesc)
2197 struct emx_txbuf *tx_buffer;
2200 /* Free Transmit Descriptor ring */
2201 if (sc->tx_desc_base) {
2202 bus_dmamap_unload(sc->tx_desc_dtag, sc->tx_desc_dmap);
2203 bus_dmamem_free(sc->tx_desc_dtag, sc->tx_desc_base,
2205 bus_dma_tag_destroy(sc->tx_desc_dtag);
2207 sc->tx_desc_base = NULL;
2210 if (sc->tx_buf == NULL)
2213 for (i = 0; i < ndesc; i++) {
2214 tx_buffer = &sc->tx_buf[i];
2216 KKASSERT(tx_buffer->m_head == NULL);
2217 bus_dmamap_destroy(sc->txtag, tx_buffer->map);
2219 bus_dma_tag_destroy(sc->txtag);
2221 kfree(sc->tx_buf, M_DEVBUF);
2226 * The offload context needs to be set when we transfer the first
2227 * packet of a particular protocol (TCP/UDP). This routine has been
2228 * enhanced to deal with inserted VLAN headers.
2230 * If the new packet's ether header length, ip header length and
2231 * csum offloading type are same as the previous packet, we should
2232 * avoid allocating a new csum context descriptor; mainly to take
2233 * advantage of the pipeline effect of the TX data read request.
2235 * This function returns number of TX descrptors allocated for
2239 emx_txcsum(struct emx_softc *sc, struct mbuf *mp,
2240 uint32_t *txd_upper, uint32_t *txd_lower)
2242 struct e1000_context_desc *TXD;
2243 int curr_txd, ehdrlen, csum_flags;
2244 uint32_t cmd, hdr_len, ip_hlen;
2246 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2247 ip_hlen = mp->m_pkthdr.csum_iphlen;
2248 ehdrlen = mp->m_pkthdr.csum_lhlen;
2250 if (sc->csum_lhlen == ehdrlen && sc->csum_iphlen == ip_hlen &&
2251 sc->csum_flags == csum_flags) {
2253 * Same csum offload context as the previous packets;
2256 *txd_upper = sc->csum_txd_upper;
2257 *txd_lower = sc->csum_txd_lower;
2262 * Setup a new csum offload context.
2265 curr_txd = sc->next_avail_tx_desc;
2266 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd];
2270 /* Setup of IP header checksum. */
2271 if (csum_flags & CSUM_IP) {
2273 * Start offset for header checksum calculation.
2274 * End offset for header checksum calculation.
2275 * Offset of place to put the checksum.
2277 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2278 TXD->lower_setup.ip_fields.ipcse =
2279 htole16(ehdrlen + ip_hlen - 1);
2280 TXD->lower_setup.ip_fields.ipcso =
2281 ehdrlen + offsetof(struct ip, ip_sum);
2282 cmd |= E1000_TXD_CMD_IP;
2283 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2285 hdr_len = ehdrlen + ip_hlen;
2287 if (csum_flags & CSUM_TCP) {
2289 * Start offset for payload checksum calculation.
2290 * End offset for payload checksum calculation.
2291 * Offset of place to put the checksum.
2293 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2294 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2295 TXD->upper_setup.tcp_fields.tucso =
2296 hdr_len + offsetof(struct tcphdr, th_sum);
2297 cmd |= E1000_TXD_CMD_TCP;
2298 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2299 } else if (csum_flags & CSUM_UDP) {
2301 * Start offset for header checksum calculation.
2302 * End offset for header checksum calculation.
2303 * Offset of place to put the checksum.
2305 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2306 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2307 TXD->upper_setup.tcp_fields.tucso =
2308 hdr_len + offsetof(struct udphdr, uh_sum);
2309 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2312 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2313 E1000_TXD_DTYP_D; /* Data descr */
2315 /* Save the information for this csum offloading context */
2316 sc->csum_lhlen = ehdrlen;
2317 sc->csum_iphlen = ip_hlen;
2318 sc->csum_flags = csum_flags;
2319 sc->csum_txd_upper = *txd_upper;
2320 sc->csum_txd_lower = *txd_lower;
2322 TXD->tcp_seg_setup.data = htole32(0);
2323 TXD->cmd_and_length =
2324 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2326 if (++curr_txd == sc->num_tx_desc)
2329 KKASSERT(sc->num_tx_desc_avail > 0);
2330 sc->num_tx_desc_avail--;
2332 sc->next_avail_tx_desc = curr_txd;
2337 emx_txeof(struct emx_softc *sc)
2339 struct ifnet *ifp = &sc->arpcom.ac_if;
2340 struct emx_txbuf *tx_buffer;
2341 int first, num_avail;
2343 if (sc->tx_dd_head == sc->tx_dd_tail)
2346 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2349 num_avail = sc->num_tx_desc_avail;
2350 first = sc->next_tx_to_clean;
2352 while (sc->tx_dd_head != sc->tx_dd_tail) {
2353 int dd_idx = sc->tx_dd[sc->tx_dd_head];
2354 struct e1000_tx_desc *tx_desc;
2356 tx_desc = &sc->tx_desc_base[dd_idx];
2357 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2358 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2360 if (++dd_idx == sc->num_tx_desc)
2363 while (first != dd_idx) {
2368 tx_buffer = &sc->tx_buf[first];
2369 if (tx_buffer->m_head) {
2371 bus_dmamap_unload(sc->txtag,
2373 m_freem(tx_buffer->m_head);
2374 tx_buffer->m_head = NULL;
2377 if (++first == sc->num_tx_desc)
2384 sc->next_tx_to_clean = first;
2385 sc->num_tx_desc_avail = num_avail;
2387 if (sc->tx_dd_head == sc->tx_dd_tail) {
2392 if (!EMX_IS_OACTIVE(sc)) {
2393 ifp->if_flags &= ~IFF_OACTIVE;
2395 /* All clean, turn off the timer */
2396 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2402 emx_tx_collect(struct emx_softc *sc)
2404 struct ifnet *ifp = &sc->arpcom.ac_if;
2405 struct emx_txbuf *tx_buffer;
2406 int tdh, first, num_avail, dd_idx = -1;
2408 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2411 tdh = E1000_READ_REG(&sc->hw, E1000_TDH(0));
2412 if (tdh == sc->next_tx_to_clean)
2415 if (sc->tx_dd_head != sc->tx_dd_tail)
2416 dd_idx = sc->tx_dd[sc->tx_dd_head];
2418 num_avail = sc->num_tx_desc_avail;
2419 first = sc->next_tx_to_clean;
2421 while (first != tdh) {
2426 tx_buffer = &sc->tx_buf[first];
2427 if (tx_buffer->m_head) {
2429 bus_dmamap_unload(sc->txtag,
2431 m_freem(tx_buffer->m_head);
2432 tx_buffer->m_head = NULL;
2435 if (first == dd_idx) {
2436 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2437 if (sc->tx_dd_head == sc->tx_dd_tail) {
2442 dd_idx = sc->tx_dd[sc->tx_dd_head];
2446 if (++first == sc->num_tx_desc)
2449 sc->next_tx_to_clean = first;
2450 sc->num_tx_desc_avail = num_avail;
2452 if (!EMX_IS_OACTIVE(sc)) {
2453 ifp->if_flags &= ~IFF_OACTIVE;
2455 /* All clean, turn off the timer */
2456 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2462 * When Link is lost sometimes there is work still in the TX ring
2463 * which will result in a watchdog, rather than allow that do an
2464 * attempted cleanup and then reinit here. Note that this has been
2465 * seens mostly with fiber adapters.
2468 emx_tx_purge(struct emx_softc *sc)
2470 struct ifnet *ifp = &sc->arpcom.ac_if;
2472 if (!sc->link_active && ifp->if_timer) {
2474 if (ifp->if_timer) {
2475 if_printf(ifp, "Link lost, TX pending, reinit\n");
2483 emx_newbuf(struct emx_rxdata *rdata, int i, int init)
2486 bus_dma_segment_t seg;
2488 struct emx_rxbuf *rx_buffer;
2491 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2494 if_printf(&rdata->sc->arpcom.ac_if,
2495 "Unable to allocate RX mbuf\n");
2499 m->m_len = m->m_pkthdr.len = MCLBYTES;
2501 if (rdata->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2502 m_adj(m, ETHER_ALIGN);
2504 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2505 rdata->rx_sparemap, m,
2506 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2510 if_printf(&rdata->sc->arpcom.ac_if,
2511 "Unable to load RX mbuf\n");
2516 rx_buffer = &rdata->rx_buf[i];
2517 if (rx_buffer->m_head != NULL)
2518 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2520 map = rx_buffer->map;
2521 rx_buffer->map = rdata->rx_sparemap;
2522 rdata->rx_sparemap = map;
2524 rx_buffer->m_head = m;
2525 rx_buffer->paddr = seg.ds_addr;
2527 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
2532 emx_create_rx_ring(struct emx_rxdata *rdata)
2534 device_t dev = rdata->sc->dev;
2535 struct emx_rxbuf *rx_buffer;
2536 int i, error, rsize, nrxd;
2539 * Validate number of receive descriptors. It must not exceed
2540 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2542 nrxd = device_getenv_int(dev, "rxd", emx_rxd);
2543 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2544 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) {
2545 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
2546 EMX_DEFAULT_RXD, nrxd);
2547 rdata->num_rx_desc = EMX_DEFAULT_RXD;
2549 rdata->num_rx_desc = nrxd;
2553 * Allocate Receive Descriptor ring
2555 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
2557 rdata->rx_desc = bus_dmamem_coherent_any(rdata->sc->parent_dtag,
2558 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2559 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2560 &rdata->rx_desc_paddr);
2561 if (rdata->rx_desc == NULL) {
2562 device_printf(dev, "Unable to allocate rx_desc memory\n");
2566 rdata->rx_buf = kmalloc(sizeof(struct emx_rxbuf) * rdata->num_rx_desc,
2567 M_DEVBUF, M_WAITOK | M_ZERO);
2570 * Create DMA tag for rx buffers
2572 error = bus_dma_tag_create(rdata->sc->parent_dtag, /* parent */
2573 1, 0, /* alignment, bounds */
2574 BUS_SPACE_MAXADDR, /* lowaddr */
2575 BUS_SPACE_MAXADDR, /* highaddr */
2576 NULL, NULL, /* filter, filterarg */
2577 MCLBYTES, /* maxsize */
2579 MCLBYTES, /* maxsegsize */
2580 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2583 device_printf(dev, "Unable to allocate RX DMA tag\n");
2584 kfree(rdata->rx_buf, M_DEVBUF);
2585 rdata->rx_buf = NULL;
2590 * Create spare DMA map for rx buffers
2592 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2593 &rdata->rx_sparemap);
2595 device_printf(dev, "Unable to create spare RX DMA map\n");
2596 bus_dma_tag_destroy(rdata->rxtag);
2597 kfree(rdata->rx_buf, M_DEVBUF);
2598 rdata->rx_buf = NULL;
2603 * Create DMA maps for rx buffers
2605 for (i = 0; i < rdata->num_rx_desc; i++) {
2606 rx_buffer = &rdata->rx_buf[i];
2608 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2611 device_printf(dev, "Unable to create RX DMA map\n");
2612 emx_destroy_rx_ring(rdata, i);
2620 emx_free_rx_ring(struct emx_rxdata *rdata)
2624 for (i = 0; i < rdata->num_rx_desc; i++) {
2625 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
2627 if (rx_buffer->m_head != NULL) {
2628 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2629 m_freem(rx_buffer->m_head);
2630 rx_buffer->m_head = NULL;
2634 if (rdata->fmp != NULL)
2635 m_freem(rdata->fmp);
2641 emx_init_rx_ring(struct emx_rxdata *rdata)
2645 /* Reset descriptor ring */
2646 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
2648 /* Allocate new ones. */
2649 for (i = 0; i < rdata->num_rx_desc; i++) {
2650 error = emx_newbuf(rdata, i, 1);
2655 /* Setup our descriptor pointers */
2656 rdata->next_rx_desc_to_check = 0;
2662 emx_init_rx_unit(struct emx_softc *sc)
2664 struct ifnet *ifp = &sc->arpcom.ac_if;
2666 uint32_t rctl, itr, rfctl;
2670 * Make sure receives are disabled while setting
2671 * up the descriptor ring
2673 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2674 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2677 * Set the interrupt throttling rate. Value is calculated
2678 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2680 if (sc->int_throttle_ceil)
2681 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2684 emx_set_itr(sc, itr);
2686 /* Use extended RX descriptor */
2687 rfctl = E1000_RFCTL_EXTEN;
2689 /* Disable accelerated ackknowledge */
2690 if (sc->hw.mac.type == e1000_82574)
2691 rfctl |= E1000_RFCTL_ACK_DIS;
2693 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
2696 * Receive Checksum Offload for TCP and UDP
2698 * Checksum offloading is also enabled if multiple receive
2699 * queue is to be supported, since we need it to figure out
2702 if ((ifp->if_capenable & IFCAP_RXCSUM) ||
2703 sc->rx_ring_cnt > 1) {
2706 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2710 * PCSD must be enabled to enable multiple
2713 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2715 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2719 * Configure multiple receive queue (RSS)
2721 if (sc->rx_ring_cnt > 1) {
2722 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2725 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING,
2726 ("invalid number of RX ring (%d)", sc->rx_ring_cnt));
2730 * When we reach here, RSS has already been disabled
2731 * in emx_stop(), so we could safely configure RSS key
2732 * and redirect table.
2738 toeplitz_get_key(key, sizeof(key));
2739 for (i = 0; i < EMX_NRSSRK; ++i) {
2742 rssrk = EMX_RSSRK_VAL(key, i);
2743 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2745 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2749 * Configure RSS redirect table in following fashion:
2750 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2753 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2756 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT;
2757 reta |= q << (8 * i);
2759 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2761 for (i = 0; i < EMX_NRETA; ++i)
2762 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
2765 * Enable multiple receive queues.
2766 * Enable IPv4 RSS standard hash functions.
2767 * Disable RSS interrupt.
2769 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2770 E1000_MRQC_ENABLE_RSS_2Q |
2771 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2772 E1000_MRQC_RSS_FIELD_IPV4);
2776 * XXX TEMPORARY WORKAROUND: on some systems with 82573
2777 * long latencies are observed, like Lenovo X60. This
2778 * change eliminates the problem, but since having positive
2779 * values in RDTR is a known source of problems on other
2780 * platforms another solution is being sought.
2782 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
2783 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
2784 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
2787 for (i = 0; i < sc->rx_ring_cnt; ++i) {
2788 struct emx_rxdata *rdata = &sc->rx_data[i];
2791 * Setup the Base and Length of the Rx Descriptor Ring
2793 bus_addr = rdata->rx_desc_paddr;
2794 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
2795 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
2796 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
2797 (uint32_t)(bus_addr >> 32));
2798 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
2799 (uint32_t)bus_addr);
2802 * Setup the HW Rx Head and Tail Descriptor Pointers
2804 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
2805 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
2806 sc->rx_data[i].num_rx_desc - 1);
2809 /* Setup the Receive Control Register */
2810 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2811 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2812 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
2813 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2815 /* Make sure VLAN Filters are off */
2816 rctl &= ~E1000_RCTL_VFE;
2818 /* Don't store bad paket */
2819 rctl &= ~E1000_RCTL_SBP;
2822 rctl |= E1000_RCTL_SZ_2048;
2824 if (ifp->if_mtu > ETHERMTU)
2825 rctl |= E1000_RCTL_LPE;
2827 rctl &= ~E1000_RCTL_LPE;
2829 /* Enable Receives */
2830 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
2834 emx_destroy_rx_ring(struct emx_rxdata *rdata, int ndesc)
2836 struct emx_rxbuf *rx_buffer;
2839 /* Free Receive Descriptor ring */
2840 if (rdata->rx_desc) {
2841 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
2842 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
2843 rdata->rx_desc_dmap);
2844 bus_dma_tag_destroy(rdata->rx_desc_dtag);
2846 rdata->rx_desc = NULL;
2849 if (rdata->rx_buf == NULL)
2852 for (i = 0; i < ndesc; i++) {
2853 rx_buffer = &rdata->rx_buf[i];
2855 KKASSERT(rx_buffer->m_head == NULL);
2856 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
2858 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
2859 bus_dma_tag_destroy(rdata->rxtag);
2861 kfree(rdata->rx_buf, M_DEVBUF);
2862 rdata->rx_buf = NULL;
2866 emx_rxeof(struct emx_rxdata *rdata, int count)
2868 struct ifnet *ifp = &rdata->sc->arpcom.ac_if;
2870 emx_rxdesc_t *current_desc;
2874 i = rdata->next_rx_desc_to_check;
2875 current_desc = &rdata->rx_desc[i];
2876 staterr = le32toh(current_desc->rxd_staterr);
2878 if (!(staterr & E1000_RXD_STAT_DD))
2881 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2882 struct pktinfo *pi = NULL, pi0;
2883 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
2884 struct mbuf *m = NULL;
2889 mp = rx_buf->m_head;
2892 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
2893 * needs to access the last received byte in the mbuf.
2895 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
2896 BUS_DMASYNC_POSTREAD);
2898 len = le16toh(current_desc->rxd_length);
2899 if (staterr & E1000_RXD_STAT_EOP) {
2906 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2908 uint32_t mrq, rss_hash;
2911 * Save several necessary information,
2912 * before emx_newbuf() destroy it.
2914 if ((staterr & E1000_RXD_STAT_VP) && eop)
2915 vlan = le16toh(current_desc->rxd_vlan);
2917 mrq = le32toh(current_desc->rxd_mrq);
2918 rss_hash = le32toh(current_desc->rxd_rss);
2920 EMX_RSS_DPRINTF(rdata->sc, 10,
2921 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
2922 rdata->idx, mrq, rss_hash);
2924 if (emx_newbuf(rdata, i, 0) != 0) {
2929 /* Assign correct length to the current fragment */
2932 if (rdata->fmp == NULL) {
2933 mp->m_pkthdr.len = len;
2934 rdata->fmp = mp; /* Store the first mbuf */
2938 * Chain mbuf's together
2940 rdata->lmp->m_next = mp;
2941 rdata->lmp = rdata->lmp->m_next;
2942 rdata->fmp->m_pkthdr.len += len;
2946 rdata->fmp->m_pkthdr.rcvif = ifp;
2949 if (ifp->if_capenable & IFCAP_RXCSUM)
2950 emx_rxcsum(staterr, rdata->fmp);
2952 if (staterr & E1000_RXD_STAT_VP) {
2953 rdata->fmp->m_pkthdr.ether_vlantag =
2955 rdata->fmp->m_flags |= M_VLANTAG;
2961 if (ifp->if_capenable & IFCAP_RSS) {
2962 pi = emx_rssinfo(m, &pi0, mrq,
2965 #ifdef EMX_RSS_DEBUG
2972 emx_setup_rxdesc(current_desc, rx_buf);
2973 if (rdata->fmp != NULL) {
2974 m_freem(rdata->fmp);
2982 ether_input_pkt(ifp, m, pi);
2984 /* Advance our pointers to the next descriptor. */
2985 if (++i == rdata->num_rx_desc)
2988 current_desc = &rdata->rx_desc[i];
2989 staterr = le32toh(current_desc->rxd_staterr);
2991 rdata->next_rx_desc_to_check = i;
2993 /* Advance the E1000's Receive Queue "Tail Pointer". */
2995 i = rdata->num_rx_desc - 1;
2996 E1000_WRITE_REG(&rdata->sc->hw, E1000_RDT(rdata->idx), i);
3000 emx_enable_intr(struct emx_softc *sc)
3002 uint32_t ims_mask = IMS_ENABLE_MASK;
3004 lwkt_serialize_handler_enable(&sc->main_serialize);
3007 if (sc->hw.mac.type == e1000_82574) {
3008 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
3009 ims_mask |= EM_MSIX_MASK;
3012 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
3016 emx_disable_intr(struct emx_softc *sc)
3018 if (sc->hw.mac.type == e1000_82574)
3019 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
3020 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
3022 lwkt_serialize_handler_disable(&sc->main_serialize);
3026 * Bit of a misnomer, what this really means is
3027 * to enable OS management of the system... aka
3028 * to disable special hardware management features
3031 emx_get_mgmt(struct emx_softc *sc)
3033 /* A shared code workaround */
3034 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3035 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
3036 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3038 /* disable hardware interception of ARP */
3039 manc &= ~(E1000_MANC_ARP_EN);
3041 /* enable receiving management packets to the host */
3042 manc |= E1000_MANC_EN_MNG2HOST;
3043 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3044 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3045 manc2h |= E1000_MNG2HOST_PORT_623;
3046 manc2h |= E1000_MNG2HOST_PORT_664;
3047 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3049 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3054 * Give control back to hardware management
3055 * controller if there is one.
3058 emx_rel_mgmt(struct emx_softc *sc)
3060 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3061 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3063 /* re-enable hardware interception of ARP */
3064 manc |= E1000_MANC_ARP_EN;
3065 manc &= ~E1000_MANC_EN_MNG2HOST;
3067 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3072 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3073 * For ASF and Pass Through versions of f/w this means that
3074 * the driver is loaded. For AMT version (only with 82573)
3075 * of the f/w this means that the network i/f is open.
3078 emx_get_hw_control(struct emx_softc *sc)
3080 /* Let firmware know the driver has taken over */
3081 if (sc->hw.mac.type == e1000_82573) {
3084 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3085 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3086 swsm | E1000_SWSM_DRV_LOAD);
3090 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3091 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3092 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3094 sc->flags |= EMX_FLAG_HW_CTRL;
3098 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3099 * For ASF and Pass Through versions of f/w this means that the
3100 * driver is no longer loaded. For AMT version (only with 82573)
3101 * of the f/w this means that the network i/f is closed.
3104 emx_rel_hw_control(struct emx_softc *sc)
3106 if ((sc->flags & EMX_FLAG_HW_CTRL) == 0)
3108 sc->flags &= ~EMX_FLAG_HW_CTRL;
3110 /* Let firmware taken over control of h/w */
3111 if (sc->hw.mac.type == e1000_82573) {
3114 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3115 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3116 swsm & ~E1000_SWSM_DRV_LOAD);
3120 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3121 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3122 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3127 emx_is_valid_eaddr(const uint8_t *addr)
3129 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3131 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3138 * Enable PCI Wake On Lan capability
3141 emx_enable_wol(device_t dev)
3143 uint16_t cap, status;
3146 /* First find the capabilities pointer*/
3147 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3149 /* Read the PM Capabilities */
3150 id = pci_read_config(dev, cap, 1);
3151 if (id != PCIY_PMG) /* Something wrong */
3155 * OK, we have the power capabilities,
3156 * so now get the status register
3158 cap += PCIR_POWER_STATUS;
3159 status = pci_read_config(dev, cap, 2);
3160 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3161 pci_write_config(dev, cap, status, 2);
3165 emx_update_stats(struct emx_softc *sc)
3167 struct ifnet *ifp = &sc->arpcom.ac_if;
3169 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3170 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3171 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3172 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3174 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3175 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3176 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3177 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3179 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3180 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3181 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3182 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3183 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3184 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3185 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3186 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3187 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3188 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3189 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3190 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3191 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3192 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3193 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3194 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3195 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3196 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3197 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3198 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3200 /* For the 64-bit byte counters the low dword must be read first. */
3201 /* Both registers clear on the read of the high dword */
3203 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3204 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3206 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3207 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3208 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3209 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3210 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3212 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3213 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3215 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3216 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3217 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3218 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3219 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3220 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3221 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3222 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3223 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3224 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3226 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3227 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3228 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3229 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3230 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3231 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3233 ifp->if_collisions = sc->stats.colc;
3236 ifp->if_ierrors = sc->stats.rxerrc +
3237 sc->stats.crcerrs + sc->stats.algnerrc +
3238 sc->stats.ruc + sc->stats.roc +
3239 sc->stats.mpc + sc->stats.cexterr;
3242 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol;
3246 emx_print_debug_info(struct emx_softc *sc)
3248 device_t dev = sc->dev;
3249 uint8_t *hw_addr = sc->hw.hw_addr;
3251 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3252 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3253 E1000_READ_REG(&sc->hw, E1000_CTRL),
3254 E1000_READ_REG(&sc->hw, E1000_RCTL));
3255 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3256 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3257 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3258 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3259 sc->hw.fc.high_water, sc->hw.fc.low_water);
3260 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3261 E1000_READ_REG(&sc->hw, E1000_TIDV),
3262 E1000_READ_REG(&sc->hw, E1000_TADV));
3263 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3264 E1000_READ_REG(&sc->hw, E1000_RDTR),
3265 E1000_READ_REG(&sc->hw, E1000_RADV));
3266 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3267 E1000_READ_REG(&sc->hw, E1000_TDH(0)),
3268 E1000_READ_REG(&sc->hw, E1000_TDT(0)));
3269 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3270 E1000_READ_REG(&sc->hw, E1000_RDH(0)),
3271 E1000_READ_REG(&sc->hw, E1000_RDT(0)));
3272 device_printf(dev, "Num Tx descriptors avail = %d\n",
3273 sc->num_tx_desc_avail);
3275 device_printf(dev, "TSO segments %lu\n", sc->tso_segments);
3276 device_printf(dev, "TSO ctx reused %lu\n", sc->tso_ctx_reused);
3280 emx_print_hw_stats(struct emx_softc *sc)
3282 device_t dev = sc->dev;
3284 device_printf(dev, "Excessive collisions = %lld\n",
3285 (long long)sc->stats.ecol);
3286 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3287 device_printf(dev, "Symbol errors = %lld\n",
3288 (long long)sc->stats.symerrs);
3290 device_printf(dev, "Sequence errors = %lld\n",
3291 (long long)sc->stats.sec);
3292 device_printf(dev, "Defer count = %lld\n",
3293 (long long)sc->stats.dc);
3294 device_printf(dev, "Missed Packets = %lld\n",
3295 (long long)sc->stats.mpc);
3296 device_printf(dev, "Receive No Buffers = %lld\n",
3297 (long long)sc->stats.rnbc);
3298 /* RLEC is inaccurate on some hardware, calculate our own. */
3299 device_printf(dev, "Receive Length Errors = %lld\n",
3300 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3301 device_printf(dev, "Receive errors = %lld\n",
3302 (long long)sc->stats.rxerrc);
3303 device_printf(dev, "Crc errors = %lld\n",
3304 (long long)sc->stats.crcerrs);
3305 device_printf(dev, "Alignment errors = %lld\n",
3306 (long long)sc->stats.algnerrc);
3307 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3308 (long long)sc->stats.cexterr);
3309 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3310 device_printf(dev, "XON Rcvd = %lld\n",
3311 (long long)sc->stats.xonrxc);
3312 device_printf(dev, "XON Xmtd = %lld\n",
3313 (long long)sc->stats.xontxc);
3314 device_printf(dev, "XOFF Rcvd = %lld\n",
3315 (long long)sc->stats.xoffrxc);
3316 device_printf(dev, "XOFF Xmtd = %lld\n",
3317 (long long)sc->stats.xofftxc);
3318 device_printf(dev, "Good Packets Rcvd = %lld\n",
3319 (long long)sc->stats.gprc);
3320 device_printf(dev, "Good Packets Xmtd = %lld\n",
3321 (long long)sc->stats.gptc);
3325 emx_print_nvm_info(struct emx_softc *sc)
3327 uint16_t eeprom_data;
3330 /* Its a bit crude, but it gets the job done */
3331 kprintf("\nInterface EEPROM Dump:\n");
3332 kprintf("Offset\n0x0000 ");
3333 for (i = 0, j = 0; i < 32; i++, j++) {
3334 if (j == 8) { /* Make the offset block */
3336 kprintf("\n0x00%x0 ",row);
3338 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3339 kprintf("%04x ", eeprom_data);
3345 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3347 struct emx_softc *sc;
3352 error = sysctl_handle_int(oidp, &result, 0, req);
3353 if (error || !req->newptr)
3356 sc = (struct emx_softc *)arg1;
3357 ifp = &sc->arpcom.ac_if;
3359 ifnet_serialize_all(ifp);
3362 emx_print_debug_info(sc);
3365 * This value will cause a hex dump of the
3366 * first 32 16-bit words of the EEPROM to
3370 emx_print_nvm_info(sc);
3372 ifnet_deserialize_all(ifp);
3378 emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3383 error = sysctl_handle_int(oidp, &result, 0, req);
3384 if (error || !req->newptr)
3388 struct emx_softc *sc = (struct emx_softc *)arg1;
3389 struct ifnet *ifp = &sc->arpcom.ac_if;
3391 ifnet_serialize_all(ifp);
3392 emx_print_hw_stats(sc);
3393 ifnet_deserialize_all(ifp);
3399 emx_add_sysctl(struct emx_softc *sc)
3401 #ifdef EMX_RSS_DEBUG
3406 sysctl_ctx_init(&sc->sysctl_ctx);
3407 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
3408 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
3409 device_get_nameunit(sc->dev),
3411 if (sc->sysctl_tree == NULL) {
3412 device_printf(sc->dev, "can't add sysctl node\n");
3416 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3417 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3418 emx_sysctl_debug_info, "I", "Debug Information");
3420 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3421 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3422 emx_sysctl_stats, "I", "Statistics");
3424 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3425 OID_AUTO, "rxd", CTLFLAG_RD,
3426 &sc->rx_data[0].num_rx_desc, 0, NULL);
3427 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3428 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL);
3430 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3431 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW,
3432 sc, 0, emx_sysctl_int_throttle, "I",
3433 "interrupt throttling rate");
3434 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3435 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW,
3436 sc, 0, emx_sysctl_int_tx_nsegs, "I",
3437 "# segments per TX interrupt");
3439 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3440 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD,
3441 &sc->rx_ring_cnt, 0, "RX ring count");
3443 #ifdef IFPOLL_ENABLE
3444 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3445 OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
3446 sc, 0, emx_sysctl_npoll_rxoff, "I",
3447 "NPOLLING RX cpu offset");
3448 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3449 OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
3450 sc, 0, emx_sysctl_npoll_txoff, "I",
3451 "NPOLLING TX cpu offset");
3454 #ifdef EMX_RSS_DEBUG
3455 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3456 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3457 0, "RSS debug level");
3458 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3459 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i);
3460 SYSCTL_ADD_UINT(&sc->sysctl_ctx,
3461 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
3463 &sc->rx_data[i].rx_pkts, 0, "RXed packets");
3469 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3471 struct emx_softc *sc = (void *)arg1;
3472 struct ifnet *ifp = &sc->arpcom.ac_if;
3473 int error, throttle;
3475 throttle = sc->int_throttle_ceil;
3476 error = sysctl_handle_int(oidp, &throttle, 0, req);
3477 if (error || req->newptr == NULL)
3479 if (throttle < 0 || throttle > 1000000000 / 256)
3484 * Set the interrupt throttling rate in 256ns increments,
3485 * recalculate sysctl value assignment to get exact frequency.
3487 throttle = 1000000000 / 256 / throttle;
3489 /* Upper 16bits of ITR is reserved and should be zero */
3490 if (throttle & 0xffff0000)
3494 ifnet_serialize_all(ifp);
3497 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3499 sc->int_throttle_ceil = 0;
3501 if (ifp->if_flags & IFF_RUNNING)
3502 emx_set_itr(sc, throttle);
3504 ifnet_deserialize_all(ifp);
3507 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3508 sc->int_throttle_ceil);
3514 emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS)
3516 struct emx_softc *sc = (void *)arg1;
3517 struct ifnet *ifp = &sc->arpcom.ac_if;
3520 segs = sc->tx_int_nsegs;
3521 error = sysctl_handle_int(oidp, &segs, 0, req);
3522 if (error || req->newptr == NULL)
3527 ifnet_serialize_all(ifp);
3530 * Don't allow int_tx_nsegs to become:
3531 * o Less the oact_tx_desc
3532 * o Too large that no TX desc will cause TX interrupt to
3533 * be generated (OACTIVE will never recover)
3534 * o Too small that will cause tx_dd[] overflow
3536 if (segs < sc->oact_tx_desc ||
3537 segs >= sc->num_tx_desc - sc->oact_tx_desc ||
3538 segs < sc->num_tx_desc / EMX_TXDD_SAFE) {
3542 sc->tx_int_nsegs = segs;
3545 ifnet_deserialize_all(ifp);
3550 #ifdef IFPOLL_ENABLE
3553 emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3555 struct emx_softc *sc = (void *)arg1;
3556 struct ifnet *ifp = &sc->arpcom.ac_if;
3559 off = sc->rx_npoll_off;
3560 error = sysctl_handle_int(oidp, &off, 0, req);
3561 if (error || req->newptr == NULL)
3566 ifnet_serialize_all(ifp);
3567 if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3571 sc->rx_npoll_off = off;
3573 ifnet_deserialize_all(ifp);
3579 emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3581 struct emx_softc *sc = (void *)arg1;
3582 struct ifnet *ifp = &sc->arpcom.ac_if;
3585 off = sc->tx_npoll_off;
3586 error = sysctl_handle_int(oidp, &off, 0, req);
3587 if (error || req->newptr == NULL)
3592 ifnet_serialize_all(ifp);
3593 if (off >= ncpus2) {
3597 sc->tx_npoll_off = off;
3599 ifnet_deserialize_all(ifp);
3604 #endif /* IFPOLL_ENABLE */
3607 emx_dma_alloc(struct emx_softc *sc)
3612 * Create top level busdma tag
3614 error = bus_dma_tag_create(NULL, 1, 0,
3615 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3617 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3618 0, &sc->parent_dtag);
3620 device_printf(sc->dev, "could not create top level DMA tag\n");
3625 * Allocate transmit descriptors ring and buffers
3627 error = emx_create_tx_ring(sc);
3629 device_printf(sc->dev, "Could not setup transmit structures\n");
3634 * Allocate receive descriptors ring and buffers
3636 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3637 error = emx_create_rx_ring(&sc->rx_data[i]);
3639 device_printf(sc->dev,
3640 "Could not setup receive structures\n");
3648 emx_dma_free(struct emx_softc *sc)
3652 emx_destroy_tx_ring(sc, sc->num_tx_desc);
3654 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3655 emx_destroy_rx_ring(&sc->rx_data[i],
3656 sc->rx_data[i].num_rx_desc);
3659 /* Free top level busdma tag */
3660 if (sc->parent_dtag != NULL)
3661 bus_dma_tag_destroy(sc->parent_dtag);
3665 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3667 struct emx_softc *sc = ifp->if_softc;
3669 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE,
3670 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
3674 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3676 struct emx_softc *sc = ifp->if_softc;
3678 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE,
3679 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
3683 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3685 struct emx_softc *sc = ifp->if_softc;
3687 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE,
3688 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
3692 emx_serialize_skipmain(struct emx_softc *sc)
3694 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3698 emx_deserialize_skipmain(struct emx_softc *sc)
3700 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3706 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3707 boolean_t serialized)
3709 struct emx_softc *sc = ifp->if_softc;
3711 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE,
3712 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz, serialized);
3715 #endif /* INVARIANTS */
3717 #ifdef IFPOLL_ENABLE
3720 emx_npoll_status(struct ifnet *ifp)
3722 struct emx_softc *sc = ifp->if_softc;
3725 ASSERT_SERIALIZED(&sc->main_serialize);
3727 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3728 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3729 callout_stop(&sc->timer);
3730 sc->hw.mac.get_link_status = 1;
3731 emx_update_link_status(sc);
3732 callout_reset(&sc->timer, hz, emx_timer, sc);
3737 emx_npoll_tx(struct ifnet *ifp, void *arg __unused, int cycle __unused)
3739 struct emx_softc *sc = ifp->if_softc;
3741 ASSERT_SERIALIZED(&sc->tx_serialize);
3744 if (!ifq_is_empty(&ifp->if_snd))
3749 emx_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
3751 struct emx_rxdata *rdata = arg;
3753 ASSERT_SERIALIZED(&rdata->rx_serialize);
3755 emx_rxeof(rdata, cycle);
3759 emx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3761 struct emx_softc *sc = ifp->if_softc;
3763 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3768 info->ifpi_status.status_func = emx_npoll_status;
3769 info->ifpi_status.serializer = &sc->main_serialize;
3771 off = sc->tx_npoll_off;
3772 KKASSERT(off < ncpus2);
3773 info->ifpi_tx[off].poll_func = emx_npoll_tx;
3774 info->ifpi_tx[off].arg = NULL;
3775 info->ifpi_tx[off].serializer = &sc->tx_serialize;
3777 off = sc->rx_npoll_off;
3778 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3779 struct emx_rxdata *rdata = &sc->rx_data[i];
3782 KKASSERT(idx < ncpus2);
3783 info->ifpi_rx[idx].poll_func = emx_npoll_rx;
3784 info->ifpi_rx[idx].arg = rdata;
3785 info->ifpi_rx[idx].serializer = &rdata->rx_serialize;
3788 if (ifp->if_flags & IFF_RUNNING)
3789 emx_disable_intr(sc);
3790 ifp->if_npoll_cpuid = sc->tx_npoll_off;
3792 if (ifp->if_flags & IFF_RUNNING)
3793 emx_enable_intr(sc);
3794 ifp->if_npoll_cpuid = -1;
3798 #endif /* IFPOLL_ENABLE */
3801 emx_set_itr(struct emx_softc *sc, uint32_t itr)
3803 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr);
3804 if (sc->hw.mac.type == e1000_82574) {
3808 * When using MSIX interrupts we need to
3809 * throttle using the EITR register
3811 for (i = 0; i < 4; ++i)
3812 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr);
3817 * Disable the L0s, 82574L Errata #20
3820 emx_disable_aspm(struct emx_softc *sc)
3822 uint16_t link_cap, link_ctrl, disable;
3823 uint8_t pcie_ptr, reg;
3824 device_t dev = sc->dev;
3826 switch (sc->hw.mac.type) {
3831 * 82573 specification update
3832 * errata #8 disable L0s
3833 * errata #41 disable L1
3835 * 82571/82572 specification update
3836 # errata #13 disable L1
3837 * errata #68 disable L0s
3839 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1;
3844 * 82574 specification update errata #20
3846 * There is no need to disable L1
3848 disable = PCIEM_LNKCTL_ASPM_L0S;
3855 pcie_ptr = pci_get_pciecap_ptr(dev);
3859 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2);
3860 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0)
3864 if_printf(&sc->arpcom.ac_if, "disable ASPM %#02x\n", disable);
3866 reg = pcie_ptr + PCIER_LINKCTRL;
3867 link_ctrl = pci_read_config(dev, reg, 2);
3868 link_ctrl &= ~disable;
3869 pci_write_config(dev, reg, link_ctrl, 2);
3873 emx_tso_pullup(struct emx_softc *sc, struct mbuf **mp)
3875 int iphlen, hoff, thoff, ex = 0;
3880 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
3882 iphlen = m->m_pkthdr.csum_iphlen;
3883 thoff = m->m_pkthdr.csum_thlen;
3884 hoff = m->m_pkthdr.csum_lhlen;
3886 KASSERT(iphlen > 0, ("invalid ip hlen"));
3887 KASSERT(thoff > 0, ("invalid tcp hlen"));
3888 KASSERT(hoff > 0, ("invalid ether hlen"));
3890 if (sc->flags & EMX_FLAG_TSO_PULLEX)
3893 if (m->m_len < hoff + iphlen + thoff + ex) {
3894 m = m_pullup(m, hoff + iphlen + thoff + ex);
3901 ip = mtodoff(m, struct ip *, hoff);
3908 emx_tso_setup(struct emx_softc *sc, struct mbuf *mp,
3909 uint32_t *txd_upper, uint32_t *txd_lower)
3911 struct e1000_context_desc *TXD;
3912 int hoff, iphlen, thoff, hlen;
3913 int mss, pktlen, curr_txd;
3915 #ifdef EMX_TSO_DEBUG
3919 iphlen = mp->m_pkthdr.csum_iphlen;
3920 thoff = mp->m_pkthdr.csum_thlen;
3921 hoff = mp->m_pkthdr.csum_lhlen;
3922 mss = mp->m_pkthdr.tso_segsz;
3923 pktlen = mp->m_pkthdr.len;
3925 if (sc->csum_flags == CSUM_TSO &&
3926 sc->csum_iphlen == iphlen &&
3927 sc->csum_lhlen == hoff &&
3928 sc->csum_thlen == thoff &&
3929 sc->csum_mss == mss &&
3930 sc->csum_pktlen == pktlen) {
3931 *txd_upper = sc->csum_txd_upper;
3932 *txd_lower = sc->csum_txd_lower;
3933 #ifdef EMX_TSO_DEBUG
3934 sc->tso_ctx_reused++;
3938 hlen = hoff + iphlen + thoff;
3941 * Setup a new TSO context.
3944 curr_txd = sc->next_avail_tx_desc;
3945 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd];
3947 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
3948 E1000_TXD_DTYP_D | /* Data descr type */
3949 E1000_TXD_CMD_TSE; /* Do TSE on this packet */
3951 /* IP and/or TCP header checksum calculation and insertion. */
3952 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8;
3955 * Start offset for header checksum calculation.
3956 * End offset for header checksum calculation.
3957 * Offset of place put the checksum.
3959 TXD->lower_setup.ip_fields.ipcss = hoff;
3960 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1);
3961 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum);
3964 * Start offset for payload checksum calculation.
3965 * End offset for payload checksum calculation.
3966 * Offset of place to put the checksum.
3968 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen;
3969 TXD->upper_setup.tcp_fields.tucse = 0;
3970 TXD->upper_setup.tcp_fields.tucso =
3971 hoff + iphlen + offsetof(struct tcphdr, th_sum);
3974 * Payload size per packet w/o any headers.
3975 * Length of all headers up to payload.
3977 TXD->tcp_seg_setup.fields.mss = htole16(mss);
3978 TXD->tcp_seg_setup.fields.hdr_len = hlen;
3979 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS |
3980 E1000_TXD_CMD_DEXT | /* Extended descr */
3981 E1000_TXD_CMD_TSE | /* TSE context */
3982 E1000_TXD_CMD_IP | /* Do IP csum */
3983 E1000_TXD_CMD_TCP | /* Do TCP checksum */
3984 (pktlen - hlen)); /* Total len */
3986 /* Save the information for this TSO context */
3987 sc->csum_flags = CSUM_TSO;
3988 sc->csum_lhlen = hoff;
3989 sc->csum_iphlen = iphlen;
3990 sc->csum_thlen = thoff;
3992 sc->csum_pktlen = pktlen;
3993 sc->csum_txd_upper = *txd_upper;
3994 sc->csum_txd_lower = *txd_lower;
3996 if (++curr_txd == sc->num_tx_desc)
3999 KKASSERT(sc->num_tx_desc_avail > 0);
4000 sc->num_tx_desc_avail--;
4002 sc->next_avail_tx_desc = curr_txd;