sys/dev/netif/igb/if_igb.c

   1 /*
   2  * Copyright (c) 2001-2011, Intel Corporation
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  *  1. Redistributions of source code must retain the above copyright notice,
   9  *     this list of conditions and the following disclaimer.
  10  *
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  3. Neither the name of the Intel Corporation nor the names of its
  16  *     contributors may be used to endorse or promote products derived from
  17  *     this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include "opt_ifpoll.h"
  33 #include "opt_igb.h"
  34
  35 #include <sys/param.h>
  36 #include <sys/bus.h>
  37 #include <sys/endian.h>
  38 #include <sys/interrupt.h>
  39 #include <sys/kernel.h>
  40 #include <sys/malloc.h>
  41 #include <sys/mbuf.h>
  42 #include <sys/proc.h>
  43 #include <sys/rman.h>
  44 #include <sys/serialize.h>
  45 #include <sys/serialize2.h>
  46 #include <sys/socket.h>
  47 #include <sys/sockio.h>
  48 #include <sys/sysctl.h>
  49 #include <sys/systm.h>
  50
  51 #include <net/bpf.h>
  52 #include <net/ethernet.h>
  53 #include <net/if.h>
  54 #include <net/if_arp.h>
  55 #include <net/if_dl.h>
  56 #include <net/if_media.h>
  57 #include <net/ifq_var.h>
  58 #include <net/toeplitz.h>
  59 #include <net/toeplitz2.h>
  60 #include <net/vlan/if_vlan_var.h>
  61 #include <net/vlan/if_vlan_ether.h>
  62 #include <net/if_poll.h>
  63
  64 #include <netinet/in_systm.h>
  65 #include <netinet/in.h>
  66 #include <netinet/ip.h>
  67 #include <netinet/tcp.h>
  68 #include <netinet/udp.h>
  69
  70 #include <bus/pci/pcivar.h>
  71 #include <bus/pci/pcireg.h>
  72
  73 #include <dev/netif/ig_hal/e1000_api.h>
  74 #include <dev/netif/ig_hal/e1000_82575.h>
  75 #include <dev/netif/igb/if_igb.h>
  76
  77 #ifdef IGB_RSS_DEBUG
  78 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
  79 do { \
  80         if (sc->rss_debug >= lvl) \
  81                 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
  82 } while (0)
  83 #else   /* !IGB_RSS_DEBUG */
  84 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
  85 #endif  /* IGB_RSS_DEBUG */
  86
  87 #define IGB_NAME        "Intel(R) PRO/1000 "
  88 #define IGB_DEVICE(id)  \
  89         { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
  90 #define IGB_DEVICE_NULL { 0, 0, NULL }
  91
  92 static struct igb_device {
  93         uint16_t        vid;
  94         uint16_t        did;
  95         const char      *desc;
  96 } igb_devices[] = {
  97         IGB_DEVICE(82575EB_COPPER),
  98         IGB_DEVICE(82575EB_FIBER_SERDES),
  99         IGB_DEVICE(82575GB_QUAD_COPPER),
 100         IGB_DEVICE(82576),
 101         IGB_DEVICE(82576_NS),
 102         IGB_DEVICE(82576_NS_SERDES),
 103         IGB_DEVICE(82576_FIBER),
 104         IGB_DEVICE(82576_SERDES),
 105         IGB_DEVICE(82576_SERDES_QUAD),
 106         IGB_DEVICE(82576_QUAD_COPPER),
 107         IGB_DEVICE(82576_QUAD_COPPER_ET2),
 108         IGB_DEVICE(82576_VF),
 109         IGB_DEVICE(82580_COPPER),
 110         IGB_DEVICE(82580_FIBER),
 111         IGB_DEVICE(82580_SERDES),
 112         IGB_DEVICE(82580_SGMII),
 113         IGB_DEVICE(82580_COPPER_DUAL),
 114         IGB_DEVICE(82580_QUAD_FIBER),
 115         IGB_DEVICE(DH89XXCC_SERDES),
 116         IGB_DEVICE(DH89XXCC_SGMII),
 117         IGB_DEVICE(DH89XXCC_SFP),
 118         IGB_DEVICE(DH89XXCC_BACKPLANE),
 119         IGB_DEVICE(I350_COPPER),
 120         IGB_DEVICE(I350_FIBER),
 121         IGB_DEVICE(I350_SERDES),
 122         IGB_DEVICE(I350_SGMII),
 123         IGB_DEVICE(I350_VF),
 124
 125         /* required last entry */
 126         IGB_DEVICE_NULL
 127 };
 128
 129 static int      igb_probe(device_t);
 130 static int      igb_attach(device_t);
 131 static int      igb_detach(device_t);
 132 static int      igb_shutdown(device_t);
 133 static int      igb_suspend(device_t);
 134 static int      igb_resume(device_t);
 135
 136 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
 137 static void     igb_setup_ifp(struct igb_softc *);
 138 static boolean_t igb_txcsum_ctx(struct igb_tx_ring *, struct mbuf *);
 139 static int      igb_tso_pullup(struct igb_tx_ring *, struct mbuf **);
 140 static void     igb_tso_ctx(struct igb_tx_ring *, struct mbuf *, uint32_t *);
 141 static void     igb_add_sysctl(struct igb_softc *);
 142 static int      igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
 143 static int      igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS);
 144 static int      igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
 145 static int      igb_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
 146 static int      igb_sysctl_rx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
 147 static void     igb_set_ring_inuse(struct igb_softc *, boolean_t);
 148 static int      igb_get_rxring_inuse(const struct igb_softc *, boolean_t);
 149 static int      igb_get_txring_inuse(const struct igb_softc *, boolean_t);
 150 #ifdef IFPOLL_ENABLE
 151 static int      igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
 152 static int      igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
 153 #endif
 154
 155 static void     igb_vf_init_stats(struct igb_softc *);
 156 static void     igb_reset(struct igb_softc *);
 157 static void     igb_update_stats_counters(struct igb_softc *);
 158 static void     igb_update_vf_stats_counters(struct igb_softc *);
 159 static void     igb_update_link_status(struct igb_softc *);
 160 static void     igb_init_tx_unit(struct igb_softc *);
 161 static void     igb_init_rx_unit(struct igb_softc *);
 162
 163 static void     igb_set_vlan(struct igb_softc *);
 164 static void     igb_set_multi(struct igb_softc *);
 165 static void     igb_set_promisc(struct igb_softc *);
 166 static void     igb_disable_promisc(struct igb_softc *);
 167
 168 static int      igb_alloc_rings(struct igb_softc *);
 169 static void     igb_free_rings(struct igb_softc *);
 170 static int      igb_create_tx_ring(struct igb_tx_ring *);
 171 static int      igb_create_rx_ring(struct igb_rx_ring *);
 172 static void     igb_free_tx_ring(struct igb_tx_ring *);
 173 static void     igb_free_rx_ring(struct igb_rx_ring *);
 174 static void     igb_destroy_tx_ring(struct igb_tx_ring *, int);
 175 static void     igb_destroy_rx_ring(struct igb_rx_ring *, int);
 176 static void     igb_init_tx_ring(struct igb_tx_ring *);
 177 static int      igb_init_rx_ring(struct igb_rx_ring *);
 178 static int      igb_newbuf(struct igb_rx_ring *, int, boolean_t);
 179 static int      igb_encap(struct igb_tx_ring *, struct mbuf **, int *, int *);
 180 static void     igb_rx_refresh(struct igb_rx_ring *, int);
 181 static void     igb_setup_serializer(struct igb_softc *);
 182
 183 static void     igb_stop(struct igb_softc *);
 184 static void     igb_init(void *);
 185 static int      igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 186 static void     igb_media_status(struct ifnet *, struct ifmediareq *);
 187 static int      igb_media_change(struct ifnet *);
 188 static void     igb_timer(void *);
 189 static void     igb_watchdog(struct ifaltq_subque *);
 190 static void     igb_start(struct ifnet *, struct ifaltq_subque *);
 191 #ifdef IFPOLL_ENABLE
 192 static void     igb_npoll(struct ifnet *, struct ifpoll_info *);
 193 static void     igb_npoll_rx(struct ifnet *, void *, int);
 194 static void     igb_npoll_tx(struct ifnet *, void *, int);
 195 static void     igb_npoll_status(struct ifnet *);
 196 #endif
 197 static void     igb_serialize(struct ifnet *, enum ifnet_serialize);
 198 static void     igb_deserialize(struct ifnet *, enum ifnet_serialize);
 199 static int      igb_tryserialize(struct ifnet *, enum ifnet_serialize);
 200 #ifdef INVARIANTS
 201 static void     igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
 202                     boolean_t);
 203 #endif
 204
 205 static void     igb_intr(void *);
 206 static void     igb_intr_shared(void *);
 207 static void     igb_rxeof(struct igb_rx_ring *, int);
 208 static void     igb_txeof(struct igb_tx_ring *);
 209 static void     igb_set_eitr(struct igb_softc *, int, int);
 210 static void     igb_enable_intr(struct igb_softc *);
 211 static void     igb_disable_intr(struct igb_softc *);
 212 static void     igb_init_unshared_intr(struct igb_softc *);
 213 static void     igb_init_intr(struct igb_softc *);
 214 static int      igb_setup_intr(struct igb_softc *);
 215 static void     igb_set_txintr_mask(struct igb_tx_ring *, int *, int);
 216 static void     igb_set_rxintr_mask(struct igb_rx_ring *, int *, int);
 217 static void     igb_set_intr_mask(struct igb_softc *);
 218 static int      igb_alloc_intr(struct igb_softc *);
 219 static void     igb_free_intr(struct igb_softc *);
 220 static void     igb_teardown_intr(struct igb_softc *);
 221 static void     igb_msix_try_alloc(struct igb_softc *);
 222 static void     igb_msix_free(struct igb_softc *, boolean_t);
 223 static int      igb_msix_setup(struct igb_softc *);
 224 static void     igb_msix_teardown(struct igb_softc *, int);
 225 static void     igb_msix_rx(void *);
 226 static void     igb_msix_tx(void *);
 227 static void     igb_msix_status(void *);
 228
 229 /* Management and WOL Support */
 230 static void     igb_get_mgmt(struct igb_softc *);
 231 static void     igb_rel_mgmt(struct igb_softc *);
 232 static void     igb_get_hw_control(struct igb_softc *);
 233 static void     igb_rel_hw_control(struct igb_softc *);
 234 static void     igb_enable_wol(device_t);
 235
 236 static device_method_t igb_methods[] = {
 237         /* Device interface */
 238         DEVMETHOD(device_probe,         igb_probe),
 239         DEVMETHOD(device_attach,        igb_attach),
 240         DEVMETHOD(device_detach,        igb_detach),
 241         DEVMETHOD(device_shutdown,      igb_shutdown),
 242         DEVMETHOD(device_suspend,       igb_suspend),
 243         DEVMETHOD(device_resume,        igb_resume),
 244         { 0, 0 }
 245 };
 246
 247 static driver_t igb_driver = {
 248         "igb",
 249         igb_methods,
 250         sizeof(struct igb_softc),
 251 };
 252
 253 static devclass_t igb_devclass;
 254
 255 DECLARE_DUMMY_MODULE(if_igb);
 256 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
 257 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
 258
 259 static int      igb_rxd = IGB_DEFAULT_RXD;
 260 static int      igb_txd = IGB_DEFAULT_TXD;
 261 static int      igb_rxr = 0;
 262 static int      igb_txr = 0;
 263 static int      igb_msi_enable = 1;
 264 static int      igb_msix_enable = 1;
 265 static int      igb_eee_disabled = 1;   /* Energy Efficient Ethernet */
 266 static int      igb_fc_setting = e1000_fc_full;
 267
 268 /*
 269  * DMA Coalescing, only for i350 - default to off,
 270  * this feature is for power savings
 271  */
 272 static int      igb_dma_coalesce = 0;
 273
 274 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
 275 TUNABLE_INT("hw.igb.txd", &igb_txd);
 276 TUNABLE_INT("hw.igb.rxr", &igb_rxr);
 277 TUNABLE_INT("hw.igb.txr", &igb_txr);
 278 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
 279 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
 280 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
 281
 282 /* i350 specific */
 283 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
 284 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
 285
 286 static __inline void
 287 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
 288 {
 289         /* Ignore Checksum bit is set */
 290         if (staterr & E1000_RXD_STAT_IXSM)
 291                 return;
 292
 293         if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
 294             E1000_RXD_STAT_IPCS)
 295                 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
 296
 297         if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
 298                 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
 299                         mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
 300                             CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
 301                         mp->m_pkthdr.csum_data = htons(0xffff);
 302                 }
 303         }
 304 }
 305
 306 static __inline struct pktinfo *
 307 igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
 308     uint32_t hash, uint32_t hashtype, uint32_t staterr)
 309 {
 310         switch (hashtype) {
 311         case E1000_RXDADV_RSSTYPE_IPV4_TCP:
 312                 pi->pi_netisr = NETISR_IP;
 313                 pi->pi_flags = 0;
 314                 pi->pi_l3proto = IPPROTO_TCP;
 315                 break;
 316
 317         case E1000_RXDADV_RSSTYPE_IPV4:
 318                 if (staterr & E1000_RXD_STAT_IXSM)
 319                         return NULL;
 320
 321                 if ((staterr &
 322                      (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
 323                     E1000_RXD_STAT_TCPCS) {
 324                         pi->pi_netisr = NETISR_IP;
 325                         pi->pi_flags = 0;
 326                         pi->pi_l3proto = IPPROTO_UDP;
 327                         break;
 328                 }
 329                 /* FALL THROUGH */
 330         default:
 331                 return NULL;
 332         }
 333
 334         m->m_flags |= M_HASH;
 335         m->m_pkthdr.hash = toeplitz_hash(hash);
 336         return pi;
 337 }
 338
 339 static int
 340 igb_probe(device_t dev)
 341 {
 342         const struct igb_device *d;
 343         uint16_t vid, did;
 344
 345         vid = pci_get_vendor(dev);
 346         did = pci_get_device(dev);
 347
 348         for (d = igb_devices; d->desc != NULL; ++d) {
 349                 if (vid == d->vid && did == d->did) {
 350                         device_set_desc(dev, d->desc);
 351                         return 0;
 352                 }
 353         }
 354         return ENXIO;
 355 }
 356
 357 static int
 358 igb_attach(device_t dev)
 359 {
 360         struct igb_softc *sc = device_get_softc(dev);
 361         uint16_t eeprom_data;
 362         int error = 0, i, ring_max;
 363 #ifdef IFPOLL_ENABLE
 364         int offset, offset_def;
 365 #endif
 366
 367 #ifdef notyet
 368         /* SYSCTL stuff */
 369         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 370             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 371             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 372             igb_sysctl_nvm_info, "I", "NVM Information");
 373         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 374             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 375             OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
 376             adapter, 0, igb_set_flowcntl, "I", "Flow Control");
 377 #endif
 378
 379         callout_init_mp(&sc->timer);
 380         lwkt_serialize_init(&sc->main_serialize);
 381
 382         if_initname(&sc->arpcom.ac_if, device_get_name(dev),
 383             device_get_unit(dev));
 384         sc->dev = sc->osdep.dev = dev;
 385
 386         /*
 387          * Determine hardware and mac type
 388          */
 389         sc->hw.vendor_id = pci_get_vendor(dev);
 390         sc->hw.device_id = pci_get_device(dev);
 391         sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
 392         sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
 393         sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
 394
 395         if (e1000_set_mac_type(&sc->hw))
 396                 return ENXIO;
 397
 398         /* Are we a VF device? */
 399         if (sc->hw.mac.type == e1000_vfadapt ||
 400             sc->hw.mac.type == e1000_vfadapt_i350)
 401                 sc->vf_ifp = 1;
 402         else
 403                 sc->vf_ifp = 0;
 404
 405         /*
 406          * Configure total supported RX/TX ring count
 407          */
 408         switch (sc->hw.mac.type) {
 409         case e1000_82575:
 410                 ring_max = IGB_MAX_RING_82575;
 411                 break;
 412         case e1000_82580:
 413                 ring_max = IGB_MAX_RING_82580;
 414                 break;
 415         case e1000_i350:
 416                 ring_max = IGB_MAX_RING_I350;
 417                 break;
 418         case e1000_82576:
 419                 ring_max = IGB_MAX_RING_82576;
 420                 break;
 421         default:
 422                 ring_max = IGB_MIN_RING;
 423                 break;
 424         }
 425
 426         sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
 427         sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
 428 #ifdef IGB_RSS_DEBUG
 429         sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
 430 #endif
 431         sc->rx_ring_inuse = sc->rx_ring_cnt;
 432
 433         sc->tx_ring_cnt = device_getenv_int(dev, "txr", igb_txr);
 434         sc->tx_ring_cnt = if_ring_count2(sc->tx_ring_cnt, /* XXX ring_max */1);
 435 #ifdef IGB_TSS_DEBUG
 436         sc->tx_ring_cnt = device_getenv_int(dev, "txr_debug", sc->tx_ring_cnt);
 437 #endif
 438         sc->tx_ring_inuse = sc->tx_ring_cnt;
 439
 440         /* Enable bus mastering */
 441         pci_enable_busmaster(dev);
 442
 443         /*
 444          * Allocate IO memory
 445          */
 446         sc->mem_rid = PCIR_BAR(0);
 447         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
 448             RF_ACTIVE);
 449         if (sc->mem_res == NULL) {
 450                 device_printf(dev, "Unable to allocate bus resource: memory\n");
 451                 error = ENXIO;
 452                 goto failed;
 453         }
 454         sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
 455         sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
 456
 457         sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
 458
 459         /* Save PCI command register for Shared Code */
 460         sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
 461         sc->hw.back = &sc->osdep;
 462
 463         /* Do Shared Code initialization */
 464         if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
 465                 device_printf(dev, "Setup of Shared code failed\n");
 466                 error = ENXIO;
 467                 goto failed;
 468         }
 469
 470         e1000_get_bus_info(&sc->hw);
 471
 472         sc->hw.mac.autoneg = DO_AUTO_NEG;
 473         sc->hw.phy.autoneg_wait_to_complete = FALSE;
 474         sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 475
 476         /* Copper options */
 477         if (sc->hw.phy.media_type == e1000_media_type_copper) {
 478                 sc->hw.phy.mdix = AUTO_ALL_MODES;
 479                 sc->hw.phy.disable_polarity_correction = FALSE;
 480                 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
 481         }
 482
 483         /* Set the frame limits assuming  standard ethernet sized frames. */
 484         sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
 485
 486         /* Allocate RX/TX rings */
 487         error = igb_alloc_rings(sc);
 488         if (error)
 489                 goto failed;
 490
 491 #ifdef IFPOLL_ENABLE
 492         /*
 493          * NPOLLING RX CPU offset
 494          */
 495         if (sc->rx_ring_cnt == ncpus2) {
 496                 offset = 0;
 497         } else {
 498                 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
 499                 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
 500                 if (offset >= ncpus2 ||
 501                     offset % sc->rx_ring_cnt != 0) {
 502                         device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
 503                             offset, offset_def);
 504                         offset = offset_def;
 505                 }
 506         }
 507         sc->rx_npoll_off = offset;
 508
 509         /*
 510          * NPOLLING TX CPU offset
 511          */
 512         if (sc->tx_ring_cnt == ncpus2) {
 513                 offset = 0;
 514         } else {
 515                 offset_def = (sc->tx_ring_cnt * device_get_unit(dev)) % ncpus2;
 516                 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
 517                 if (offset >= ncpus2 ||
 518                     offset % sc->tx_ring_cnt != 0) {
 519                         device_printf(dev, "invalid npoll.txoff %d, use %d\n",
 520                             offset, offset_def);
 521                         offset = offset_def;
 522                 }
 523         }
 524         sc->tx_npoll_off = offset;
 525 #endif
 526
 527         /* Allocate interrupt */
 528         error = igb_alloc_intr(sc);
 529         if (error)
 530                 goto failed;
 531
 532         /* Setup serializers */
 533         igb_setup_serializer(sc);
 534
 535         /* Allocate the appropriate stats memory */
 536         if (sc->vf_ifp) {
 537                 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
 538                     M_WAITOK | M_ZERO);
 539                 igb_vf_init_stats(sc);
 540         } else {
 541                 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
 542                     M_WAITOK | M_ZERO);
 543         }
 544
 545         /* Allocate multicast array memory. */
 546         sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
 547             M_DEVBUF, M_WAITOK);
 548
 549         /* Some adapter-specific advanced features */
 550         if (sc->hw.mac.type >= e1000_i350) {
 551 #ifdef notyet
 552                 igb_set_sysctl_value(adapter, "dma_coalesce",
 553                     "configure dma coalesce",
 554                     &adapter->dma_coalesce, igb_dma_coalesce);
 555                 igb_set_sysctl_value(adapter, "eee_disabled",
 556                     "enable Energy Efficient Ethernet",
 557                     &adapter->hw.dev_spec._82575.eee_disable,
 558                     igb_eee_disabled);
 559 #else
 560                 sc->dma_coalesce = igb_dma_coalesce;
 561                 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
 562 #endif
 563                 e1000_set_eee_i350(&sc->hw);
 564         }
 565
 566         /*
 567          * Start from a known state, this is important in reading the nvm and
 568          * mac from that.
 569          */
 570         e1000_reset_hw(&sc->hw);
 571
 572         /* Make sure we have a good EEPROM before we read from it */
 573         if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
 574                 /*
 575                  * Some PCI-E parts fail the first check due to
 576                  * the link being in sleep state, call it again,
 577                  * if it fails a second time its a real issue.
 578                  */
 579                 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
 580                         device_printf(dev,
 581                             "The EEPROM Checksum Is Not Valid\n");
 582                         error = EIO;
 583                         goto failed;
 584                 }
 585         }
 586
 587         /* Copy the permanent MAC address out of the EEPROM */
 588         if (e1000_read_mac_addr(&sc->hw) < 0) {
 589                 device_printf(dev, "EEPROM read error while reading MAC"
 590                     " address\n");
 591                 error = EIO;
 592                 goto failed;
 593         }
 594         if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
 595                 device_printf(dev, "Invalid MAC address\n");
 596                 error = EIO;
 597                 goto failed;
 598         }
 599
 600         /* Setup OS specific network interface */
 601         igb_setup_ifp(sc);
 602
 603         /* Add sysctl tree, must after igb_setup_ifp() */
 604         igb_add_sysctl(sc);
 605
 606         /* Now get a good starting state */
 607         igb_reset(sc);
 608
 609         /* Initialize statistics */
 610         igb_update_stats_counters(sc);
 611
 612         sc->hw.mac.get_link_status = 1;
 613         igb_update_link_status(sc);
 614
 615         /* Indicate SOL/IDER usage */
 616         if (e1000_check_reset_block(&sc->hw)) {
 617                 device_printf(dev,
 618                     "PHY reset is blocked due to SOL/IDER session.\n");
 619         }
 620
 621         /* Determine if we have to control management hardware */
 622         if (e1000_enable_mng_pass_thru(&sc->hw))
 623                 sc->flags |= IGB_FLAG_HAS_MGMT;
 624
 625         /*
 626          * Setup Wake-on-Lan
 627          */
 628         /* APME bit in EEPROM is mapped to WUC.APME */
 629         eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
 630         if (eeprom_data)
 631                 sc->wol = E1000_WUFC_MAG;
 632         /* XXX disable WOL */
 633         sc->wol = 0;
 634
 635 #ifdef notyet
 636         /* Register for VLAN events */
 637         adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
 638              igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 639         adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
 640              igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 641 #endif
 642
 643 #ifdef notyet
 644         igb_add_hw_stats(adapter);
 645 #endif
 646
 647         error = igb_setup_intr(sc);
 648         if (error) {
 649                 ether_ifdetach(&sc->arpcom.ac_if);
 650                 goto failed;
 651         }
 652
 653         for (i = 0; i < sc->tx_ring_cnt; ++i) {
 654                 struct ifaltq_subque *ifsq =
 655                     ifq_get_subq(&sc->arpcom.ac_if.if_snd, i);
 656                 struct igb_tx_ring *txr = &sc->tx_rings[i];
 657
 658                 ifsq_set_cpuid(ifsq, txr->tx_intr_cpuid);
 659                 ifsq_set_priv(ifsq, txr);
 660                 txr->ifsq = ifsq;
 661
 662                 ifsq_watchdog_init(&txr->tx_watchdog, ifsq, igb_watchdog);
 663         }
 664
 665         return 0;
 666
 667 failed:
 668         igb_detach(dev);
 669         return error;
 670 }
 671
 672 static int
 673 igb_detach(device_t dev)
 674 {
 675         struct igb_softc *sc = device_get_softc(dev);
 676
 677         if (device_is_attached(dev)) {
 678                 struct ifnet *ifp = &sc->arpcom.ac_if;
 679
 680                 ifnet_serialize_all(ifp);
 681
 682                 igb_stop(sc);
 683
 684                 e1000_phy_hw_reset(&sc->hw);
 685
 686                 /* Give control back to firmware */
 687                 igb_rel_mgmt(sc);
 688                 igb_rel_hw_control(sc);
 689
 690                 if (sc->wol) {
 691                         E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 692                         E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 693                         igb_enable_wol(dev);
 694                 }
 695
 696                 igb_teardown_intr(sc);
 697
 698                 ifnet_deserialize_all(ifp);
 699
 700                 ether_ifdetach(ifp);
 701         } else if (sc->mem_res != NULL) {
 702                 igb_rel_hw_control(sc);
 703         }
 704         bus_generic_detach(dev);
 705
 706         if (sc->sysctl_tree != NULL)
 707                 sysctl_ctx_free(&sc->sysctl_ctx);
 708
 709         igb_free_intr(sc);
 710
 711         if (sc->msix_mem_res != NULL) {
 712                 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_mem_rid,
 713                     sc->msix_mem_res);
 714         }
 715         if (sc->mem_res != NULL) {
 716                 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
 717                     sc->mem_res);
 718         }
 719
 720         igb_free_rings(sc);
 721
 722         if (sc->mta != NULL)
 723                 kfree(sc->mta, M_DEVBUF);
 724         if (sc->stats != NULL)
 725                 kfree(sc->stats, M_DEVBUF);
 726         if (sc->serializes != NULL)
 727                 kfree(sc->serializes, M_DEVBUF);
 728
 729         return 0;
 730 }
 731
 732 static int
 733 igb_shutdown(device_t dev)
 734 {
 735         return igb_suspend(dev);
 736 }
 737
 738 static int
 739 igb_suspend(device_t dev)
 740 {
 741         struct igb_softc *sc = device_get_softc(dev);
 742         struct ifnet *ifp = &sc->arpcom.ac_if;
 743
 744         ifnet_serialize_all(ifp);
 745
 746         igb_stop(sc);
 747
 748         igb_rel_mgmt(sc);
 749         igb_rel_hw_control(sc);
 750
 751         if (sc->wol) {
 752                 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 753                 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 754                 igb_enable_wol(dev);
 755         }
 756
 757         ifnet_deserialize_all(ifp);
 758
 759         return bus_generic_suspend(dev);
 760 }
 761
 762 static int
 763 igb_resume(device_t dev)
 764 {
 765         struct igb_softc *sc = device_get_softc(dev);
 766         struct ifnet *ifp = &sc->arpcom.ac_if;
 767         int i;
 768
 769         ifnet_serialize_all(ifp);
 770
 771         igb_init(sc);
 772         igb_get_mgmt(sc);
 773
 774         for (i = 0; i < sc->tx_ring_inuse; ++i)
 775                 ifsq_devstart_sched(sc->tx_rings[i].ifsq);
 776
 777         ifnet_deserialize_all(ifp);
 778
 779         return bus_generic_resume(dev);
 780 }
 781
 782 static int
 783 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
 784 {
 785         struct igb_softc *sc = ifp->if_softc;
 786         struct ifreq *ifr = (struct ifreq *)data;
 787         int max_frame_size, mask, reinit;
 788         int error = 0;
 789
 790         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 791
 792         switch (command) {
 793         case SIOCSIFMTU:
 794                 max_frame_size = 9234;
 795                 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
 796                     ETHER_CRC_LEN) {
 797                         error = EINVAL;
 798                         break;
 799                 }
 800
 801                 ifp->if_mtu = ifr->ifr_mtu;
 802                 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
 803                     ETHER_CRC_LEN;
 804
 805                 if (ifp->if_flags & IFF_RUNNING)
 806                         igb_init(sc);
 807                 break;
 808
 809         case SIOCSIFFLAGS:
 810                 if (ifp->if_flags & IFF_UP) {
 811                         if (ifp->if_flags & IFF_RUNNING) {
 812                                 if ((ifp->if_flags ^ sc->if_flags) &
 813                                     (IFF_PROMISC | IFF_ALLMULTI)) {
 814                                         igb_disable_promisc(sc);
 815                                         igb_set_promisc(sc);
 816                                 }
 817                         } else {
 818                                 igb_init(sc);
 819                         }
 820                 } else if (ifp->if_flags & IFF_RUNNING) {
 821                         igb_stop(sc);
 822                 }
 823                 sc->if_flags = ifp->if_flags;
 824                 break;
 825
 826         case SIOCADDMULTI:
 827         case SIOCDELMULTI:
 828                 if (ifp->if_flags & IFF_RUNNING) {
 829                         igb_disable_intr(sc);
 830                         igb_set_multi(sc);
 831 #ifdef IFPOLL_ENABLE
 832                         if (!(ifp->if_flags & IFF_NPOLLING))
 833 #endif
 834                                 igb_enable_intr(sc);
 835                 }
 836                 break;
 837
 838         case SIOCSIFMEDIA:
 839                 /*
 840                  * As the speed/duplex settings are being
 841                  * changed, we need toreset the PHY.
 842                  */
 843                 sc->hw.phy.reset_disable = FALSE;
 844
 845                 /* Check SOL/IDER usage */
 846                 if (e1000_check_reset_block(&sc->hw)) {
 847                         if_printf(ifp, "Media change is "
 848                             "blocked due to SOL/IDER session.\n");
 849                         break;
 850                 }
 851                 /* FALL THROUGH */
 852
 853         case SIOCGIFMEDIA:
 854                 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
 855                 break;
 856
 857         case SIOCSIFCAP:
 858                 reinit = 0;
 859                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 860                 if (mask & IFCAP_RXCSUM) {
 861                         ifp->if_capenable ^= IFCAP_RXCSUM;
 862                         reinit = 1;
 863                 }
 864                 if (mask & IFCAP_VLAN_HWTAGGING) {
 865                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
 866                         reinit = 1;
 867                 }
 868                 if (mask & IFCAP_TXCSUM) {
 869                         ifp->if_capenable ^= IFCAP_TXCSUM;
 870                         if (ifp->if_capenable & IFCAP_TXCSUM)
 871                                 ifp->if_hwassist |= IGB_CSUM_FEATURES;
 872                         else
 873                                 ifp->if_hwassist &= ~IGB_CSUM_FEATURES;
 874                 }
 875                 if (mask & IFCAP_TSO) {
 876                         ifp->if_capenable ^= IFCAP_TSO;
 877                         if (ifp->if_capenable & IFCAP_TSO)
 878                                 ifp->if_hwassist |= CSUM_TSO;
 879                         else
 880                                 ifp->if_hwassist &= ~CSUM_TSO;
 881                 }
 882                 if (mask & IFCAP_RSS)
 883                         ifp->if_capenable ^= IFCAP_RSS;
 884                 if (reinit && (ifp->if_flags & IFF_RUNNING))
 885                         igb_init(sc);
 886                 break;
 887
 888         default:
 889                 error = ether_ioctl(ifp, command, data);
 890                 break;
 891         }
 892         return error;
 893 }
 894
 895 static void
 896 igb_init(void *xsc)
 897 {
 898         struct igb_softc *sc = xsc;
 899         struct ifnet *ifp = &sc->arpcom.ac_if;
 900         boolean_t polling;
 901         int i;
 902
 903         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 904
 905         igb_stop(sc);
 906
 907         /* Get the latest mac address, User can use a LAA */
 908         bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
 909
 910         /* Put the address into the Receive Address Array */
 911         e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
 912
 913         igb_reset(sc);
 914         igb_update_link_status(sc);
 915
 916         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
 917
 918         /* Configure for OS presence */
 919         igb_get_mgmt(sc);
 920
 921         polling = FALSE;
 922 #ifdef IFPOLL_ENABLE
 923         if (ifp->if_flags & IFF_NPOLLING)
 924                 polling = TRUE;
 925 #endif
 926
 927         /* Configured used RX/TX rings */
 928         igb_set_ring_inuse(sc, polling);
 929         ifq_set_subq_mask(&ifp->if_snd, sc->tx_ring_inuse - 1);
 930
 931         /* Initialize interrupt */
 932         igb_init_intr(sc);
 933
 934         /* Prepare transmit descriptors and buffers */
 935         for (i = 0; i < sc->tx_ring_inuse; ++i)
 936                 igb_init_tx_ring(&sc->tx_rings[i]);
 937         igb_init_tx_unit(sc);
 938
 939         /* Setup Multicast table */
 940         igb_set_multi(sc);
 941
 942 #if 0
 943         /*
 944          * Figure out the desired mbuf pool
 945          * for doing jumbo/packetsplit
 946          */
 947         if (adapter->max_frame_size <= 2048)
 948                 adapter->rx_mbuf_sz = MCLBYTES;
 949         else if (adapter->max_frame_size <= 4096)
 950                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
 951         else
 952                 adapter->rx_mbuf_sz = MJUM9BYTES;
 953 #endif
 954
 955         /* Prepare receive descriptors and buffers */
 956         for (i = 0; i < sc->rx_ring_inuse; ++i) {
 957                 int error;
 958
 959                 error = igb_init_rx_ring(&sc->rx_rings[i]);
 960                 if (error) {
 961                         if_printf(ifp, "Could not setup receive structures\n");
 962                         igb_stop(sc);
 963                         return;
 964                 }
 965         }
 966         igb_init_rx_unit(sc);
 967
 968         /* Enable VLAN support */
 969         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
 970                 igb_set_vlan(sc);
 971
 972         /* Don't lose promiscuous settings */
 973         igb_set_promisc(sc);
 974
 975         ifp->if_flags |= IFF_RUNNING;
 976         for (i = 0; i < sc->tx_ring_inuse; ++i) {
 977                 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
 978                 ifsq_watchdog_start(&sc->tx_rings[i].tx_watchdog);
 979         }
 980
 981         if (polling || sc->intr_type == PCI_INTR_TYPE_MSIX)
 982                 sc->timer_cpuid = 0; /* XXX fixed */
 983         else
 984                 sc->timer_cpuid = rman_get_cpuid(sc->intr_res);
 985         callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
 986         e1000_clear_hw_cntrs_base_generic(&sc->hw);
 987
 988         /* This clears any pending interrupts */
 989         E1000_READ_REG(&sc->hw, E1000_ICR);
 990
 991         /*
 992          * Only enable interrupts if we are not polling, make sure
 993          * they are off otherwise.
 994          */
 995         if (polling) {
 996                 igb_disable_intr(sc);
 997         } else {
 998                 igb_enable_intr(sc);
 999                 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
1000         }
1001
1002         /* Set Energy Efficient Ethernet */
1003         e1000_set_eee_i350(&sc->hw);
1004
1005         /* Don't reset the phy next time init gets called */
1006         sc->hw.phy.reset_disable = TRUE;
1007 }
1008
1009 static void
1010 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1011 {
1012         struct igb_softc *sc = ifp->if_softc;
1013         u_char fiber_type = IFM_1000_SX;
1014
1015         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1016
1017         igb_update_link_status(sc);
1018
1019         ifmr->ifm_status = IFM_AVALID;
1020         ifmr->ifm_active = IFM_ETHER;
1021
1022         if (!sc->link_active)
1023                 return;
1024
1025         ifmr->ifm_status |= IFM_ACTIVE;
1026
1027         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1028             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1029                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1030         } else {
1031                 switch (sc->link_speed) {
1032                 case 10:
1033                         ifmr->ifm_active |= IFM_10_T;
1034                         break;
1035
1036                 case 100:
1037                         ifmr->ifm_active |= IFM_100_TX;
1038                         break;
1039
1040                 case 1000:
1041                         ifmr->ifm_active |= IFM_1000_T;
1042                         break;
1043                 }
1044                 if (sc->link_duplex == FULL_DUPLEX)
1045                         ifmr->ifm_active |= IFM_FDX;
1046                 else
1047                         ifmr->ifm_active |= IFM_HDX;
1048         }
1049 }
1050
1051 static int
1052 igb_media_change(struct ifnet *ifp)
1053 {
1054         struct igb_softc *sc = ifp->if_softc;
1055         struct ifmedia *ifm = &sc->media;
1056
1057         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1058
1059         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1060                 return EINVAL;
1061
1062         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1063         case IFM_AUTO:
1064                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1065                 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1066                 break;
1067
1068         case IFM_1000_LX:
1069         case IFM_1000_SX:
1070         case IFM_1000_T:
1071                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1072                 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1073                 break;
1074
1075         case IFM_100_TX:
1076                 sc->hw.mac.autoneg = FALSE;
1077                 sc->hw.phy.autoneg_advertised = 0;
1078                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1079                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1080                 else
1081                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1082                 break;
1083
1084         case IFM_10_T:
1085                 sc->hw.mac.autoneg = FALSE;
1086                 sc->hw.phy.autoneg_advertised = 0;
1087                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1088                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1089                 else
1090                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1091                 break;
1092
1093         default:
1094                 if_printf(ifp, "Unsupported media type\n");
1095                 break;
1096         }
1097
1098         igb_init(sc);
1099
1100         return 0;
1101 }
1102
1103 static void
1104 igb_set_promisc(struct igb_softc *sc)
1105 {
1106         struct ifnet *ifp = &sc->arpcom.ac_if;
1107         struct e1000_hw *hw = &sc->hw;
1108         uint32_t reg;
1109
1110         if (sc->vf_ifp) {
1111                 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1112                 return;
1113         }
1114
1115         reg = E1000_READ_REG(hw, E1000_RCTL);
1116         if (ifp->if_flags & IFF_PROMISC) {
1117                 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1118                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1119         } else if (ifp->if_flags & IFF_ALLMULTI) {
1120                 reg |= E1000_RCTL_MPE;
1121                 reg &= ~E1000_RCTL_UPE;
1122                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1123         }
1124 }
1125
1126 static void
1127 igb_disable_promisc(struct igb_softc *sc)
1128 {
1129         struct e1000_hw *hw = &sc->hw;
1130         uint32_t reg;
1131
1132         if (sc->vf_ifp) {
1133                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1134                 return;
1135         }
1136         reg = E1000_READ_REG(hw, E1000_RCTL);
1137         reg &= ~E1000_RCTL_UPE;
1138         reg &= ~E1000_RCTL_MPE;
1139         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1140 }
1141
1142 static void
1143 igb_set_multi(struct igb_softc *sc)
1144 {
1145         struct ifnet *ifp = &sc->arpcom.ac_if;
1146         struct ifmultiaddr *ifma;
1147         uint32_t reg_rctl = 0;
1148         uint8_t *mta;
1149         int mcnt = 0;
1150
1151         mta = sc->mta;
1152         bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1153
1154         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1155                 if (ifma->ifma_addr->sa_family != AF_LINK)
1156                         continue;
1157
1158                 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1159                         break;
1160
1161                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1162                     &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1163                 mcnt++;
1164         }
1165
1166         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1167                 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1168                 reg_rctl |= E1000_RCTL_MPE;
1169                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1170         } else {
1171                 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1172         }
1173 }
1174
1175 static void
1176 igb_timer(void *xsc)
1177 {
1178         struct igb_softc *sc = xsc;
1179
1180         lwkt_serialize_enter(&sc->main_serialize);
1181
1182         igb_update_link_status(sc);
1183         igb_update_stats_counters(sc);
1184
1185         callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
1186
1187         lwkt_serialize_exit(&sc->main_serialize);
1188 }
1189
1190 static void
1191 igb_update_link_status(struct igb_softc *sc)
1192 {
1193         struct ifnet *ifp = &sc->arpcom.ac_if;
1194         struct e1000_hw *hw = &sc->hw;
1195         uint32_t link_check, thstat, ctrl;
1196
1197         link_check = thstat = ctrl = 0;
1198
1199         /* Get the cached link value or read for real */
1200         switch (hw->phy.media_type) {
1201         case e1000_media_type_copper:
1202                 if (hw->mac.get_link_status) {
1203                         /* Do the work to read phy */
1204                         e1000_check_for_link(hw);
1205                         link_check = !hw->mac.get_link_status;
1206                 } else {
1207                         link_check = TRUE;
1208                 }
1209                 break;
1210
1211         case e1000_media_type_fiber:
1212                 e1000_check_for_link(hw);
1213                 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1214                 break;
1215
1216         case e1000_media_type_internal_serdes:
1217                 e1000_check_for_link(hw);
1218                 link_check = hw->mac.serdes_has_link;
1219                 break;
1220
1221         /* VF device is type_unknown */
1222         case e1000_media_type_unknown:
1223                 e1000_check_for_link(hw);
1224                 link_check = !hw->mac.get_link_status;
1225                 /* Fall thru */
1226         default:
1227                 break;
1228         }
1229
1230         /* Check for thermal downshift or shutdown */
1231         if (hw->mac.type == e1000_i350) {
1232                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1233                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1234         }
1235
1236         /* Now we check if a transition has happened */
1237         if (link_check && sc->link_active == 0) {
1238                 e1000_get_speed_and_duplex(hw,
1239                     &sc->link_speed, &sc->link_duplex);
1240                 if (bootverbose) {
1241                         if_printf(ifp, "Link is up %d Mbps %s\n",
1242                             sc->link_speed,
1243                             sc->link_duplex == FULL_DUPLEX ?
1244                             "Full Duplex" : "Half Duplex");
1245                 }
1246                 sc->link_active = 1;
1247
1248                 ifp->if_baudrate = sc->link_speed * 1000000;
1249                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1250                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1251                         if_printf(ifp, "Link: thermal downshift\n");
1252                 /* This can sleep */
1253                 ifp->if_link_state = LINK_STATE_UP;
1254                 if_link_state_change(ifp);
1255         } else if (!link_check && sc->link_active == 1) {
1256                 ifp->if_baudrate = sc->link_speed = 0;
1257                 sc->link_duplex = 0;
1258                 if (bootverbose)
1259                         if_printf(ifp, "Link is Down\n");
1260                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1261                     (thstat & E1000_THSTAT_PWR_DOWN))
1262                         if_printf(ifp, "Link: thermal shutdown\n");
1263                 sc->link_active = 0;
1264                 /* This can sleep */
1265                 ifp->if_link_state = LINK_STATE_DOWN;
1266                 if_link_state_change(ifp);
1267         }
1268 }
1269
1270 static void
1271 igb_stop(struct igb_softc *sc)
1272 {
1273         struct ifnet *ifp = &sc->arpcom.ac_if;
1274         int i;
1275
1276         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1277
1278         igb_disable_intr(sc);
1279
1280         callout_stop(&sc->timer);
1281
1282         ifp->if_flags &= ~IFF_RUNNING;
1283         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1284                 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
1285                 ifsq_watchdog_stop(&sc->tx_rings[i].tx_watchdog);
1286                 sc->tx_rings[i].tx_flags &= ~IGB_TXFLAG_ENABLED;
1287         }
1288
1289         e1000_reset_hw(&sc->hw);
1290         E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1291
1292         e1000_led_off(&sc->hw);
1293         e1000_cleanup_led(&sc->hw);
1294
1295         for (i = 0; i < sc->tx_ring_cnt; ++i)
1296                 igb_free_tx_ring(&sc->tx_rings[i]);
1297         for (i = 0; i < sc->rx_ring_cnt; ++i)
1298                 igb_free_rx_ring(&sc->rx_rings[i]);
1299 }
1300
1301 static void
1302 igb_reset(struct igb_softc *sc)
1303 {
1304         struct ifnet *ifp = &sc->arpcom.ac_if;
1305         struct e1000_hw *hw = &sc->hw;
1306         struct e1000_fc_info *fc = &hw->fc;
1307         uint32_t pba = 0;
1308         uint16_t hwm;
1309
1310         /* Let the firmware know the OS is in control */
1311         igb_get_hw_control(sc);
1312
1313         /*
1314          * Packet Buffer Allocation (PBA)
1315          * Writing PBA sets the receive portion of the buffer
1316          * the remainder is used for the transmit buffer.
1317          */
1318         switch (hw->mac.type) {
1319         case e1000_82575:
1320                 pba = E1000_PBA_32K;
1321                 break;
1322
1323         case e1000_82576:
1324         case e1000_vfadapt:
1325                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1326                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1327                 break;
1328
1329         case e1000_82580:
1330         case e1000_i350:
1331         case e1000_vfadapt_i350:
1332                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1333                 pba = e1000_rxpbs_adjust_82580(pba);
1334                 break;
1335                 /* XXX pba = E1000_PBA_35K; */
1336
1337         default:
1338                 break;
1339         }
1340
1341         /* Special needs in case of Jumbo frames */
1342         if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1343                 uint32_t tx_space, min_tx, min_rx;
1344
1345                 pba = E1000_READ_REG(hw, E1000_PBA);
1346                 tx_space = pba >> 16;
1347                 pba &= 0xffff;
1348
1349                 min_tx = (sc->max_frame_size +
1350                     sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1351                 min_tx = roundup2(min_tx, 1024);
1352                 min_tx >>= 10;
1353                 min_rx = sc->max_frame_size;
1354                 min_rx = roundup2(min_rx, 1024);
1355                 min_rx >>= 10;
1356                 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1357                         pba = pba - (min_tx - tx_space);
1358                         /*
1359                          * if short on rx space, rx wins
1360                          * and must trump tx adjustment
1361                          */
1362                         if (pba < min_rx)
1363                                 pba = min_rx;
1364                 }
1365                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1366         }
1367
1368         /*
1369          * These parameters control the automatic generation (Tx) and
1370          * response (Rx) to Ethernet PAUSE frames.
1371          * - High water mark should allow for at least two frames to be
1372          *   received after sending an XOFF.
1373          * - Low water mark works best when it is very near the high water mark.
1374          *   This allows the receiver to restart by sending XON when it has
1375          *   drained a bit.
1376          */
1377         hwm = min(((pba << 10) * 9 / 10),
1378             ((pba << 10) - 2 * sc->max_frame_size));
1379
1380         if (hw->mac.type < e1000_82576) {
1381                 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1382                 fc->low_water = fc->high_water - 8;
1383         } else {
1384                 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1385                 fc->low_water = fc->high_water - 16;
1386         }
1387         fc->pause_time = IGB_FC_PAUSE_TIME;
1388         fc->send_xon = TRUE;
1389
1390         /* Issue a global reset */
1391         e1000_reset_hw(hw);
1392         E1000_WRITE_REG(hw, E1000_WUC, 0);
1393
1394         if (e1000_init_hw(hw) < 0)
1395                 if_printf(ifp, "Hardware Initialization Failed\n");
1396
1397         /* Setup DMA Coalescing */
1398         if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1399                 uint32_t reg;
1400
1401                 hwm = (pba - 4) << 10;
1402                 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1403                     & E1000_DMACR_DMACTHR_MASK;
1404
1405                 /* transition to L0x or L1 if available..*/
1406                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1407
1408                 /* timer = +-1000 usec in 32usec intervals */
1409                 reg |= (1000 >> 5);
1410                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1411
1412                 /* No lower threshold */
1413                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1414
1415                 /* set hwm to PBA -  2 * max frame size */
1416                 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1417
1418                 /* Set the interval before transition */
1419                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1420                 reg |= 0x800000FF; /* 255 usec */
1421                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1422
1423                 /* free space in tx packet buffer to wake from DMA coal */
1424                 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1425                     (20480 - (2 * sc->max_frame_size)) >> 6);
1426
1427                 /* make low power state decision controlled by DMA coal */
1428                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1429                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1430                     reg | E1000_PCIEMISC_LX_DECISION);
1431                 if_printf(ifp, "DMA Coalescing enabled\n");
1432         }
1433
1434         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1435         e1000_get_phy_info(hw);
1436         e1000_check_for_link(hw);
1437 }
1438
1439 static void
1440 igb_setup_ifp(struct igb_softc *sc)
1441 {
1442         struct ifnet *ifp = &sc->arpcom.ac_if;
1443
1444         ifp->if_softc = sc;
1445         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1446         ifp->if_init = igb_init;
1447         ifp->if_ioctl = igb_ioctl;
1448         ifp->if_start = igb_start;
1449         ifp->if_serialize = igb_serialize;
1450         ifp->if_deserialize = igb_deserialize;
1451         ifp->if_tryserialize = igb_tryserialize;
1452 #ifdef INVARIANTS
1453         ifp->if_serialize_assert = igb_serialize_assert;
1454 #endif
1455 #ifdef IFPOLL_ENABLE
1456         ifp->if_npoll = igb_npoll;
1457 #endif
1458
1459         ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1460         ifq_set_ready(&ifp->if_snd);
1461         ifq_set_subq_cnt(&ifp->if_snd, sc->tx_ring_cnt);
1462
1463         ifp->if_mapsubq = ifq_mapsubq_mask;
1464         ifq_set_subq_mask(&ifp->if_snd, 0);
1465
1466         ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1467
1468         ifp->if_capabilities =
1469             IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_TSO;
1470         if (IGB_ENABLE_HWRSS(sc))
1471                 ifp->if_capabilities |= IFCAP_RSS;
1472         ifp->if_capenable = ifp->if_capabilities;
1473         ifp->if_hwassist = IGB_CSUM_FEATURES | CSUM_TSO;
1474
1475         /*
1476          * Tell the upper layer(s) we support long frames
1477          */
1478         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1479
1480         /*
1481          * Specify the media types supported by this adapter and register
1482          * callbacks to update media and link information
1483          */
1484         ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1485         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1486             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1487                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1488                     0, NULL);
1489                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1490         } else {
1491                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1492                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1493                     0, NULL);
1494                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1495                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1496                     0, NULL);
1497                 if (sc->hw.phy.type != e1000_phy_ife) {
1498                         ifmedia_add(&sc->media,
1499                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1500                         ifmedia_add(&sc->media,
1501                             IFM_ETHER | IFM_1000_T, 0, NULL);
1502                 }
1503         }
1504         ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1505         ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1506 }
1507
1508 static void
1509 igb_add_sysctl(struct igb_softc *sc)
1510 {
1511         char node[32];
1512         int i;
1513
1514         sysctl_ctx_init(&sc->sysctl_ctx);
1515         sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1516             SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1517             device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1518         if (sc->sysctl_tree == NULL) {
1519                 device_printf(sc->dev, "can't add sysctl node\n");
1520                 return;
1521         }
1522
1523         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1524             OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1525         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1526             OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1527             "# of RX rings used");
1528         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1529             OID_AUTO, "txr", CTLFLAG_RD, &sc->tx_ring_cnt, 0, "# of TX rings");
1530         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1531             OID_AUTO, "txr_inuse", CTLFLAG_RD, &sc->tx_ring_inuse, 0,
1532             "# of TX rings used");
1533         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1534             OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1535             "# of RX descs");
1536         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1537             OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1538             "# of TX descs");
1539
1540         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
1541                 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1542                     SYSCTL_CHILDREN(sc->sysctl_tree),
1543                     OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1544                     sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1545         } else {
1546                 for (i = 0; i < sc->msix_cnt; ++i) {
1547                         struct igb_msix_data *msix = &sc->msix_data[i];
1548
1549                         ksnprintf(node, sizeof(node), "msix%d_rate", i);
1550                         SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1551                             SYSCTL_CHILDREN(sc->sysctl_tree),
1552                             OID_AUTO, node, CTLTYPE_INT | CTLFLAG_RW,
1553                             msix, 0, igb_sysctl_msix_rate, "I",
1554                             msix->msix_rate_desc);
1555                 }
1556         }
1557
1558         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1559             OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1560             sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1561             "# of segments per TX interrupt");
1562
1563         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1564             OID_AUTO, "tx_wreg_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1565             sc, 0, igb_sysctl_tx_wreg_nsegs, "I",
1566             "# of segments sent before write to hardware register");
1567
1568         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1569             OID_AUTO, "rx_wreg_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1570             sc, 0, igb_sysctl_rx_wreg_nsegs, "I",
1571             "# of segments received before write to hardware register");
1572
1573 #ifdef IFPOLL_ENABLE
1574         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1575             OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
1576             sc, 0, igb_sysctl_npoll_rxoff, "I", "NPOLLING RX cpu offset");
1577         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1578             OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
1579             sc, 0, igb_sysctl_npoll_txoff, "I", "NPOLLING TX cpu offset");
1580 #endif
1581
1582 #ifdef IGB_RSS_DEBUG
1583         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1584             OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1585             "RSS debug level");
1586         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1587                 ksnprintf(node, sizeof(node), "rx%d_pkt", i);
1588                 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1589                     SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1590                     CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1591         }
1592 #endif
1593 #ifdef IGB_TSS_DEBUG
1594         for  (i = 0; i < sc->tx_ring_cnt; ++i) {
1595                 ksnprintf(node, sizeof(node), "tx%d_pkt", i);
1596                 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1597                     SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1598                     CTLFLAG_RW, &sc->tx_rings[i].tx_packets, "TXed packets");
1599         }
1600 #endif
1601 }
1602
1603 static int
1604 igb_alloc_rings(struct igb_softc *sc)
1605 {
1606         int error, i;
1607
1608         /*
1609          * Create top level busdma tag
1610          */
1611         error = bus_dma_tag_create(NULL, 1, 0,
1612             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1613             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1614             &sc->parent_tag);
1615         if (error) {
1616                 device_printf(sc->dev, "could not create top level DMA tag\n");
1617                 return error;
1618         }
1619
1620         /*
1621          * Allocate TX descriptor rings and buffers
1622          */
1623         sc->tx_rings = kmalloc_cachealign(
1624             sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1625             M_DEVBUF, M_WAITOK | M_ZERO);
1626         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1627                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1628
1629                 /* Set up some basics */
1630                 txr->sc = sc;
1631                 txr->me = i;
1632                 lwkt_serialize_init(&txr->tx_serialize);
1633
1634                 error = igb_create_tx_ring(txr);
1635                 if (error)
1636                         return error;
1637         }
1638
1639         /*
1640          * Allocate RX descriptor rings and buffers
1641          */
1642         sc->rx_rings = kmalloc_cachealign(
1643             sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1644             M_DEVBUF, M_WAITOK | M_ZERO);
1645         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1646                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1647
1648                 /* Set up some basics */
1649                 rxr->sc = sc;
1650                 rxr->me = i;
1651                 lwkt_serialize_init(&rxr->rx_serialize);
1652
1653                 error = igb_create_rx_ring(rxr);
1654                 if (error)
1655                         return error;
1656         }
1657
1658         return 0;
1659 }
1660
1661 static void
1662 igb_free_rings(struct igb_softc *sc)
1663 {
1664         int i;
1665
1666         if (sc->tx_rings != NULL) {
1667                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1668                         struct igb_tx_ring *txr = &sc->tx_rings[i];
1669
1670                         igb_destroy_tx_ring(txr, txr->num_tx_desc);
1671                 }
1672                 kfree(sc->tx_rings, M_DEVBUF);
1673         }
1674
1675         if (sc->rx_rings != NULL) {
1676                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1677                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
1678
1679                         igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1680                 }
1681                 kfree(sc->rx_rings, M_DEVBUF);
1682         }
1683 }
1684
1685 static int
1686 igb_create_tx_ring(struct igb_tx_ring *txr)
1687 {
1688         int tsize, error, i, ntxd;
1689
1690         /*
1691          * Validate number of transmit descriptors. It must not exceed
1692          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1693          */
1694         ntxd = device_getenv_int(txr->sc->dev, "txd", igb_txd);
1695         if ((ntxd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN != 0 ||
1696             ntxd > IGB_MAX_TXD || ntxd < IGB_MIN_TXD) {
1697                 device_printf(txr->sc->dev,
1698                     "Using %d TX descriptors instead of %d!\n",
1699                     IGB_DEFAULT_TXD, ntxd);
1700                 txr->num_tx_desc = IGB_DEFAULT_TXD;
1701         } else {
1702                 txr->num_tx_desc = ntxd;
1703         }
1704
1705         /*
1706          * Allocate TX descriptor ring
1707          */
1708         tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1709             IGB_DBA_ALIGN);
1710         txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1711             IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1712             &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1713         if (txr->txdma.dma_vaddr == NULL) {
1714                 device_printf(txr->sc->dev,
1715                     "Unable to allocate TX Descriptor memory\n");
1716                 return ENOMEM;
1717         }
1718         txr->tx_base = txr->txdma.dma_vaddr;
1719         bzero(txr->tx_base, tsize);
1720
1721         tsize = __VM_CACHELINE_ALIGN(
1722             sizeof(struct igb_tx_buf) * txr->num_tx_desc);
1723         txr->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
1724
1725         /*
1726          * Allocate TX head write-back buffer
1727          */
1728         txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1729             __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1730             &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1731         if (txr->tx_hdr == NULL) {
1732                 device_printf(txr->sc->dev,
1733                     "Unable to allocate TX head write-back buffer\n");
1734                 return ENOMEM;
1735         }
1736
1737         /*
1738          * Create DMA tag for TX buffers
1739          */
1740         error = bus_dma_tag_create(txr->sc->parent_tag,
1741             1, 0,               /* alignment, bounds */
1742             BUS_SPACE_MAXADDR,  /* lowaddr */
1743             BUS_SPACE_MAXADDR,  /* highaddr */
1744             NULL, NULL,         /* filter, filterarg */
1745             IGB_TSO_SIZE,       /* maxsize */
1746             IGB_MAX_SCATTER,    /* nsegments */
1747             PAGE_SIZE,          /* maxsegsize */
1748             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1749             BUS_DMA_ONEBPAGE,   /* flags */
1750             &txr->tx_tag);
1751         if (error) {
1752                 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1753                 kfree(txr->tx_buf, M_DEVBUF);
1754                 txr->tx_buf = NULL;
1755                 return error;
1756         }
1757
1758         /*
1759          * Create DMA maps for TX buffers
1760          */
1761         for (i = 0; i < txr->num_tx_desc; ++i) {
1762                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1763
1764                 error = bus_dmamap_create(txr->tx_tag,
1765                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1766                 if (error) {
1767                         device_printf(txr->sc->dev,
1768                             "Unable to create TX DMA map\n");
1769                         igb_destroy_tx_ring(txr, i);
1770                         return error;
1771                 }
1772         }
1773
1774         if (txr->sc->hw.mac.type == e1000_82575)
1775                 txr->tx_flags |= IGB_TXFLAG_TSO_IPLEN0;
1776
1777         /*
1778          * Initialize various watermark
1779          */
1780         txr->spare_desc = IGB_TX_SPARE;
1781         txr->intr_nsegs = txr->num_tx_desc / 16;
1782         txr->wreg_nsegs = IGB_DEF_TXWREG_NSEGS;
1783         txr->oact_hi_desc = txr->num_tx_desc / 2;
1784         txr->oact_lo_desc = txr->num_tx_desc / 8;
1785         if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1786                 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1787         if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1788                 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1789
1790         return 0;
1791 }
1792
1793 static void
1794 igb_free_tx_ring(struct igb_tx_ring *txr)
1795 {
1796         int i;
1797
1798         for (i = 0; i < txr->num_tx_desc; ++i) {
1799                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1800
1801                 if (txbuf->m_head != NULL) {
1802                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1803                         m_freem(txbuf->m_head);
1804                         txbuf->m_head = NULL;
1805                 }
1806         }
1807 }
1808
1809 static void
1810 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1811 {
1812         int i;
1813
1814         if (txr->txdma.dma_vaddr != NULL) {
1815                 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1816                 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1817                     txr->txdma.dma_map);
1818                 bus_dma_tag_destroy(txr->txdma.dma_tag);
1819                 txr->txdma.dma_vaddr = NULL;
1820         }
1821
1822         if (txr->tx_hdr != NULL) {
1823                 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1824                 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1825                     txr->tx_hdr_dmap);
1826                 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1827                 txr->tx_hdr = NULL;
1828         }
1829
1830         if (txr->tx_buf == NULL)
1831                 return;
1832
1833         for (i = 0; i < ndesc; ++i) {
1834                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1835
1836                 KKASSERT(txbuf->m_head == NULL);
1837                 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1838         }
1839         bus_dma_tag_destroy(txr->tx_tag);
1840
1841         kfree(txr->tx_buf, M_DEVBUF);
1842         txr->tx_buf = NULL;
1843 }
1844
1845 static void
1846 igb_init_tx_ring(struct igb_tx_ring *txr)
1847 {
1848         /* Clear the old descriptor contents */
1849         bzero(txr->tx_base,
1850             sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1851
1852         /* Clear TX head write-back buffer */
1853         *(txr->tx_hdr) = 0;
1854
1855         /* Reset indices */
1856         txr->next_avail_desc = 0;
1857         txr->next_to_clean = 0;
1858         txr->tx_nsegs = 0;
1859
1860         /* Set number of descriptors available */
1861         txr->tx_avail = txr->num_tx_desc;
1862
1863         /* Enable this TX ring */
1864         txr->tx_flags |= IGB_TXFLAG_ENABLED;
1865 }
1866
1867 static void
1868 igb_init_tx_unit(struct igb_softc *sc)
1869 {
1870         struct e1000_hw *hw = &sc->hw;
1871         uint32_t tctl;
1872         int i;
1873
1874         /* Setup the Tx Descriptor Rings */
1875         for (i = 0; i < sc->tx_ring_inuse; ++i) {
1876                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1877                 uint64_t bus_addr = txr->txdma.dma_paddr;
1878                 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1879                 uint32_t txdctl = 0;
1880                 uint32_t dca_txctrl;
1881
1882                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1883                     txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1884                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1885                     (uint32_t)(bus_addr >> 32));
1886                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1887                     (uint32_t)bus_addr);
1888
1889                 /* Setup the HW Tx Head and Tail descriptor pointers */
1890                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1891                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1892
1893                 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1894                 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1895                 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1896
1897                 /*
1898                  * Don't set WB_on_EITR:
1899                  * - 82575 does not have it
1900                  * - It almost has no effect on 82576, see:
1901                  *   82576 specification update errata #26
1902                  * - It causes unnecessary bus traffic
1903                  */
1904                 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1905                     (uint32_t)(hdr_paddr >> 32));
1906                 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1907                     ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1908
1909                 /*
1910                  * WTHRESH is ignored by the hardware, since header
1911                  * write back mode is used.
1912                  */
1913                 txdctl |= IGB_TX_PTHRESH;
1914                 txdctl |= IGB_TX_HTHRESH << 8;
1915                 txdctl |= IGB_TX_WTHRESH << 16;
1916                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1917                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1918         }
1919
1920         if (sc->vf_ifp)
1921                 return;
1922
1923         e1000_config_collision_dist(hw);
1924
1925         /* Program the Transmit Control Register */
1926         tctl = E1000_READ_REG(hw, E1000_TCTL);
1927         tctl &= ~E1000_TCTL_CT;
1928         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1929             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1930
1931         /* This write will effectively turn on the transmit unit. */
1932         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1933 }
1934
1935 static boolean_t
1936 igb_txcsum_ctx(struct igb_tx_ring *txr, struct mbuf *mp)
1937 {
1938         struct e1000_adv_tx_context_desc *TXD;
1939         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1940         int ehdrlen, ctxd, ip_hlen = 0;
1941         boolean_t offload = TRUE;
1942
1943         if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1944                 offload = FALSE;
1945
1946         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1947
1948         ctxd = txr->next_avail_desc;
1949         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1950
1951         /*
1952          * In advanced descriptors the vlan tag must
1953          * be placed into the context descriptor, thus
1954          * we need to be here just for that setup.
1955          */
1956         if (mp->m_flags & M_VLANTAG) {
1957                 uint16_t vlantag;
1958
1959                 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1960                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1961         } else if (!offload) {
1962                 return FALSE;
1963         }
1964
1965         ehdrlen = mp->m_pkthdr.csum_lhlen;
1966         KASSERT(ehdrlen > 0, ("invalid ether hlen"));
1967
1968         /* Set the ether header length */
1969         vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1970         if (mp->m_pkthdr.csum_flags & CSUM_IP) {
1971                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1972                 ip_hlen = mp->m_pkthdr.csum_iphlen;
1973                 KASSERT(ip_hlen > 0, ("invalid ip hlen"));
1974         }
1975         vlan_macip_lens |= ip_hlen;
1976
1977         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1978         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1979                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1980         else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1981                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1982
1983         /* 82575 needs the queue index added */
1984         if (txr->sc->hw.mac.type == e1000_82575)
1985                 mss_l4len_idx = txr->me << 4;
1986
1987         /* Now copy bits into descriptor */
1988         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1989         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1990         TXD->seqnum_seed = htole32(0);
1991         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1992
1993         /* We've consumed the first desc, adjust counters */
1994         if (++ctxd == txr->num_tx_desc)
1995                 ctxd = 0;
1996         txr->next_avail_desc = ctxd;
1997         --txr->tx_avail;
1998
1999         return offload;
2000 }
2001
2002 static void
2003 igb_txeof(struct igb_tx_ring *txr)
2004 {
2005         struct ifnet *ifp = &txr->sc->arpcom.ac_if;
2006         int first, hdr, avail;
2007
2008         if (txr->tx_avail == txr->num_tx_desc)
2009                 return;
2010
2011         first = txr->next_to_clean;
2012         hdr = *(txr->tx_hdr);
2013
2014         if (first == hdr)
2015                 return;
2016
2017         avail = txr->tx_avail;
2018         while (first != hdr) {
2019                 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
2020
2021                 ++avail;
2022                 if (txbuf->m_head) {
2023                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
2024                         m_freem(txbuf->m_head);
2025                         txbuf->m_head = NULL;
2026                         ++ifp->if_opackets;
2027                 }
2028                 if (++first == txr->num_tx_desc)
2029                         first = 0;
2030         }
2031         txr->next_to_clean = first;
2032         txr->tx_avail = avail;
2033
2034         /*
2035          * If we have a minimum free, clear OACTIVE
2036          * to tell the stack that it is OK to send packets.
2037          */
2038         if (IGB_IS_NOT_OACTIVE(txr)) {
2039                 ifsq_clr_oactive(txr->ifsq);
2040
2041                 /*
2042                  * We have enough TX descriptors, turn off
2043                  * the watchdog.  We allow small amount of
2044                  * packets (roughly intr_nsegs) pending on
2045                  * the transmit ring.
2046                  */
2047                 txr->tx_watchdog.wd_timer = 0;
2048         }
2049 }
2050
2051 static int
2052 igb_create_rx_ring(struct igb_rx_ring *rxr)
2053 {
2054         int rsize, i, error, nrxd;
2055
2056         /*
2057          * Validate number of receive descriptors. It must not exceed
2058          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
2059          */
2060         nrxd = device_getenv_int(rxr->sc->dev, "rxd", igb_rxd);
2061         if ((nrxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN != 0 ||
2062             nrxd > IGB_MAX_RXD || nrxd < IGB_MIN_RXD) {
2063                 device_printf(rxr->sc->dev,
2064                     "Using %d RX descriptors instead of %d!\n",
2065                     IGB_DEFAULT_RXD, nrxd);
2066                 rxr->num_rx_desc = IGB_DEFAULT_RXD;
2067         } else {
2068                 rxr->num_rx_desc = nrxd;
2069         }
2070
2071         /*
2072          * Allocate RX descriptor ring
2073          */
2074         rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
2075             IGB_DBA_ALIGN);
2076         rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
2077             IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2078             &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
2079             &rxr->rxdma.dma_paddr);
2080         if (rxr->rxdma.dma_vaddr == NULL) {
2081                 device_printf(rxr->sc->dev,
2082                     "Unable to allocate RxDescriptor memory\n");
2083                 return ENOMEM;
2084         }
2085         rxr->rx_base = rxr->rxdma.dma_vaddr;
2086         bzero(rxr->rx_base, rsize);
2087
2088         rsize = __VM_CACHELINE_ALIGN(
2089             sizeof(struct igb_rx_buf) * rxr->num_rx_desc);
2090         rxr->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
2091
2092         /*
2093          * Create DMA tag for RX buffers
2094          */
2095         error = bus_dma_tag_create(rxr->sc->parent_tag,
2096             1, 0,               /* alignment, bounds */
2097             BUS_SPACE_MAXADDR,  /* lowaddr */
2098             BUS_SPACE_MAXADDR,  /* highaddr */
2099             NULL, NULL,         /* filter, filterarg */
2100             MCLBYTES,           /* maxsize */
2101             1,                  /* nsegments */
2102             MCLBYTES,           /* maxsegsize */
2103             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2104             &rxr->rx_tag);
2105         if (error) {
2106                 device_printf(rxr->sc->dev,
2107                     "Unable to create RX payload DMA tag\n");
2108                 kfree(rxr->rx_buf, M_DEVBUF);
2109                 rxr->rx_buf = NULL;
2110                 return error;
2111         }
2112
2113         /*
2114          * Create spare DMA map for RX buffers
2115          */
2116         error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2117             &rxr->rx_sparemap);
2118         if (error) {
2119                 device_printf(rxr->sc->dev,
2120                     "Unable to create spare RX DMA maps\n");
2121                 bus_dma_tag_destroy(rxr->rx_tag);
2122                 kfree(rxr->rx_buf, M_DEVBUF);
2123                 rxr->rx_buf = NULL;
2124                 return error;
2125         }
2126
2127         /*
2128          * Create DMA maps for RX buffers
2129          */
2130         for (i = 0; i < rxr->num_rx_desc; i++) {
2131                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2132
2133                 error = bus_dmamap_create(rxr->rx_tag,
2134                     BUS_DMA_WAITOK, &rxbuf->map);
2135                 if (error) {
2136                         device_printf(rxr->sc->dev,
2137                             "Unable to create RX DMA maps\n");
2138                         igb_destroy_rx_ring(rxr, i);
2139                         return error;
2140                 }
2141         }
2142
2143         /*
2144          * Initialize various watermark
2145          */
2146         rxr->wreg_nsegs = IGB_DEF_RXWREG_NSEGS;
2147
2148         return 0;
2149 }
2150
2151 static void
2152 igb_free_rx_ring(struct igb_rx_ring *rxr)
2153 {
2154         int i;
2155
2156         for (i = 0; i < rxr->num_rx_desc; ++i) {
2157                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2158
2159                 if (rxbuf->m_head != NULL) {
2160                         bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2161                         m_freem(rxbuf->m_head);
2162                         rxbuf->m_head = NULL;
2163                 }
2164         }
2165
2166         if (rxr->fmp != NULL)
2167                 m_freem(rxr->fmp);
2168         rxr->fmp = NULL;
2169         rxr->lmp = NULL;
2170 }
2171
2172 static void
2173 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2174 {
2175         int i;
2176
2177         if (rxr->rxdma.dma_vaddr != NULL) {
2178                 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2179                 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2180                     rxr->rxdma.dma_map);
2181                 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2182                 rxr->rxdma.dma_vaddr = NULL;
2183         }
2184
2185         if (rxr->rx_buf == NULL)
2186                 return;
2187
2188         for (i = 0; i < ndesc; ++i) {
2189                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2190
2191                 KKASSERT(rxbuf->m_head == NULL);
2192                 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2193         }
2194         bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2195         bus_dma_tag_destroy(rxr->rx_tag);
2196
2197         kfree(rxr->rx_buf, M_DEVBUF);
2198         rxr->rx_buf = NULL;
2199 }
2200
2201 static void
2202 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2203 {
2204         rxd->read.pkt_addr = htole64(rxbuf->paddr);
2205         rxd->wb.upper.status_error = 0;
2206 }
2207
2208 static int
2209 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2210 {
2211         struct mbuf *m;
2212         bus_dma_segment_t seg;
2213         bus_dmamap_t map;
2214         struct igb_rx_buf *rxbuf;
2215         int error, nseg;
2216
2217         m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2218         if (m == NULL) {
2219                 if (wait) {
2220                         if_printf(&rxr->sc->arpcom.ac_if,
2221                             "Unable to allocate RX mbuf\n");
2222                 }
2223                 return ENOBUFS;
2224         }
2225         m->m_len = m->m_pkthdr.len = MCLBYTES;
2226
2227         if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2228                 m_adj(m, ETHER_ALIGN);
2229
2230         error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2231             rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2232         if (error) {
2233                 m_freem(m);
2234                 if (wait) {
2235                         if_printf(&rxr->sc->arpcom.ac_if,
2236                             "Unable to load RX mbuf\n");
2237                 }
2238                 return error;
2239         }
2240
2241         rxbuf = &rxr->rx_buf[i];
2242         if (rxbuf->m_head != NULL)
2243                 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2244
2245         map = rxbuf->map;
2246         rxbuf->map = rxr->rx_sparemap;
2247         rxr->rx_sparemap = map;
2248
2249         rxbuf->m_head = m;
2250         rxbuf->paddr = seg.ds_addr;
2251
2252         igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2253         return 0;
2254 }
2255
2256 static int
2257 igb_init_rx_ring(struct igb_rx_ring *rxr)
2258 {
2259         int i;
2260
2261         /* Clear the ring contents */
2262         bzero(rxr->rx_base,
2263             rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2264
2265         /* Now replenish the ring mbufs */
2266         for (i = 0; i < rxr->num_rx_desc; ++i) {
2267                 int error;
2268
2269                 error = igb_newbuf(rxr, i, TRUE);
2270                 if (error)
2271                         return error;
2272         }
2273
2274         /* Setup our descriptor indices */
2275         rxr->next_to_check = 0;
2276
2277         rxr->fmp = NULL;
2278         rxr->lmp = NULL;
2279         rxr->discard = FALSE;
2280
2281         return 0;
2282 }
2283
2284 static void
2285 igb_init_rx_unit(struct igb_softc *sc)
2286 {
2287         struct ifnet *ifp = &sc->arpcom.ac_if;
2288         struct e1000_hw *hw = &sc->hw;
2289         uint32_t rctl, rxcsum, srrctl = 0;
2290         int i;
2291
2292         /*
2293          * Make sure receives are disabled while setting
2294          * up the descriptor ring
2295          */
2296         rctl = E1000_READ_REG(hw, E1000_RCTL);
2297         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2298
2299 #if 0
2300         /*
2301         ** Set up for header split
2302         */
2303         if (igb_header_split) {
2304                 /* Use a standard mbuf for the header */
2305                 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2306                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2307         } else
2308 #endif
2309                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2310
2311         /*
2312         ** Set up for jumbo frames
2313         */
2314         if (ifp->if_mtu > ETHERMTU) {
2315                 rctl |= E1000_RCTL_LPE;
2316 #if 0
2317                 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2318                         srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2319                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2320                 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2321                         srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2322                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2323                 }
2324                 /* Set maximum packet len */
2325                 psize = adapter->max_frame_size;
2326                 /* are we on a vlan? */
2327                 if (adapter->ifp->if_vlantrunk != NULL)
2328                         psize += VLAN_TAG_SIZE;
2329                 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2330 #else
2331                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2332                 rctl |= E1000_RCTL_SZ_2048;
2333 #endif
2334         } else {
2335                 rctl &= ~E1000_RCTL_LPE;
2336                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2337                 rctl |= E1000_RCTL_SZ_2048;
2338         }
2339
2340         /* Setup the Base and Length of the Rx Descriptor Rings */
2341         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2342                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2343                 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2344                 uint32_t rxdctl;
2345
2346                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2347                     rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
2348                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2349                     (uint32_t)(bus_addr >> 32));
2350                 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2351                     (uint32_t)bus_addr);
2352                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2353                 /* Enable this Queue */
2354                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2355                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2356                 rxdctl &= 0xFFF00000;
2357                 rxdctl |= IGB_RX_PTHRESH;
2358                 rxdctl |= IGB_RX_HTHRESH << 8;
2359                 /*
2360                  * Don't set WTHRESH to a value above 1 on 82576, see:
2361                  * 82576 specification update errata #26
2362                  */
2363                 rxdctl |= IGB_RX_WTHRESH << 16;
2364                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2365         }
2366
2367         rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2368         rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2369
2370         /*
2371          * Receive Checksum Offload for TCP and UDP
2372          *
2373          * Checksum offloading is also enabled if multiple receive
2374          * queue is to be supported, since we need it to figure out
2375          * fragments.
2376          */
2377         if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2378                 /*
2379                  * NOTE:
2380                  * PCSD must be enabled to enable multiple
2381                  * receive queues.
2382                  */
2383                 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2384                     E1000_RXCSUM_PCSD;
2385         } else {
2386                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2387                     E1000_RXCSUM_PCSD);
2388         }
2389         E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2390
2391         if (IGB_ENABLE_HWRSS(sc)) {
2392                 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
2393                 uint32_t reta_shift;
2394                 int j, r;
2395
2396                 /*
2397                  * NOTE:
2398                  * When we reach here, RSS has already been disabled
2399                  * in igb_stop(), so we could safely configure RSS key
2400                  * and redirect table.
2401                  */
2402
2403                 /*
2404                  * Configure RSS key
2405                  */
2406                 toeplitz_get_key(key, sizeof(key));
2407                 for (i = 0; i < IGB_NRSSRK; ++i) {
2408                         uint32_t rssrk;
2409
2410                         rssrk = IGB_RSSRK_VAL(key, i);
2411                         IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2412
2413                         E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
2414                 }
2415
2416                 /*
2417                  * Configure RSS redirect table in following fashion:
2418                  * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2419                  */
2420                 reta_shift = IGB_RETA_SHIFT;
2421                 if (hw->mac.type == e1000_82575)
2422                         reta_shift = IGB_RETA_SHIFT_82575;
2423
2424                 r = 0;
2425                 for (j = 0; j < IGB_NRETA; ++j) {
2426                         uint32_t reta = 0;
2427
2428                         for (i = 0; i < IGB_RETA_SIZE; ++i) {
2429                                 uint32_t q;
2430
2431                                 q = (r % sc->rx_ring_inuse) << reta_shift;
2432                                 reta |= q << (8 * i);
2433                                 ++r;
2434                         }
2435                         IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2436                         E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2437                 }
2438
2439                 /*
2440                  * Enable multiple receive queues.
2441                  * Enable IPv4 RSS standard hash functions.
2442                  * Disable RSS interrupt on 82575
2443                  */
2444                 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2445                                 E1000_MRQC_ENABLE_RSS_4Q |
2446                                 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2447                                 E1000_MRQC_RSS_FIELD_IPV4);
2448         }
2449
2450         /* Setup the Receive Control Register */
2451         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2452         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2453             E1000_RCTL_RDMTS_HALF |
2454             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2455         /* Strip CRC bytes. */
2456         rctl |= E1000_RCTL_SECRC;
2457         /* Make sure VLAN Filters are off */
2458         rctl &= ~E1000_RCTL_VFE;
2459         /* Don't store bad packets */
2460         rctl &= ~E1000_RCTL_SBP;
2461
2462         /* Enable Receives */
2463         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2464
2465         /*
2466          * Setup the HW Rx Head and Tail Descriptor Pointers
2467          *   - needs to be after enable
2468          */
2469         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2470                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2471
2472                 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2473                 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
2474         }
2475 }
2476
2477 static void
2478 igb_rx_refresh(struct igb_rx_ring *rxr, int i)
2479 {
2480         if (--i < 0)
2481                 i = rxr->num_rx_desc - 1;
2482         E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2483 }
2484
2485 static void
2486 igb_rxeof(struct igb_rx_ring *rxr, int count)
2487 {
2488         struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2489         union e1000_adv_rx_desc *cur;
2490         uint32_t staterr;
2491         int i, ncoll = 0;
2492
2493         i = rxr->next_to_check;
2494         cur = &rxr->rx_base[i];
2495         staterr = le32toh(cur->wb.upper.status_error);
2496
2497         if ((staterr & E1000_RXD_STAT_DD) == 0)
2498                 return;
2499
2500         while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2501                 struct pktinfo *pi = NULL, pi0;
2502                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2503                 struct mbuf *m = NULL;
2504                 boolean_t eop;
2505
2506                 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2507                 if (eop)
2508                         --count;
2509
2510                 ++ncoll;
2511                 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2512                     !rxr->discard) {
2513                         struct mbuf *mp = rxbuf->m_head;
2514                         uint32_t hash, hashtype;
2515                         uint16_t vlan;
2516                         int len;
2517
2518                         len = le16toh(cur->wb.upper.length);
2519                         if (rxr->sc->hw.mac.type == e1000_i350 &&
2520                             (staterr & E1000_RXDEXT_STATERR_LB))
2521                                 vlan = be16toh(cur->wb.upper.vlan);
2522                         else
2523                                 vlan = le16toh(cur->wb.upper.vlan);
2524
2525                         hash = le32toh(cur->wb.lower.hi_dword.rss);
2526                         hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2527                             E1000_RXDADV_RSSTYPE_MASK;
2528
2529                         IGB_RSS_DPRINTF(rxr->sc, 10,
2530                             "ring%d, hash 0x%08x, hashtype %u\n",
2531                             rxr->me, hash, hashtype);
2532
2533                         bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2534                             BUS_DMASYNC_POSTREAD);
2535
2536                         if (igb_newbuf(rxr, i, FALSE) != 0) {
2537                                 ifp->if_iqdrops++;
2538                                 goto discard;
2539                         }
2540
2541                         mp->m_len = len;
2542                         if (rxr->fmp == NULL) {
2543                                 mp->m_pkthdr.len = len;
2544                                 rxr->fmp = mp;
2545                                 rxr->lmp = mp;
2546                         } else {
2547                                 rxr->lmp->m_next = mp;
2548                                 rxr->lmp = rxr->lmp->m_next;
2549                                 rxr->fmp->m_pkthdr.len += len;
2550                         }
2551
2552                         if (eop) {
2553                                 m = rxr->fmp;
2554                                 rxr->fmp = NULL;
2555                                 rxr->lmp = NULL;
2556
2557                                 m->m_pkthdr.rcvif = ifp;
2558                                 ifp->if_ipackets++;
2559
2560                                 if (ifp->if_capenable & IFCAP_RXCSUM)
2561                                         igb_rxcsum(staterr, m);
2562
2563                                 if (staterr & E1000_RXD_STAT_VP) {
2564                                         m->m_pkthdr.ether_vlantag = vlan;
2565                                         m->m_flags |= M_VLANTAG;
2566                                 }
2567
2568                                 if (ifp->if_capenable & IFCAP_RSS) {
2569                                         pi = igb_rssinfo(m, &pi0,
2570                                             hash, hashtype, staterr);
2571                                 }
2572 #ifdef IGB_RSS_DEBUG
2573                                 rxr->rx_packets++;
2574 #endif
2575                         }
2576                 } else {
2577                         ifp->if_ierrors++;
2578 discard:
2579                         igb_setup_rxdesc(cur, rxbuf);
2580                         if (!eop)
2581                                 rxr->discard = TRUE;
2582                         else
2583                                 rxr->discard = FALSE;
2584                         if (rxr->fmp != NULL) {
2585                                 m_freem(rxr->fmp);
2586                                 rxr->fmp = NULL;
2587                                 rxr->lmp = NULL;
2588                         }
2589                         m = NULL;
2590                 }
2591
2592                 if (m != NULL)
2593                         ether_input_pkt(ifp, m, pi);
2594
2595                 /* Advance our pointers to the next descriptor. */
2596                 if (++i == rxr->num_rx_desc)
2597                         i = 0;
2598
2599                 if (ncoll >= rxr->wreg_nsegs) {
2600                         igb_rx_refresh(rxr, i);
2601                         ncoll = 0;
2602                 }
2603
2604                 cur = &rxr->rx_base[i];
2605                 staterr = le32toh(cur->wb.upper.status_error);
2606         }
2607         rxr->next_to_check = i;
2608
2609         if (ncoll > 0)
2610                 igb_rx_refresh(rxr, i);
2611 }
2612
2613
2614 static void
2615 igb_set_vlan(struct igb_softc *sc)
2616 {
2617         struct e1000_hw *hw = &sc->hw;
2618         uint32_t reg;
2619 #if 0
2620         struct ifnet *ifp = sc->arpcom.ac_if;
2621 #endif
2622
2623         if (sc->vf_ifp) {
2624                 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2625                 return;
2626         }
2627
2628         reg = E1000_READ_REG(hw, E1000_CTRL);
2629         reg |= E1000_CTRL_VME;
2630         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2631
2632 #if 0
2633         /* Enable the Filter Table */
2634         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2635                 reg = E1000_READ_REG(hw, E1000_RCTL);
2636                 reg &= ~E1000_RCTL_CFIEN;
2637                 reg |= E1000_RCTL_VFE;
2638                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2639         }
2640 #endif
2641
2642         /* Update the frame size */
2643         E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2644             sc->max_frame_size + VLAN_TAG_SIZE);
2645
2646 #if 0
2647         /* Don't bother with table if no vlans */
2648         if ((adapter->num_vlans == 0) ||
2649             ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2650                 return;
2651         /*
2652         ** A soft reset zero's out the VFTA, so
2653         ** we need to repopulate it now.
2654         */
2655         for (int i = 0; i < IGB_VFTA_SIZE; i++)
2656                 if (adapter->shadow_vfta[i] != 0) {
2657                         if (adapter->vf_ifp)
2658                                 e1000_vfta_set_vf(hw,
2659                                     adapter->shadow_vfta[i], TRUE);
2660                         else
2661                                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2662                                  i, adapter->shadow_vfta[i]);
2663                 }
2664 #endif
2665 }
2666
2667 static void
2668 igb_enable_intr(struct igb_softc *sc)
2669 {
2670         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2671                 lwkt_serialize_handler_enable(&sc->main_serialize);
2672         } else {
2673                 int i;
2674
2675                 for (i = 0; i < sc->msix_cnt; ++i) {
2676                         lwkt_serialize_handler_enable(
2677                             sc->msix_data[i].msix_serialize);
2678                 }
2679         }
2680
2681         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2682                 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
2683                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, sc->intr_mask);
2684                 else
2685                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2686                 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2687                 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2688                 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2689         } else {
2690                 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2691         }
2692         E1000_WRITE_FLUSH(&sc->hw);
2693 }
2694
2695 static void
2696 igb_disable_intr(struct igb_softc *sc)
2697 {
2698         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2699                 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2700                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2701         }
2702         E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2703         E1000_WRITE_FLUSH(&sc->hw);
2704
2705         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2706                 lwkt_serialize_handler_disable(&sc->main_serialize);
2707         } else {
2708                 int i;
2709
2710                 for (i = 0; i < sc->msix_cnt; ++i) {
2711                         lwkt_serialize_handler_disable(
2712                             sc->msix_data[i].msix_serialize);
2713                 }
2714         }
2715 }
2716
2717 /*
2718  * Bit of a misnomer, what this really means is
2719  * to enable OS management of the system... aka
2720  * to disable special hardware management features
2721  */
2722 static void
2723 igb_get_mgmt(struct igb_softc *sc)
2724 {
2725         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2726                 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2727                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2728
2729                 /* disable hardware interception of ARP */
2730                 manc &= ~E1000_MANC_ARP_EN;
2731
2732                 /* enable receiving management packets to the host */
2733                 manc |= E1000_MANC_EN_MNG2HOST;
2734                 manc2h |= 1 << 5; /* Mng Port 623 */
2735                 manc2h |= 1 << 6; /* Mng Port 664 */
2736                 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2737                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2738         }
2739 }
2740
2741 /*
2742  * Give control back to hardware management controller
2743  * if there is one.
2744  */
2745 static void
2746 igb_rel_mgmt(struct igb_softc *sc)
2747 {
2748         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2749                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2750
2751                 /* Re-enable hardware interception of ARP */
2752                 manc |= E1000_MANC_ARP_EN;
2753                 manc &= ~E1000_MANC_EN_MNG2HOST;
2754
2755                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2756         }
2757 }
2758
2759 /*
2760  * Sets CTRL_EXT:DRV_LOAD bit.
2761  *
2762  * For ASF and Pass Through versions of f/w this means that
2763  * the driver is loaded.
2764  */
2765 static void
2766 igb_get_hw_control(struct igb_softc *sc)
2767 {
2768         uint32_t ctrl_ext;
2769
2770         if (sc->vf_ifp)
2771                 return;
2772
2773         /* Let firmware know the driver has taken over */
2774         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2775         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2776             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2777 }
2778
2779 /*
2780  * Resets CTRL_EXT:DRV_LOAD bit.
2781  *
2782  * For ASF and Pass Through versions of f/w this means that the
2783  * driver is no longer loaded.
2784  */
2785 static void
2786 igb_rel_hw_control(struct igb_softc *sc)
2787 {
2788         uint32_t ctrl_ext;
2789
2790         if (sc->vf_ifp)
2791                 return;
2792
2793         /* Let firmware taken over control of h/w */
2794         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2795         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2796             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2797 }
2798
2799 static int
2800 igb_is_valid_ether_addr(const uint8_t *addr)
2801 {
2802         uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2803
2804         if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2805                 return FALSE;
2806         return TRUE;
2807 }
2808
2809 /*
2810  * Enable PCI Wake On Lan capability
2811  */
2812 static void
2813 igb_enable_wol(device_t dev)
2814 {
2815         uint16_t cap, status;
2816         uint8_t id;
2817
2818         /* First find the capabilities pointer*/
2819         cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2820
2821         /* Read the PM Capabilities */
2822         id = pci_read_config(dev, cap, 1);
2823         if (id != PCIY_PMG)     /* Something wrong */
2824                 return;
2825
2826         /*
2827          * OK, we have the power capabilities,
2828          * so now get the status register
2829          */
2830         cap += PCIR_POWER_STATUS;
2831         status = pci_read_config(dev, cap, 2);
2832         status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2833         pci_write_config(dev, cap, status, 2);
2834 }
2835
2836 static void
2837 igb_update_stats_counters(struct igb_softc *sc)
2838 {
2839         struct e1000_hw *hw = &sc->hw;
2840         struct e1000_hw_stats *stats;
2841         struct ifnet *ifp = &sc->arpcom.ac_if;
2842
2843         /*
2844          * The virtual function adapter has only a
2845          * small controlled set of stats, do only
2846          * those and return.
2847          */
2848         if (sc->vf_ifp) {
2849                 igb_update_vf_stats_counters(sc);
2850                 return;
2851         }
2852         stats = sc->stats;
2853
2854         if (sc->hw.phy.media_type == e1000_media_type_copper ||
2855             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2856                 stats->symerrs +=
2857                     E1000_READ_REG(hw,E1000_SYMERRS);
2858                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2859         }
2860
2861         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2862         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2863         stats->scc += E1000_READ_REG(hw, E1000_SCC);
2864         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2865
2866         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2867         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2868         stats->colc += E1000_READ_REG(hw, E1000_COLC);
2869         stats->dc += E1000_READ_REG(hw, E1000_DC);
2870         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2871         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2872         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2873
2874         /*
2875          * For watchdog management we need to know if we have been
2876          * paused during the last interval, so capture that here.
2877          */
2878         sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2879         stats->xoffrxc += sc->pause_frames;
2880         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2881         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2882         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2883         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2884         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2885         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2886         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2887         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2888         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2889         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2890         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2891         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2892
2893         /* For the 64-bit byte counters the low dword must be read first. */
2894         /* Both registers clear on the read of the high dword */
2895
2896         stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2897             ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2898         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2899             ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2900
2901         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2902         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2903         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2904         stats->roc += E1000_READ_REG(hw, E1000_ROC);
2905         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2906
2907         stats->tor += E1000_READ_REG(hw, E1000_TORH);
2908         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2909
2910         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2911         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2912         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2913         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2914         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2915         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2916         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2917         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2918         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2919         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2920
2921         /* Interrupt Counts */
2922
2923         stats->iac += E1000_READ_REG(hw, E1000_IAC);
2924         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2925         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2926         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2927         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2928         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2929         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2930         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2931         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2932
2933         /* Host to Card Statistics */
2934
2935         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2936         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2937         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2938         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2939         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2940         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2941         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2942         stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2943             ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2944         stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2945             ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2946         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2947         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2948         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2949
2950         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2951         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2952         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2953         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2954         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2955         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2956
2957         ifp->if_collisions = stats->colc;
2958
2959         /* Rx Errors */
2960         ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2961             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2962
2963         /* Tx Errors */
2964         ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2965
2966         /* Driver specific counters */
2967         sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2968         sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2969         sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2970         sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2971         sc->packet_buf_alloc_tx =
2972             ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2973         sc->packet_buf_alloc_rx =
2974             (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2975 }
2976
2977 static void
2978 igb_vf_init_stats(struct igb_softc *sc)
2979 {
2980         struct e1000_hw *hw = &sc->hw;
2981         struct e1000_vf_stats *stats;
2982
2983         stats = sc->stats;
2984         stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2985         stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2986         stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2987         stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2988         stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2989 }
2990
2991 static void
2992 igb_update_vf_stats_counters(struct igb_softc *sc)
2993 {
2994         struct e1000_hw *hw = &sc->hw;
2995         struct e1000_vf_stats *stats;
2996
2997         if (sc->link_speed == 0)
2998                 return;
2999
3000         stats = sc->stats;
3001         UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
3002         UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
3003         UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
3004         UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
3005         UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
3006 }
3007
3008 #ifdef IFPOLL_ENABLE
3009
3010 static void
3011 igb_npoll_status(struct ifnet *ifp)
3012 {
3013         struct igb_softc *sc = ifp->if_softc;
3014         uint32_t reg_icr;
3015
3016         ASSERT_SERIALIZED(&sc->main_serialize);
3017
3018         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3019         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3020                 sc->hw.mac.get_link_status = 1;
3021                 igb_update_link_status(sc);
3022         }
3023 }
3024
3025 static void
3026 igb_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
3027 {
3028         struct igb_tx_ring *txr = arg;
3029
3030         ASSERT_SERIALIZED(&txr->tx_serialize);
3031
3032         igb_txeof(txr);
3033         if (!ifsq_is_empty(txr->ifsq))
3034                 ifsq_devstart(txr->ifsq);
3035 }
3036
3037 static void
3038 igb_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
3039 {
3040         struct igb_rx_ring *rxr = arg;
3041
3042         ASSERT_SERIALIZED(&rxr->rx_serialize);
3043
3044         igb_rxeof(rxr, cycle);
3045 }
3046
3047 static void
3048 igb_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3049 {
3050         struct igb_softc *sc = ifp->if_softc;
3051         int i, txr_cnt, rxr_cnt;
3052
3053         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3054
3055         if (info) {
3056                 int off;
3057
3058                 info->ifpi_status.status_func = igb_npoll_status;
3059                 info->ifpi_status.serializer = &sc->main_serialize;
3060
3061                 txr_cnt = igb_get_txring_inuse(sc, TRUE);
3062                 off = sc->tx_npoll_off;
3063                 for (i = 0; i < txr_cnt; ++i) {
3064                         struct igb_tx_ring *txr = &sc->tx_rings[i];
3065                         int idx = i + off;
3066
3067                         KKASSERT(idx < ncpus2);
3068                         info->ifpi_tx[idx].poll_func = igb_npoll_tx;
3069                         info->ifpi_tx[idx].arg = txr;
3070                         info->ifpi_tx[idx].serializer = &txr->tx_serialize;
3071                         ifsq_set_cpuid(txr->ifsq, idx);
3072                 }
3073
3074                 rxr_cnt = igb_get_rxring_inuse(sc, TRUE);
3075                 off = sc->rx_npoll_off;
3076                 for (i = 0; i < rxr_cnt; ++i) {
3077                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
3078                         int idx = i + off;
3079
3080                         KKASSERT(idx < ncpus2);
3081                         info->ifpi_rx[idx].poll_func = igb_npoll_rx;
3082                         info->ifpi_rx[idx].arg = rxr;
3083                         info->ifpi_rx[idx].serializer = &rxr->rx_serialize;
3084                 }
3085
3086                 if (ifp->if_flags & IFF_RUNNING) {
3087                         if (rxr_cnt == sc->rx_ring_inuse &&
3088                             txr_cnt == sc->tx_ring_inuse)
3089                                 igb_disable_intr(sc);
3090                         else
3091                                 igb_init(sc);
3092                 }
3093         } else {
3094                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3095                         struct igb_tx_ring *txr = &sc->tx_rings[i];
3096
3097                         ifsq_set_cpuid(txr->ifsq, txr->tx_intr_cpuid);
3098                 }
3099
3100                 if (ifp->if_flags & IFF_RUNNING) {
3101                         txr_cnt = igb_get_txring_inuse(sc, FALSE);
3102                         rxr_cnt = igb_get_rxring_inuse(sc, FALSE);
3103
3104                         if (rxr_cnt == sc->rx_ring_inuse &&
3105                             txr_cnt == sc->tx_ring_inuse)
3106                                 igb_enable_intr(sc);
3107                         else
3108                                 igb_init(sc);
3109                 }
3110         }
3111 }
3112
3113 #endif /* IFPOLL_ENABLE */
3114
3115 static void
3116 igb_intr(void *xsc)
3117 {
3118         struct igb_softc *sc = xsc;
3119         struct ifnet *ifp = &sc->arpcom.ac_if;
3120         uint32_t eicr;
3121
3122         ASSERT_SERIALIZED(&sc->main_serialize);
3123
3124         eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
3125
3126         if (eicr == 0)
3127                 return;
3128
3129         if (ifp->if_flags & IFF_RUNNING) {
3130                 struct igb_tx_ring *txr = &sc->tx_rings[0];
3131                 int i;
3132
3133                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3134                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
3135
3136                         if (eicr & rxr->rx_intr_mask) {
3137                                 lwkt_serialize_enter(&rxr->rx_serialize);
3138                                 igb_rxeof(rxr, -1);
3139                                 lwkt_serialize_exit(&rxr->rx_serialize);
3140                         }
3141                 }
3142
3143                 if (eicr & txr->tx_intr_mask) {
3144                         lwkt_serialize_enter(&txr->tx_serialize);
3145                         igb_txeof(txr);
3146                         if (!ifsq_is_empty(txr->ifsq))
3147                                 ifsq_devstart(txr->ifsq);
3148                         lwkt_serialize_exit(&txr->tx_serialize);
3149                 }
3150         }
3151
3152         if (eicr & E1000_EICR_OTHER) {
3153                 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3154
3155                 /* Link status change */
3156                 if (icr & E1000_ICR_LSC) {
3157                         sc->hw.mac.get_link_status = 1;
3158                         igb_update_link_status(sc);
3159                 }
3160         }
3161
3162         /*
3163          * Reading EICR has the side effect to clear interrupt mask,
3164          * so all interrupts need to be enabled here.
3165          */
3166         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
3167 }
3168
3169 static void
3170 igb_intr_shared(void *xsc)
3171 {
3172         struct igb_softc *sc = xsc;
3173         struct ifnet *ifp = &sc->arpcom.ac_if;
3174         uint32_t reg_icr;
3175
3176         ASSERT_SERIALIZED(&sc->main_serialize);
3177
3178         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3179
3180         /* Hot eject?  */
3181         if (reg_icr == 0xffffffff)
3182                 return;
3183
3184         /* Definitely not our interrupt.  */
3185         if (reg_icr == 0x0)
3186                 return;
3187
3188         if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3189                 return;
3190
3191         if (ifp->if_flags & IFF_RUNNING) {
3192                 if (reg_icr &
3193                     (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3194                         int i;
3195
3196                         for (i = 0; i < sc->rx_ring_inuse; ++i) {
3197                                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3198
3199                                 lwkt_serialize_enter(&rxr->rx_serialize);
3200                                 igb_rxeof(rxr, -1);
3201                                 lwkt_serialize_exit(&rxr->rx_serialize);
3202                         }
3203                 }
3204
3205                 if (reg_icr & E1000_ICR_TXDW) {
3206                         struct igb_tx_ring *txr = &sc->tx_rings[0];
3207
3208                         lwkt_serialize_enter(&txr->tx_serialize);
3209                         igb_txeof(txr);
3210                         if (!ifsq_is_empty(txr->ifsq))
3211                                 ifsq_devstart(txr->ifsq);
3212                         lwkt_serialize_exit(&txr->tx_serialize);
3213                 }
3214         }
3215
3216         /* Link status change */
3217         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3218                 sc->hw.mac.get_link_status = 1;
3219                 igb_update_link_status(sc);
3220         }
3221
3222         if (reg_icr & E1000_ICR_RXO)
3223                 sc->rx_overruns++;
3224 }
3225
3226 static int
3227 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp,
3228     int *segs_used, int *idx)
3229 {
3230         bus_dma_segment_t segs[IGB_MAX_SCATTER];
3231         bus_dmamap_t map;
3232         struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3233         union e1000_adv_tx_desc *txd = NULL;
3234         struct mbuf *m_head = *m_headp;
3235         uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3236         int maxsegs, nsegs, i, j, error;
3237         uint32_t hdrlen = 0;
3238
3239         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3240                 error = igb_tso_pullup(txr, m_headp);
3241                 if (error)
3242                         return error;
3243                 m_head = *m_headp;
3244         }
3245
3246         /* Set basic descriptor constants */
3247         cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3248         cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3249         if (m_head->m_flags & M_VLANTAG)
3250                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3251
3252         /*
3253          * Map the packet for DMA.
3254          */
3255         tx_buf = &txr->tx_buf[txr->next_avail_desc];
3256         tx_buf_mapped = tx_buf;
3257         map = tx_buf->map;
3258
3259         maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3260         KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
3261         if (maxsegs > IGB_MAX_SCATTER)
3262                 maxsegs = IGB_MAX_SCATTER;
3263
3264         error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3265             segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3266         if (error) {
3267                 if (error == ENOBUFS)
3268                         txr->sc->mbuf_defrag_failed++;
3269                 else
3270                         txr->sc->no_tx_dma_setup++;
3271
3272                 m_freem(*m_headp);
3273                 *m_headp = NULL;
3274                 return error;
3275         }
3276         bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3277
3278         m_head = *m_headp;
3279
3280         /*
3281          * Set up the TX context descriptor, if any hardware offloading is
3282          * needed.  This includes CSUM, VLAN, and TSO.  It will consume one
3283          * TX descriptor.
3284          *
3285          * Unlike these chips' predecessors (em/emx), TX context descriptor
3286          * will _not_ interfere TX data fetching pipelining.
3287          */
3288         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3289                 igb_tso_ctx(txr, m_head, &hdrlen);
3290                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3291                 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3292                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3293                 txr->tx_nsegs++;
3294                 (*segs_used)++;
3295         } else if (igb_txcsum_ctx(txr, m_head)) {
3296                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3297                         olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
3298                 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3299                         olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
3300                 txr->tx_nsegs++;
3301                 (*segs_used)++;
3302         }
3303
3304         *segs_used += nsegs;
3305         txr->tx_nsegs += nsegs;
3306         if (txr->tx_nsegs >= txr->intr_nsegs) {
3307                 /*
3308                  * Report Status (RS) is turned on every intr_nsegs
3309                  * descriptors (roughly).
3310                  */
3311                 txr->tx_nsegs = 0;
3312                 cmd_rs = E1000_ADVTXD_DCMD_RS;
3313         }
3314
3315         /* Calculate payload length */
3316         olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3317             << E1000_ADVTXD_PAYLEN_SHIFT);
3318
3319         /* 82575 needs the queue index added */
3320         if (txr->sc->hw.mac.type == e1000_82575)
3321                 olinfo_status |= txr->me << 4;
3322
3323         /* Set up our transmit descriptors */
3324         i = txr->next_avail_desc;
3325         for (j = 0; j < nsegs; j++) {
3326                 bus_size_t seg_len;
3327                 bus_addr_t seg_addr;
3328
3329                 tx_buf = &txr->tx_buf[i];
3330                 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3331                 seg_addr = segs[j].ds_addr;
3332                 seg_len = segs[j].ds_len;
3333
3334                 txd->read.buffer_addr = htole64(seg_addr);
3335                 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3336                 txd->read.olinfo_status = htole32(olinfo_status);
3337                 if (++i == txr->num_tx_desc)
3338                         i = 0;
3339                 tx_buf->m_head = NULL;
3340         }
3341
3342         KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3343         txr->next_avail_desc = i;
3344         txr->tx_avail -= nsegs;
3345
3346         tx_buf->m_head = m_head;
3347         tx_buf_mapped->map = tx_buf->map;
3348         tx_buf->map = map;
3349
3350         /*
3351          * Last Descriptor of Packet needs End Of Packet (EOP)
3352          */
3353         txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3354
3355         /*
3356          * Defer TDT updating, until enough descrptors are setup
3357          */
3358         *idx = i;
3359 #ifdef IGB_TSS_DEBUG
3360         ++txr->tx_packets;
3361 #endif
3362
3363         return 0;
3364 }
3365
3366 static void
3367 igb_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
3368 {
3369         struct igb_softc *sc = ifp->if_softc;
3370         struct igb_tx_ring *txr = ifsq_get_priv(ifsq);
3371         struct mbuf *m_head;
3372         int idx = -1, nsegs = 0;
3373
3374         KKASSERT(txr->ifsq == ifsq);
3375         ASSERT_SERIALIZED(&txr->tx_serialize);
3376
3377         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
3378                 return;
3379
3380         if (!sc->link_active || (txr->tx_flags & IGB_TXFLAG_ENABLED) == 0) {
3381                 ifsq_purge(ifsq);
3382                 return;
3383         }
3384
3385         if (!IGB_IS_NOT_OACTIVE(txr))
3386                 igb_txeof(txr);
3387
3388         while (!ifsq_is_empty(ifsq)) {
3389                 if (IGB_IS_OACTIVE(txr)) {
3390                         ifsq_set_oactive(ifsq);
3391                         /* Set watchdog on */
3392                         txr->tx_watchdog.wd_timer = 5;
3393                         break;
3394                 }
3395
3396                 m_head = ifsq_dequeue(ifsq, NULL);
3397                 if (m_head == NULL)
3398                         break;
3399
3400                 if (igb_encap(txr, &m_head, &nsegs, &idx)) {
3401                         ifp->if_oerrors++;
3402                         continue;
3403                 }
3404
3405                 if (nsegs >= txr->wreg_nsegs) {
3406                         E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3407                         idx = -1;
3408                         nsegs = 0;
3409                 }
3410
3411                 /* Send a copy of the frame to the BPF listener */
3412                 ETHER_BPF_MTAP(ifp, m_head);
3413         }
3414         if (idx >= 0)
3415                 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3416 }
3417
3418 static void
3419 igb_watchdog(struct ifaltq_subque *ifsq)
3420 {
3421         struct igb_tx_ring *txr = ifsq_get_priv(ifsq);
3422         struct ifnet *ifp = ifsq_get_ifp(ifsq);
3423         struct igb_softc *sc = ifp->if_softc;
3424         int i;
3425
3426         KKASSERT(txr->ifsq == ifsq);
3427         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3428
3429         /*
3430          * If flow control has paused us since last checking
3431          * it invalidates the watchdog timing, so dont run it.
3432          */
3433         if (sc->pause_frames) {
3434                 sc->pause_frames = 0;
3435                 txr->tx_watchdog.wd_timer = 5;
3436                 return;
3437         }
3438
3439         if_printf(ifp, "Watchdog timeout -- resetting\n");
3440         if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3441             E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3442             E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3443         if_printf(ifp, "TX(%d) desc avail = %d, "
3444             "Next TX to Clean = %d\n",
3445             txr->me, txr->tx_avail, txr->next_to_clean);
3446
3447         ifp->if_oerrors++;
3448         sc->watchdog_events++;
3449
3450         igb_init(sc);
3451         for (i = 0; i < sc->tx_ring_inuse; ++i)
3452                 ifsq_devstart_sched(sc->tx_rings[i].ifsq);
3453 }
3454
3455 static void
3456 igb_set_eitr(struct igb_softc *sc, int idx, int rate)
3457 {
3458         uint32_t eitr = 0;
3459
3460         if (rate > 0) {
3461                 if (sc->hw.mac.type == e1000_82575) {
3462                         eitr = 1000000000 / 256 / rate;
3463                         /*
3464                          * NOTE:
3465                          * Document is wrong on the 2 bits left shift
3466                          */
3467                 } else {
3468                         eitr = 1000000 / rate;
3469                         eitr <<= IGB_EITR_INTVL_SHIFT;
3470                 }
3471
3472                 if (eitr == 0) {
3473                         /* Don't disable it */
3474                         eitr = 1 << IGB_EITR_INTVL_SHIFT;
3475                 } else if (eitr > IGB_EITR_INTVL_MASK) {
3476                         /* Don't allow it to be too large */
3477                         eitr = IGB_EITR_INTVL_MASK;
3478                 }
3479         }
3480         if (sc->hw.mac.type == e1000_82575)
3481                 eitr |= eitr << 16;
3482         else
3483                 eitr |= E1000_EITR_CNT_IGNR;
3484         E1000_WRITE_REG(&sc->hw, E1000_EITR(idx), eitr);
3485 }
3486
3487 static int
3488 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3489 {
3490         struct igb_softc *sc = (void *)arg1;
3491         struct ifnet *ifp = &sc->arpcom.ac_if;
3492         int error, intr_rate;
3493
3494         intr_rate = sc->intr_rate;
3495         error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3496         if (error || req->newptr == NULL)
3497                 return error;
3498         if (intr_rate < 0)
3499                 return EINVAL;
3500
3501         ifnet_serialize_all(ifp);
3502
3503         sc->intr_rate = intr_rate;
3504         if (ifp->if_flags & IFF_RUNNING)
3505                 igb_set_eitr(sc, 0, sc->intr_rate);
3506
3507         if (bootverbose)
3508                 if_printf(ifp, "interrupt rate set to %d/sec\n", sc->intr_rate);
3509
3510         ifnet_deserialize_all(ifp);
3511
3512         return 0;
3513 }
3514
3515 static int
3516 igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS)
3517 {
3518         struct igb_msix_data *msix = (void *)arg1;
3519         struct igb_softc *sc = msix->msix_sc;
3520         struct ifnet *ifp = &sc->arpcom.ac_if;
3521         int error, msix_rate;
3522
3523         msix_rate = msix->msix_rate;
3524         error = sysctl_handle_int(oidp, &msix_rate, 0, req);
3525         if (error || req->newptr == NULL)
3526                 return error;
3527         if (msix_rate < 0)
3528                 return EINVAL;
3529
3530         lwkt_serialize_enter(msix->msix_serialize);
3531
3532         msix->msix_rate = msix_rate;
3533         if (ifp->if_flags & IFF_RUNNING)
3534                 igb_set_eitr(sc, msix->msix_vector, msix->msix_rate);
3535
3536         if (bootverbose) {
3537                 if_printf(ifp, "%s set to %d/sec\n", msix->msix_rate_desc,
3538                     msix->msix_rate);
3539         }
3540
3541         lwkt_serialize_exit(msix->msix_serialize);
3542
3543         return 0;
3544 }
3545
3546 static int
3547 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3548 {
3549         struct igb_softc *sc = (void *)arg1;
3550         struct ifnet *ifp = &sc->arpcom.ac_if;
3551         struct igb_tx_ring *txr = &sc->tx_rings[0];
3552         int error, nsegs;
3553
3554         nsegs = txr->intr_nsegs;
3555         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3556         if (error || req->newptr == NULL)
3557                 return error;
3558         if (nsegs <= 0)
3559                 return EINVAL;
3560
3561         ifnet_serialize_all(ifp);
3562
3563         if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
3564             nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3565                 error = EINVAL;
3566         } else {
3567                 int i;
3568
3569                 error = 0;
3570                 for (i = 0; i < sc->tx_ring_cnt; ++i)
3571                         sc->tx_rings[i].intr_nsegs = nsegs;
3572         }
3573
3574         ifnet_deserialize_all(ifp);
3575
3576         return error;
3577 }
3578
3579 static int
3580 igb_sysctl_rx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3581 {
3582         struct igb_softc *sc = (void *)arg1;
3583         struct ifnet *ifp = &sc->arpcom.ac_if;
3584         int error, nsegs, i;
3585
3586         nsegs = sc->rx_rings[0].wreg_nsegs;
3587         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3588         if (error || req->newptr == NULL)
3589                 return error;
3590
3591         ifnet_serialize_all(ifp);
3592         for (i = 0; i < sc->rx_ring_cnt; ++i)
3593                 sc->rx_rings[i].wreg_nsegs =nsegs;
3594         ifnet_deserialize_all(ifp);
3595
3596         return 0;
3597 }
3598
3599 static int
3600 igb_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3601 {
3602         struct igb_softc *sc = (void *)arg1;
3603         struct ifnet *ifp = &sc->arpcom.ac_if;
3604         int error, nsegs, i;
3605
3606         nsegs = sc->tx_rings[0].wreg_nsegs;
3607         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3608         if (error || req->newptr == NULL)
3609                 return error;
3610
3611         ifnet_serialize_all(ifp);
3612         for (i = 0; i < sc->tx_ring_cnt; ++i)
3613                 sc->tx_rings[i].wreg_nsegs =nsegs;
3614         ifnet_deserialize_all(ifp);
3615
3616         return 0;
3617 }
3618
3619 #ifdef IFPOLL_ENABLE
3620
3621 static int
3622 igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3623 {
3624         struct igb_softc *sc = (void *)arg1;
3625         struct ifnet *ifp = &sc->arpcom.ac_if;
3626         int error, off;
3627
3628         off = sc->rx_npoll_off;
3629         error = sysctl_handle_int(oidp, &off, 0, req);
3630         if (error || req->newptr == NULL)
3631                 return error;
3632         if (off < 0)
3633                 return EINVAL;
3634
3635         ifnet_serialize_all(ifp);
3636         if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3637                 error = EINVAL;
3638         } else {
3639                 error = 0;
3640                 sc->rx_npoll_off = off;
3641         }
3642         ifnet_deserialize_all(ifp);
3643
3644         return error;
3645 }
3646
3647 static int
3648 igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3649 {
3650         struct igb_softc *sc = (void *)arg1;
3651         struct ifnet *ifp = &sc->arpcom.ac_if;
3652         int error, off;
3653
3654         off = sc->tx_npoll_off;
3655         error = sysctl_handle_int(oidp, &off, 0, req);
3656         if (error || req->newptr == NULL)
3657                 return error;
3658         if (off < 0)
3659                 return EINVAL;
3660
3661         ifnet_serialize_all(ifp);
3662         if (off >= ncpus2 || off % sc->tx_ring_cnt != 0) {
3663                 error = EINVAL;
3664         } else {
3665                 error = 0;
3666                 sc->tx_npoll_off = off;
3667         }
3668         ifnet_deserialize_all(ifp);
3669
3670         return error;
3671 }
3672
3673 #endif  /* IFPOLL_ENABLE */
3674
3675 static void
3676 igb_init_intr(struct igb_softc *sc)
3677 {
3678         igb_set_intr_mask(sc);
3679
3680         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0)
3681                 igb_init_unshared_intr(sc);
3682
3683         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3684                 igb_set_eitr(sc, 0, sc->intr_rate);
3685         } else {
3686                 int i;
3687
3688                 for (i = 0; i < sc->msix_cnt; ++i)
3689                         igb_set_eitr(sc, i, sc->msix_data[i].msix_rate);
3690         }
3691 }
3692
3693 static void
3694 igb_init_unshared_intr(struct igb_softc *sc)
3695 {
3696         struct e1000_hw *hw = &sc->hw;
3697         const struct igb_rx_ring *rxr;
3698         const struct igb_tx_ring *txr;
3699         uint32_t ivar, index;
3700         int i;
3701
3702         /*
3703          * Enable extended mode
3704          */
3705         if (sc->hw.mac.type != e1000_82575) {
3706                 uint32_t gpie;
3707                 int ivar_max;
3708
3709                 gpie = E1000_GPIE_NSICR;
3710                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3711                         gpie |= E1000_GPIE_MSIX_MODE |
3712                             E1000_GPIE_EIAME |
3713                             E1000_GPIE_PBA;
3714                 }
3715                 E1000_WRITE_REG(hw, E1000_GPIE, gpie);
3716
3717                 /*
3718                  * Clear IVARs
3719                  */
3720                 switch (sc->hw.mac.type) {
3721                 case e1000_82580:
3722                         ivar_max = IGB_MAX_IVAR_82580;
3723                         break;
3724
3725                 case e1000_i350:
3726                         ivar_max = IGB_MAX_IVAR_I350;
3727                         break;
3728
3729                 case e1000_vfadapt:
3730                 case e1000_vfadapt_i350:
3731                         ivar_max = IGB_MAX_IVAR_VF;
3732                         break;
3733
3734                 case e1000_82576:
3735                         ivar_max = IGB_MAX_IVAR_82576;
3736                         break;
3737
3738                 default:
3739                         panic("unknown mac type %d\n", sc->hw.mac.type);
3740                 }
3741                 for (i = 0; i < ivar_max; ++i)
3742                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, 0);
3743                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3744         } else {
3745                 uint32_t tmp;
3746
3747                 KASSERT(sc->intr_type != PCI_INTR_TYPE_MSIX,
3748                     ("82575 w/ MSI-X"));
3749                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3750                 tmp |= E1000_CTRL_EXT_IRCA;
3751                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3752         }
3753
3754         /*
3755          * Map TX/RX interrupts to EICR
3756          */
3757         switch (sc->hw.mac.type) {
3758         case e1000_82580:
3759         case e1000_i350:
3760         case e1000_vfadapt:
3761         case e1000_vfadapt_i350:
3762                 /* RX entries */
3763                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3764                         rxr = &sc->rx_rings[i];
3765
3766                         index = i >> 1;
3767                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3768
3769                         if (i & 1) {
3770                                 ivar &= 0xff00ffff;
3771                                 ivar |=
3772                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3773                         } else {
3774                                 ivar &= 0xffffff00;
3775                                 ivar |=
3776                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3777                         }
3778                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3779                 }
3780                 /* TX entries */
3781                 for (i = 0; i < sc->tx_ring_inuse; ++i) {
3782                         txr = &sc->tx_rings[i];
3783
3784                         index = i >> 1;
3785                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3786
3787                         if (i & 1) {
3788                                 ivar &= 0x00ffffff;
3789                                 ivar |=
3790                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3791                         } else {
3792                                 ivar &= 0xffff00ff;
3793                                 ivar |=
3794                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3795                         }
3796                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3797                 }
3798                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3799                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3800                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3801                 }
3802                 break;
3803
3804         case e1000_82576:
3805                 /* RX entries */
3806                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3807                         rxr = &sc->rx_rings[i];
3808
3809                         index = i & 0x7; /* Each IVAR has two entries */
3810                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3811
3812                         if (i < 8) {
3813                                 ivar &= 0xffffff00;
3814                                 ivar |=
3815                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3816                         } else {
3817                                 ivar &= 0xff00ffff;
3818                                 ivar |=
3819                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3820                         }
3821                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3822                 }
3823                 /* TX entries */
3824                 for (i = 0; i < sc->tx_ring_inuse; ++i) {
3825                         txr = &sc->tx_rings[i];
3826
3827                         index = i & 0x7; /* Each IVAR has two entries */
3828                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3829
3830                         if (i < 8) {
3831                                 ivar &= 0xffff00ff;
3832                                 ivar |=
3833                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3834                         } else {
3835                                 ivar &= 0x00ffffff;
3836                                 ivar |=
3837                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3838                         }
3839                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3840                 }
3841                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3842                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3843                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3844                 }
3845                 break;
3846
3847         case e1000_82575:
3848                 /*
3849                  * Enable necessary interrupt bits.
3850                  *
3851                  * The name of the register is confusing; in addition to
3852                  * configuring the first vector of MSI-X, it also configures
3853                  * which bits of EICR could be set by the hardware even when
3854                  * MSI or line interrupt is used; it thus controls interrupt
3855                  * generation.  It MUST be configured explicitly; the default
3856                  * value mentioned in the datasheet is wrong: RX queue0 and
3857                  * TX queue0 are NOT enabled by default.
3858                  */
3859                 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3860                 break;
3861
3862         default:
3863                 panic("unknown mac type %d\n", sc->hw.mac.type);
3864         }
3865 }
3866
3867 static int
3868 igb_setup_intr(struct igb_softc *sc)
3869 {
3870         int error, i;
3871
3872         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3873                 return igb_msix_setup(sc);
3874
3875         error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
3876             (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_intr_shared : igb_intr,
3877             sc, &sc->intr_tag, &sc->main_serialize);
3878         if (error) {
3879                 device_printf(sc->dev, "Failed to register interrupt handler");
3880                 return error;
3881         }
3882
3883         for (i = 0; i < sc->tx_ring_cnt; ++i)
3884                 sc->tx_rings[i].tx_intr_cpuid = rman_get_cpuid(sc->intr_res);
3885
3886         return 0;
3887 }
3888
3889 static void
3890 igb_set_txintr_mask(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
3891 {
3892         if (txr->sc->hw.mac.type == e1000_82575) {
3893                 txr->tx_intr_bit = 0;   /* unused */
3894                 switch (txr->me) {
3895                 case 0:
3896                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3897                         break;
3898                 case 1:
3899                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3900                         break;
3901                 case 2:
3902                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3903                         break;
3904                 case 3:
3905                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3906                         break;
3907                 default:
3908                         panic("unsupported # of TX ring, %d\n", txr->me);
3909                 }
3910         } else {
3911                 int intr_bit = *intr_bit0;
3912
3913                 txr->tx_intr_bit = intr_bit % intr_bitmax;
3914                 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
3915
3916                 *intr_bit0 = intr_bit + 1;
3917         }
3918 }
3919
3920 static void
3921 igb_set_rxintr_mask(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
3922 {
3923         if (rxr->sc->hw.mac.type == e1000_82575) {
3924                 rxr->rx_intr_bit = 0;   /* unused */
3925                 switch (rxr->me) {
3926                 case 0:
3927                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3928                         break;
3929                 case 1:
3930                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3931                         break;
3932                 case 2:
3933                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3934                         break;
3935                 case 3:
3936                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3937                         break;
3938                 default:
3939                         panic("unsupported # of RX ring, %d\n", rxr->me);
3940                 }
3941         } else {
3942                 int intr_bit = *intr_bit0;
3943
3944                 rxr->rx_intr_bit = intr_bit % intr_bitmax;
3945                 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
3946
3947                 *intr_bit0 = intr_bit + 1;
3948         }
3949 }
3950
3951 static void
3952 igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3953 {
3954         struct igb_softc *sc = ifp->if_softc;
3955
3956         ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt,
3957             sc->tx_serialize, sc->rx_serialize, slz);
3958 }
3959
3960 static void
3961 igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3962 {
3963         struct igb_softc *sc = ifp->if_softc;
3964
3965         ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt,
3966             sc->tx_serialize, sc->rx_serialize, slz);
3967 }
3968
3969 static int
3970 igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3971 {
3972         struct igb_softc *sc = ifp->if_softc;
3973
3974         return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
3975             sc->tx_serialize, sc->rx_serialize, slz);
3976 }
3977
3978 #ifdef INVARIANTS
3979
3980 static void
3981 igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3982     boolean_t serialized)
3983 {
3984         struct igb_softc *sc = ifp->if_softc;
3985
3986         ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
3987             sc->tx_serialize, sc->rx_serialize, slz, serialized);
3988 }
3989
3990 #endif  /* INVARIANTS */
3991
3992 static void
3993 igb_set_intr_mask(struct igb_softc *sc)
3994 {
3995         int i;
3996
3997         sc->intr_mask = sc->sts_intr_mask;
3998         for (i = 0; i < sc->rx_ring_inuse; ++i)
3999                 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
4000         for (i = 0; i < sc->tx_ring_inuse; ++i)
4001                 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
4002         if (bootverbose) {
4003                 if_printf(&sc->arpcom.ac_if, "intr mask 0x%08x\n",
4004                     sc->intr_mask);
4005         }
4006 }
4007
4008 static int
4009 igb_alloc_intr(struct igb_softc *sc)
4010 {
4011         int i, intr_bit, intr_bitmax;
4012         u_int intr_flags;
4013
4014         igb_msix_try_alloc(sc);
4015         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
4016                 goto done;
4017
4018         /*
4019          * Allocate MSI/legacy interrupt resource
4020          */
4021         sc->intr_type = pci_alloc_1intr(sc->dev, igb_msi_enable,
4022             &sc->intr_rid, &intr_flags);
4023
4024         if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
4025                 int unshared;
4026
4027                 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
4028                 if (!unshared) {
4029                         sc->flags |= IGB_FLAG_SHARED_INTR;
4030                         if (bootverbose)
4031                                 device_printf(sc->dev, "IRQ shared\n");
4032                 } else {
4033                         intr_flags &= ~RF_SHAREABLE;
4034                         if (bootverbose)
4035                                 device_printf(sc->dev, "IRQ unshared\n");
4036                 }
4037         }
4038
4039         sc->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
4040             &sc->intr_rid, intr_flags);
4041         if (sc->intr_res == NULL) {
4042                 device_printf(sc->dev, "Unable to allocate bus resource: "
4043                     "interrupt\n");
4044                 return ENXIO;
4045         }
4046
4047         /*
4048          * Setup MSI/legacy interrupt mask
4049          */
4050         switch (sc->hw.mac.type) {
4051         case e1000_82575:
4052                 intr_bitmax = IGB_MAX_TXRXINT_82575;
4053                 break;
4054         case e1000_82580:
4055                 intr_bitmax = IGB_MAX_TXRXINT_82580;
4056                 break;
4057         case e1000_i350:
4058                 intr_bitmax = IGB_MAX_TXRXINT_I350;
4059                 break;
4060         case e1000_82576:
4061                 intr_bitmax = IGB_MAX_TXRXINT_82576;
4062                 break;
4063         default:
4064                 intr_bitmax = IGB_MIN_TXRXINT;
4065                 break;
4066         }
4067         intr_bit = 0;
4068         for (i = 0; i < sc->tx_ring_cnt; ++i)
4069                 igb_set_txintr_mask(&sc->tx_rings[i], &intr_bit, intr_bitmax);
4070         for (i = 0; i < sc->rx_ring_cnt; ++i)
4071                 igb_set_rxintr_mask(&sc->rx_rings[i], &intr_bit, intr_bitmax);
4072         sc->sts_intr_bit = 0;
4073         sc->sts_intr_mask = E1000_EICR_OTHER;
4074
4075         /* Initialize interrupt rate */
4076         sc->intr_rate = IGB_INTR_RATE;
4077 done:
4078         igb_set_ring_inuse(sc, FALSE);
4079         igb_set_intr_mask(sc);
4080         return 0;
4081 }
4082
4083 static void
4084 igb_free_intr(struct igb_softc *sc)
4085 {
4086         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
4087                 if (sc->intr_res != NULL) {
4088                         bus_release_resource(sc->dev, SYS_RES_IRQ, sc->intr_rid,
4089                             sc->intr_res);
4090                 }
4091                 if (sc->intr_type == PCI_INTR_TYPE_MSI)
4092                         pci_release_msi(sc->dev);
4093         } else {
4094                 igb_msix_free(sc, TRUE);
4095         }
4096 }
4097
4098 static void
4099 igb_teardown_intr(struct igb_softc *sc)
4100 {
4101         if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4102                 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_tag);
4103         else
4104                 igb_msix_teardown(sc, sc->msix_cnt);
4105 }
4106
4107 static void
4108 igb_msix_try_alloc(struct igb_softc *sc)
4109 {
4110         int msix_enable, msix_cnt, msix_cnt2, alloc_cnt;
4111         int i, x, error;
4112         struct igb_msix_data *msix;
4113         boolean_t aggregate, setup = FALSE;
4114
4115         /*
4116          * Don't enable MSI-X on 82575, see:
4117          * 82575 specification update errata #25
4118          */
4119         if (sc->hw.mac.type == e1000_82575)
4120                 return;
4121
4122         /* Don't enable MSI-X on VF */
4123         if (sc->vf_ifp)
4124                 return;
4125
4126         msix_enable = device_getenv_int(sc->dev, "msix.enable",
4127             igb_msix_enable);
4128         if (!msix_enable)
4129                 return;
4130
4131         msix_cnt = pci_msix_count(sc->dev);
4132 #ifdef IGB_MSIX_DEBUG
4133         msix_cnt = device_getenv_int(sc->dev, "msix.count", msix_cnt);
4134 #endif
4135         if (msix_cnt <= 1) {
4136                 /* One MSI-X model does not make sense */
4137                 return;
4138         }
4139
4140         i = 0;
4141         while ((1 << (i + 1)) <= msix_cnt)
4142                 ++i;
4143         msix_cnt2 = 1 << i;
4144
4145         if (bootverbose) {
4146                 device_printf(sc->dev, "MSI-X count %d/%d\n",
4147                     msix_cnt2, msix_cnt);
4148         }
4149
4150         KKASSERT(msix_cnt2 <= msix_cnt);
4151         if (msix_cnt == msix_cnt2) {
4152                 /* We need at least one MSI-X for link status */
4153                 msix_cnt2 >>= 1;
4154                 if (msix_cnt2 <= 1) {
4155                         /* One MSI-X for RX/TX does not make sense */
4156                         device_printf(sc->dev, "not enough MSI-X for TX/RX, "
4157                             "MSI-X count %d/%d\n", msix_cnt2, msix_cnt);
4158                         return;
4159                 }
4160                 KKASSERT(msix_cnt > msix_cnt2);
4161
4162                 if (bootverbose) {
4163                         device_printf(sc->dev, "MSI-X count fixup %d/%d\n",
4164                             msix_cnt2, msix_cnt);
4165                 }
4166         }
4167
4168         sc->rx_ring_msix = sc->rx_ring_cnt;
4169         if (sc->rx_ring_msix > msix_cnt2)
4170                 sc->rx_ring_msix = msix_cnt2;
4171
4172         sc->tx_ring_msix = sc->tx_ring_cnt;
4173         if (sc->tx_ring_msix > msix_cnt2)
4174                 sc->tx_ring_msix = msix_cnt2;
4175
4176         if (msix_cnt >= sc->tx_ring_msix + sc->rx_ring_msix + 1) {
4177                 /*
4178                  * Independent TX/RX MSI-X
4179                  */
4180                 aggregate = FALSE;
4181                 if (bootverbose)
4182                         device_printf(sc->dev, "independent TX/RX MSI-X\n");
4183                 alloc_cnt = sc->tx_ring_msix + sc->rx_ring_msix;
4184         } else {
4185                 /*
4186                  * Aggregate TX/RX MSI-X
4187                  */
4188                 aggregate = TRUE;
4189                 if (bootverbose)
4190                         device_printf(sc->dev, "aggregate TX/RX MSI-X\n");
4191                 alloc_cnt = msix_cnt2;
4192                 if (alloc_cnt > ncpus2)
4193                         alloc_cnt = ncpus2;
4194                 if (sc->rx_ring_msix > alloc_cnt)
4195                         sc->rx_ring_msix = alloc_cnt;
4196                 if (sc->tx_ring_msix > alloc_cnt)
4197                         sc->tx_ring_msix = alloc_cnt;
4198         }
4199         ++alloc_cnt;    /* For link status */
4200
4201         if (bootverbose) {
4202                 device_printf(sc->dev, "MSI-X alloc %d, "
4203                     "RX ring %d, TX ring %d\n", alloc_cnt,
4204                     sc->rx_ring_msix, sc->tx_ring_msix);
4205         }
4206
4207         sc->msix_mem_rid = PCIR_BAR(IGB_MSIX_BAR);
4208         sc->msix_mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4209             &sc->msix_mem_rid, RF_ACTIVE);
4210         if (sc->msix_mem_res == NULL) {
4211                 device_printf(sc->dev, "Unable to map MSI-X table\n");
4212                 return;
4213         }
4214
4215         sc->msix_cnt = alloc_cnt;
4216         sc->msix_data = kmalloc_cachealign(
4217             sizeof(struct igb_msix_data) * sc->msix_cnt,
4218             M_DEVBUF, M_WAITOK | M_ZERO);
4219         for (x = 0; x < sc->msix_cnt; ++x) {
4220                 msix = &sc->msix_data[x];
4221
4222                 lwkt_serialize_init(&msix->msix_serialize0);
4223                 msix->msix_sc = sc;
4224                 msix->msix_rid = -1;
4225                 msix->msix_vector = x;
4226                 msix->msix_mask = 1 << msix->msix_vector;
4227                 msix->msix_rate = IGB_INTR_RATE;
4228         }
4229
4230         x = 0;
4231         if (!aggregate) {
4232                 int offset, offset_def;
4233
4234                 /*
4235                  * RX rings
4236                  */
4237                 if (sc->rx_ring_msix == ncpus2) {
4238                         offset = 0;
4239                 } else {
4240                         offset_def = (sc->rx_ring_msix *
4241                             device_get_unit(sc->dev)) % ncpus2;
4242
4243                         offset = device_getenv_int(sc->dev,
4244                             "msix.rxoff", offset_def);
4245                         if (offset >= ncpus2 ||
4246                             offset % sc->rx_ring_msix != 0) {
4247                                 device_printf(sc->dev,
4248                                     "invalid msix.rxoff %d, use %d\n",
4249                                     offset, offset_def);
4250                                 offset = offset_def;
4251                         }
4252                 }
4253
4254                 for (i = 0; i < sc->rx_ring_msix; ++i) {
4255                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
4256
4257                         KKASSERT(x < sc->msix_cnt);
4258                         msix = &sc->msix_data[x++];
4259                         rxr->rx_intr_bit = msix->msix_vector;
4260                         rxr->rx_intr_mask = msix->msix_mask;
4261
4262                         msix->msix_serialize = &rxr->rx_serialize;
4263                         msix->msix_func = igb_msix_rx;
4264                         msix->msix_arg = rxr;
4265                         msix->msix_cpuid = i + offset;
4266                         KKASSERT(msix->msix_cpuid < ncpus2);
4267                         ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
4268                             "%s rx%d", device_get_nameunit(sc->dev), i);
4269                         msix->msix_rate = IGB_MSIX_RX_RATE;
4270                         ksnprintf(msix->msix_rate_desc,
4271                             sizeof(msix->msix_rate_desc),
4272                             "RX%d interrupt rate", i);
4273                 }
4274
4275                 /*
4276                  * TX rings
4277                  */
4278                 if (sc->tx_ring_msix == ncpus2) {
4279                         offset = 0;
4280                 } else {
4281                         offset_def = (sc->tx_ring_msix *
4282                             device_get_unit(sc->dev)) % ncpus2;
4283
4284                         offset = device_getenv_int(sc->dev,
4285                             "msix.txoff", offset_def);
4286                         if (offset >= ncpus2 ||
4287                             offset % sc->tx_ring_msix != 0) {
4288                                 device_printf(sc->dev,
4289                                     "invalid msix.txoff %d, use %d\n",
4290                                     offset, offset_def);
4291                                 offset = offset_def;
4292                         }
4293                 }
4294
4295                 for (i = 0; i < sc->tx_ring_msix; ++i) {
4296                         struct igb_tx_ring *txr = &sc->tx_rings[i];
4297
4298                         KKASSERT(x < sc->msix_cnt);
4299                         msix = &sc->msix_data[x++];
4300                         txr->tx_intr_bit = msix->msix_vector;
4301                         txr->tx_intr_mask = msix->msix_mask;
4302
4303                         msix->msix_serialize = &txr->tx_serialize;
4304                         msix->msix_func = igb_msix_tx;
4305                         msix->msix_arg = txr;
4306                         msix->msix_cpuid = i + offset;
4307                         txr->tx_intr_cpuid = msix->msix_cpuid;
4308                         KKASSERT(msix->msix_cpuid < ncpus2);
4309                         ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
4310                             "%s tx%d", device_get_nameunit(sc->dev), i);
4311                         msix->msix_rate = IGB_MSIX_TX_RATE;
4312                         ksnprintf(msix->msix_rate_desc,
4313                             sizeof(msix->msix_rate_desc),
4314                             "TX%d interrupt rate", i);
4315                 }
4316         } else {
4317                 /* TODO */
4318                 error = EOPNOTSUPP;
4319                 goto back;
4320         }
4321
4322         /*
4323          * Link status
4324          */
4325         KKASSERT(x < sc->msix_cnt);
4326         msix = &sc->msix_data[x++];
4327         sc->sts_intr_bit = msix->msix_vector;
4328         sc->sts_intr_mask = msix->msix_mask;
4329
4330         msix->msix_serialize = &sc->main_serialize;
4331         msix->msix_func = igb_msix_status;
4332         msix->msix_arg = sc;
4333         msix->msix_cpuid = 0;
4334         ksnprintf(msix->msix_desc, sizeof(msix->msix_desc), "%s sts",
4335             device_get_nameunit(sc->dev));
4336         ksnprintf(msix->msix_rate_desc, sizeof(msix->msix_rate_desc),
4337             "status interrupt rate");
4338
4339         KKASSERT(x == sc->msix_cnt);
4340
4341         error = pci_setup_msix(sc->dev);
4342         if (error) {
4343                 device_printf(sc->dev, "Setup MSI-X failed\n");
4344                 goto back;
4345         }
4346         setup = TRUE;
4347
4348         for (i = 0; i < sc->msix_cnt; ++i) {
4349                 msix = &sc->msix_data[i];
4350
4351                 error = pci_alloc_msix_vector(sc->dev, msix->msix_vector,
4352                     &msix->msix_rid, msix->msix_cpuid);
4353                 if (error) {
4354                         device_printf(sc->dev,
4355                             "Unable to allocate MSI-X %d on cpu%d\n",
4356                             msix->msix_vector, msix->msix_cpuid);
4357                         goto back;
4358                 }
4359
4360                 msix->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
4361                     &msix->msix_rid, RF_ACTIVE);
4362                 if (msix->msix_res == NULL) {
4363                         device_printf(sc->dev,
4364                             "Unable to allocate MSI-X %d resource\n",
4365                             msix->msix_vector);
4366                         error = ENOMEM;
4367                         goto back;
4368                 }
4369         }
4370
4371         pci_enable_msix(sc->dev);
4372         sc->intr_type = PCI_INTR_TYPE_MSIX;
4373 back:
4374         if (error)
4375                 igb_msix_free(sc, setup);
4376 }
4377
4378 static void
4379 igb_msix_free(struct igb_softc *sc, boolean_t setup)
4380 {
4381         int i;
4382
4383         KKASSERT(sc->msix_cnt > 1);
4384
4385         for (i = 0; i < sc->msix_cnt; ++i) {
4386                 struct igb_msix_data *msix = &sc->msix_data[i];
4387
4388                 if (msix->msix_res != NULL) {
4389                         bus_release_resource(sc->dev, SYS_RES_IRQ,
4390                             msix->msix_rid, msix->msix_res);
4391                 }
4392                 if (msix->msix_rid >= 0)
4393                         pci_release_msix_vector(sc->dev, msix->msix_rid);
4394         }
4395         if (setup)
4396                 pci_teardown_msix(sc->dev);
4397
4398         sc->msix_cnt = 0;
4399         kfree(sc->msix_data, M_DEVBUF);
4400         sc->msix_data = NULL;
4401 }
4402
4403 static int
4404 igb_msix_setup(struct igb_softc *sc)
4405 {
4406         int i;
4407
4408         for (i = 0; i < sc->msix_cnt; ++i) {
4409                 struct igb_msix_data *msix = &sc->msix_data[i];
4410                 int error;
4411
4412                 error = bus_setup_intr_descr(sc->dev, msix->msix_res,
4413                     INTR_MPSAFE, msix->msix_func, msix->msix_arg,
4414                     &msix->msix_handle, msix->msix_serialize, msix->msix_desc);
4415                 if (error) {
4416                         device_printf(sc->dev, "could not set up %s "
4417                             "interrupt handler.\n", msix->msix_desc);
4418                         igb_msix_teardown(sc, i);
4419                         return error;
4420                 }
4421         }
4422         return 0;
4423 }
4424
4425 static void
4426 igb_msix_teardown(struct igb_softc *sc, int msix_cnt)
4427 {
4428         int i;
4429
4430         for (i = 0; i < msix_cnt; ++i) {
4431                 struct igb_msix_data *msix = &sc->msix_data[i];
4432
4433                 bus_teardown_intr(sc->dev, msix->msix_res, msix->msix_handle);
4434         }
4435 }
4436
4437 static void
4438 igb_msix_rx(void *arg)
4439 {
4440         struct igb_rx_ring *rxr = arg;
4441
4442         ASSERT_SERIALIZED(&rxr->rx_serialize);
4443         igb_rxeof(rxr, -1);
4444
4445         E1000_WRITE_REG(&rxr->sc->hw, E1000_EIMS, rxr->rx_intr_mask);
4446 }
4447
4448 static void
4449 igb_msix_tx(void *arg)
4450 {
4451         struct igb_tx_ring *txr = arg;
4452
4453         ASSERT_SERIALIZED(&txr->tx_serialize);
4454
4455         igb_txeof(txr);
4456         if (!ifsq_is_empty(txr->ifsq))
4457                 ifsq_devstart(txr->ifsq);
4458
4459         E1000_WRITE_REG(&txr->sc->hw, E1000_EIMS, txr->tx_intr_mask);
4460 }
4461
4462 static void
4463 igb_msix_status(void *arg)
4464 {
4465         struct igb_softc *sc = arg;
4466         uint32_t icr;
4467
4468         ASSERT_SERIALIZED(&sc->main_serialize);
4469
4470         icr = E1000_READ_REG(&sc->hw, E1000_ICR);
4471         if (icr & E1000_ICR_LSC) {
4472                 sc->hw.mac.get_link_status = 1;
4473                 igb_update_link_status(sc);
4474         }
4475
4476         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->sts_intr_mask);
4477 }
4478
4479 static void
4480 igb_set_ring_inuse(struct igb_softc *sc, boolean_t polling)
4481 {
4482         sc->rx_ring_inuse = igb_get_rxring_inuse(sc, polling);
4483         sc->tx_ring_inuse = igb_get_txring_inuse(sc, polling);
4484         if (bootverbose) {
4485                 if_printf(&sc->arpcom.ac_if, "RX rings %d/%d, TX rings %d/%d\n",
4486                     sc->rx_ring_inuse, sc->rx_ring_cnt,
4487                     sc->tx_ring_inuse, sc->tx_ring_cnt);
4488         }
4489 }
4490
4491 static int
4492 igb_get_rxring_inuse(const struct igb_softc *sc, boolean_t polling)
4493 {
4494         if (!IGB_ENABLE_HWRSS(sc))
4495                 return 1;
4496
4497         if (polling)
4498                 return sc->rx_ring_cnt;
4499         else if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4500                 return IGB_MIN_RING_RSS;
4501         else
4502                 return sc->rx_ring_msix;
4503 }
4504
4505 static int
4506 igb_get_txring_inuse(const struct igb_softc *sc, boolean_t polling)
4507 {
4508         if (!IGB_ENABLE_HWTSS(sc))
4509                 return 1;
4510
4511         if (polling)
4512                 return sc->tx_ring_cnt;
4513         else if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4514                 return IGB_MIN_RING;
4515         else
4516                 return sc->tx_ring_msix;
4517 }
4518
4519 static int
4520 igb_tso_pullup(struct igb_tx_ring *txr, struct mbuf **mp)
4521 {
4522         int hoff, iphlen, thoff;
4523         struct mbuf *m;
4524
4525         m = *mp;
4526         KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4527
4528         iphlen = m->m_pkthdr.csum_iphlen;
4529         thoff = m->m_pkthdr.csum_thlen;
4530         hoff = m->m_pkthdr.csum_lhlen;
4531
4532         KASSERT(iphlen > 0, ("invalid ip hlen"));
4533         KASSERT(thoff > 0, ("invalid tcp hlen"));
4534         KASSERT(hoff > 0, ("invalid ether hlen"));
4535
4536         if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
4537                 m = m_pullup(m, hoff + iphlen + thoff);
4538                 if (m == NULL) {
4539                         *mp = NULL;
4540                         return ENOBUFS;
4541                 }
4542                 *mp = m;
4543         }
4544         if (txr->tx_flags & IGB_TXFLAG_TSO_IPLEN0) {
4545                 struct ip *ip;
4546
4547                 ip = mtodoff(m, struct ip *, hoff);
4548                 ip->ip_len = 0;
4549         }
4550
4551         return 0;
4552 }
4553
4554 static void
4555 igb_tso_ctx(struct igb_tx_ring *txr, struct mbuf *m, uint32_t *hlen)
4556 {
4557         struct e1000_adv_tx_context_desc *TXD;
4558         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
4559         int hoff, ctxd, iphlen, thoff;
4560
4561         iphlen = m->m_pkthdr.csum_iphlen;
4562         thoff = m->m_pkthdr.csum_thlen;
4563         hoff = m->m_pkthdr.csum_lhlen;
4564
4565         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
4566
4567         ctxd = txr->next_avail_desc;
4568         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
4569
4570         if (m->m_flags & M_VLANTAG) {
4571                 uint16_t vlantag;
4572
4573                 vlantag = htole16(m->m_pkthdr.ether_vlantag);
4574                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
4575         }
4576
4577         vlan_macip_lens |= (hoff << E1000_ADVTXD_MACLEN_SHIFT);
4578         vlan_macip_lens |= iphlen;
4579
4580         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4581         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
4582         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
4583
4584         mss_l4len_idx |= (m->m_pkthdr.tso_segsz << E1000_ADVTXD_MSS_SHIFT);
4585         mss_l4len_idx |= (thoff << E1000_ADVTXD_L4LEN_SHIFT);
4586         /* 82575 needs the queue index added */
4587         if (txr->sc->hw.mac.type == e1000_82575)
4588                 mss_l4len_idx |= txr->me << 4;
4589
4590         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
4591         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
4592         TXD->seqnum_seed = htole32(0);
4593         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
4594
4595         /* We've consumed the first desc, adjust counters */
4596         if (++ctxd == txr->num_tx_desc)
4597                 ctxd = 0;
4598         txr->next_avail_desc = ctxd;
4599         --txr->tx_avail;
4600
4601         *hlen = hoff + iphlen + thoff;
4602 }
4603
4604 static void
4605 igb_setup_serializer(struct igb_softc *sc)
4606 {
4607         const struct igb_msix_data *msix;
4608         int i, j;
4609
4610         /*
4611          * Allocate serializer array
4612          */
4613
4614         /* Main + TX + RX */
4615         sc->serialize_cnt = 1 + sc->tx_ring_cnt + sc->rx_ring_cnt;
4616
4617         /* Aggregate TX/RX MSI-X */
4618         for (i = 0; i < sc->msix_cnt; ++i) {
4619                 msix = &sc->msix_data[i];
4620                 if (msix->msix_serialize == &msix->msix_serialize0)
4621                         sc->serialize_cnt++;
4622         }
4623
4624         sc->serializes =
4625             kmalloc(sc->serialize_cnt * sizeof(struct lwkt_serialize *),
4626                 M_DEVBUF, M_WAITOK | M_ZERO);
4627
4628         /*
4629          * Setup serializers
4630          *
4631          * NOTE: Order is critical
4632          */
4633
4634         i = 0;
4635         KKASSERT(i < sc->serialize_cnt);
4636         sc->serializes[i++] = &sc->main_serialize;
4637
4638         for (j = 0; j < sc->msix_cnt; ++j) {
4639                 msix = &sc->msix_data[j];
4640                 if (msix->msix_serialize == &msix->msix_serialize0) {
4641                         KKASSERT(i < sc->serialize_cnt);
4642                         sc->serializes[i++] = msix->msix_serialize;
4643                 }
4644         }
4645
4646         sc->tx_serialize = i;
4647         for (j = 0; j < sc->tx_ring_cnt; ++j) {
4648                 KKASSERT(i < sc->serialize_cnt);
4649                 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
4650         }
4651
4652         sc->rx_serialize = i;
4653         for (j = 0; j < sc->rx_ring_cnt; ++j) {
4654                 KKASSERT(i < sc->serialize_cnt);
4655                 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
4656         }
4657
4658         KKASSERT(i == sc->serialize_cnt);
4659 }