sys/dev/netif/bge/if_bge.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  */
  35
  36 /*
  37  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  38  *
  39  * Written by Bill Paul <wpaul@windriver.com>
  40  * Senior Engineer, Wind River Systems
  41  */
  42
  43 /*
  44  * The Broadcom BCM5700 is based on technology originally developed by
  45  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  46  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  47  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  48  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  49  * frames, highly configurable RX filtering, and 16 RX and TX queues
  50  * (which, along with RX filter rules, can be used for QOS applications).
  51  * Other features, such as TCP segmentation, may be available as part
  52  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  53  * firmware images can be stored in hardware and need not be compiled
  54  * into the driver.
  55  *
  56  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  57  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  58  *
  59  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  60  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  61  * does not support external SSRAM.
  62  *
  63  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  64  * brand name, which is functionally similar but lacks PCI-X support.
  65  *
  66  * Without external SSRAM, you can only have at most 4 TX rings,
  67  * and the use of the mini RX ring is disabled. This seems to imply
  68  * that these features are simply not available on the BCM5701. As a
  69  * result, this driver does not implement any support for the mini RX
  70  * ring.
  71  */
  72
  73 #include "opt_polling.h"
  74
  75 #include <sys/param.h>
  76 #include <sys/bus.h>
  77 #include <sys/endian.h>
  78 #include <sys/kernel.h>
  79 #include <sys/ktr.h>
  80 #include <sys/interrupt.h>
  81 #include <sys/mbuf.h>
  82 #include <sys/malloc.h>
  83 #include <sys/queue.h>
  84 #include <sys/rman.h>
  85 #include <sys/serialize.h>
  86 #include <sys/socket.h>
  87 #include <sys/sockio.h>
  88 #include <sys/sysctl.h>
  89
  90 #include <net/bpf.h>
  91 #include <net/ethernet.h>
  92 #include <net/if.h>
  93 #include <net/if_arp.h>
  94 #include <net/if_dl.h>
  95 #include <net/if_media.h>
  96 #include <net/if_types.h>
  97 #include <net/ifq_var.h>
  98 #include <net/vlan/if_vlan_var.h>
  99 #include <net/vlan/if_vlan_ether.h>
 100
 101 #include <dev/netif/mii_layer/mii.h>
 102 #include <dev/netif/mii_layer/miivar.h>
 103 #include <dev/netif/mii_layer/brgphyreg.h>
 104
 105 #include <bus/pci/pcidevs.h>
 106 #include <bus/pci/pcireg.h>
 107 #include <bus/pci/pcivar.h>
 108
 109 #include <dev/netif/bge/if_bgereg.h>
 110
 111 /* "device miibus" required.  See GENERIC if you get errors here. */
 112 #include "miibus_if.h"
 113
 114 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP)
 115 #define BGE_MIN_FRAME           60
 116
 117 static const struct bge_type bge_devs[] = {
 118         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
 119                 "3COM 3C996 Gigabit Ethernet" },
 120
 121         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 122                 "Alteon BCM5700 Gigabit Ethernet" },
 123         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
 124                 "Alteon BCM5701 Gigabit Ethernet" },
 125
 126         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
 127                 "Altima AC1000 Gigabit Ethernet" },
 128         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
 129                 "Altima AC1002 Gigabit Ethernet" },
 130         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
 131                 "Altima AC9100 Gigabit Ethernet" },
 132
 133         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
 134                 "Apple BCM5701 Gigabit Ethernet" },
 135
 136         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
 137                 "Broadcom BCM5700 Gigabit Ethernet" },
 138         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
 139                 "Broadcom BCM5701 Gigabit Ethernet" },
 140         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
 141                 "Broadcom BCM5702 Gigabit Ethernet" },
 142         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
 143                 "Broadcom BCM5702X Gigabit Ethernet" },
 144         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
 145                 "Broadcom BCM5702 Gigabit Ethernet" },
 146         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
 147                 "Broadcom BCM5703 Gigabit Ethernet" },
 148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
 149                 "Broadcom BCM5703X Gigabit Ethernet" },
 150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
 151                 "Broadcom BCM5703 Gigabit Ethernet" },
 152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
 153                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
 154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
 155                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
 157                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
 159                 "Broadcom BCM5705 Gigabit Ethernet" },
 160         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
 161                 "Broadcom BCM5705F Gigabit Ethernet" },
 162         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
 163                 "Broadcom BCM5705K Gigabit Ethernet" },
 164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
 165                 "Broadcom BCM5705M Gigabit Ethernet" },
 166         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
 167                 "Broadcom BCM5705M Gigabit Ethernet" },
 168         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
 169                 "Broadcom BCM5714C Gigabit Ethernet" },
 170         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
 171                 "Broadcom BCM5714S Gigabit Ethernet" },
 172         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
 173                 "Broadcom BCM5715 Gigabit Ethernet" },
 174         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
 175                 "Broadcom BCM5715S Gigabit Ethernet" },
 176         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
 177                 "Broadcom BCM5720 Gigabit Ethernet" },
 178         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
 179                 "Broadcom BCM5721 Gigabit Ethernet" },
 180         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
 181                 "Broadcom BCM5722 Gigabit Ethernet" },
 182         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723,
 183                 "Broadcom BCM5723 Gigabit Ethernet" },
 184         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
 185                 "Broadcom BCM5750 Gigabit Ethernet" },
 186         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
 187                 "Broadcom BCM5750M Gigabit Ethernet" },
 188         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
 189                 "Broadcom BCM5751 Gigabit Ethernet" },
 190         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
 191                 "Broadcom BCM5751F Gigabit Ethernet" },
 192         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
 193                 "Broadcom BCM5751M Gigabit Ethernet" },
 194         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
 195                 "Broadcom BCM5752 Gigabit Ethernet" },
 196         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
 197                 "Broadcom BCM5752M Gigabit Ethernet" },
 198         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
 199                 "Broadcom BCM5753 Gigabit Ethernet" },
 200         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
 201                 "Broadcom BCM5753F Gigabit Ethernet" },
 202         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
 203                 "Broadcom BCM5753M Gigabit Ethernet" },
 204         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
 205                 "Broadcom BCM5754 Gigabit Ethernet" },
 206         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
 207                 "Broadcom BCM5754M Gigabit Ethernet" },
 208         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
 209                 "Broadcom BCM5755 Gigabit Ethernet" },
 210         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
 211                 "Broadcom BCM5755M Gigabit Ethernet" },
 212         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
 213                 "Broadcom BCM5756 Gigabit Ethernet" },
 214         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761,
 215                 "Broadcom BCM5761 Gigabit Ethernet" },
 216         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E,
 217                 "Broadcom BCM5761E Gigabit Ethernet" },
 218         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S,
 219                 "Broadcom BCM5761S Gigabit Ethernet" },
 220         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE,
 221                 "Broadcom BCM5761SE Gigabit Ethernet" },
 222         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764,
 223                 "Broadcom BCM5764 Gigabit Ethernet" },
 224         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
 225                 "Broadcom BCM5780 Gigabit Ethernet" },
 226         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
 227                 "Broadcom BCM5780S Gigabit Ethernet" },
 228         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
 229                 "Broadcom BCM5781 Gigabit Ethernet" },
 230         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
 231                 "Broadcom BCM5782 Gigabit Ethernet" },
 232         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784,
 233                 "Broadcom BCM5784 Gigabit Ethernet" },
 234         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F,
 235                 "Broadcom BCM5785F Gigabit Ethernet" },
 236         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G,
 237                 "Broadcom BCM5785G Gigabit Ethernet" },
 238         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
 239                 "Broadcom BCM5786 Gigabit Ethernet" },
 240         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
 241                 "Broadcom BCM5787 Gigabit Ethernet" },
 242         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
 243                 "Broadcom BCM5787F Gigabit Ethernet" },
 244         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
 245                 "Broadcom BCM5787M Gigabit Ethernet" },
 246         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
 247                 "Broadcom BCM5788 Gigabit Ethernet" },
 248         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
 249                 "Broadcom BCM5789 Gigabit Ethernet" },
 250         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
 251                 "Broadcom BCM5901 Fast Ethernet" },
 252         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
 253                 "Broadcom BCM5901A2 Fast Ethernet" },
 254         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
 255                 "Broadcom BCM5903M Fast Ethernet" },
 256         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
 257                 "Broadcom BCM5906 Fast Ethernet"},
 258         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
 259                 "Broadcom BCM5906M Fast Ethernet"},
 260         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760,
 261                 "Broadcom BCM57760 Gigabit Ethernet"},
 262         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780,
 263                 "Broadcom BCM57780 Gigabit Ethernet"},
 264         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788,
 265                 "Broadcom BCM57788 Gigabit Ethernet"},
 266         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790,
 267                 "Broadcom BCM57790 Gigabit Ethernet"},
 268         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
 269                 "SysKonnect Gigabit Ethernet" },
 270
 271         { 0, 0, NULL }
 272 };
 273
 274 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 275 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 276 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 277 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 278 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 279 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
 280 #define BGE_IS_5788(sc)                 ((sc)->bge_flags & BGE_FLAG_5788)
 281
 282 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 283
 284 static int      bge_probe(device_t);
 285 static int      bge_attach(device_t);
 286 static int      bge_detach(device_t);
 287 static void     bge_txeof(struct bge_softc *);
 288 static void     bge_rxeof(struct bge_softc *);
 289
 290 static void     bge_tick(void *);
 291 static void     bge_stats_update(struct bge_softc *);
 292 static void     bge_stats_update_regs(struct bge_softc *);
 293 static int      bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 294
 295 #ifdef DEVICE_POLLING
 296 static void     bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 297 #endif
 298 static void     bge_intr(void *);
 299 static void     bge_enable_intr(struct bge_softc *);
 300 static void     bge_disable_intr(struct bge_softc *);
 301 static void     bge_start(struct ifnet *);
 302 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 303 static void     bge_init(void *);
 304 static void     bge_stop(struct bge_softc *);
 305 static void     bge_watchdog(struct ifnet *);
 306 static void     bge_shutdown(device_t);
 307 static int      bge_suspend(device_t);
 308 static int      bge_resume(device_t);
 309 static int      bge_ifmedia_upd(struct ifnet *);
 310 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 311
 312 static uint8_t  bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 313 static int      bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 314
 315 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
 316 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
 317
 318 static void     bge_setmulti(struct bge_softc *);
 319 static void     bge_setpromisc(struct bge_softc *);
 320
 321 static int      bge_alloc_jumbo_mem(struct bge_softc *);
 322 static void     bge_free_jumbo_mem(struct bge_softc *);
 323 static struct bge_jslot
 324                 *bge_jalloc(struct bge_softc *);
 325 static void     bge_jfree(void *);
 326 static void     bge_jref(void *);
 327 static int      bge_newbuf_std(struct bge_softc *, int, int);
 328 static int      bge_newbuf_jumbo(struct bge_softc *, int, int);
 329 static void     bge_setup_rxdesc_std(struct bge_softc *, int);
 330 static void     bge_setup_rxdesc_jumbo(struct bge_softc *, int);
 331 static int      bge_init_rx_ring_std(struct bge_softc *);
 332 static void     bge_free_rx_ring_std(struct bge_softc *);
 333 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
 334 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
 335 static void     bge_free_tx_ring(struct bge_softc *);
 336 static int      bge_init_tx_ring(struct bge_softc *);
 337
 338 static int      bge_chipinit(struct bge_softc *);
 339 static int      bge_blockinit(struct bge_softc *);
 340
 341 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
 342 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
 343 #ifdef notdef
 344 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
 345 #endif
 346 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
 347 static void     bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
 348 static void     bge_writembx(struct bge_softc *, int, int);
 349
 350 static int      bge_miibus_readreg(device_t, int, int);
 351 static int      bge_miibus_writereg(device_t, int, int, int);
 352 static void     bge_miibus_statchg(device_t);
 353 static void     bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
 354 static void     bge_tbi_link_upd(struct bge_softc *, uint32_t);
 355 static void     bge_copper_link_upd(struct bge_softc *, uint32_t);
 356 static void     bge_autopoll_link_upd(struct bge_softc *, uint32_t);
 357
 358 static void     bge_reset(struct bge_softc *);
 359
 360 static int      bge_dma_alloc(struct bge_softc *);
 361 static void     bge_dma_free(struct bge_softc *);
 362 static int      bge_dma_block_alloc(struct bge_softc *, bus_size_t,
 363                                     bus_dma_tag_t *, bus_dmamap_t *,
 364                                     void **, bus_addr_t *);
 365 static void     bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 366
 367 static int      bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 368 static int      bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 369 static int      bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 370 static int      bge_get_eaddr(struct bge_softc *, uint8_t[]);
 371
 372 static void     bge_coal_change(struct bge_softc *);
 373 static int      bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 374 static int      bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 375 static int      bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 376 static int      bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 377 static int      bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
 378
 379 /*
 380  * Set following tunable to 1 for some IBM blade servers with the DNLK
 381  * switch module. Auto negotiation is broken for those configurations.
 382  */
 383 static int      bge_fake_autoneg = 0;
 384 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
 385
 386 /* Interrupt moderation control variables. */
 387 static int      bge_rx_coal_ticks = 100;        /* usec */
 388 static int      bge_tx_coal_ticks = 1023;       /* usec */
 389 static int      bge_rx_max_coal_bds = 80;
 390 static int      bge_tx_max_coal_bds = 128;
 391
 392 TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
 393 TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
 394 TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
 395 TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
 396
 397 #if !defined(KTR_IF_BGE)
 398 #define KTR_IF_BGE      KTR_ALL
 399 #endif
 400 KTR_INFO_MASTER(if_bge);
 401 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr");
 402 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt");
 403 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt");
 404 #define logif(name)     KTR_LOG(if_bge_ ## name)
 405
 406 static device_method_t bge_methods[] = {
 407         /* Device interface */
 408         DEVMETHOD(device_probe,         bge_probe),
 409         DEVMETHOD(device_attach,        bge_attach),
 410         DEVMETHOD(device_detach,        bge_detach),
 411         DEVMETHOD(device_shutdown,      bge_shutdown),
 412         DEVMETHOD(device_suspend,       bge_suspend),
 413         DEVMETHOD(device_resume,        bge_resume),
 414
 415         /* bus interface */
 416         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 417         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 418
 419         /* MII interface */
 420         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 421         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 422         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 423
 424         { 0, 0 }
 425 };
 426
 427 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
 428 static devclass_t bge_devclass;
 429
 430 DECLARE_DUMMY_MODULE(if_bge);
 431 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL);
 432 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL);
 433
 434 static uint32_t
 435 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
 436 {
 437         device_t dev = sc->bge_dev;
 438         uint32_t val;
 439
 440         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 441             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 442                 return 0;
 443
 444         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 445         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 446         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 447         return (val);
 448 }
 449
 450 static void
 451 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 452 {
 453         device_t dev = sc->bge_dev;
 454
 455         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 456             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 457                 return;
 458
 459         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 460         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 461         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 462 }
 463
 464 #ifdef notdef
 465 static uint32_t
 466 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
 467 {
 468         device_t dev = sc->bge_dev;
 469
 470         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 471         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 472 }
 473 #endif
 474
 475 static void
 476 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 477 {
 478         device_t dev = sc->bge_dev;
 479
 480         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 481         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 482 }
 483
 484 static void
 485 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
 486 {
 487         CSR_WRITE_4(sc, off, val);
 488 }
 489
 490 static void
 491 bge_writembx(struct bge_softc *sc, int off, int val)
 492 {
 493         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 494                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 495
 496         CSR_WRITE_4(sc, off, val);
 497 }
 498
 499 static uint8_t
 500 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 501 {
 502         uint32_t access, byte = 0;
 503         int i;
 504
 505         /* Lock. */
 506         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 507         for (i = 0; i < 8000; i++) {
 508                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 509                         break;
 510                 DELAY(20);
 511         }
 512         if (i == 8000)
 513                 return (1);
 514
 515         /* Enable access. */
 516         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 517         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 518
 519         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 520         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 521         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 522                 DELAY(10);
 523                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 524                         DELAY(10);
 525                         break;
 526                 }
 527         }
 528
 529         if (i == BGE_TIMEOUT * 10) {
 530                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
 531                 return (1);
 532         }
 533
 534         /* Get result. */
 535         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 536
 537         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 538
 539         /* Disable access. */
 540         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 541
 542         /* Unlock. */
 543         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 544         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 545
 546         return (0);
 547 }
 548
 549 /*
 550  * Read a sequence of bytes from NVRAM.
 551  */
 552 static int
 553 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 554 {
 555         int err = 0, i;
 556         uint8_t byte = 0;
 557
 558         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 559                 return (1);
 560
 561         for (i = 0; i < cnt; i++) {
 562                 err = bge_nvram_getbyte(sc, off + i, &byte);
 563                 if (err)
 564                         break;
 565                 *(dest + i) = byte;
 566         }
 567
 568         return (err ? 1 : 0);
 569 }
 570
 571 /*
 572  * Read a byte of data stored in the EEPROM at address 'addr.' The
 573  * BCM570x supports both the traditional bitbang interface and an
 574  * auto access interface for reading the EEPROM. We use the auto
 575  * access method.
 576  */
 577 static uint8_t
 578 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
 579 {
 580         int i;
 581         uint32_t byte = 0;
 582
 583         /*
 584          * Enable use of auto EEPROM access so we can avoid
 585          * having to use the bitbang method.
 586          */
 587         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 588
 589         /* Reset the EEPROM, load the clock period. */
 590         CSR_WRITE_4(sc, BGE_EE_ADDR,
 591             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 592         DELAY(20);
 593
 594         /* Issue the read EEPROM command. */
 595         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 596
 597         /* Wait for completion */
 598         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 599                 DELAY(10);
 600                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 601                         break;
 602         }
 603
 604         if (i == BGE_TIMEOUT) {
 605                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 606                 return(1);
 607         }
 608
 609         /* Get result. */
 610         byte = CSR_READ_4(sc, BGE_EE_DATA);
 611
 612         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 613
 614         return(0);
 615 }
 616
 617 /*
 618  * Read a sequence of bytes from the EEPROM.
 619  */
 620 static int
 621 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
 622 {
 623         size_t i;
 624         int err;
 625         uint8_t byte;
 626
 627         for (byte = 0, err = 0, i = 0; i < len; i++) {
 628                 err = bge_eeprom_getbyte(sc, off + i, &byte);
 629                 if (err)
 630                         break;
 631                 *(dest + i) = byte;
 632         }
 633
 634         return(err ? 1 : 0);
 635 }
 636
 637 static int
 638 bge_miibus_readreg(device_t dev, int phy, int reg)
 639 {
 640         struct bge_softc *sc = device_get_softc(dev);
 641         uint32_t val;
 642         int i;
 643
 644         KASSERT(phy == sc->bge_phyno,
 645             ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
 646
 647         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 648         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
 649                 CSR_WRITE_4(sc, BGE_MI_MODE,
 650                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 651                 DELAY(80);
 652         }
 653
 654         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 655             BGE_MIPHY(phy) | BGE_MIREG(reg));
 656
 657         /* Poll for the PHY register access to complete. */
 658         for (i = 0; i < BGE_TIMEOUT; i++) {
 659                 DELAY(10);
 660                 val = CSR_READ_4(sc, BGE_MI_COMM);
 661                 if ((val & BGE_MICOMM_BUSY) == 0) {
 662                         DELAY(5);
 663                         val = CSR_READ_4(sc, BGE_MI_COMM);
 664                         break;
 665                 }
 666         }
 667         if (i == BGE_TIMEOUT) {
 668                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
 669                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
 670                 val = 0;
 671         }
 672
 673         /* Restore the autopoll bit if necessary. */
 674         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
 675                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
 676                 DELAY(80);
 677         }
 678
 679         if (val & BGE_MICOMM_READFAIL)
 680                 return 0;
 681
 682         return (val & 0xFFFF);
 683 }
 684
 685 static int
 686 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 687 {
 688         struct bge_softc *sc = device_get_softc(dev);
 689         int i;
 690
 691         KASSERT(phy == sc->bge_phyno,
 692             ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
 693
 694         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 695             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 696                return 0;
 697
 698         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 699         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
 700                 CSR_WRITE_4(sc, BGE_MI_MODE,
 701                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 702                 DELAY(80);
 703         }
 704
 705         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 706             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 707
 708         for (i = 0; i < BGE_TIMEOUT; i++) {
 709                 DELAY(10);
 710                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 711                         DELAY(5);
 712                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 713                         break;
 714                 }
 715         }
 716         if (i == BGE_TIMEOUT) {
 717                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
 718                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
 719         }
 720
 721         /* Restore the autopoll bit if necessary. */
 722         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
 723                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
 724                 DELAY(80);
 725         }
 726
 727         return 0;
 728 }
 729
 730 static void
 731 bge_miibus_statchg(device_t dev)
 732 {
 733         struct bge_softc *sc;
 734         struct mii_data *mii;
 735
 736         sc = device_get_softc(dev);
 737         mii = device_get_softc(sc->bge_miibus);
 738
 739         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 740             (IFM_ACTIVE | IFM_AVALID)) {
 741                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 742                 case IFM_10_T:
 743                 case IFM_100_TX:
 744                         sc->bge_link = 1;
 745                         break;
 746                 case IFM_1000_T:
 747                 case IFM_1000_SX:
 748                 case IFM_2500_SX:
 749                         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 750                                 sc->bge_link = 1;
 751                         else
 752                                 sc->bge_link = 0;
 753                         break;
 754                 default:
 755                         sc->bge_link = 0;
 756                         break;
 757                 }
 758         } else {
 759                 sc->bge_link = 0;
 760         }
 761         if (sc->bge_link == 0)
 762                 return;
 763
 764         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 765         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 766             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
 767                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 768         } else {
 769                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 770         }
 771
 772         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 773                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 774         } else {
 775                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 776         }
 777 }
 778
 779 /*
 780  * Memory management for jumbo frames.
 781  */
 782 static int
 783 bge_alloc_jumbo_mem(struct bge_softc *sc)
 784 {
 785         struct ifnet *ifp = &sc->arpcom.ac_if;
 786         struct bge_jslot *entry;
 787         uint8_t *ptr;
 788         bus_addr_t paddr;
 789         int i, error;
 790
 791         /*
 792          * Create tag for jumbo mbufs.
 793          * This is really a bit of a kludge. We allocate a special
 794          * jumbo buffer pool which (thanks to the way our DMA
 795          * memory allocation works) will consist of contiguous
 796          * pages. This means that even though a jumbo buffer might
 797          * be larger than a page size, we don't really need to
 798          * map it into more than one DMA segment. However, the
 799          * default mbuf tag will result in multi-segment mappings,
 800          * so we have to create a special jumbo mbuf tag that
 801          * lets us get away with mapping the jumbo buffers as
 802          * a single segment. I think eventually the driver should
 803          * be changed so that it uses ordinary mbufs and cluster
 804          * buffers, i.e. jumbo frames can span multiple DMA
 805          * descriptors. But that's a project for another day.
 806          */
 807
 808         /*
 809          * Create DMA stuffs for jumbo RX ring.
 810          */
 811         error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 812                                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
 813                                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
 814                                     (void *)&sc->bge_ldata.bge_rx_jumbo_ring,
 815                                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
 816         if (error) {
 817                 if_printf(ifp, "could not create jumbo RX ring\n");
 818                 return error;
 819         }
 820
 821         /*
 822          * Create DMA stuffs for jumbo buffer block.
 823          */
 824         error = bge_dma_block_alloc(sc, BGE_JMEM,
 825                                     &sc->bge_cdata.bge_jumbo_tag,
 826                                     &sc->bge_cdata.bge_jumbo_map,
 827                                     (void **)&sc->bge_ldata.bge_jumbo_buf,
 828                                     &paddr);
 829         if (error) {
 830                 if_printf(ifp, "could not create jumbo buffer\n");
 831                 return error;
 832         }
 833
 834         SLIST_INIT(&sc->bge_jfree_listhead);
 835
 836         /*
 837          * Now divide it up into 9K pieces and save the addresses
 838          * in an array. Note that we play an evil trick here by using
 839          * the first few bytes in the buffer to hold the the address
 840          * of the softc structure for this interface. This is because
 841          * bge_jfree() needs it, but it is called by the mbuf management
 842          * code which will not pass it to us explicitly.
 843          */
 844         for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
 845                 entry = &sc->bge_cdata.bge_jslots[i];
 846                 entry->bge_sc = sc;
 847                 entry->bge_buf = ptr;
 848                 entry->bge_paddr = paddr;
 849                 entry->bge_inuse = 0;
 850                 entry->bge_slot = i;
 851                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 852
 853                 ptr += BGE_JLEN;
 854                 paddr += BGE_JLEN;
 855         }
 856         return 0;
 857 }
 858
 859 static void
 860 bge_free_jumbo_mem(struct bge_softc *sc)
 861 {
 862         /* Destroy jumbo RX ring. */
 863         bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 864                            sc->bge_cdata.bge_rx_jumbo_ring_map,
 865                            sc->bge_ldata.bge_rx_jumbo_ring);
 866
 867         /* Destroy jumbo buffer block. */
 868         bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
 869                            sc->bge_cdata.bge_jumbo_map,
 870                            sc->bge_ldata.bge_jumbo_buf);
 871 }
 872
 873 /*
 874  * Allocate a jumbo buffer.
 875  */
 876 static struct bge_jslot *
 877 bge_jalloc(struct bge_softc *sc)
 878 {
 879         struct bge_jslot *entry;
 880
 881         lwkt_serialize_enter(&sc->bge_jslot_serializer);
 882         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
 883         if (entry) {
 884                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
 885                 entry->bge_inuse = 1;
 886         } else {
 887                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 888         }
 889         lwkt_serialize_exit(&sc->bge_jslot_serializer);
 890         return(entry);
 891 }
 892
 893 /*
 894  * Adjust usage count on a jumbo buffer.
 895  */
 896 static void
 897 bge_jref(void *arg)
 898 {
 899         struct bge_jslot *entry = (struct bge_jslot *)arg;
 900         struct bge_softc *sc = entry->bge_sc;
 901
 902         if (sc == NULL)
 903                 panic("bge_jref: can't find softc pointer!");
 904
 905         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 906                 panic("bge_jref: asked to reference buffer "
 907                     "that we don't manage!");
 908         } else if (entry->bge_inuse == 0) {
 909                 panic("bge_jref: buffer already free!");
 910         } else {
 911                 atomic_add_int(&entry->bge_inuse, 1);
 912         }
 913 }
 914
 915 /*
 916  * Release a jumbo buffer.
 917  */
 918 static void
 919 bge_jfree(void *arg)
 920 {
 921         struct bge_jslot *entry = (struct bge_jslot *)arg;
 922         struct bge_softc *sc = entry->bge_sc;
 923
 924         if (sc == NULL)
 925                 panic("bge_jfree: can't find softc pointer!");
 926
 927         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 928                 panic("bge_jfree: asked to free buffer that we don't manage!");
 929         } else if (entry->bge_inuse == 0) {
 930                 panic("bge_jfree: buffer already free!");
 931         } else {
 932                 /*
 933                  * Possible MP race to 0, use the serializer.  The atomic insn
 934                  * is still needed for races against bge_jref().
 935                  */
 936                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
 937                 atomic_subtract_int(&entry->bge_inuse, 1);
 938                 if (entry->bge_inuse == 0) {
 939                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
 940                                           entry, jslot_link);
 941                 }
 942                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
 943         }
 944 }
 945
 946
 947 /*
 948  * Intialize a standard receive ring descriptor.
 949  */
 950 static int
 951 bge_newbuf_std(struct bge_softc *sc, int i, int init)
 952 {
 953         struct mbuf *m_new = NULL;
 954         bus_dma_segment_t seg;
 955         bus_dmamap_t map;
 956         int error, nsegs;
 957
 958         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 959         if (m_new == NULL)
 960                 return ENOBUFS;
 961         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 962
 963         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 964                 m_adj(m_new, ETHER_ALIGN);
 965
 966         error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag,
 967                         sc->bge_cdata.bge_rx_tmpmap, m_new,
 968                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
 969         if (error) {
 970                 m_freem(m_new);
 971                 return error;
 972         }
 973
 974         if (!init) {
 975                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 976                                 sc->bge_cdata.bge_rx_std_dmamap[i],
 977                                 BUS_DMASYNC_POSTREAD);
 978                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
 979                         sc->bge_cdata.bge_rx_std_dmamap[i]);
 980         }
 981
 982         map = sc->bge_cdata.bge_rx_tmpmap;
 983         sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i];
 984         sc->bge_cdata.bge_rx_std_dmamap[i] = map;
 985
 986         sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new;
 987         sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr;
 988
 989         bge_setup_rxdesc_std(sc, i);
 990         return 0;
 991 }
 992
 993 static void
 994 bge_setup_rxdesc_std(struct bge_softc *sc, int i)
 995 {
 996         struct bge_rxchain *rc;
 997         struct bge_rx_bd *r;
 998
 999         rc = &sc->bge_cdata.bge_rx_std_chain[i];
1000         r = &sc->bge_ldata.bge_rx_std_ring[i];
1001
1002         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1003         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1004         r->bge_len = rc->bge_mbuf->m_len;
1005         r->bge_idx = i;
1006         r->bge_flags = BGE_RXBDFLAG_END;
1007 }
1008
1009 /*
1010  * Initialize a jumbo receive ring descriptor. This allocates
1011  * a jumbo buffer from the pool managed internally by the driver.
1012  */
1013 static int
1014 bge_newbuf_jumbo(struct bge_softc *sc, int i, int init)
1015 {
1016         struct mbuf *m_new = NULL;
1017         struct bge_jslot *buf;
1018         bus_addr_t paddr;
1019
1020         /* Allocate the mbuf. */
1021         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1022         if (m_new == NULL)
1023                 return ENOBUFS;
1024
1025         /* Allocate the jumbo buffer */
1026         buf = bge_jalloc(sc);
1027         if (buf == NULL) {
1028                 m_freem(m_new);
1029                 return ENOBUFS;
1030         }
1031
1032         /* Attach the buffer to the mbuf. */
1033         m_new->m_ext.ext_arg = buf;
1034         m_new->m_ext.ext_buf = buf->bge_buf;
1035         m_new->m_ext.ext_free = bge_jfree;
1036         m_new->m_ext.ext_ref = bge_jref;
1037         m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
1038
1039         m_new->m_flags |= M_EXT;
1040
1041         m_new->m_data = m_new->m_ext.ext_buf;
1042         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1043
1044         paddr = buf->bge_paddr;
1045         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
1046                 m_adj(m_new, ETHER_ALIGN);
1047                 paddr += ETHER_ALIGN;
1048         }
1049
1050         /* Save necessary information */
1051         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new;
1052         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr;
1053
1054         /* Set up the descriptor. */
1055         bge_setup_rxdesc_jumbo(sc, i);
1056         return 0;
1057 }
1058
1059 static void
1060 bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i)
1061 {
1062         struct bge_rx_bd *r;
1063         struct bge_rxchain *rc;
1064
1065         r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1066         rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1067
1068         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1069         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1070         r->bge_len = rc->bge_mbuf->m_len;
1071         r->bge_idx = i;
1072         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
1073 }
1074
1075 static int
1076 bge_init_rx_ring_std(struct bge_softc *sc)
1077 {
1078         int i, error;
1079
1080         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1081                 error = bge_newbuf_std(sc, i, 1);
1082                 if (error)
1083                         return error;
1084         };
1085
1086         sc->bge_std = BGE_STD_RX_RING_CNT - 1;
1087         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1088
1089         return(0);
1090 }
1091
1092 static void
1093 bge_free_rx_ring_std(struct bge_softc *sc)
1094 {
1095         int i;
1096
1097         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1098                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i];
1099
1100                 if (rc->bge_mbuf != NULL) {
1101                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1102                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
1103                         m_freem(rc->bge_mbuf);
1104                         rc->bge_mbuf = NULL;
1105                 }
1106                 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
1107                     sizeof(struct bge_rx_bd));
1108         }
1109 }
1110
1111 static int
1112 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1113 {
1114         struct bge_rcb *rcb;
1115         int i, error;
1116
1117         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1118                 error = bge_newbuf_jumbo(sc, i, 1);
1119                 if (error)
1120                         return error;
1121         };
1122
1123         sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
1124
1125         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1126         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1127         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1128
1129         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1130
1131         return(0);
1132 }
1133
1134 static void
1135 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1136 {
1137         int i;
1138
1139         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1140                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1141
1142                 if (rc->bge_mbuf != NULL) {
1143                         m_freem(rc->bge_mbuf);
1144                         rc->bge_mbuf = NULL;
1145                 }
1146                 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1147                     sizeof(struct bge_rx_bd));
1148         }
1149 }
1150
1151 static void
1152 bge_free_tx_ring(struct bge_softc *sc)
1153 {
1154         int i;
1155
1156         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1157                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1158                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1159                                           sc->bge_cdata.bge_tx_dmamap[i]);
1160                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1161                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1162                 }
1163                 bzero(&sc->bge_ldata.bge_tx_ring[i],
1164                     sizeof(struct bge_tx_bd));
1165         }
1166 }
1167
1168 static int
1169 bge_init_tx_ring(struct bge_softc *sc)
1170 {
1171         sc->bge_txcnt = 0;
1172         sc->bge_tx_saved_considx = 0;
1173         sc->bge_tx_prodidx = 0;
1174
1175         /* Initialize transmit producer index for host-memory send ring. */
1176         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1177
1178         /* 5700 b2 errata */
1179         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1180                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1181
1182         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1183         /* 5700 b2 errata */
1184         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1185                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1186
1187         return(0);
1188 }
1189
1190 static void
1191 bge_setmulti(struct bge_softc *sc)
1192 {
1193         struct ifnet *ifp;
1194         struct ifmultiaddr *ifma;
1195         uint32_t hashes[4] = { 0, 0, 0, 0 };
1196         int h, i;
1197
1198         ifp = &sc->arpcom.ac_if;
1199
1200         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1201                 for (i = 0; i < 4; i++)
1202                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1203                 return;
1204         }
1205
1206         /* First, zot all the existing filters. */
1207         for (i = 0; i < 4; i++)
1208                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1209
1210         /* Now program new ones. */
1211         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1212                 if (ifma->ifma_addr->sa_family != AF_LINK)
1213                         continue;
1214                 h = ether_crc32_le(
1215                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1216                     ETHER_ADDR_LEN) & 0x7f;
1217                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1218         }
1219
1220         for (i = 0; i < 4; i++)
1221                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1222 }
1223
1224 /*
1225  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1226  * self-test results.
1227  */
1228 static int
1229 bge_chipinit(struct bge_softc *sc)
1230 {
1231         int i;
1232         uint32_t dma_rw_ctl;
1233         uint16_t val;
1234
1235         /* Set endian type before we access any non-PCI registers. */
1236         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1237
1238         /* Clear the MAC control register */
1239         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1240
1241         /*
1242          * Clear the MAC statistics block in the NIC's
1243          * internal memory.
1244          */
1245         for (i = BGE_STATS_BLOCK;
1246             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1247                 BGE_MEMWIN_WRITE(sc, i, 0);
1248
1249         for (i = BGE_STATUS_BLOCK;
1250             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1251                 BGE_MEMWIN_WRITE(sc, i, 0);
1252
1253         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1254                 /*
1255                  * Fix data corruption caused by non-qword write with WB.
1256                  * Fix master abort in PCI mode.
1257                  * Fix PCI latency timer.
1258                  */
1259                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1260                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1261                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1262         }
1263
1264         /* Set up the PCI DMA control register. */
1265         if (sc->bge_flags & BGE_FLAG_PCIE) {
1266                 /* PCI Express */
1267                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1268                     (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1269                     (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1270         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1271                 /* PCI-X bus */
1272                 if (BGE_IS_5714_FAMILY(sc)) {
1273                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1274                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1275                         /* XXX magic values, Broadcom-supplied Linux driver */
1276                         if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1277                                 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1278                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1279                         } else {
1280                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1281                         }
1282                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1283                         /*
1284                          * In the BCM5703, the DMA read watermark should
1285                          * be set to less than or equal to the maximum
1286                          * memory read byte count of the PCI-X command
1287                          * register.
1288                          */
1289                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1290                             (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1291                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1292                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1293                         /*
1294                          * The 5704 uses a different encoding of read/write
1295                          * watermarks.
1296                          */
1297                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1298                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1299                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1300                 } else {
1301                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1302                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1303                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1304                             (0x0F);
1305                 }
1306
1307                 /*
1308                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1309                  * for hardware bugs.
1310                  */
1311                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1312                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1313                         uint32_t tmp;
1314
1315                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1316                         if (tmp == 0x6 || tmp == 0x7)
1317                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1318                 }
1319         } else {
1320                 /* Conventional PCI bus */
1321                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1322                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1323                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1324                     (0x0F);
1325         }
1326
1327         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1328             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1329             sc->bge_asicrev == BGE_ASICREV_BCM5705)
1330                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1331         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1332
1333         /*
1334          * Set up general mode register.
1335          */
1336         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1337             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1338             BGE_MODECTL_TX_NO_PHDR_CSUM);
1339
1340         /*
1341          * BCM5701 B5 have a bug causing data corruption when using
1342          * 64-bit DMA reads, which can be terminated early and then
1343          * completed later as 32-bit accesses, in combination with
1344          * certain bridges.
1345          */
1346         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1347             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1348                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1349
1350         /*
1351          * Disable memory write invalidate.  Apparently it is not supported
1352          * properly by these devices.
1353          */
1354         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1355
1356         /* Set the timer prescaler (always 66Mhz) */
1357         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1358
1359         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1360                 DELAY(40);      /* XXX */
1361
1362                 /* Put PHY into ready state */
1363                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1364                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1365                 DELAY(40);
1366         }
1367
1368         return(0);
1369 }
1370
1371 static int
1372 bge_blockinit(struct bge_softc *sc)
1373 {
1374         struct bge_rcb *rcb;
1375         bus_size_t vrcb;
1376         bge_hostaddr taddr;
1377         uint32_t val;
1378         int i, limit;
1379
1380         /*
1381          * Initialize the memory window pointer register so that
1382          * we can access the first 32K of internal NIC RAM. This will
1383          * allow us to set up the TX send ring RCBs and the RX return
1384          * ring RCBs, plus other things which live in NIC memory.
1385          */
1386         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1387
1388         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1389
1390         if (!BGE_IS_5705_PLUS(sc)) {
1391                 /* Configure mbuf memory pool */
1392                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1393                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1394                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1395                 else
1396                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1397
1398                 /* Configure DMA resource pool */
1399                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1400                     BGE_DMA_DESCRIPTORS);
1401                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1402         }
1403
1404         /* Configure mbuf pool watermarks */
1405         if (!BGE_IS_5705_PLUS(sc)) {
1406                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1407                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1408                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1409         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1410                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1411                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1412                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1413         } else {
1414                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1415                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1416                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1417         }
1418
1419         /* Configure DMA resource watermarks */
1420         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1421         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1422
1423         /* Enable buffer manager */
1424         if (!BGE_IS_5705_PLUS(sc)) {
1425                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1426                     BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1427
1428                 /* Poll for buffer manager start indication */
1429                 for (i = 0; i < BGE_TIMEOUT; i++) {
1430                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1431                                 break;
1432                         DELAY(10);
1433                 }
1434
1435                 if (i == BGE_TIMEOUT) {
1436                         if_printf(&sc->arpcom.ac_if,
1437                                   "buffer manager failed to start\n");
1438                         return(ENXIO);
1439                 }
1440         }
1441
1442         /* Enable flow-through queues */
1443         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1444         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1445
1446         /* Wait until queue initialization is complete */
1447         for (i = 0; i < BGE_TIMEOUT; i++) {
1448                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1449                         break;
1450                 DELAY(10);
1451         }
1452
1453         if (i == BGE_TIMEOUT) {
1454                 if_printf(&sc->arpcom.ac_if,
1455                           "flow-through queue init failed\n");
1456                 return(ENXIO);
1457         }
1458
1459         /*
1460          * Summary of rings supported by the controller:
1461          *
1462          * Standard Receive Producer Ring
1463          * - This ring is used to feed receive buffers for "standard"
1464          *   sized frames (typically 1536 bytes) to the controller.
1465          *
1466          * Jumbo Receive Producer Ring
1467          * - This ring is used to feed receive buffers for jumbo sized
1468          *   frames (i.e. anything bigger than the "standard" frames)
1469          *   to the controller.
1470          *
1471          * Mini Receive Producer Ring
1472          * - This ring is used to feed receive buffers for "mini"
1473          *   sized frames to the controller.
1474          * - This feature required external memory for the controller
1475          *   but was never used in a production system.  Should always
1476          *   be disabled.
1477          *
1478          * Receive Return Ring
1479          * - After the controller has placed an incoming frame into a
1480          *   receive buffer that buffer is moved into a receive return
1481          *   ring.  The driver is then responsible to passing the
1482          *   buffer up to the stack.  Many versions of the controller
1483          *   support multiple RR rings.
1484          *
1485          * Send Ring
1486          * - This ring is used for outgoing frames.  Many versions of
1487          *   the controller support multiple send rings.
1488          */
1489
1490         /* Initialize the standard receive producer ring control block. */
1491         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1492         rcb->bge_hostaddr.bge_addr_lo =
1493             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1494         rcb->bge_hostaddr.bge_addr_hi =
1495             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1496         if (BGE_IS_5705_PLUS(sc)) {
1497                 /*
1498                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1499                  * Bits 15-2 : Reserved (should be 0)
1500                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1501                  * Bit 0     : Reserved
1502                  */
1503                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1504         } else {
1505                 /*
1506                  * Ring size is always XXX entries
1507                  * Bits 31-16: Maximum RX frame size
1508                  * Bits 15-2 : Reserved (should be 0)
1509                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1510                  * Bit 0     : Reserved
1511                  */
1512                 rcb->bge_maxlen_flags =
1513                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1514         }
1515         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1516         /* Write the standard receive producer ring control block. */
1517         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1518         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1519         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1520         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1521         /* Reset the standard receive producer ring producer index. */
1522         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1523
1524         /*
1525          * Initialize the jumbo RX producer ring control
1526          * block.  We set the 'ring disabled' bit in the
1527          * flags field until we're actually ready to start
1528          * using this ring (i.e. once we set the MTU
1529          * high enough to require it).
1530          */
1531         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1532                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1533                 /* Get the jumbo receive producer ring RCB parameters. */
1534                 rcb->bge_hostaddr.bge_addr_lo =
1535                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1536                 rcb->bge_hostaddr.bge_addr_hi =
1537                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1538                 rcb->bge_maxlen_flags =
1539                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1540                     BGE_RCB_FLAG_RING_DISABLED);
1541                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1542                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1543                     rcb->bge_hostaddr.bge_addr_hi);
1544                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1545                     rcb->bge_hostaddr.bge_addr_lo);
1546                 /* Program the jumbo receive producer ring RCB parameters. */
1547                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1548                     rcb->bge_maxlen_flags);
1549                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1550                 /* Reset the jumbo receive producer ring producer index. */
1551                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1552         }
1553
1554         /* Disable the mini receive producer ring RCB. */
1555         if (BGE_IS_5700_FAMILY(sc)) {
1556                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1557                 rcb->bge_maxlen_flags =
1558                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1559                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1560                     rcb->bge_maxlen_flags);
1561                 /* Reset the mini receive producer ring producer index. */
1562                 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1563         }
1564
1565         /*
1566          * The BD ring replenish thresholds control how often the
1567          * hardware fetches new BD's from the producer rings in host
1568          * memory.  Setting the value too low on a busy system can
1569          * starve the hardware and recue the throughpout.
1570          *
1571          * Set the BD ring replentish thresholds. The recommended
1572          * values are 1/8th the number of descriptors allocated to
1573          * each ring.
1574          */
1575         if (BGE_IS_5705_PLUS(sc))
1576                 val = 8;
1577         else
1578                 val = BGE_STD_RX_RING_CNT / 8;
1579         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1580         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1581                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1582                     BGE_JUMBO_RX_RING_CNT/8);
1583         }
1584
1585         /*
1586          * Disable all send rings by setting the 'ring disabled' bit
1587          * in the flags field of all the TX send ring control blocks,
1588          * located in NIC memory.
1589          */
1590         if (!BGE_IS_5705_PLUS(sc)) {
1591                 /* 5700 to 5704 had 16 send rings. */
1592                 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
1593         } else {
1594                 limit = 1;
1595         }
1596         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1597         for (i = 0; i < limit; i++) {
1598                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1599                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1600                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1601                 vrcb += sizeof(struct bge_rcb);
1602         }
1603
1604         /* Configure send ring RCB 0 (we use only the first ring) */
1605         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1606         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1607         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1608         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1609         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1610             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1611         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1612             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1613
1614         /*
1615          * Disable all receive return rings by setting the
1616          * 'ring diabled' bit in the flags field of all the receive
1617          * return ring control blocks, located in NIC memory.
1618          */
1619         if (!BGE_IS_5705_PLUS(sc))
1620                 limit = BGE_RX_RINGS_MAX;
1621         else if (sc->bge_asicrev == BGE_ASICREV_BCM5755)
1622                 limit = 4;
1623         else
1624                 limit = 1;
1625         /* Disable all receive return rings. */
1626         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1627         for (i = 0; i < limit; i++) {
1628                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1629                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1630                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1631                     BGE_RCB_FLAG_RING_DISABLED);
1632                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1633                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1634                     (i * (sizeof(uint64_t))), 0);
1635                 vrcb += sizeof(struct bge_rcb);
1636         }
1637
1638         /*
1639          * Set up receive return ring 0.  Note that the NIC address
1640          * for RX return rings is 0x0.  The return rings live entirely
1641          * within the host, so the nicaddr field in the RCB isn't used.
1642          */
1643         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1644         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1645         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1646         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1647         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1648         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1649             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1650
1651         /* Set random backoff seed for TX */
1652         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1653             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1654             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1655             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1656             BGE_TX_BACKOFF_SEED_MASK);
1657
1658         /* Set inter-packet gap */
1659         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1660
1661         /*
1662          * Specify which ring to use for packets that don't match
1663          * any RX rules.
1664          */
1665         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1666
1667         /*
1668          * Configure number of RX lists. One interrupt distribution
1669          * list, sixteen active lists, one bad frames class.
1670          */
1671         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1672
1673         /* Inialize RX list placement stats mask. */
1674         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1675         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1676
1677         /* Disable host coalescing until we get it set up */
1678         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1679
1680         /* Poll to make sure it's shut down. */
1681         for (i = 0; i < BGE_TIMEOUT; i++) {
1682                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1683                         break;
1684                 DELAY(10);
1685         }
1686
1687         if (i == BGE_TIMEOUT) {
1688                 if_printf(&sc->arpcom.ac_if,
1689                           "host coalescing engine failed to idle\n");
1690                 return(ENXIO);
1691         }
1692
1693         /* Set up host coalescing defaults */
1694         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1695         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1696         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1697         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1698         if (!BGE_IS_5705_PLUS(sc)) {
1699                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1700                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1701         }
1702         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1703         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1704
1705         /* Set up address of statistics block */
1706         if (!BGE_IS_5705_PLUS(sc)) {
1707                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1708                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1709                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1710                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1711
1712                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1713                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1714                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1715         }
1716
1717         /* Set up address of status block */
1718         bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
1719         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1720             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1721         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1722             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1723
1724         /*
1725          * Set up status block partail update size.
1726          *
1727          * Because only single TX ring, RX produce ring and Rx return ring
1728          * are used, ask device to update only minimum part of status block
1729          * except for BCM5700 AX/BX, whose status block partial update size
1730          * can't be configured.
1731          */
1732         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1733             sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
1734                 /* XXX Actually reserved on BCM5700 AX/BX */
1735                 val = BGE_STATBLKSZ_FULL;
1736         } else {
1737                 val = BGE_STATBLKSZ_32BYTE;
1738         }
1739
1740         /* Turn on host coalescing state machine */
1741         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1742
1743         /* Turn on RX BD completion state machine and enable attentions */
1744         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1745             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1746
1747         /* Turn on RX list placement state machine */
1748         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1749
1750         /* Turn on RX list selector state machine. */
1751         if (!BGE_IS_5705_PLUS(sc))
1752                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1753
1754         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1755             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1756             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1757             BGE_MACMODE_FRMHDR_DMA_ENB;
1758
1759         if (sc->bge_flags & BGE_FLAG_TBI)
1760                 val |= BGE_PORTMODE_TBI;
1761         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
1762                 val |= BGE_PORTMODE_GMII;
1763         else
1764                 val |= BGE_PORTMODE_MII;
1765
1766         /* Turn on DMA, clear stats */
1767         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1768
1769         /* Set misc. local control, enable interrupts on attentions */
1770         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1771
1772 #ifdef notdef
1773         /* Assert GPIO pins for PHY reset */
1774         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1775             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1776         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1777             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1778 #endif
1779
1780         /* Turn on DMA completion state machine */
1781         if (!BGE_IS_5705_PLUS(sc))
1782                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1783
1784         /* Turn on write DMA state machine */
1785         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1786         if (BGE_IS_5755_PLUS(sc)) {
1787                 /* Enable host coalescing bug fix. */
1788                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1789         }
1790         if (sc->bge_asicrev == BGE_ASICREV_BCM5785) {
1791                 /* Request larger DMA burst size to get better performance. */
1792                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1793         }
1794         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1795         DELAY(40);
1796
1797         if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
1798             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1799             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1800             sc->bge_asicrev == BGE_ASICREV_BCM57780) {
1801                 /*
1802                  * Enable fix for read DMA FIFO overruns.
1803                  * The fix is to limit the number of RX BDs
1804                  * the hardware would fetch at a fime.
1805                  */
1806                 val = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
1807                 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
1808                     val| BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1809         }
1810
1811         /* Turn on read DMA state machine */
1812         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1813         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1814             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1815             sc->bge_asicrev == BGE_ASICREV_BCM57780)
1816                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1817                   BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1818                   BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1819         if (sc->bge_flags & BGE_FLAG_PCIE)
1820                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1821         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1822         DELAY(40);
1823
1824         /* Turn on RX data completion state machine */
1825         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1826
1827         /* Turn on RX BD initiator state machine */
1828         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1829
1830         /* Turn on RX data and RX BD initiator state machine */
1831         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1832
1833         /* Turn on Mbuf cluster free state machine */
1834         if (!BGE_IS_5705_PLUS(sc))
1835                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1836
1837         /* Turn on send BD completion state machine */
1838         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1839
1840         /* Turn on send data completion state machine */
1841         val = BGE_SDCMODE_ENABLE;
1842         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1843                 val |= BGE_SDCMODE_CDELAY;
1844         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1845
1846         /* Turn on send data initiator state machine */
1847         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1848
1849         /* Turn on send BD initiator state machine */
1850         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1851
1852         /* Turn on send BD selector state machine */
1853         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1854
1855         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1856         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1857             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1858
1859         /* ack/clear link change events */
1860         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1861             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1862             BGE_MACSTAT_LINK_CHANGED);
1863         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1864
1865         /*
1866          * Enable attention when the link has changed state for
1867          * devices that use auto polling.
1868          */
1869         if (sc->bge_flags & BGE_FLAG_TBI) {
1870                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1871         } else {
1872                 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
1873                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1874                         DELAY(80);
1875                 }
1876                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1877                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1878                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1879                             BGE_EVTENB_MI_INTERRUPT);
1880                 }
1881         }
1882
1883         /*
1884          * Clear any pending link state attention.
1885          * Otherwise some link state change events may be lost until attention
1886          * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1887          * It's not necessary on newer BCM chips - perhaps enabling link
1888          * state change attentions implies clearing pending attention.
1889          */
1890         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1891             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1892             BGE_MACSTAT_LINK_CHANGED);
1893
1894         /* Enable link state change attentions. */
1895         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1896
1897         return(0);
1898 }
1899
1900 /*
1901  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1902  * against our list and return its name if we find a match. Note
1903  * that since the Broadcom controller contains VPD support, we
1904  * can get the device name string from the controller itself instead
1905  * of the compiled-in string. This is a little slow, but it guarantees
1906  * we'll always announce the right product name.
1907  */
1908 static int
1909 bge_probe(device_t dev)
1910 {
1911         const struct bge_type *t;
1912         uint16_t product, vendor;
1913
1914         product = pci_get_device(dev);
1915         vendor = pci_get_vendor(dev);
1916
1917         for (t = bge_devs; t->bge_name != NULL; t++) {
1918                 if (vendor == t->bge_vid && product == t->bge_did)
1919                         break;
1920         }
1921         if (t->bge_name == NULL)
1922                 return(ENXIO);
1923
1924         device_set_desc(dev, t->bge_name);
1925         return(0);
1926 }
1927
1928 static int
1929 bge_attach(device_t dev)
1930 {
1931         struct ifnet *ifp;
1932         struct bge_softc *sc;
1933         uint32_t hwcfg = 0, misccfg;
1934         int error = 0, rid, capmask;
1935         uint8_t ether_addr[ETHER_ADDR_LEN];
1936         uint16_t product, vendor;
1937
1938         sc = device_get_softc(dev);
1939         sc->bge_dev = dev;
1940         callout_init(&sc->bge_stat_timer);
1941         lwkt_serialize_init(&sc->bge_jslot_serializer);
1942
1943 #ifndef BURN_BRIDGES
1944         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1945                 uint32_t irq, mem;
1946
1947                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1948                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1949
1950                 device_printf(dev, "chip is in D%d power mode "
1951                     "-- setting to D0\n", pci_get_powerstate(dev));
1952
1953                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1954
1955                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1956                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1957         }
1958 #endif  /* !BURN_BRIDGE */
1959
1960         /*
1961          * Map control/status registers.
1962          */
1963         pci_enable_busmaster(dev);
1964
1965         rid = BGE_PCI_BAR0;
1966         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1967             RF_ACTIVE);
1968
1969         if (sc->bge_res == NULL) {
1970                 device_printf(dev, "couldn't map memory\n");
1971                 return ENXIO;
1972         }
1973
1974         sc->bge_btag = rman_get_bustag(sc->bge_res);
1975         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1976
1977         /* Save various chip information */
1978         sc->bge_chipid =
1979             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1980             BGE_PCIMISCCTL_ASICREV_SHIFT;
1981         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
1982                 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
1983         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1984         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1985
1986         /* Save chipset family. */
1987         switch (sc->bge_asicrev) {
1988         case BGE_ASICREV_BCM5755:
1989         case BGE_ASICREV_BCM5761:
1990         case BGE_ASICREV_BCM5784:
1991         case BGE_ASICREV_BCM5785:
1992         case BGE_ASICREV_BCM5787:
1993         case BGE_ASICREV_BCM57780:
1994             sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
1995                 BGE_FLAG_5705_PLUS;
1996             break;
1997
1998         case BGE_ASICREV_BCM5700:
1999         case BGE_ASICREV_BCM5701:
2000         case BGE_ASICREV_BCM5703:
2001         case BGE_ASICREV_BCM5704:
2002                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2003                 break;
2004
2005         case BGE_ASICREV_BCM5714_A0:
2006         case BGE_ASICREV_BCM5780:
2007         case BGE_ASICREV_BCM5714:
2008                 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
2009                 /* Fall through */
2010
2011         case BGE_ASICREV_BCM5750:
2012         case BGE_ASICREV_BCM5752:
2013         case BGE_ASICREV_BCM5906:
2014                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2015                 /* Fall through */
2016
2017         case BGE_ASICREV_BCM5705:
2018                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2019                 break;
2020         }
2021
2022         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
2023                 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
2024
2025         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
2026         if (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2027             (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2028              misccfg == BGE_MISCCFG_BOARD_ID_5788M))
2029                 sc->bge_flags |= BGE_FLAG_5788;
2030
2031         /*
2032          * Set various quirk flags.
2033          */
2034
2035         product = pci_get_device(dev);
2036         vendor = pci_get_vendor(dev);
2037
2038         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2039              sc->bge_asicrev == BGE_ASICREV_BCM5701) &&
2040             pci_get_subvendor(dev) == PCI_VENDOR_DELL)
2041                 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
2042
2043         capmask = MII_CAPMASK_DEFAULT;
2044         if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
2045              (misccfg == 0x4000 || misccfg == 0x8000)) ||
2046             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2047              vendor == PCI_VENDOR_BROADCOM &&
2048              (product == PCI_PRODUCT_BROADCOM_BCM5901 ||
2049               product == PCI_PRODUCT_BROADCOM_BCM5901A2 ||
2050               product == PCI_PRODUCT_BROADCOM_BCM5705F)) ||
2051             (vendor == PCI_VENDOR_BROADCOM &&
2052              (product == PCI_PRODUCT_BROADCOM_BCM5751F ||
2053               product == PCI_PRODUCT_BROADCOM_BCM5753F ||
2054               product == PCI_PRODUCT_BROADCOM_BCM5787F)) ||
2055             product == PCI_PRODUCT_BROADCOM_BCM57790 ||
2056             sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2057                 /* 10/100 only */
2058                 capmask &= ~BMSR_EXTSTAT;
2059         }
2060
2061         sc->bge_phy_flags |= BGE_PHY_WIRESPEED;
2062         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2063             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2064              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2065               sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
2066             sc->bge_asicrev == BGE_ASICREV_BCM5906)
2067                 sc->bge_phy_flags &= ~BGE_PHY_WIRESPEED;
2068
2069         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2070             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2071                 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
2072
2073         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2074             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2075                 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
2076
2077         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2078                 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
2079
2080         if (BGE_IS_5705_PLUS(sc) &&
2081             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2082             /* sc->bge_asicrev != BGE_ASICREV_BCM5717 && */
2083             sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2084             /* sc->bge_asicrev != BGE_ASICREV_BCM57765 && */
2085             sc->bge_asicrev != BGE_ASICREV_BCM57780) {
2086                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2087                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2088                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2089                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2090                         if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
2091                             product != PCI_PRODUCT_BROADCOM_BCM5756)
2092                                 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
2093                         if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
2094                                 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
2095                 } else {
2096                         sc->bge_phy_flags |= BGE_PHY_BER_BUG;
2097                 }
2098         }
2099
2100         /* Identify the chips that use an CPMU. */
2101         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2102             sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2103             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2104             sc->bge_asicrev == BGE_ASICREV_BCM57780)
2105                 sc->bge_flags |= BGE_FLAG_CPMU;
2106         if (sc->bge_flags & BGE_FLAG_CPMU)
2107                 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
2108         else
2109                 sc->bge_mi_mode = BGE_MIMODE_BASE;
2110
2111         /* Enable auto polling for BCM570[0-5]. */
2112         if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
2113                 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
2114
2115         /* Allocate interrupt */
2116         rid = 0;
2117
2118         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2119             RF_SHAREABLE | RF_ACTIVE);
2120
2121         if (sc->bge_irq == NULL) {
2122                 device_printf(dev, "couldn't map interrupt\n");
2123                 error = ENXIO;
2124                 goto fail;
2125         }
2126
2127         /*
2128          * Check if this is a PCI-X or PCI Express device.
2129          */
2130         if (BGE_IS_5705_PLUS(sc)) {
2131                 if (pci_is_pcie(dev)) {
2132                         sc->bge_flags |= BGE_FLAG_PCIE;
2133                         pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
2134                 }
2135         } else {
2136                 /*
2137                  * Check if the device is in PCI-X Mode.
2138                  * (This bit is not valid on PCI Express controllers.)
2139                  */
2140                 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
2141                     BGE_PCISTATE_PCI_BUSMODE) == 0) {
2142                         sc->bge_flags |= BGE_FLAG_PCIX;
2143                         sc->bge_pcixcap = pci_get_pcixcap_ptr(sc->bge_dev);
2144                 }
2145         }
2146
2147         device_printf(dev, "CHIP ID 0x%08x; "
2148                       "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
2149                       sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
2150                       (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
2151                       : ((sc->bge_flags & BGE_FLAG_PCIE) ?
2152                         "PCI-E" : "PCI"));
2153
2154         /*
2155          * The 40bit DMA bug applies to the 5714/5715 controllers and is
2156          * not actually a MAC controller bug but an issue with the embedded
2157          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2158          */
2159         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
2160                 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT;
2161
2162         ifp = &sc->arpcom.ac_if;
2163         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2164
2165         /* Try to reset the chip. */
2166         bge_reset(sc);
2167
2168         if (bge_chipinit(sc)) {
2169                 device_printf(dev, "chip initialization failed\n");
2170                 error = ENXIO;
2171                 goto fail;
2172         }
2173
2174         /*
2175          * Get station address
2176          */
2177         error = bge_get_eaddr(sc, ether_addr);
2178         if (error) {
2179                 device_printf(dev, "failed to read station address\n");
2180                 goto fail;
2181         }
2182
2183         /* 5705/5750 limits RX return ring to 512 entries. */
2184         if (BGE_IS_5705_PLUS(sc))
2185                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2186         else
2187                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2188
2189         error = bge_dma_alloc(sc);
2190         if (error)
2191                 goto fail;
2192
2193         /* Set default tuneable values. */
2194         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2195         sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
2196         sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
2197         sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
2198         sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
2199
2200         /* Set up ifnet structure */
2201         ifp->if_softc = sc;
2202         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2203         ifp->if_ioctl = bge_ioctl;
2204         ifp->if_start = bge_start;
2205 #ifdef DEVICE_POLLING
2206         ifp->if_poll = bge_poll;
2207 #endif
2208         ifp->if_watchdog = bge_watchdog;
2209         ifp->if_init = bge_init;
2210         ifp->if_mtu = ETHERMTU;
2211         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2212         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2213         ifq_set_ready(&ifp->if_snd);
2214
2215         /*
2216          * 5700 B0 chips do not support checksumming correctly due
2217          * to hardware bugs.
2218          */
2219         if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
2220                 ifp->if_capabilities |= IFCAP_HWCSUM;
2221                 ifp->if_hwassist = BGE_CSUM_FEATURES;
2222         }
2223         ifp->if_capenable = ifp->if_capabilities;
2224
2225         /*
2226          * Figure out what sort of media we have by checking the
2227          * hardware config word in the first 32k of NIC internal memory,
2228          * or fall back to examining the EEPROM if necessary.
2229          * Note: on some BCM5700 cards, this value appears to be unset.
2230          * If that's the case, we have to rely on identifying the NIC
2231          * by its PCI subsystem ID, as we do below for the SysKonnect
2232          * SK-9D41.
2233          */
2234         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2235                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2236         else {
2237                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2238                                     sizeof(hwcfg))) {
2239                         device_printf(dev, "failed to read EEPROM\n");
2240                         error = ENXIO;
2241                         goto fail;
2242                 }
2243                 hwcfg = ntohl(hwcfg);
2244         }
2245
2246         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2247         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
2248             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
2249                 if (BGE_IS_5714_FAMILY(sc))
2250                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
2251                 else
2252                         sc->bge_flags |= BGE_FLAG_TBI;
2253         }
2254
2255         /*
2256          * Broadcom's own driver always assumes the internal
2257          * PHY is at GMII address 1.  On some chips, the PHY responds
2258          * to accesses at all addresses, which could cause us to
2259          * bogusly attach the PHY 32 times at probe type.  Always
2260          * restricting the lookup to address 1 is simpler than
2261          * trying to figure out which chips revisions should be
2262          * special-cased.
2263          */
2264         sc->bge_phyno = 1;
2265
2266         if (sc->bge_flags & BGE_FLAG_TBI) {
2267                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
2268                     bge_ifmedia_upd, bge_ifmedia_sts);
2269                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2270                 ifmedia_add(&sc->bge_ifmedia,
2271                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2272                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2273                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
2274                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2275         } else {
2276                 struct mii_probe_args mii_args;
2277
2278                 mii_probe_args_init(&mii_args, bge_ifmedia_upd, bge_ifmedia_sts);
2279                 mii_args.mii_probemask = 1 << sc->bge_phyno;
2280                 mii_args.mii_capmask = capmask;
2281
2282                 error = mii_probe(dev, &sc->bge_miibus, &mii_args);
2283                 if (error) {
2284                         device_printf(dev, "MII without any PHY!\n");
2285                         goto fail;
2286                 }
2287         }
2288
2289         /*
2290          * When using the BCM5701 in PCI-X mode, data corruption has
2291          * been observed in the first few bytes of some received packets.
2292          * Aligning the packet buffer in memory eliminates the corruption.
2293          * Unfortunately, this misaligns the packet payloads.  On platforms
2294          * which do not support unaligned accesses, we will realign the
2295          * payloads by copying the received packets.
2296          */
2297         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2298             (sc->bge_flags & BGE_FLAG_PCIX))
2299                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2300
2301         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2302             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2303                 sc->bge_link_upd = bge_bcm5700_link_upd;
2304                 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
2305         } else if (sc->bge_flags & BGE_FLAG_TBI) {
2306                 sc->bge_link_upd = bge_tbi_link_upd;
2307                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2308         } else if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2309                 sc->bge_link_upd = bge_autopoll_link_upd;
2310                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2311         } else {
2312                 sc->bge_link_upd = bge_copper_link_upd;
2313                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2314         }
2315
2316         /*
2317          * Create sysctl nodes.
2318          */
2319         sysctl_ctx_init(&sc->bge_sysctl_ctx);
2320         sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
2321                                               SYSCTL_STATIC_CHILDREN(_hw),
2322                                               OID_AUTO,
2323                                               device_get_nameunit(dev),
2324                                               CTLFLAG_RD, 0, "");
2325         if (sc->bge_sysctl_tree == NULL) {
2326                 device_printf(dev, "can't add sysctl node\n");
2327                 error = ENXIO;
2328                 goto fail;
2329         }
2330
2331         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2332                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2333                         OID_AUTO, "rx_coal_ticks",
2334                         CTLTYPE_INT | CTLFLAG_RW,
2335                         sc, 0, bge_sysctl_rx_coal_ticks, "I",
2336                         "Receive coalescing ticks (usec).");
2337         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2338                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2339                         OID_AUTO, "tx_coal_ticks",
2340                         CTLTYPE_INT | CTLFLAG_RW,
2341                         sc, 0, bge_sysctl_tx_coal_ticks, "I",
2342                         "Transmit coalescing ticks (usec).");
2343         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2344                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2345                         OID_AUTO, "rx_max_coal_bds",
2346                         CTLTYPE_INT | CTLFLAG_RW,
2347                         sc, 0, bge_sysctl_rx_max_coal_bds, "I",
2348                         "Receive max coalesced BD count.");
2349         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2350                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2351                         OID_AUTO, "tx_max_coal_bds",
2352                         CTLTYPE_INT | CTLFLAG_RW,
2353                         sc, 0, bge_sysctl_tx_max_coal_bds, "I",
2354                         "Transmit max coalesced BD count.");
2355
2356         if (sc->bge_flags & BGE_FLAG_PCIE) {
2357                 /*
2358                  * A common design characteristic for many Broadcom
2359                  * client controllers is that they only support a
2360                  * single outstanding DMA read operation on the PCIe
2361                  * bus. This means that it will take twice as long to
2362                  * fetch a TX frame that is split into header and
2363                  * payload buffers as it does to fetch a single,
2364                  * contiguous TX frame (2 reads vs. 1 read). For these
2365                  * controllers, coalescing buffers to reduce the number
2366                  * of memory reads is effective way to get maximum
2367                  * performance(about 940Mbps).  Without collapsing TX
2368                  * buffers the maximum TCP bulk transfer performance
2369                  * is about 850Mbps. However forcing coalescing mbufs
2370                  * consumes a lot of CPU cycles, so leave it off by
2371                  * default.
2372                  */
2373                 SYSCTL_ADD_INT(&sc->bge_sysctl_ctx,
2374                                SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2375                                OID_AUTO, "force_defrag", CTLFLAG_RW,
2376                                &sc->bge_force_defrag, 0,
2377                                "Force defragment on TX path");
2378         }
2379
2380         /*
2381          * Call MI attach routine.
2382          */
2383         ether_ifattach(ifp, ether_addr, NULL);
2384
2385         error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE,
2386                                bge_intr, sc, &sc->bge_intrhand,
2387                                ifp->if_serializer);
2388         if (error) {
2389                 ether_ifdetach(ifp);
2390                 device_printf(dev, "couldn't set up irq\n");
2391                 goto fail;
2392         }
2393
2394         ifp->if_cpuid = rman_get_cpuid(sc->bge_irq);
2395         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2396
2397         return(0);
2398 fail:
2399         bge_detach(dev);
2400         return(error);
2401 }
2402
2403 static int
2404 bge_detach(device_t dev)
2405 {
2406         struct bge_softc *sc = device_get_softc(dev);
2407
2408         if (device_is_attached(dev)) {
2409                 struct ifnet *ifp = &sc->arpcom.ac_if;
2410
2411                 lwkt_serialize_enter(ifp->if_serializer);
2412                 bge_stop(sc);
2413                 bge_reset(sc);
2414                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2415                 lwkt_serialize_exit(ifp->if_serializer);
2416
2417                 ether_ifdetach(ifp);
2418         }
2419
2420         if (sc->bge_flags & BGE_FLAG_TBI)
2421                 ifmedia_removeall(&sc->bge_ifmedia);
2422         if (sc->bge_miibus)
2423                 device_delete_child(dev, sc->bge_miibus);
2424         bus_generic_detach(dev);
2425
2426         if (sc->bge_irq != NULL)
2427                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
2428
2429         if (sc->bge_res != NULL)
2430                 bus_release_resource(dev, SYS_RES_MEMORY,
2431                     BGE_PCI_BAR0, sc->bge_res);
2432
2433         if (sc->bge_sysctl_tree != NULL)
2434                 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2435
2436         bge_dma_free(sc);
2437
2438         return 0;
2439 }
2440
2441 static void
2442 bge_reset(struct bge_softc *sc)
2443 {
2444         device_t dev;
2445         uint32_t cachesize, command, pcistate, reset;
2446         void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2447         int i, val = 0;
2448
2449         dev = sc->bge_dev;
2450
2451         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2452             sc->bge_asicrev != BGE_ASICREV_BCM5906) {
2453                 if (sc->bge_flags & BGE_FLAG_PCIE)
2454                         write_op = bge_writemem_direct;
2455                 else
2456                         write_op = bge_writemem_ind;
2457         } else {
2458                 write_op = bge_writereg_ind;
2459         }
2460
2461         /* Save some important PCI state. */
2462         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2463         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2464         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2465
2466         pci_write_config(dev, BGE_PCI_MISC_CTL,
2467             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2468             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2469
2470         /* Disable fastboot on controllers that support it. */
2471         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2472             BGE_IS_5755_PLUS(sc)) {
2473                 if (bootverbose)
2474                         if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2475                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2476         }
2477
2478         /*
2479          * Write the magic number to SRAM at offset 0xB50.
2480          * When firmware finishes its initialization it will
2481          * write ~BGE_MAGIC_NUMBER to the same location.
2482          */
2483         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2484
2485         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2486
2487         /* XXX: Broadcom Linux driver. */
2488         if (sc->bge_flags & BGE_FLAG_PCIE) {
2489                 if (CSR_READ_4(sc, 0x7e2c) == 0x60)     /* PCIE 1.0 */
2490                         CSR_WRITE_4(sc, 0x7e2c, 0x20);
2491                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2492                         /* Prevent PCIE link training during global reset */
2493                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2494                         reset |= (1<<29);
2495                 }
2496         }
2497
2498         /*
2499          * Set GPHY Power Down Override to leave GPHY
2500          * powered up in D0 uninitialized.
2501          */
2502         if (BGE_IS_5705_PLUS(sc))
2503                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2504
2505         /* Issue global reset */
2506         write_op(sc, BGE_MISC_CFG, reset);
2507
2508         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2509                 uint32_t status, ctrl;
2510
2511                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2512                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2513                     status | BGE_VCPU_STATUS_DRV_RESET);
2514                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2515                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2516                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2517         }
2518
2519         DELAY(1000);
2520
2521         /* XXX: Broadcom Linux driver. */
2522         if (sc->bge_flags & BGE_FLAG_PCIE) {
2523                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2524                         uint32_t v;
2525
2526                         DELAY(500000); /* wait for link training to complete */
2527                         v = pci_read_config(dev, 0xc4, 4);
2528                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
2529                 }
2530                 /*
2531                  * Set PCIE max payload size to 128 bytes and
2532                  * clear error status.
2533                  */
2534                 pci_write_config(dev, 0xd8, 0xf5000, 4);
2535         }
2536
2537         /* Reset some of the PCI state that got zapped by reset */
2538         pci_write_config(dev, BGE_PCI_MISC_CTL,
2539             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2540             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2541         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2542         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2543         write_op(sc, BGE_MISC_CFG, (65 << 1));
2544
2545         /*
2546          * Disable PCI-X relaxed ordering to ensure status block update
2547          * comes first then packet buffer DMA. Otherwise driver may
2548          * read stale status block.
2549          */
2550         if (sc->bge_flags & BGE_FLAG_PCIX) {
2551                 uint16_t devctl;
2552
2553                 devctl = pci_read_config(dev,
2554                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
2555                 devctl &= ~PCIXM_COMMAND_ERO;
2556                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
2557                         devctl &= ~PCIXM_COMMAND_MAX_READ;
2558                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2559                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2560                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
2561                             PCIXM_COMMAND_MAX_READ);
2562                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2563                 }
2564                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
2565                     devctl, 2);
2566         }
2567
2568         /* Enable memory arbiter. */
2569         if (BGE_IS_5714_FAMILY(sc)) {
2570                 uint32_t val;
2571
2572                 val = CSR_READ_4(sc, BGE_MARB_MODE);
2573                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2574         } else {
2575                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2576         }
2577
2578         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2579                 for (i = 0; i < BGE_TIMEOUT; i++) {
2580                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2581                         if (val & BGE_VCPU_STATUS_INIT_DONE)
2582                                 break;
2583                         DELAY(100);
2584                 }
2585                 if (i == BGE_TIMEOUT) {
2586                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2587                         return;
2588                 }
2589         } else {
2590                 /*
2591                  * Poll until we see the 1's complement of the magic number.
2592                  * This indicates that the firmware initialization
2593                  * is complete.
2594                  */
2595                 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
2596                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2597                         if (val == ~BGE_MAGIC_NUMBER)
2598                                 break;
2599                         DELAY(10);
2600                 }
2601                 if (i == BGE_FIRMWARE_TIMEOUT) {
2602                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
2603                                   "timed out, found 0x%08x\n", val);
2604                         return;
2605                 }
2606         }
2607
2608         /*
2609          * XXX Wait for the value of the PCISTATE register to
2610          * return to its original pre-reset state. This is a
2611          * fairly good indicator of reset completion. If we don't
2612          * wait for the reset to fully complete, trying to read
2613          * from the device's non-PCI registers may yield garbage
2614          * results.
2615          */
2616         for (i = 0; i < BGE_TIMEOUT; i++) {
2617                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2618                         break;
2619                 DELAY(10);
2620         }
2621
2622         /* Fix up byte swapping */
2623         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2624             BGE_MODECTL_BYTESWAP_DATA);
2625
2626         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2627
2628         /*
2629          * The 5704 in TBI mode apparently needs some special
2630          * adjustment to insure the SERDES drive level is set
2631          * to 1.2V.
2632          */
2633         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2634             (sc->bge_flags & BGE_FLAG_TBI)) {
2635                 uint32_t serdescfg;
2636
2637                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2638                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2639                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2640         }
2641
2642         /* XXX: Broadcom Linux driver. */
2643         if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2644             sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
2645             sc->bge_asicrev != BGE_ASICREV_BCM5785) {
2646                 uint32_t v;
2647
2648                 /* Enable Data FIFO protection. */
2649                 v = CSR_READ_4(sc, 0x7c00);
2650                 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2651         }
2652
2653         DELAY(10000);
2654 }
2655
2656 /*
2657  * Frame reception handling. This is called if there's a frame
2658  * on the receive return list.
2659  *
2660  * Note: we have to be able to handle two possibilities here:
2661  * 1) the frame is from the jumbo recieve ring
2662  * 2) the frame is from the standard receive ring
2663  */
2664
2665 static void
2666 bge_rxeof(struct bge_softc *sc)
2667 {
2668         struct ifnet *ifp;
2669         int stdcnt = 0, jumbocnt = 0;
2670
2671         if (sc->bge_rx_saved_considx ==
2672             sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2673                 return;
2674
2675         ifp = &sc->arpcom.ac_if;
2676
2677         while (sc->bge_rx_saved_considx !=
2678                sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2679                 struct bge_rx_bd        *cur_rx;
2680                 uint32_t                rxidx;
2681                 struct mbuf             *m = NULL;
2682                 uint16_t                vlan_tag = 0;
2683                 int                     have_tag = 0;
2684
2685                 cur_rx =
2686             &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2687
2688                 rxidx = cur_rx->bge_idx;
2689                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2690                 logif(rx_pkt);
2691
2692                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2693                         have_tag = 1;
2694                         vlan_tag = cur_rx->bge_vlan_tag;
2695                 }
2696
2697                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2698                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2699                         jumbocnt++;
2700
2701                         if (rxidx != sc->bge_jumbo) {
2702                                 ifp->if_ierrors++;
2703                                 if_printf(ifp, "sw jumbo index(%d) "
2704                                     "and hw jumbo index(%d) mismatch, drop!\n",
2705                                     sc->bge_jumbo, rxidx);
2706                                 bge_setup_rxdesc_jumbo(sc, rxidx);
2707                                 continue;
2708                         }
2709
2710                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf;
2711                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2712                                 ifp->if_ierrors++;
2713                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2714                                 continue;
2715                         }
2716                         if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) {
2717                                 ifp->if_ierrors++;
2718                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2719                                 continue;
2720                         }
2721                 } else {
2722                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2723                         stdcnt++;
2724
2725                         if (rxidx != sc->bge_std) {
2726                                 ifp->if_ierrors++;
2727                                 if_printf(ifp, "sw std index(%d) "
2728                                     "and hw std index(%d) mismatch, drop!\n",
2729                                     sc->bge_std, rxidx);
2730                                 bge_setup_rxdesc_std(sc, rxidx);
2731                                 continue;
2732                         }
2733
2734                         m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf;
2735                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2736                                 ifp->if_ierrors++;
2737                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2738                                 continue;
2739                         }
2740                         if (bge_newbuf_std(sc, sc->bge_std, 0)) {
2741                                 ifp->if_ierrors++;
2742                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2743                                 continue;
2744                         }
2745                 }
2746
2747                 ifp->if_ipackets++;
2748 #if !defined(__i386__) && !defined(__x86_64__)
2749                 /*
2750                  * The x86 allows unaligned accesses, but for other
2751                  * platforms we must make sure the payload is aligned.
2752                  */
2753                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2754                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2755                             cur_rx->bge_len);
2756                         m->m_data += ETHER_ALIGN;
2757                 }
2758 #endif
2759                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2760                 m->m_pkthdr.rcvif = ifp;
2761
2762                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2763                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2764                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2765                                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2766                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2767                         }
2768                         if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
2769                             m->m_pkthdr.len >= BGE_MIN_FRAME) {
2770                                 m->m_pkthdr.csum_data =
2771                                         cur_rx->bge_tcp_udp_csum;
2772                                 m->m_pkthdr.csum_flags |=
2773                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2774                         }
2775                 }
2776
2777                 /*
2778                  * If we received a packet with a vlan tag, pass it
2779                  * to vlan_input() instead of ether_input().
2780                  */
2781                 if (have_tag) {
2782                         m->m_flags |= M_VLANTAG;
2783                         m->m_pkthdr.ether_vlantag = vlan_tag;
2784                         have_tag = vlan_tag = 0;
2785                 }
2786                 ifp->if_input(ifp, m);
2787         }
2788
2789         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2790         if (stdcnt)
2791                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2792         if (jumbocnt)
2793                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2794 }
2795
2796 static void
2797 bge_txeof(struct bge_softc *sc)
2798 {
2799         struct bge_tx_bd *cur_tx = NULL;
2800         struct ifnet *ifp;
2801
2802         if (sc->bge_tx_saved_considx ==
2803             sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2804                 return;
2805
2806         ifp = &sc->arpcom.ac_if;
2807
2808         /*
2809          * Go through our tx ring and free mbufs for those
2810          * frames that have been sent.
2811          */
2812         while (sc->bge_tx_saved_considx !=
2813                sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2814                 uint32_t idx = 0;
2815
2816                 idx = sc->bge_tx_saved_considx;
2817                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2818                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2819                         ifp->if_opackets++;
2820                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2821                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
2822                             sc->bge_cdata.bge_tx_dmamap[idx]);
2823                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2824                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2825                 }
2826                 sc->bge_txcnt--;
2827                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2828                 logif(tx_pkt);
2829         }
2830
2831         if (cur_tx != NULL &&
2832             (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2833             (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2834                 ifp->if_flags &= ~IFF_OACTIVE;
2835
2836         if (sc->bge_txcnt == 0)
2837                 ifp->if_timer = 0;
2838
2839         if (!ifq_is_empty(&ifp->if_snd))
2840                 if_devstart(ifp);
2841 }
2842
2843 #ifdef DEVICE_POLLING
2844
2845 static void
2846 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2847 {
2848         struct bge_softc *sc = ifp->if_softc;
2849         uint32_t status;
2850
2851         switch(cmd) {
2852         case POLL_REGISTER:
2853                 bge_disable_intr(sc);
2854                 break;
2855         case POLL_DEREGISTER:
2856                 bge_enable_intr(sc);
2857                 break;
2858         case POLL_AND_CHECK_STATUS:
2859                 /*
2860                  * Process link state changes.
2861                  */
2862                 status = CSR_READ_4(sc, BGE_MAC_STS);
2863                 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2864                         sc->bge_link_evt = 0;
2865                         sc->bge_link_upd(sc, status);
2866                 }
2867                 /* fall through */
2868         case POLL_ONLY:
2869                 if (ifp->if_flags & IFF_RUNNING) {
2870                         bge_rxeof(sc);
2871                         bge_txeof(sc);
2872                 }
2873                 break;
2874         }
2875 }
2876
2877 #endif
2878
2879 static void
2880 bge_intr(void *xsc)
2881 {
2882         struct bge_softc *sc = xsc;
2883         struct ifnet *ifp = &sc->arpcom.ac_if;
2884         uint32_t status;
2885
2886         logif(intr);
2887
2888         /*
2889          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
2890          * disable interrupts by writing nonzero like we used to, since with
2891          * our current organization this just gives complications and
2892          * pessimizations for re-enabling interrupts.  We used to have races
2893          * instead of the necessary complications.  Disabling interrupts
2894          * would just reduce the chance of a status update while we are
2895          * running (by switching to the interrupt-mode coalescence
2896          * parameters), but this chance is already very low so it is more
2897          * efficient to get another interrupt than prevent it.
2898          *
2899          * We do the ack first to ensure another interrupt if there is a
2900          * status update after the ack.  We don't check for the status
2901          * changing later because it is more efficient to get another
2902          * interrupt than prevent it, not quite as above (not checking is
2903          * a smaller optimization than not toggling the interrupt enable,
2904          * since checking doesn't involve PCI accesses and toggling require
2905          * the status check).  So toggling would probably be a pessimization
2906          * even with MSI.  It would only be needed for using a task queue.
2907          */
2908         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
2909
2910         /*
2911          * Process link state changes.
2912          */
2913         status = CSR_READ_4(sc, BGE_MAC_STS);
2914         if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2915                 sc->bge_link_evt = 0;
2916                 sc->bge_link_upd(sc, status);
2917         }
2918
2919         if (ifp->if_flags & IFF_RUNNING) {
2920                 /* Check RX return ring producer/consumer */
2921                 bge_rxeof(sc);
2922
2923                 /* Check TX ring producer/consumer */
2924                 bge_txeof(sc);
2925         }
2926
2927         if (sc->bge_coal_chg)
2928                 bge_coal_change(sc);
2929 }
2930
2931 static void
2932 bge_tick(void *xsc)
2933 {
2934         struct bge_softc *sc = xsc;
2935         struct ifnet *ifp = &sc->arpcom.ac_if;
2936
2937         lwkt_serialize_enter(ifp->if_serializer);
2938
2939         if (BGE_IS_5705_PLUS(sc))
2940                 bge_stats_update_regs(sc);
2941         else
2942                 bge_stats_update(sc);
2943
2944         if (sc->bge_flags & BGE_FLAG_TBI) {
2945                 /*
2946                  * Since in TBI mode auto-polling can't be used we should poll
2947                  * link status manually. Here we register pending link event
2948                  * and trigger interrupt.
2949                  */
2950                 sc->bge_link_evt++;
2951                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2952                     BGE_IS_5788(sc))
2953                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
2954                 else
2955                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
2956         } else if (!sc->bge_link) {
2957                 mii_tick(device_get_softc(sc->bge_miibus));
2958         }
2959
2960         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2961
2962         lwkt_serialize_exit(ifp->if_serializer);
2963 }
2964
2965 static void
2966 bge_stats_update_regs(struct bge_softc *sc)
2967 {
2968         struct ifnet *ifp = &sc->arpcom.ac_if;
2969         struct bge_mac_stats_regs stats;
2970         uint32_t *s;
2971         int i;
2972
2973         s = (uint32_t *)&stats;
2974         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2975                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2976                 s++;
2977         }
2978
2979         ifp->if_collisions +=
2980            (stats.dot3StatsSingleCollisionFrames +
2981            stats.dot3StatsMultipleCollisionFrames +
2982            stats.dot3StatsExcessiveCollisions +
2983            stats.dot3StatsLateCollisions) -
2984            ifp->if_collisions;
2985 }
2986
2987 static void
2988 bge_stats_update(struct bge_softc *sc)
2989 {
2990         struct ifnet *ifp = &sc->arpcom.ac_if;
2991         bus_size_t stats;
2992
2993         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
2994
2995 #define READ_STAT(sc, stats, stat)      \
2996         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
2997
2998         ifp->if_collisions +=
2999            (READ_STAT(sc, stats,
3000                 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
3001             READ_STAT(sc, stats,
3002                 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
3003             READ_STAT(sc, stats,
3004                 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
3005             READ_STAT(sc, stats,
3006                 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
3007            ifp->if_collisions;
3008
3009 #undef READ_STAT
3010
3011 #ifdef notdef
3012         ifp->if_collisions +=
3013            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
3014            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
3015            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
3016            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
3017            ifp->if_collisions;
3018 #endif
3019 }
3020
3021 /*
3022  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
3023  * pointers to descriptors.
3024  */
3025 static int
3026 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
3027 {
3028         struct bge_tx_bd *d = NULL;
3029         uint16_t csum_flags = 0;
3030         bus_dma_segment_t segs[BGE_NSEG_NEW];
3031         bus_dmamap_t map;
3032         int error, maxsegs, nsegs, idx, i;
3033         struct mbuf *m_head = *m_head0;
3034
3035         if (m_head->m_pkthdr.csum_flags) {
3036                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3037                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3038                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
3039                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3040                 if (m_head->m_flags & M_LASTFRAG)
3041                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3042                 else if (m_head->m_flags & M_FRAG)
3043                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3044         }
3045
3046         idx = *txidx;
3047         map = sc->bge_cdata.bge_tx_dmamap[idx];
3048
3049         maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
3050         KASSERT(maxsegs >= BGE_NSEG_SPARE,
3051                 ("not enough segments %d", maxsegs));
3052
3053         if (maxsegs > BGE_NSEG_NEW)
3054                 maxsegs = BGE_NSEG_NEW;
3055
3056         /*
3057          * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
3058          * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
3059          * but when such padded frames employ the bge IP/TCP checksum
3060          * offload, the hardware checksum assist gives incorrect results
3061          * (possibly from incorporating its own padding into the UDP/TCP
3062          * checksum; who knows).  If we pad such runts with zeros, the
3063          * onboard checksum comes out correct.
3064          */
3065         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
3066             m_head->m_pkthdr.len < BGE_MIN_FRAME) {
3067                 error = m_devpad(m_head, BGE_MIN_FRAME);
3068                 if (error)
3069                         goto back;
3070         }
3071
3072         if (sc->bge_force_defrag && (sc->bge_flags & BGE_FLAG_PCIE) &&
3073             m_head->m_next != NULL) {
3074                 struct mbuf *m_new;
3075
3076                 /*
3077                  * Forcefully defragment mbuf chain to overcome hardware
3078                  * limitation which only support a single outstanding
3079                  * DMA read operation.  If it fails, keep moving on using
3080                  * the original mbuf chain.
3081                  */
3082                 m_new = m_defrag(m_head, MB_DONTWAIT);
3083                 if (m_new != NULL)
3084                         *m_head0 = m_head = m_new;
3085         }
3086
3087         error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map,
3088                         m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3089         if (error)
3090                 goto back;
3091
3092         m_head = *m_head0;
3093         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
3094
3095         for (i = 0; ; i++) {
3096                 d = &sc->bge_ldata.bge_tx_ring[idx];
3097
3098                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3099                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3100                 d->bge_len = segs[i].ds_len;
3101                 d->bge_flags = csum_flags;
3102
3103                 if (i == nsegs - 1)
3104                         break;
3105                 BGE_INC(idx, BGE_TX_RING_CNT);
3106         }
3107         /* Mark the last segment as end of packet... */
3108         d->bge_flags |= BGE_TXBDFLAG_END;
3109
3110         /* Set vlan tag to the first segment of the packet. */
3111         d = &sc->bge_ldata.bge_tx_ring[*txidx];
3112         if (m_head->m_flags & M_VLANTAG) {
3113                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3114                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
3115         } else {
3116                 d->bge_vlan_tag = 0;
3117         }
3118
3119         /*
3120          * Insure that the map for this transmission is placed at
3121          * the array index of the last descriptor in this chain.
3122          */
3123         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
3124         sc->bge_cdata.bge_tx_dmamap[idx] = map;
3125         sc->bge_cdata.bge_tx_chain[idx] = m_head;
3126         sc->bge_txcnt += nsegs;
3127
3128         BGE_INC(idx, BGE_TX_RING_CNT);
3129         *txidx = idx;
3130 back:
3131         if (error) {
3132                 m_freem(*m_head0);
3133                 *m_head0 = NULL;
3134         }
3135         return error;
3136 }
3137
3138 /*
3139  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3140  * to the mbuf data regions directly in the transmit descriptors.
3141  */
3142 static void
3143 bge_start(struct ifnet *ifp)
3144 {
3145         struct bge_softc *sc = ifp->if_softc;
3146         struct mbuf *m_head = NULL;
3147         uint32_t prodidx;
3148         int need_trans;
3149
3150         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
3151                 return;
3152
3153         prodidx = sc->bge_tx_prodidx;
3154
3155         need_trans = 0;
3156         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
3157                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3158                 if (m_head == NULL)
3159                         break;
3160
3161                 /*
3162                  * XXX
3163                  * The code inside the if() block is never reached since we
3164                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
3165                  * requests to checksum TCP/UDP in a fragmented packet.
3166                  *
3167                  * XXX
3168                  * safety overkill.  If this is a fragmented packet chain
3169                  * with delayed TCP/UDP checksums, then only encapsulate
3170                  * it if we have enough descriptors to handle the entire
3171                  * chain at once.
3172                  * (paranoia -- may not actually be needed)
3173                  */
3174                 if ((m_head->m_flags & M_FIRSTFRAG) &&
3175                     (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
3176                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3177                             m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
3178                                 ifp->if_flags |= IFF_OACTIVE;
3179                                 ifq_prepend(&ifp->if_snd, m_head);
3180                                 break;
3181                         }
3182                 }
3183
3184                 /*
3185                  * Sanity check: avoid coming within BGE_NSEG_RSVD
3186                  * descriptors of the end of the ring.  Also make
3187                  * sure there are BGE_NSEG_SPARE descriptors for
3188                  * jumbo buffers' defragmentation.
3189                  */
3190                 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3191                     (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
3192                         ifp->if_flags |= IFF_OACTIVE;
3193                         ifq_prepend(&ifp->if_snd, m_head);
3194                         break;
3195                 }
3196
3197                 /*
3198                  * Pack the data into the transmit ring. If we
3199                  * don't have room, set the OACTIVE flag and wait
3200                  * for the NIC to drain the ring.
3201                  */
3202                 if (bge_encap(sc, &m_head, &prodidx)) {
3203                         ifp->if_flags |= IFF_OACTIVE;
3204                         ifp->if_oerrors++;
3205                         break;
3206                 }
3207                 need_trans = 1;
3208
3209                 ETHER_BPF_MTAP(ifp, m_head);
3210         }
3211
3212         if (!need_trans)
3213                 return;
3214
3215         /* Transmit */
3216         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3217         /* 5700 b2 errata */
3218         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
3219                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3220
3221         sc->bge_tx_prodidx = prodidx;
3222
3223         /*
3224          * Set a timeout in case the chip goes out to lunch.
3225          */
3226         ifp->if_timer = 5;
3227 }
3228
3229 static void
3230 bge_init(void *xsc)
3231 {
3232         struct bge_softc *sc = xsc;
3233         struct ifnet *ifp = &sc->arpcom.ac_if;
3234         uint16_t *m;
3235
3236         ASSERT_SERIALIZED(ifp->if_serializer);
3237
3238         /* Cancel pending I/O and flush buffers. */
3239         bge_stop(sc);
3240         bge_reset(sc);
3241         bge_chipinit(sc);
3242
3243         /*
3244          * Init the various state machines, ring
3245          * control blocks and firmware.
3246          */
3247         if (bge_blockinit(sc)) {
3248                 if_printf(ifp, "initialization failure\n");
3249                 bge_stop(sc);
3250                 return;
3251         }
3252
3253         /* Specify MTU. */
3254         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3255             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3256
3257         /* Load our MAC address. */
3258         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3259         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3260         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3261
3262         /* Enable or disable promiscuous mode as needed. */
3263         bge_setpromisc(sc);
3264
3265         /* Program multicast filter. */
3266         bge_setmulti(sc);
3267
3268         /* Init RX ring. */
3269         if (bge_init_rx_ring_std(sc)) {
3270                 if_printf(ifp, "RX ring initialization failed\n");
3271                 bge_stop(sc);
3272                 return;
3273         }
3274
3275         /*
3276          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3277          * memory to insure that the chip has in fact read the first
3278          * entry of the ring.
3279          */
3280         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3281                 uint32_t                v, i;
3282                 for (i = 0; i < 10; i++) {
3283                         DELAY(20);
3284                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3285                         if (v == (MCLBYTES - ETHER_ALIGN))
3286                                 break;
3287                 }
3288                 if (i == 10)
3289                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
3290         }
3291
3292         /* Init jumbo RX ring. */
3293         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3294                 if (bge_init_rx_ring_jumbo(sc)) {
3295                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
3296                         bge_stop(sc);
3297                         return;
3298                 }
3299         }
3300
3301         /* Init our RX return ring index */
3302         sc->bge_rx_saved_considx = 0;
3303
3304         /* Init TX ring. */
3305         bge_init_tx_ring(sc);
3306
3307         /* Turn on transmitter */
3308         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
3309
3310         /* Turn on receiver */
3311         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3312
3313         /*
3314          * Set the number of good frames to receive after RX MBUF
3315          * Low Watermark has been reached.  After the RX MAC receives
3316          * this number of frames, it will drop subsequent incoming
3317          * frames until the MBUF High Watermark is reached.
3318          */
3319         CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3320
3321         /* Tell firmware we're alive. */
3322         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3323
3324         /* Enable host interrupts if polling(4) is not enabled. */
3325         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
3326 #ifdef DEVICE_POLLING
3327         if (ifp->if_flags & IFF_POLLING)
3328                 bge_disable_intr(sc);
3329         else
3330 #endif
3331         bge_enable_intr(sc);
3332
3333         bge_ifmedia_upd(ifp);
3334
3335         ifp->if_flags |= IFF_RUNNING;
3336         ifp->if_flags &= ~IFF_OACTIVE;
3337
3338         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3339 }
3340
3341 /*
3342  * Set media options.
3343  */
3344 static int
3345 bge_ifmedia_upd(struct ifnet *ifp)
3346 {
3347         struct bge_softc *sc = ifp->if_softc;
3348
3349         /* If this is a 1000baseX NIC, enable the TBI port. */
3350         if (sc->bge_flags & BGE_FLAG_TBI) {
3351                 struct ifmedia *ifm = &sc->bge_ifmedia;
3352
3353                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3354                         return(EINVAL);
3355
3356                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3357                 case IFM_AUTO:
3358                         /*
3359                          * The BCM5704 ASIC appears to have a special
3360                          * mechanism for programming the autoneg
3361                          * advertisement registers in TBI mode.
3362                          */
3363                         if (!bge_fake_autoneg &&
3364                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3365                                 uint32_t sgdig;
3366
3367                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3368                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3369                                 sgdig |= BGE_SGDIGCFG_AUTO |
3370                                          BGE_SGDIGCFG_PAUSE_CAP |
3371                                          BGE_SGDIGCFG_ASYM_PAUSE;
3372                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3373                                             sgdig | BGE_SGDIGCFG_SEND);
3374                                 DELAY(5);
3375                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3376                         }
3377                         break;
3378                 case IFM_1000_SX:
3379                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3380                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3381                                     BGE_MACMODE_HALF_DUPLEX);
3382                         } else {
3383                                 BGE_SETBIT(sc, BGE_MAC_MODE,
3384                                     BGE_MACMODE_HALF_DUPLEX);
3385                         }
3386                         break;
3387                 default:
3388                         return(EINVAL);
3389                 }
3390         } else {
3391                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3392
3393                 sc->bge_link_evt++;
3394                 sc->bge_link = 0;
3395                 if (mii->mii_instance) {
3396                         struct mii_softc *miisc;
3397
3398                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3399                                 mii_phy_reset(miisc);
3400                 }
3401                 mii_mediachg(mii);
3402
3403                 /*
3404                  * Force an interrupt so that we will call bge_link_upd
3405                  * if needed and clear any pending link state attention.
3406                  * Without this we are not getting any further interrupts
3407                  * for link state changes and thus will not UP the link and
3408                  * not be able to send in bge_start.  The only way to get
3409                  * things working was to receive a packet and get an RX
3410                  * intr.
3411                  *
3412                  * bge_tick should help for fiber cards and we might not
3413                  * need to do this here if BGE_FLAG_TBI is set but as
3414                  * we poll for fiber anyway it should not harm.
3415                  */
3416                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3417                     BGE_IS_5788(sc))
3418                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3419                 else
3420                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3421         }
3422         return(0);
3423 }
3424
3425 /*
3426  * Report current media status.
3427  */
3428 static void
3429 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3430 {
3431         struct bge_softc *sc = ifp->if_softc;
3432
3433         if (sc->bge_flags & BGE_FLAG_TBI) {
3434                 ifmr->ifm_status = IFM_AVALID;
3435                 ifmr->ifm_active = IFM_ETHER;
3436                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3437                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3438                         ifmr->ifm_status |= IFM_ACTIVE;
3439                 } else {
3440                         ifmr->ifm_active |= IFM_NONE;
3441                         return;
3442                 }
3443
3444                 ifmr->ifm_active |= IFM_1000_SX;
3445                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3446                         ifmr->ifm_active |= IFM_HDX;
3447                 else
3448                         ifmr->ifm_active |= IFM_FDX;
3449         } else {
3450                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3451
3452                 mii_pollstat(mii);
3453                 ifmr->ifm_active = mii->mii_media_active;
3454                 ifmr->ifm_status = mii->mii_media_status;
3455         }
3456 }
3457
3458 static int
3459 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3460 {
3461         struct bge_softc *sc = ifp->if_softc;
3462         struct ifreq *ifr = (struct ifreq *)data;
3463         int mask, error = 0;
3464
3465         ASSERT_SERIALIZED(ifp->if_serializer);
3466
3467         switch (command) {
3468         case SIOCSIFMTU:
3469                 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3470                     (BGE_IS_JUMBO_CAPABLE(sc) &&
3471                      ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3472                         error = EINVAL;
3473                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3474                         ifp->if_mtu = ifr->ifr_mtu;
3475                         if (ifp->if_flags & IFF_RUNNING)
3476                                 bge_init(sc);
3477                 }
3478                 break;
3479         case SIOCSIFFLAGS:
3480                 if (ifp->if_flags & IFF_UP) {
3481                         if (ifp->if_flags & IFF_RUNNING) {
3482                                 mask = ifp->if_flags ^ sc->bge_if_flags;
3483
3484                                 /*
3485                                  * If only the state of the PROMISC flag
3486                                  * changed, then just use the 'set promisc
3487                                  * mode' command instead of reinitializing
3488                                  * the entire NIC. Doing a full re-init
3489                                  * means reloading the firmware and waiting
3490                                  * for it to start up, which may take a
3491                                  * second or two.  Similarly for ALLMULTI.
3492                                  */
3493                                 if (mask & IFF_PROMISC)
3494                                         bge_setpromisc(sc);
3495                                 if (mask & IFF_ALLMULTI)
3496                                         bge_setmulti(sc);
3497                         } else {
3498                                 bge_init(sc);
3499                         }
3500                 } else if (ifp->if_flags & IFF_RUNNING) {
3501                         bge_stop(sc);
3502                 }
3503                 sc->bge_if_flags = ifp->if_flags;
3504                 break;
3505         case SIOCADDMULTI:
3506         case SIOCDELMULTI:
3507                 if (ifp->if_flags & IFF_RUNNING)
3508                         bge_setmulti(sc);
3509                 break;
3510         case SIOCSIFMEDIA:
3511         case SIOCGIFMEDIA:
3512                 if (sc->bge_flags & BGE_FLAG_TBI) {
3513                         error = ifmedia_ioctl(ifp, ifr,
3514                             &sc->bge_ifmedia, command);
3515                 } else {
3516                         struct mii_data *mii;
3517
3518                         mii = device_get_softc(sc->bge_miibus);
3519                         error = ifmedia_ioctl(ifp, ifr,
3520                                               &mii->mii_media, command);
3521                 }
3522                 break;
3523         case SIOCSIFCAP:
3524                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3525                 if (mask & IFCAP_HWCSUM) {
3526                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3527                         if (IFCAP_HWCSUM & ifp->if_capenable)
3528                                 ifp->if_hwassist = BGE_CSUM_FEATURES;
3529                         else
3530                                 ifp->if_hwassist = 0;
3531                 }
3532                 break;
3533         default:
3534                 error = ether_ioctl(ifp, command, data);
3535                 break;
3536         }
3537         return error;
3538 }
3539
3540 static void
3541 bge_watchdog(struct ifnet *ifp)
3542 {
3543         struct bge_softc *sc = ifp->if_softc;
3544
3545         if_printf(ifp, "watchdog timeout -- resetting\n");
3546
3547         bge_init(sc);
3548
3549         ifp->if_oerrors++;
3550
3551         if (!ifq_is_empty(&ifp->if_snd))
3552                 if_devstart(ifp);
3553 }
3554
3555 /*
3556  * Stop the adapter and free any mbufs allocated to the
3557  * RX and TX lists.
3558  */
3559 static void
3560 bge_stop(struct bge_softc *sc)
3561 {
3562         struct ifnet *ifp = &sc->arpcom.ac_if;
3563
3564         ASSERT_SERIALIZED(ifp->if_serializer);
3565
3566         callout_stop(&sc->bge_stat_timer);
3567
3568         /*
3569          * Disable all of the receiver blocks
3570          */
3571         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3572         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3573         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3574         if (!BGE_IS_5705_PLUS(sc))
3575                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3576         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3577         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3578         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3579
3580         /*
3581          * Disable all of the transmit blocks
3582          */
3583         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3584         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3585         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3586         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3587         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3588         if (!BGE_IS_5705_PLUS(sc))
3589                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3590         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3591
3592         /*
3593          * Shut down all of the memory managers and related
3594          * state machines.
3595          */
3596         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3597         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3598         if (!BGE_IS_5705_PLUS(sc))
3599                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3600         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3601         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3602         if (!BGE_IS_5705_PLUS(sc)) {
3603                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3604                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3605         }
3606
3607         /* Disable host interrupts. */
3608         bge_disable_intr(sc);
3609
3610         /*
3611          * Tell firmware we're shutting down.
3612          */
3613         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3614
3615         /* Free the RX lists. */
3616         bge_free_rx_ring_std(sc);
3617
3618         /* Free jumbo RX list. */
3619         if (BGE_IS_JUMBO_CAPABLE(sc))
3620                 bge_free_rx_ring_jumbo(sc);
3621
3622         /* Free TX buffers. */
3623         bge_free_tx_ring(sc);
3624
3625         sc->bge_link = 0;
3626         sc->bge_coal_chg = 0;
3627
3628         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3629
3630         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3631         ifp->if_timer = 0;
3632 }
3633
3634 /*
3635  * Stop all chip I/O so that the kernel's probe routines don't
3636  * get confused by errant DMAs when rebooting.
3637  */
3638 static void
3639 bge_shutdown(device_t dev)
3640 {
3641         struct bge_softc *sc = device_get_softc(dev);
3642         struct ifnet *ifp = &sc->arpcom.ac_if;
3643
3644         lwkt_serialize_enter(ifp->if_serializer);
3645         bge_stop(sc);
3646         bge_reset(sc);
3647         lwkt_serialize_exit(ifp->if_serializer);
3648 }
3649
3650 static int
3651 bge_suspend(device_t dev)
3652 {
3653         struct bge_softc *sc = device_get_softc(dev);
3654         struct ifnet *ifp = &sc->arpcom.ac_if;
3655
3656         lwkt_serialize_enter(ifp->if_serializer);
3657         bge_stop(sc);
3658         lwkt_serialize_exit(ifp->if_serializer);
3659
3660         return 0;
3661 }
3662
3663 static int
3664 bge_resume(device_t dev)
3665 {
3666         struct bge_softc *sc = device_get_softc(dev);
3667         struct ifnet *ifp = &sc->arpcom.ac_if;
3668
3669         lwkt_serialize_enter(ifp->if_serializer);
3670
3671         if (ifp->if_flags & IFF_UP) {
3672                 bge_init(sc);
3673
3674                 if (!ifq_is_empty(&ifp->if_snd))
3675                         if_devstart(ifp);
3676         }
3677
3678         lwkt_serialize_exit(ifp->if_serializer);
3679
3680         return 0;
3681 }
3682
3683 static void
3684 bge_setpromisc(struct bge_softc *sc)
3685 {
3686         struct ifnet *ifp = &sc->arpcom.ac_if;
3687
3688         if (ifp->if_flags & IFF_PROMISC)
3689                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3690         else
3691                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3692 }
3693
3694 static void
3695 bge_dma_free(struct bge_softc *sc)
3696 {
3697         int i;
3698
3699         /* Destroy RX mbuf DMA stuffs. */
3700         if (sc->bge_cdata.bge_rx_mtag != NULL) {
3701                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3702                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3703                             sc->bge_cdata.bge_rx_std_dmamap[i]);
3704                 }
3705                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3706                                    sc->bge_cdata.bge_rx_tmpmap);
3707                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3708         }
3709
3710         /* Destroy TX mbuf DMA stuffs. */
3711         if (sc->bge_cdata.bge_tx_mtag != NULL) {
3712                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3713                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3714                             sc->bge_cdata.bge_tx_dmamap[i]);
3715                 }
3716                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3717         }
3718
3719         /* Destroy standard RX ring */
3720         bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3721                            sc->bge_cdata.bge_rx_std_ring_map,
3722                            sc->bge_ldata.bge_rx_std_ring);
3723
3724         if (BGE_IS_JUMBO_CAPABLE(sc))
3725                 bge_free_jumbo_mem(sc);
3726
3727         /* Destroy RX return ring */
3728         bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3729                            sc->bge_cdata.bge_rx_return_ring_map,
3730                            sc->bge_ldata.bge_rx_return_ring);
3731
3732         /* Destroy TX ring */
3733         bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3734                            sc->bge_cdata.bge_tx_ring_map,
3735                            sc->bge_ldata.bge_tx_ring);
3736
3737         /* Destroy status block */
3738         bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3739                            sc->bge_cdata.bge_status_map,
3740                            sc->bge_ldata.bge_status_block);
3741
3742         /* Destroy statistics block */
3743         bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3744                            sc->bge_cdata.bge_stats_map,
3745                            sc->bge_ldata.bge_stats);
3746
3747         /* Destroy the parent tag */
3748         if (sc->bge_cdata.bge_parent_tag != NULL)
3749                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3750 }
3751
3752 static int
3753 bge_dma_alloc(struct bge_softc *sc)
3754 {
3755         struct ifnet *ifp = &sc->arpcom.ac_if;
3756         int i, error;
3757         bus_addr_t lowaddr;
3758
3759         lowaddr = BUS_SPACE_MAXADDR;
3760         if (sc->bge_flags & BGE_FLAG_MAXADDR_40BIT)
3761                 lowaddr = BGE_DMA_MAXADDR_40BIT;
3762
3763         /*
3764          * Allocate the parent bus DMA tag appropriate for PCI.
3765          *
3766          * All of the NetExtreme/NetLink controllers have 4GB boundary
3767          * DMA bug.
3768          * Whenever an address crosses a multiple of the 4GB boundary
3769          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3770          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3771          * state machine will lockup and cause the device to hang.
3772          */
3773         error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
3774                                    lowaddr, BUS_SPACE_MAXADDR,
3775                                    NULL, NULL,
3776                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3777                                    BUS_SPACE_MAXSIZE_32BIT,
3778                                    0, &sc->bge_cdata.bge_parent_tag);
3779         if (error) {
3780                 if_printf(ifp, "could not allocate parent dma tag\n");
3781                 return error;
3782         }
3783
3784         /*
3785          * Create DMA tag and maps for RX mbufs.
3786          */
3787         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3788                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3789                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
3790                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3791                                    &sc->bge_cdata.bge_rx_mtag);
3792         if (error) {
3793                 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
3794                 return error;
3795         }
3796
3797         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3798                                   BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_tmpmap);
3799         if (error) {
3800                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3801                 sc->bge_cdata.bge_rx_mtag = NULL;
3802                 return error;
3803         }
3804
3805         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3806                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3807                                           BUS_DMA_WAITOK,
3808                                           &sc->bge_cdata.bge_rx_std_dmamap[i]);
3809                 if (error) {
3810                         int j;
3811
3812                         for (j = 0; j < i; ++j) {
3813                                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3814                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3815                         }
3816                         bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3817                         sc->bge_cdata.bge_rx_mtag = NULL;
3818
3819                         if_printf(ifp, "could not create DMA map for RX\n");
3820                         return error;
3821                 }
3822         }
3823
3824         /*
3825          * Create DMA tag and maps for TX mbufs.
3826          */
3827         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3828                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3829                                    NULL, NULL,
3830                                    BGE_JUMBO_FRAMELEN, BGE_NSEG_NEW, MCLBYTES,
3831                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
3832                                    BUS_DMA_ONEBPAGE,
3833                                    &sc->bge_cdata.bge_tx_mtag);
3834         if (error) {
3835                 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
3836                 return error;
3837         }
3838
3839         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3840                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag,
3841                                           BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
3842                                           &sc->bge_cdata.bge_tx_dmamap[i]);
3843                 if (error) {
3844                         int j;
3845
3846                         for (j = 0; j < i; ++j) {
3847                                 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3848                                         sc->bge_cdata.bge_tx_dmamap[j]);
3849                         }
3850                         bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3851                         sc->bge_cdata.bge_tx_mtag = NULL;
3852
3853                         if_printf(ifp, "could not create DMA map for TX\n");
3854                         return error;
3855                 }
3856         }
3857
3858         /*
3859          * Create DMA stuffs for standard RX ring.
3860          */
3861         error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3862                                     &sc->bge_cdata.bge_rx_std_ring_tag,
3863                                     &sc->bge_cdata.bge_rx_std_ring_map,
3864                                     (void *)&sc->bge_ldata.bge_rx_std_ring,
3865                                     &sc->bge_ldata.bge_rx_std_ring_paddr);
3866         if (error) {
3867                 if_printf(ifp, "could not create std RX ring\n");
3868                 return error;
3869         }
3870
3871         /*
3872          * Create jumbo buffer pool.
3873          */
3874         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3875                 error = bge_alloc_jumbo_mem(sc);
3876                 if (error) {
3877                         if_printf(ifp, "could not create jumbo buffer pool\n");
3878                         return error;
3879                 }
3880         }
3881
3882         /*
3883          * Create DMA stuffs for RX return ring.
3884          */
3885         error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3886                                     &sc->bge_cdata.bge_rx_return_ring_tag,
3887                                     &sc->bge_cdata.bge_rx_return_ring_map,
3888                                     (void *)&sc->bge_ldata.bge_rx_return_ring,
3889                                     &sc->bge_ldata.bge_rx_return_ring_paddr);
3890         if (error) {
3891                 if_printf(ifp, "could not create RX ret ring\n");
3892                 return error;
3893         }
3894
3895         /*
3896          * Create DMA stuffs for TX ring.
3897          */
3898         error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
3899                                     &sc->bge_cdata.bge_tx_ring_tag,
3900                                     &sc->bge_cdata.bge_tx_ring_map,
3901                                     (void *)&sc->bge_ldata.bge_tx_ring,
3902                                     &sc->bge_ldata.bge_tx_ring_paddr);
3903         if (error) {
3904                 if_printf(ifp, "could not create TX ring\n");
3905                 return error;
3906         }
3907
3908         /*
3909          * Create DMA stuffs for status block.
3910          */
3911         error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3912                                     &sc->bge_cdata.bge_status_tag,
3913                                     &sc->bge_cdata.bge_status_map,
3914                                     (void *)&sc->bge_ldata.bge_status_block,
3915                                     &sc->bge_ldata.bge_status_block_paddr);
3916         if (error) {
3917                 if_printf(ifp, "could not create status block\n");
3918                 return error;
3919         }
3920
3921         /*
3922          * Create DMA stuffs for statistics block.
3923          */
3924         error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
3925                                     &sc->bge_cdata.bge_stats_tag,
3926                                     &sc->bge_cdata.bge_stats_map,
3927                                     (void *)&sc->bge_ldata.bge_stats,
3928                                     &sc->bge_ldata.bge_stats_paddr);
3929         if (error) {
3930                 if_printf(ifp, "could not create stats block\n");
3931                 return error;
3932         }
3933         return 0;
3934 }
3935
3936 static int
3937 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3938                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3939 {
3940         bus_dmamem_t dmem;
3941         int error;
3942
3943         error = bus_dmamem_coherent(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
3944                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3945                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3946         if (error)
3947                 return error;
3948
3949         *tag = dmem.dmem_tag;
3950         *map = dmem.dmem_map;
3951         *addr = dmem.dmem_addr;
3952         *paddr = dmem.dmem_busaddr;
3953
3954         return 0;
3955 }
3956
3957 static void
3958 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3959 {
3960         if (tag != NULL) {
3961                 bus_dmamap_unload(tag, map);
3962                 bus_dmamem_free(tag, addr, map);
3963                 bus_dma_tag_destroy(tag);
3964         }
3965 }
3966
3967 /*
3968  * Grrr. The link status word in the status block does
3969  * not work correctly on the BCM5700 rev AX and BX chips,
3970  * according to all available information. Hence, we have
3971  * to enable MII interrupts in order to properly obtain
3972  * async link changes. Unfortunately, this also means that
3973  * we have to read the MAC status register to detect link
3974  * changes, thereby adding an additional register access to
3975  * the interrupt handler.
3976  *
3977  * XXX: perhaps link state detection procedure used for
3978  * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
3979  */
3980 static void
3981 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
3982 {
3983         struct ifnet *ifp = &sc->arpcom.ac_if;
3984         struct mii_data *mii = device_get_softc(sc->bge_miibus);
3985
3986         mii_pollstat(mii);
3987
3988         if (!sc->bge_link &&
3989             (mii->mii_media_status & IFM_ACTIVE) &&
3990             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3991                 sc->bge_link++;
3992                 if (bootverbose)
3993                         if_printf(ifp, "link UP\n");
3994         } else if (sc->bge_link &&
3995             (!(mii->mii_media_status & IFM_ACTIVE) ||
3996             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3997                 sc->bge_link = 0;
3998                 if (bootverbose)
3999                         if_printf(ifp, "link DOWN\n");
4000         }
4001
4002         /* Clear the interrupt. */
4003         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
4004         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
4005         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
4006 }
4007
4008 static void
4009 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
4010 {
4011         struct ifnet *ifp = &sc->arpcom.ac_if;
4012
4013 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
4014
4015         /*
4016          * Sometimes PCS encoding errors are detected in
4017          * TBI mode (on fiber NICs), and for some reason
4018          * the chip will signal them as link changes.
4019          * If we get a link change event, but the 'PCS
4020          * encoding error' bit in the MAC status register
4021          * is set, don't bother doing a link check.
4022          * This avoids spurious "gigabit link up" messages
4023          * that sometimes appear on fiber NICs during
4024          * periods of heavy traffic.
4025          */
4026         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4027                 if (!sc->bge_link) {
4028                         sc->bge_link++;
4029                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4030                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
4031                                     BGE_MACMODE_TBI_SEND_CFGS);
4032                         }
4033                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4034
4035                         if (bootverbose)
4036                                 if_printf(ifp, "link UP\n");
4037
4038                         ifp->if_link_state = LINK_STATE_UP;
4039                         if_link_state_change(ifp);
4040                 }
4041         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
4042                 if (sc->bge_link) {
4043                         sc->bge_link = 0;
4044
4045                         if (bootverbose)
4046                                 if_printf(ifp, "link DOWN\n");
4047
4048                         ifp->if_link_state = LINK_STATE_DOWN;
4049                         if_link_state_change(ifp);
4050                 }
4051         }
4052
4053 #undef PCS_ENCODE_ERR
4054
4055         /* Clear the attention. */
4056         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4057             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4058             BGE_MACSTAT_LINK_CHANGED);
4059 }
4060
4061 static void
4062 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
4063 {
4064         struct ifnet *ifp = &sc->arpcom.ac_if;
4065         struct mii_data *mii = device_get_softc(sc->bge_miibus);
4066
4067         mii_pollstat(mii);
4068         bge_miibus_statchg(sc->bge_dev);
4069
4070         if (bootverbose) {
4071                 if (sc->bge_link)
4072                         if_printf(ifp, "link UP\n");
4073                 else
4074                         if_printf(ifp, "link DOWN\n");
4075         }
4076
4077         /* Clear the attention. */
4078         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4079             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4080             BGE_MACSTAT_LINK_CHANGED);
4081 }
4082
4083 static void
4084 bge_autopoll_link_upd(struct bge_softc *sc, uint32_t status __unused)
4085 {
4086         struct ifnet *ifp = &sc->arpcom.ac_if;
4087         struct mii_data *mii = device_get_softc(sc->bge_miibus);
4088
4089         mii_pollstat(mii);
4090
4091         if (!sc->bge_link &&
4092             (mii->mii_media_status & IFM_ACTIVE) &&
4093             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4094                 sc->bge_link++;
4095                 if (bootverbose)
4096                         if_printf(ifp, "link UP\n");
4097         } else if (sc->bge_link &&
4098             (!(mii->mii_media_status & IFM_ACTIVE) ||
4099             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4100                 sc->bge_link = 0;
4101                 if (bootverbose)
4102                         if_printf(ifp, "link DOWN\n");
4103         }
4104
4105         /* Clear the attention. */
4106         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4107             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4108             BGE_MACSTAT_LINK_CHANGED);
4109 }
4110
4111 static int
4112 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
4113 {
4114         struct bge_softc *sc = arg1;
4115
4116         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4117                                    &sc->bge_rx_coal_ticks,
4118                                    BGE_RX_COAL_TICKS_CHG);
4119 }
4120
4121 static int
4122 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
4123 {
4124         struct bge_softc *sc = arg1;
4125
4126         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4127                                    &sc->bge_tx_coal_ticks,
4128                                    BGE_TX_COAL_TICKS_CHG);
4129 }
4130
4131 static int
4132 bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS)
4133 {
4134         struct bge_softc *sc = arg1;
4135
4136         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4137                                    &sc->bge_rx_max_coal_bds,
4138                                    BGE_RX_MAX_COAL_BDS_CHG);
4139 }
4140
4141 static int
4142 bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS)
4143 {
4144         struct bge_softc *sc = arg1;
4145
4146         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4147                                    &sc->bge_tx_max_coal_bds,
4148                                    BGE_TX_MAX_COAL_BDS_CHG);
4149 }
4150
4151 static int
4152 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
4153                     uint32_t coal_chg_mask)
4154 {
4155         struct bge_softc *sc = arg1;
4156         struct ifnet *ifp = &sc->arpcom.ac_if;
4157         int error = 0, v;
4158
4159         lwkt_serialize_enter(ifp->if_serializer);
4160
4161         v = *coal;
4162         error = sysctl_handle_int(oidp, &v, 0, req);
4163         if (!error && req->newptr != NULL) {
4164                 if (v < 0) {
4165                         error = EINVAL;
4166                 } else {
4167                         *coal = v;
4168                         sc->bge_coal_chg |= coal_chg_mask;
4169                 }
4170         }
4171
4172         lwkt_serialize_exit(ifp->if_serializer);
4173         return error;
4174 }
4175
4176 static void
4177 bge_coal_change(struct bge_softc *sc)
4178 {
4179         struct ifnet *ifp = &sc->arpcom.ac_if;
4180         uint32_t val;
4181
4182         ASSERT_SERIALIZED(ifp->if_serializer);
4183
4184         if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
4185                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
4186                             sc->bge_rx_coal_ticks);
4187                 DELAY(10);
4188                 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
4189
4190                 if (bootverbose) {
4191                         if_printf(ifp, "rx_coal_ticks -> %u\n",
4192                                   sc->bge_rx_coal_ticks);
4193                 }
4194         }
4195
4196         if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
4197                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
4198                             sc->bge_tx_coal_ticks);
4199                 DELAY(10);
4200                 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
4201
4202                 if (bootverbose) {
4203                         if_printf(ifp, "tx_coal_ticks -> %u\n",
4204                                   sc->bge_tx_coal_ticks);
4205                 }
4206         }
4207
4208         if (sc->bge_coal_chg & BGE_RX_MAX_COAL_BDS_CHG) {
4209                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
4210                             sc->bge_rx_max_coal_bds);
4211                 DELAY(10);
4212                 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
4213
4214                 if (bootverbose) {
4215                         if_printf(ifp, "rx_max_coal_bds -> %u\n",
4216                                   sc->bge_rx_max_coal_bds);
4217                 }
4218         }
4219
4220         if (sc->bge_coal_chg & BGE_TX_MAX_COAL_BDS_CHG) {
4221                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
4222                             sc->bge_tx_max_coal_bds);
4223                 DELAY(10);
4224                 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
4225
4226                 if (bootverbose) {
4227                         if_printf(ifp, "tx_max_coal_bds -> %u\n",
4228                                   sc->bge_tx_max_coal_bds);
4229                 }
4230         }
4231
4232         sc->bge_coal_chg = 0;
4233 }
4234
4235 static void
4236 bge_enable_intr(struct bge_softc *sc)
4237 {
4238         struct ifnet *ifp = &sc->arpcom.ac_if;
4239
4240         lwkt_serialize_handler_enable(ifp->if_serializer);
4241
4242         /*
4243          * Enable interrupt.
4244          */
4245         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4246
4247         /*
4248          * Unmask the interrupt when we stop polling.
4249          */
4250         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4251
4252         /*
4253          * Trigger another interrupt, since above writing
4254          * to interrupt mailbox0 may acknowledge pending
4255          * interrupt.
4256          */
4257         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4258 }
4259
4260 static void
4261 bge_disable_intr(struct bge_softc *sc)
4262 {
4263         struct ifnet *ifp = &sc->arpcom.ac_if;
4264
4265         /*
4266          * Mask the interrupt when we start polling.
4267          */
4268         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4269
4270         /*
4271          * Acknowledge possible asserted interrupt.
4272          */
4273         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4274
4275         lwkt_serialize_handler_disable(ifp->if_serializer);
4276 }
4277
4278 static int
4279 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
4280 {
4281         uint32_t mac_addr;
4282         int ret = 1;
4283
4284         mac_addr = bge_readmem_ind(sc, 0x0c14);
4285         if ((mac_addr >> 16) == 0x484b) {
4286                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4287                 ether_addr[1] = (uint8_t)mac_addr;
4288                 mac_addr = bge_readmem_ind(sc, 0x0c18);
4289                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4290                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4291                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4292                 ether_addr[5] = (uint8_t)mac_addr;
4293                 ret = 0;
4294         }
4295         return ret;
4296 }
4297
4298 static int
4299 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
4300 {
4301         int mac_offset = BGE_EE_MAC_OFFSET;
4302
4303         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
4304                 mac_offset = BGE_EE_MAC_OFFSET_5906;
4305
4306         return bge_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4307 }
4308
4309 static int
4310 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
4311 {
4312         if (sc->bge_flags & BGE_FLAG_NO_EEPROM)
4313                 return 1;
4314
4315         return bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4316                                ETHER_ADDR_LEN);
4317 }
4318
4319 static int
4320 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
4321 {
4322         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
4323                 /* NOTE: Order is critical */
4324                 bge_get_eaddr_mem,
4325                 bge_get_eaddr_nvram,
4326                 bge_get_eaddr_eeprom,
4327                 NULL
4328         };
4329         const bge_eaddr_fcn_t *func;
4330
4331         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
4332                 if ((*func)(sc, eaddr) == 0)
4333                         break;
4334         }
4335         return (*func == NULL ? ENXIO : 0);
4336 }