2 * Copyright (c) 2004, 2005 David Young. All rights reserved.
4 * Programmed for NetBSD by David Young.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of David Young may not be used to endorse or promote
15 * products derived from this software without specific prior
18 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
19 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
20 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
21 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David
22 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
23 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
24 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
31 * $NetBSD: rtwphy.c,v 1.9 2006/03/08 00:24:06 dyoung Exp $
32 * $DragonFly: src/sys/dev/netif/rtw/rtwphy.c,v 1.5 2008/01/15 09:01:13 sephe Exp $
36 * Control the Philips SA2400 RF front-end and the baseband processor
37 * built into the Realtek RTL8180.
40 #include <sys/param.h>
41 #include <sys/bitops.h>
43 #include <sys/socket.h>
46 #include <net/if_arp.h>
47 #include <net/if_media.h>
49 #include <netproto/802_11/ieee80211_var.h>
50 #include <netproto/802_11/ieee80211_radiotap.h>
51 #include <netproto/802_11/wlan_ratectl/onoe/ieee80211_onoe_param.h>
53 #include <dev/netif/rtw/rtwreg.h>
54 #include <dev/netif/rtw/max2820reg.h>
55 #include <dev/netif/rtw/sa2400reg.h>
56 #include <dev/netif/rtw/rtwvar.h>
57 #include <dev/netif/rtw/rtwphyio.h>
58 #include <dev/netif/rtw/rtwphy.h>
60 static int rtw_max2820_pwrstate(struct rtw_rf *, enum rtw_pwrstate);
61 static int rtw_sa2400_pwrstate(struct rtw_rf *, enum rtw_pwrstate);
63 #define GCT_WRITE(__gr, __addr, __val, __label) \
65 if (rtw_rfbus_write(&(__gr)->gr_bus, RTW_RFCHIPID_GCT, \
66 (__addr), (__val)) == -1) \
71 rtw_bbp_preinit(struct rtw_regs *regs, u_int antatten0, int dflantb, u_int freq)
73 u_int antatten = antatten0;
76 antatten |= RTW_BBP_ANTATTEN_DFLANTB;
77 if (freq == 2484) /* channel 14 */
78 antatten |= RTW_BBP_ANTATTEN_CHAN14;
79 return rtw_bbp_write(regs, RTW_BBP_ANTATTEN, antatten);
83 rtw_bbp_init(struct rtw_regs *regs, struct rtw_bbpset *bb, int antdiv,
84 int dflantb, uint8_t cs_threshold, u_int freq)
91 sys2 |= RTW_BBP_SYS2_ANTDIV;
93 __SHIFTIN(cs_threshold, RTW_BBP_SYS3_CSTHRESH_MASK);
95 #define RTW_BBP_WRITE_OR_RETURN(reg, val) \
96 if ((rc = rtw_bbp_write(regs, reg, val)) != 0) \
99 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS1, bb->bb_sys1);
100 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_TXAGC, bb->bb_txagc);
101 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_LNADET, bb->bb_lnadet);
102 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCINI, bb->bb_ifagcini);
103 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCLIMIT, bb->bb_ifagclimit);
104 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCDET, bb->bb_ifagcdet);
106 if ((rc = rtw_bbp_preinit(regs, bb->bb_antatten, dflantb, freq)) != 0)
109 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_TRL, bb->bb_trl);
110 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS2, sys2);
111 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS3, sys3);
112 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_CHESTLIM, bb->bb_chestlim);
113 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_CHSQLIM, bb->bb_chsqlim);
118 rtw_sa2400_txpower(struct rtw_rf *rf, uint8_t opaque_txpower)
120 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf;
121 struct rtw_rfbus *bus = &sa->sa_bus;
123 return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_TX,
127 /* make sure we're using the same settings as the reference driver */
129 verify_syna(u_int freq, uint32_t val)
131 uint32_t expected_val = ~val;
135 expected_val = 0x0000096c; /* ch 1 */
138 expected_val = 0x00080970; /* ch 2 */
141 expected_val = 0x00100974; /* ch 3 */
144 expected_val = 0x00180978; /* ch 4 */
147 expected_val = 0x00000980; /* ch 5 */
150 expected_val = 0x00080984; /* ch 6 */
153 expected_val = 0x00100988; /* ch 7 */
156 expected_val = 0x0018098c; /* ch 8 */
159 expected_val = 0x00000994; /* ch 9 */
162 expected_val = 0x00080998; /* ch 10 */
165 expected_val = 0x0010099c; /* ch 11 */
168 expected_val = 0x001809a0; /* ch 12 */
171 expected_val = 0x000009a8; /* ch 13 */
174 expected_val = 0x000009b4; /* ch 14 */
177 KKASSERT(val == expected_val);
182 rtw_sa2400_tune(struct rtw_rf *rf, u_int freq)
184 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf;
185 struct rtw_rfbus *bus = &sa->sa_bus;
187 uint32_t syna, synb, sync;
191 * XO = 44MHz, R = 11, hence N is in units of XO / R = 4MHz.
193 * The channel spacing (5MHz) is not divisible by 4MHz, so
194 * we set the fractional part of N to compensate.
199 syna = __SHIFTIN(nf, SA2400_SYNA_NF_MASK) |
200 __SHIFTIN(n, SA2400_SYNA_N_MASK);
201 verify_syna(freq, syna);
204 * Divide the 44MHz crystal down to 4MHz. Set the fractional
205 * compensation charge pump value to agree with the fractional
208 synb = __SHIFTIN(11, SA2400_SYNB_R_MASK) | SA2400_SYNB_L_NORMAL |
209 SA2400_SYNB_ON | SA2400_SYNB_ONE |
210 __SHIFTIN(80, SA2400_SYNB_FC_MASK); /* agrees w/ SA2400_SYNA_FM = 0 */
212 sync = SA2400_SYNC_CP_NORMAL;
214 rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNA, syna);
218 rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNB, synb);
222 rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNC, sync);
226 return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYND, 0x0);
230 rtw_sa2400_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power)
232 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf;
233 struct rtw_rfbus *bus = &sa->sa_bus;
236 opmode = SA2400_OPMODE_DEFAULTS;
239 opmode |= SA2400_OPMODE_MODE_TXRX;
242 opmode |= SA2400_OPMODE_MODE_WAIT;
245 opmode |= SA2400_OPMODE_MODE_SLEEP;
250 opmode |= SA2400_OPMODE_DIGIN;
252 return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE,
257 rtw_sa2400_manrx_init(struct rtw_sa2400 *sa)
262 * XXX we are not supposed to be in RXMGC mode when we do this?
264 manrx = SA2400_MANRX_AHSN;
265 manrx |= SA2400_MANRX_TEN;
266 manrx |= __SHIFTIN(1023, SA2400_MANRX_RXGAIN_MASK);
268 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_MANRX,
273 rtw_sa2400_vcocal_start(struct rtw_sa2400 *sa, int start)
277 opmode = SA2400_OPMODE_DEFAULTS;
279 opmode |= SA2400_OPMODE_MODE_VCOCALIB;
281 opmode |= SA2400_OPMODE_MODE_SLEEP;
284 opmode |= SA2400_OPMODE_DIGIN;
286 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE,
291 rtw_sa2400_vco_calibration(struct rtw_sa2400 *sa)
296 if ((rc = rtw_sa2400_vcocal_start(sa, 1)) != 0)
298 DELAY(2200); /* 2.2 milliseconds */
299 /* XXX superfluous: SA2400 automatically entered SLEEP mode. */
300 return rtw_sa2400_vcocal_start(sa, 0);
304 rtw_sa2400_filter_calibration(struct rtw_sa2400 *sa)
308 opmode = SA2400_OPMODE_DEFAULTS | SA2400_OPMODE_MODE_FCALIB;
310 opmode |= SA2400_OPMODE_DIGIN;
312 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE,
317 rtw_sa2400_dc_calibration(struct rtw_sa2400 *sa)
319 struct rtw_rf *rf = &sa->sa_rf;
323 rf->rf_continuous_tx_cb(rf->rf_continuous_tx_arg, 1);
325 dccal = SA2400_OPMODE_DEFAULTS | SA2400_OPMODE_MODE_TXRX;
327 rc = rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE,
333 * DCALIB after being in Tx mode for 5 microseconds
337 dccal &= ~SA2400_OPMODE_MODE_MASK;
338 dccal |= SA2400_OPMODE_MODE_DCALIB;
340 rc = rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE,
345 DELAY(20); /* calibration takes at most 20 microseconds */
347 rf->rf_continuous_tx_cb(rf->rf_continuous_tx_arg, 0);
352 rtw_sa2400_agc_init(struct rtw_sa2400 *sa)
356 agc = __SHIFTIN(25, SA2400_AGC_MAXGAIN_MASK);
357 agc |= __SHIFTIN(7, SA2400_AGC_BBPDELAY_MASK);
358 agc |= __SHIFTIN(15, SA2400_AGC_LNADELAY_MASK);
359 agc |= __SHIFTIN(27, SA2400_AGC_RXONDELAY_MASK);
361 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_AGC,
366 rtw_sa2400_destroy(struct rtw_rf *rf)
368 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf;
370 memset(sa, 0, sizeof(*sa));
375 rtw_sa2400_calibrate(struct rtw_rf *rf, u_int freq)
377 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf;
380 /* XXX reference driver calibrates VCO twice. Is it a bug? */
381 for (i = 0; i < 2; i++) {
382 if ((rc = rtw_sa2400_vco_calibration(sa)) != 0)
385 /* VCO calibration erases synthesizer registers, so re-tune */
386 if ((rc = rtw_sa2400_tune(rf, freq)) != 0)
388 if ((rc = rtw_sa2400_filter_calibration(sa)) != 0)
390 /* analog PHY needs DC calibration */
392 return rtw_sa2400_dc_calibration(sa);
397 rtw_sa2400_init(struct rtw_rf *rf, u_int freq, uint8_t opaque_txpower,
398 enum rtw_pwrstate power)
400 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf;
403 if ((rc = rtw_sa2400_txpower(rf, opaque_txpower)) != 0)
406 /* skip configuration if it's time to sleep or to power-down. */
407 if (power == RTW_SLEEP || power == RTW_OFF)
408 return rtw_sa2400_pwrstate(rf, power);
410 /* go to sleep for configuration */
411 if ((rc = rtw_sa2400_pwrstate(rf, RTW_SLEEP)) != 0)
414 if ((rc = rtw_sa2400_tune(rf, freq)) != 0)
416 if ((rc = rtw_sa2400_agc_init(sa)) != 0)
418 if ((rc = rtw_sa2400_manrx_init(sa)) != 0)
420 if ((rc = rtw_sa2400_calibrate(rf, freq)) != 0)
423 /* enter Tx/Rx mode */
424 return rtw_sa2400_pwrstate(rf, power);
428 rtw_sa2400_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, int digphy)
430 struct rtw_sa2400 *sa;
431 struct rtw_rfbus *bus;
433 struct rtw_bbpset *bb;
435 sa = kmalloc(sizeof(*sa), M_DEVBUF, M_WAITOK | M_ZERO);
437 sa->sa_digphy = digphy;
442 rf->rf_init = rtw_sa2400_init;
443 rf->rf_destroy = rtw_sa2400_destroy;
444 rf->rf_txpower = rtw_sa2400_txpower;
445 rf->rf_tune = rtw_sa2400_tune;
446 rf->rf_pwrstate = rtw_sa2400_pwrstate;
450 bb->bb_antatten = RTW_BBP_ANTATTEN_PHILIPS_MAGIC;
451 bb->bb_chestlim = 0x00;
452 bb->bb_chsqlim = 0xa0;
453 bb->bb_ifagcdet = 0x64;
454 bb->bb_ifagcini = 0x90;
455 bb->bb_ifagclimit = 0x1a;
456 bb->bb_lnadet = 0xe0;
464 bus->b_write = rf_write;
470 rtw_grf5101_txpower(struct rtw_rf *rf, uint8_t opaque_txpower)
472 struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf;
474 GCT_WRITE(gr, 0x15, 0, err);
475 GCT_WRITE(gr, 0x06, opaque_txpower, err);
476 GCT_WRITE(gr, 0x15, 0x10, err);
477 GCT_WRITE(gr, 0x15, 0x00, err);
484 rtw_grf5101_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power)
486 struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf;
491 GCT_WRITE(gr, 0x07, 0x0000, err);
492 GCT_WRITE(gr, 0x1f, 0x0045, err);
493 GCT_WRITE(gr, 0x1f, 0x0005, err);
494 GCT_WRITE(gr, 0x00, 0x08e4, err);
498 GCT_WRITE(gr, 0x1f, 0x0001, err);
500 GCT_WRITE(gr, 0x1f, 0x0001, err);
502 GCT_WRITE(gr, 0x1f, 0x0041, err);
504 GCT_WRITE(gr, 0x1f, 0x0061, err);
506 GCT_WRITE(gr, 0x00, 0x0ae4, err);
508 GCT_WRITE(gr, 0x07, 0x1000, err);
519 rtw_grf5101_tune(struct rtw_rf *rf, u_int freq)
522 struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf;
526 } else if ((channel = (freq - 2412) / 5 + 1) < 1 || channel > 13) {
527 RTW_DPRINTF(RTW_DEBUG_PHY,
528 ("%s: invalid channel %d (freq %d)\n", __func__, channel,
533 GCT_WRITE(gr, 0x07, 0, err);
534 GCT_WRITE(gr, 0x0b, channel - 1, err);
535 GCT_WRITE(gr, 0x07, 0x1000, err);
542 rtw_grf5101_init(struct rtw_rf *rf, u_int freq, uint8_t opaque_txpower,
543 enum rtw_pwrstate power)
546 struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf;
549 * These values have been derived from the rtl8180-sa2400
550 * Linux driver. It is unknown what they all do, GCT refuse
551 * to release any documentation so these are more than
552 * likely sub optimal settings
555 GCT_WRITE(gr, 0x01, 0x1a23, err);
556 GCT_WRITE(gr, 0x02, 0x4971, err);
557 GCT_WRITE(gr, 0x03, 0x41de, err);
558 GCT_WRITE(gr, 0x04, 0x2d80, err);
560 GCT_WRITE(gr, 0x05, 0x61ff, err);
562 GCT_WRITE(gr, 0x06, 0x0, err);
564 GCT_WRITE(gr, 0x08, 0x7533, err);
565 GCT_WRITE(gr, 0x09, 0xc401, err);
566 GCT_WRITE(gr, 0x0a, 0x0, err);
567 GCT_WRITE(gr, 0x0c, 0x1c7, err);
568 GCT_WRITE(gr, 0x0d, 0x29d3, err);
569 GCT_WRITE(gr, 0x0e, 0x2e8, err);
570 GCT_WRITE(gr, 0x10, 0x192, err);
571 GCT_WRITE(gr, 0x11, 0x248, err);
572 GCT_WRITE(gr, 0x12, 0x0, err);
573 GCT_WRITE(gr, 0x13, 0x20c4, err);
574 GCT_WRITE(gr, 0x14, 0xf4fc, err);
575 GCT_WRITE(gr, 0x15, 0x0, err);
576 GCT_WRITE(gr, 0x16, 0x1500, err);
578 if ((rc = rtw_grf5101_txpower(rf, opaque_txpower)) != 0)
581 if ((rc = rtw_grf5101_tune(rf, freq)) != 0)
590 rtw_grf5101_destroy(struct rtw_rf *rf)
592 struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf;
594 memset(gr, 0, sizeof(*gr));
599 rtw_grf5101_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, int digphy)
601 struct rtw_grf5101 *gr;
602 struct rtw_rfbus *bus;
604 struct rtw_bbpset *bb;
606 gr = kmalloc(sizeof(*gr), M_DEVBUF, M_WAITOK | M_ZERO);
611 rf->rf_init = rtw_grf5101_init;
612 rf->rf_destroy = rtw_grf5101_destroy;
613 rf->rf_txpower = rtw_grf5101_txpower;
614 rf->rf_tune = rtw_grf5101_tune;
615 rf->rf_pwrstate = rtw_grf5101_pwrstate;
619 bb->bb_antatten = RTW_BBP_ANTATTEN_GCT_MAGIC;
620 bb->bb_chestlim = 0x00;
621 bb->bb_chsqlim = 0xa0;
622 bb->bb_ifagcdet = 0x64;
623 bb->bb_ifagcini = 0x90;
624 bb->bb_ifagclimit = 0x1e;
625 bb->bb_lnadet = 0xc0;
633 bus->b_write = rf_write;
640 rtw_max2820_tune(struct rtw_rf *rf, u_int freq)
642 struct rtw_max2820 *mx = (struct rtw_max2820 *)rf;
643 struct rtw_rfbus *bus = &mx->mx_bus;
645 if (freq < 2400 || freq > 2499)
648 return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_CHANNEL,
649 __SHIFTIN(freq - 2400, MAX2820_CHANNEL_CF_MASK));
653 rtw_max2820_destroy(struct rtw_rf *rf)
655 struct rtw_max2820 *mx = (struct rtw_max2820 *)rf;
657 memset(mx, 0, sizeof(*mx));
662 rtw_max2820_init(struct rtw_rf *rf, u_int freq, uint8_t opaque_txpower,
663 enum rtw_pwrstate power)
665 struct rtw_max2820 *mx = (struct rtw_max2820 *)rf;
666 struct rtw_rfbus *bus = &mx->mx_bus;
669 rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_TEST,
670 MAX2820_TEST_DEFAULT);
674 rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_ENABLE,
675 MAX2820_ENABLE_DEFAULT);
679 /* skip configuration if it's time to sleep or to power-down. */
680 if ((rc = rtw_max2820_pwrstate(rf, power)) != 0)
682 else if (power == RTW_OFF || power == RTW_SLEEP)
685 rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_SYNTH,
686 MAX2820_SYNTH_R_44MHZ);
690 if ((rc = rtw_max2820_tune(rf, freq)) != 0)
694 * XXX The MAX2820 datasheet indicates that 1C and 2C should not
695 * be changed from 7, however, the reference driver sets them
696 * to 4 and 1, respectively.
698 rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_RECEIVE,
699 MAX2820_RECEIVE_DL_DEFAULT |
700 __SHIFTIN(4, MAX2820A_RECEIVE_1C_MASK) |
701 __SHIFTIN(1, MAX2820A_RECEIVE_2C_MASK));
705 return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_TRANSMIT,
706 MAX2820_TRANSMIT_PA_DEFAULT);
710 rtw_max2820_txpower(struct rtw_rf *rf, uint8_t opaque_txpower)
717 rtw_max2820_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power)
720 struct rtw_max2820 *mx;
721 struct rtw_rfbus *bus;
723 mx = (struct rtw_max2820 *)rf;
733 enable = MAX2820_ENABLE_DEFAULT;
736 return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_ENABLE, enable);
740 rtw_max2820_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, int is_a)
742 struct rtw_max2820 *mx;
743 struct rtw_rfbus *bus;
745 struct rtw_bbpset *bb;
747 mx = kmalloc(sizeof(*mx), M_DEVBUF, M_WAITOK | M_ZERO);
754 rf->rf_init = rtw_max2820_init;
755 rf->rf_destroy = rtw_max2820_destroy;
756 rf->rf_txpower = rtw_max2820_txpower;
757 rf->rf_tune = rtw_max2820_tune;
758 rf->rf_pwrstate = rtw_max2820_pwrstate;
762 bb->bb_antatten = RTW_BBP_ANTATTEN_MAXIM_MAGIC;
764 bb->bb_chsqlim = 159;
765 bb->bb_ifagcdet = 100;
766 bb->bb_ifagcini = 144;
767 bb->bb_ifagclimit = 26;
776 bus->b_write = rf_write;
783 rtw_phy_init(struct rtw_regs *regs, struct rtw_rf *rf, uint8_t opaque_txpower,
784 uint8_t cs_threshold, u_int freq, int antdiv, int dflantb,
785 enum rtw_pwrstate power)
788 RTW_DPRINTF(RTW_DEBUG_PHY,
789 ("%s: txpower %u csthresh %u freq %u antdiv %u dflantb %u "
790 "pwrstate %s\n", __func__, opaque_txpower, cs_threshold, freq,
791 antdiv, dflantb, rtw_pwrstate_string(power)));
793 /* XXX is this really necessary? */
794 if ((rc = rtw_rf_txpower(rf, opaque_txpower)) != 0)
797 rc = rtw_bbp_preinit(regs, rf->rf_bbpset.bb_antatten, dflantb, freq);
801 if ((rc = rtw_rf_tune(rf, freq)) != 0)
805 if ((rc = rtw_rf_init(rf, freq, opaque_txpower, power)) != 0)
807 #if 0 /* what is this redundant tx power setting here for? */
808 if ((rc = rtw_rf_txpower(rf, opaque_txpower)) != 0)
811 return rtw_bbp_init(regs, &rf->rf_bbpset, antdiv, dflantb, cs_threshold, freq);